Application Note: SY6370F
Single-channel, Adjustable Voltage Monitor in Ultra-small Package
General Description
Features
The SY6370F device is a very small supervisory
circuit that monitor voltage greater than 500mV with
a 0.25% threshold accuracy and offer adjustable
delay time using external capacitor. The SY6370F
has a logic enable pin to power on and off the output.
The SY6370F operates from 1.7V to 6.5V and has a
typical quiescent current of 9μA with an open drain
output rated at 18V. The SY6370F is available in an
ultra-small DFN package.
Applications
Ordering Information
SY6370 □(□□)□
Temperature Code
Package Code
Optional Spec Code
Package type
DFN1.45×1-6
Note
--
en
tia
Typical Applications
VCC
fid
R1
500kΩ
on
orp
.C
K1
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R2
100kΩ
R3
10kΩ
VCC
SENSE
C1
1µF
AN_SY6370F Rev. 0.9
© 2020 Silergy Corp.
DSPs, Microcontrollers, and Microprocessors
Notebook and Desktop Computers
PDAs and Handheld Products
Portable and Battery-powered Products
FPGAs and ASICs
l
Ordering Number
SY6370FDTC
Adjustable Threshold Down to 500mV
Threshold Accuracy: 1% Over temperature
Capacitor-adjustable Delay Time
Low Quiescent Current: 9μA (typ.)
External Enable Input
Open Drain Output (Rated at 18V)
Compact Package Minimizes Board Space:
DFN1.45mm×1.0mm - 6
VOUT
OUT
SY6370F
EN
GND
CT
C1
47nF
R4 1MΩ
Figure1. Schematic Diagram
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1
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SY6370F
Pinout
EN
1
6
VCC
GND
2
5
CT
SENSE
3
4
OUT
(DFN1.45×1-6)
Top Mark: Vxyz (device code: V, x=year code, y=week code, z= lot number code)
Pin NO.
I/O
CT
5
I
EN
1
I
GND
2
3
I
OUT
4
O
VCC
6
I
This pin is connected to the voltage that is monitored with the use of an external
resister. The output asserts after the capacitor-adjustable delay time when VSENSE
rises above 0.5V and EN is asserted. The output de-asserts after a minimal
propagation delay (16μs) when VSENSE falls below VIT+ - VHYS.
OUT is an open drain output that is immediately driven low after V SENSE falls
below (VIT+ - VHYS) or the EN input is low. OUT goes high after the capacitoradjustable delay time when VSENSE is greater than VIT+ and the EN pin is high. Open
drain device can be pulled up to 18V independent of VCC; Pull-up resisters are
required for these devices.
Supply Voltage Input. Connect a 1.7V to 6.5V supply to VCC to power the device.
It is good analog design practice to place a 0.1μF ceramic capacitor close to this
pin.
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SENSE
Pin Description
Capacitor-adjustable delay. The CT pin offers a user-adjustable delay time.
Connecting this pin to a ground referenced capacitor sets the delay time for SENSE
rising above 0.5V to OUT asserting.
tpd(r)(s) = [CCT(μF) x 4] + 40μs
Active high input. Driving EN low immediately makes OUT go low, independent
of VSENSE. With VSENSE already above VIT+, drive EN high to make OUT go high
after 0.2μs.
Ground.
o
Pin Name
AN_SY6370F Rev. 0.9
© 2020 Silergy Corp.
Silergy Corp. Confidential-prepared for Customer Use Only
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All Rights Reserved.
SY6370F
Block Diagram
OUT
VCC
SENSE
Delay
500mV
EN
GND
CT
Figure2. Block Diagram
Absolute Maximum Ratings (Note 1)
VCC ---------------------------------------------------------------------------------------------------------- ------------ -0.3V to 7V
CT ------------------------------------------------------------------------------------------------------------- -0.3V to VCC + 0.3V
EN, SENSE ------------------------------------------------------------------------------------------------------------- -0.3V to 7V
OUT (Open Drain) ------------------------------------------------------------------------------------------- -0.3V to 20V
OUT Current ----------------------------------------------------------------------------------------------------------------- ±10mA
Power Dissipation, PD @ TA = 25°C---------------------------------------------------------------------------------------- 0.34W
Package Thermal Resistance (Note 2)
θ JA ------------------------------------------------------------------------------------------------------------- 293.8°C/W
θ JC ------------------------------------------------------------------------------------------------------------ 165.1°C/W
Junction Temperature Range ------------------------------------------------------------------------------------ -40°C to 125°C
Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------------------- 260°C
Storage Temperature Range ------------------------------------------------------------------------------------ -65°C to 150°C
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Recommended Operating Conditions (Note 3)
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VCC ------------------------------------------------------------------------------------- -------------------------------- 1.7V to 6.5V
CT ------------------------------------------------------------------------------------------------------------------------- 0V to 6.5V
EN, SENSE----------------------------------------------------------------------------------------------------------------0V to 6.5V
OUT (Open Drain) ------------------------------------------------------------------------------------------------------- 0V to 18V
OUT Current ---------------------------------------------------------------------------------------------------- 0.0003mA to 1mA
AN_SY6370F Rev. 0.9
© 2020 Silergy Corp.
Silergy Corp. Confidential-prepared for Customer Use Only
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All Rights Reserved.
SY6370F
Electrical Characteristics
(1.7V < VCC < 6.5V, typical values are at TJ = 25°C and VCC = 3.3V, unless otherwise noted.)
Parameter
Symbol Test Conditions
Min
Typ
Input Voltage Range
VCC
1.7
VOL (max) =0.2V, IOUT =15μA
Power on Reset Voltage
VPOR
0.72
(Note 4)
VCC=3.3V, TA=25°C, no load
9
Supply Current
ICC
(into VCC pin)
VCC=6.5V, TA=25°C, no load
11
Hysteresis Voltage
SENSE Input Current
CT Pin Charge Current
CT Pin Comparator
Threshold Voltage
CT Pin Down Resistance
Low-level Input Voltage
High-level Input Voltage
Under Voltage Lockout
EN Leakage
VHYS
ISENSE
ICT
Low-level Output Voltage
VOL
Open-drain Output Leakage
Current
ILKG(OD)
VSENSE falling
VSENSE = 0V to VCC (Note 5)
VCT
RCT
VIL
VIH
VUVLO
Max
6.5
V
12
μA
13.5
μA
mV
nA
nA
V
5
-15
260
310
15
360
1.18
1.238
1.299
200
0.4
VCC falling, (Note 6)
EN/#EN = VCC or GND
VCC ≥ 1.2V, ISINK = 90μA
VCC ≥ 2.25V, ISINK = 0.5mA
VCC ≥ 4.5V, ISINK = 1mA
1.4
1.3
-100
VOUT high impedance = 18V
Unit
V
1.7
100
0.3
0.3
0.4
20
Ω
V
V
V
nA
V
V
V
nA
Max
Unit
μs
ms
tPD(f)
VSENSE falling
16
μs
rp.
Typ
40
190
(Note 7)
50
μs
Co
tW
tEN_GLH
td_off
td_fix
μs
1
EN de-asserted to output
de-asserted
EN asserted to output asserted
delay
100
ns
200
ns
200
ns
Sil
EN to VOUT Delay Time
Min
Co
tPD(r)
Test Condition
VSENSE rising, CCT = open
VSESNE rising, CCT = 0.047μF
nfi
Symbol
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Parameter
SENSE (rising) to OUT
Propagation Delay
SENSE (falling) to OUT
Propagation Delay
Start-up Delay
EN Pin Minimum Pulse
Duration
EN Glitch Rejection
EN to OUT Delay Time
(Output Disable)
de
Timing Requirements
AN_SY6370F Rev. 0.9
© 2020 Silergy Corp.
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All Rights Reserved.
SY6370F
Note 1: Stresses beyond the “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: ƟJA is measured in the natural convection at T A = 25°C on a low effective single layer thermal conductivity
test board of JEDEC 51-3 thermal measurement standard.
Note 3: The device is not guaranteed to function outside its operating conditions
Note 4: The lowest supply voltage (VCC) at which output is active (OUT is low); tr_VCC > 15μs/V. below VPOR, the
output cannot be determined.
Note 5: Specified by design.
Note 6: When VCC falls below the UVLO threshold, the output de-asserts (OUT goes low). Below VPOR, the output
cannot be determined
Note 7: During power on, VCC must exceed 1.7 V for at least 50μs (plus propagation delay time, t PD(r)) before output
is in the correct state.
Sequence:
UVLO
VCC
POR
VPOR
EN
yC
tPD(r)
tPD(f)
tPD(r)
tD_OFF
tD_CT
Figure3. SY6370F Sequence
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OUT
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SENSE
AN_SY6370F Rev. 0.9
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All Rights Reserved.
SY6370F
Typical Operating Characteristics
Supply Current vs. Input Voltage
(EN=VCC SENSE=0.6V CIN=1uF CT=Null)
Shutdown Current vs. Input Voltage
(EN=0V SENSE=0V C IN=1uF CT=Null)
10
12
10
8
Supply Current (μA)
Shutdown Current (μA)
9
7
6
5
4
3
25°C
2
8
6
4
25°C
2
1
0
0
0
2
4
6
8
1
2
Input Voltage (V)
3
4
5
6
7
8
Input Voltage (V)
Output Voltage Low vs. Output Sink Current
SENSE to OUT Delay vs. CCT
(EN=3V SENSE=0V C IN=1uF CT=Null )
(VCC=3.3V EN=3V SENSE=0.6V C IN=1uF)
250
9000
8000
7000
OUT Delay(ms)
VOL (mV)
200
150
100
6000
5000
4000
3000
2000
50
VCC=1.7V
VCC=3.3V
VCC=6.5V
0
1
2
3
4
5
0
6
200
400
600
on
0
1000
Output Sink Current(mA)
.C
SENSE to OUT Delay vs. Temperature
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Output Voltage Low vs. Temperature
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30
25
20
15
Sil
VOL(mV)
35
VCC=1.7V
10
VCC=3.3V
5
0
-40
VCC=6.5V
-20
0
20
40
60
80
Temperature(°C)
AN_SY6370F Rev. 0.9
© 2020 Silergy Corp.
100
120
(EN=3V SENSE=0VC IN=1uF CT=47nF Output sink current=1mA)
210
SENSE to OUT Delay tpdr(ms)
yC
40
1000 1200 1400 1600 1800 2000
CCT (nF)
(EN=3V SENSE=0V C IN=1uF CT Null Output sink current=1mA)
50
45
800
140
200
190
180
170
VCC=1.7V
VCC=3.3V
160
VCC=6.5V
150
-40
-20
0
20
40
60
80
100
120
140
Temperature(°C)
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SENSE threshold voltage VIT+,VIT-(mV)
SY6370F
SENSE threshold voltage vs. Temperature
Startup from Enable
(EN=3V CIN=1uF CT=Null)
(VCC=3.3V, EN=0V to 3V C IN=1uF,SENSE=0.6V, CT=Null)
506
VSENSE
504
500mV/div
VEN
2V/div
VIN
1V/div
VOUT
1V/div
502
500
498
496
VCC=1.7V VIT+
VCC=3.3V VIT+
494
VCC=6.5V VIT+
VCC=1.7V VIT-
492
VCC=3.3V VITVCC=6.5V VIT-
490
-40
-20
0
20
40
60
80
100
120
140
Time (200ns/div)
Temperature(°C)
Shutdown from Enable
Startup from SENSE
(VCC=3.3V, EN=0V to 3V C IN=1uF,SENSE=0.6V, CT=Null)
(VCC=3.3V, EN=3V,SENSE=0V to 0.6V, C IN=1uF, CT=Null)
VSENSE
500mV/div
VEN
VSENSE
2V/div
200mV/div
VIN
2V/div
VIN
1V/div
VEN
2V/div
VOUT
1V/div
VOUT
2V/div
Time (10μs/div)
.C
o
Time (100ns/div)
Shutdown from SENSE
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(VCC=3.3V, EN=3V,SENSE=0.6V to 0V, C IN=1uF, CT=Null)
yC
VEN
1V/div
VSENSE
VSENSE
200mV/div
2V/div
VEN
2V/div
VIN
1V/div
VOUT
2V/div
200mV/div
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VIN
Startup from Enable
(VCC=3.3V, EN=0V to 3V C IN=1uF,SENSE=0.6V, CT=47nF)
VOUT
Time (2μs/div)
AN_SY6370F Rev. 0.9
© 2020 Silergy Corp.
1V/div
Time (200ns/div)
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SY6370F
Shutdown from Enable
Startup from SENSE
(VCC=3.3V, EN=0V to 3V C IN=1uF,SENSE=0.6V, CT=47nF)
(VCC=3.3V, EN=3V,SENSE=0V to 0.6V, C IN=1uF, CT=47nF)
VSENSE
200mV/div
VEN
VSENSE
2V/div
200mV/div
VIN
2V/div
VIN
1V/div
VEN
1V/div
VOUT
1V/div
VOUT
1V/div
Time (400ns/div)
Time (40ms/div)
Shutdown from SENSE
(VCC=3.3V, EN=3V,SENSE=0.6V to 0V, C IN=1uF, CT=47nF)
VEN
2V/div
VIN
1V/div
VSENSE
VOUT
200mV/div
1V/div
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or
Time (4μs/div)
AN_SY6370F Rev. 0.9
© 2020 Silergy Corp.
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All Rights Reserved.
SY6370F
General Description
layout parasitic. The target threshold voltage can be
calculated by using Equation 1:
The SY6370F is a very small supervisory circuit that
monitors voltage greater than 500mVwith a 0.25%
threshold accuracy and offer adjustable delay time
using external capacitor. The SY6370F has a logic
enable pin to power on and off the output.
VTARGET=(1+R1/R2)×0.5(V)
The SY6370F operates from 1.7V to 6.5V and has a
typical quiescent current of 9μA with an open drain
output rated at 18V.
The SY6370F is available in an ultra-small DFN
package.
Overview
The SY6370FDTC is an ultra-small supervisory
circuit. The SY6370F is designed to assert the
SENSE_OUT or SENSE_OUT signal, as shown in
Table 1. When the SENSE pin rises above 0.5 V and
the enable input is asserted (ENABLE = high or
ENABLE = low) , the output asserts (OUT goes high
or OUT goes low) after the capacitor-adjustable delay
time. The SENSE pin can be set to any voltage
threshold above 0.5V using an external resistor
divider. A broad range of output delay times and
voltage thresholds can be supported, allowing these
devices to be used in wide array of applications.
Table1. SY6370F Truth Table
Conditions
ENABLE = high
ENABLE = low
ENABLE = low
ENABLE = high
SENSE < VIT+
SENSE < VIT+
SENSE > VIT+
SENSE > VIT+
Output
Status
OUT = low
OUT = low
OUT = low
OUT = high
Output not asserted
Output not asserted
Output not asserted
Output asserted after delay
Applications Information
Input Pin (SENSE)
Sil
The SENSE input pin allows any system voltage
above 0.5 V to be monitored. If the voltage at the
SENSE pin exceeds VIT+, and provided that the
enable pin is asserted (ENABLE=high), then the
output is asserted after the capacitor-adjustable delay
time elapses. When the voltage at the SENSE pin
drops below (VIT+ –Vhys), the output is de-asserted.
The comparator has a built-in hysteresis to ensure
smooth output assertions and de-assertions. Although
not required in most cases, for extremely noisy
applications, it is good analog design practice to
place a 1nF to 10nF bypass capacitor at the SENSE
input in order to reduce sensitivity to transients and
AN_SY6370F Rev. 0.9
© 2020 Silergy Corp.
(1)
Output Delay Time Pin (CT)
To program a user-defined, adjustable delay time, an
external capacitor must be connected between the CT
pin and GND. If the CT pin is left open, there will be
a delay of 40μs. The adjustable delay time can be
calculated through Equation 2:
tpd(r) (s) = [CCT(μF)×4] + 40 μs
(2)
The reset delay time is determined by the time it
takes an on-chip, precision 310nA current source to
charge the external capacitor to 1.24 V. When
SENSE > VIT+ and with ENABLE high, the internal
current sources are enabled and begin to charge the
external capacitors. When the CT voltage on a
capacitor reaches 1.24 V, the corresponding OUT is
asserted. Note that a low-leakage type capacitor (such
as ceramic) should be used and that stray capacitance
around this pin may cause errors in the reset delay
time.
Output Pin (OUT)
In a typical SY6370F application, the OUT outputs is
connected to a reset/enable input of the processor
(DSP, CPU, FPGA, ASIC, and so on) or connected to
the enable input of a voltage regulator.
The SY6370F provide open-drain outputs. Pull up
resistors must be used to hold these lines high when
OUT is asserted. By connecting the pull up resistors
to the proper voltage rails, OUT can be connected to
other devices at the correct interface voltage levels.
The outputs can be pulled up to 18 V independent of
the supply voltage (VCC). To ensure proper voltage
levels, some thought should be given to choosing the
correct pull up resistor values. The ability to sink
current is determined by the supply voltage; therefore,
if VCC = 5V and the desired output pull up is 18 V,
then to obtain a sink current of 1mA or less (as
mentioned in the Electrical Characteristics), the pull
up resistor value should be greater than 18kΩ. By
using wired-OR logic, any combination of OUT can
be merged into one logic signal.
Enable Function
The enable input allows an external logic signal from
other processors, logic circuits, and/or discrete
sensors to turn on or turn off the output. The
SY6370FDTC offer an active-high enable input
(ENABLE).Driving ENABLE high forces OUT to go
high. The 0.4V (maximum) low and 1.4V (minimum)
high allow ENABLE to be driven with a 1.5V or
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SY6370F
2. Input and output capacitors should be placed
closed to the IC and connected to ground plane to
reduce noise coupling.
greater system supply. Active high input. Driving EN
low immediately makes OUT go low. With VSENSE
already above VIT+, drive EN high to make OUT go
high after 0.2μs.
3. SENSE pin is a sensitive pin. Keep SENSE trace
far away from the trace or plane that has large dv/dt.
The divider resistor should be placed as close as
possible to the SENSE pin.
PCB Layout Guide
For best performance of the SY6370F, the following
guidelines must be strictly followed:
1. Place the VCC decoupling capacitor close to the
device.
EN VCC
REN
GND
GND
EN
VCC
CIN
GND
CT
CT
SENSE
OUT
OUT
RSENSE2
RSENSE1
RVP
VCC
Pullup
Voltage
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Figure4. PCB Layout Suggestion
AN_SY6370F Rev. 0.9
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All Rights Reserved.
SY6370F
DFN1.45×1-6 Package Outline Drawing
Bottom View
orp
Top View
Recommended PCB Layout
(only for reference)
Notes:
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Side View
All dimension in millimeter and exclude mold flash & metal burr.
AN_SY6370F Rev. 0.9
© 2020 Silergy Corp.
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All Rights Reserved.
SY6370F
Taping & Reel Specification
1. Taping orientation
Feeding direction
2. Carrier Tape & Reel specification for packages
Reel
Size
Tape width
(mm)
Pocket
pitch(mm)
Reel size
(Inch)
Trailer
length(mm)
Leader length
(mm)
Qty per
reel
DFN1.45×1
8
4
7"
400
160
3000
Sil
Package
types
3. Others: NA
AN_SY6370F Rev. 0.9
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All Rights Reserved.
SY6370F
IMPORTANT NOTICE
1. Right to make changes. Silergy and its subsidiaries (hereafter Silergy) reserve the right to change any information
published in this document, including but not limited to circuitry, specification and/or product design, manufacturing or
descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the
publication hereof. Buyers should obtain the latest relevant information before placing orders and should verify that such
information is current and complete. All semiconductor products are sold subject to Silergy’s standard terms and conditions of
sale.
2. Applications. Application examples that are described herein for any of these products are for illustrative purposes only.
Silergy makes no representation or warranty that such applications will be suitable for the specified use without further testing or
modification. Buyers are responsible for the design and operation of their applications and products using Silergy products.
Silergy or its subsidiaries assume no liability for any application assistance or designs of customer products. It is customer’s sole
responsibility to determine whether the Silergy product is suitable and fit for the customer’s applications and products planned.
To minimize the risks associated with customer’s products and applications, customer should provide adequate design and
operating safeguards. Customer represents and agrees that it has all the necessary expertise to create and implement safeguards
which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures
that might cause harm and take appropriate remedial actions. Silergy assumes no liability related to any default, damage, costs or
problem in the customer’s applications or products, or the application or use by customer’s third-party buyers. Customer will
fully indemnify Silergy, its subsidiaries, and their representatives against any damages arising out of the use of any Silergy
components in safety-critical applications. It is also buyers’ sole responsibility to warrant and guarantee that any intellectual
property rights of a third party are not infringed upon when integrating Silergy products into any application. Silergy assumes no
responsibility for any said applications or for any use of any circuitry other than circuitry entirely embodied in a Silergy product.
3. Limited warranty and liability. Information furnished by Silergy in this document is believed to be accurate and reliable.
However, Silergy makes no representation or warranty, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such information. In no event shall Silergy be liable for
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interruption, costs related to the removal or replacement of any products or rework charges, whether or not such damages are
based on tort or negligence, warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer
might incur for any reason whatsoever, Silergy’ aggregate and cumulative liability towards customer for the products described
herein shall be limited in accordance with the Standard Terms and Conditions of Sale of Silergy.
4. Suitability for use. Customer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory
and safety-related requirements concerning its products, and any use of Silergy components in its applications, notwithstanding
any applications-related information or support that may be provided by Silergy. Silergy products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where
failure or malfunction of an Silergy product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. Silergy assumes no liability for inclusion and/or use of Silergy products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own risk.
orp
.
5. Terms and conditions of commercial sale. Silergy products are sold subject to the standard terms and conditions of
commercial sale, as published at http://www.silergy.com/stdterms, unless otherwise agreed in a valid written individual
agreement specifically agreed to in writing by an authorized officer of Silergy. In case an individual agreement is concluded only
the terms and conditions of the respective agreement shall apply. Silergy hereby expressly objects to and denies the application
of any customer’s general terms and conditions with regard to the purchase of Silergy products by the customer.
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6. No offer to sell or license. Nothing in this document may be interpreted or construed as an offer to sell products that is
open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or
intellectual property rights. Silergy makes no representation or warranty that any license, either express or implied, is granted
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regarding third-party products or services does not constitute a license to use such products or services or a warranty or
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property of the third party, or a license from Silergy under the patents or other intellectual property of Silergy.
For more information, please visit: www.silergy.com
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AN_SY6370F Rev. 0.9
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