ES8327
FEATURES
Low Power Audio CODEC
System
•
•
•
•
Stereo DAC
High performance and low power multibit delta-sigma audio ADC and DAC
I2S/PCM/TDM master or slave serial
data port
256/384Fs, USB 12/24 MHz and other
non standard audio system clocks
I2C interface
•
•
•
•
•
•
•
Stereo DMIC
•
•
•
Support 2-ch digital microphone
24-bit, 8 to 96 kHz sampling frequency
110 dB signal to noise ratio, -100 dB
THD+N
APPLICATIONS
•
•
•
Mono ADC
•
•
•
•
•
•
24-bit, 8 to 96 kHz sampling frequency
100 dB signal to noise ratio, -85 dB
THD+N
Ground centered headphone driver
Dynamic range compression
Headset detection
OMTP and CTIA auto switch
Pop and click noise suppression
Notebook
Tablet
PC
ORDERING INFORMATION
24-bit, 8 to 96 kHz sampling frequency
102 dB signal to noise ratio, -90 dB
THD+N
Two pairs of analog input with
differential input option
Low noise pre-amplifier
Auto level control (ALC) and noise gate
Noise reduction filter
ES8327 -40°C ~ +105°C
QFN-32
1
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1.
2.
3.
4.
5.
6.
7.
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ES8327
BLOCK DIAGRAM ................................................................................................................... 6
PIN OUT AND DESCRIPTION ................................................................................................ 7
TYPICAL APPLICATION CIRCUIT.......................................................................................... 8
CLOCK MODES AND SAMPLING FREQUENCIES ............................................................... 9
MICRO-CONTROLLER CONFIGURATION INTERFACE ...................................................... 9
DIGITAL AUDIO INTERFACE................................................................................................. 11
ELECTRICAL CHARACTERISTICS ..................................................................................... 13
ABSOLUTE MAXIMUM RATINGS................................................................................................ 13
RECOMMENDED OPERATING CONDITIONS .............................................................................. 13
ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS ........................................ 13
DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS ........................................ 14
DC CHARACTERISTICS ................................................................................................................ 14
SERIAL AUDIO PORT SWITCHING SPECIFICATIONS ................................................................... 15
I2C SWITCHING SPECIFICATIONS (SLOW SPEED MODE/HIGH SPEED MODE) ........................... 16
8.
CONFIGURATION REGISTER DEFINITION ........................................................................ 17
REGISTER 0X00 -RESET, DEFAULT 00011111 ............................................................................. 17
REGISTER 0X01 -CLOCK MANAGER, DEFAULT 00000000 .......................................................... 17
REGISTER 0X02-CLOCK MANAGER, DEFAULT 00000000 ........................................................... 18
REGISTER 0X03-CLOCK MANAGER, DEFAULT 00000010 ........................................................... 18
REGISTER 0X04-CLOCK MANAGER, DEFAULT 0000 0000 .......................................................... 19
REGISTER 0X05-CLOCK MANAGER, DEFAULT 0000 0000 .......................................................... 19
REGISTER 0X06-CLOCK MANAGER, DEFAULT 0000 0000 .......................................................... 19
REGISTER 0X07-CLOCK MANAGER, DEFAULT 0010 1101 .......................................................... 19
REGISTER 0X08-CLOCK MANAGER, DEFAULT 0000 1010 .......................................................... 20
REGISTER 0X09-CLOCK MANAGER, DEFAULT 0000 1010 .......................................................... 20
REGISTER 0X0A-CLOCK MANAGER, DEFAULT 00011111 .......................................................... 21
REGISTER 0X0B-CLOCK MANAGER, DEFAULT 00011111........................................................... 21
REGISTER 0X0C-CLOCK MANAGER, DEFAULT 00011111 ........................................................... 21
REGISTER 0X0D-CLOCK MANAGER, DEFAULT 0000 0011 ......................................................... 22
REGISTER 0X0E-CLOCK MANAGER, DEFAULT 0000 0000 .......................................................... 22
REGISTER 0X0F-CLOCK MANAGER, DEFAULT 11111111 ........................................................... 22
REGISTER 0X10 -CLOCK MANAGER, DEFAULT 1110 0000 ......................................................... 22
REGISTER 0X11-CLOCK MANAGER, DEFAULT 1010 0000 .......................................................... 23
REGISTER 0X12-CLOCK MANAGER, DEFAULT 0100 0000 .......................................................... 24
REGISTER 0X13-SDP, DEFAULT 00000000 ................................................................................. 24
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REGISTER 0X14-SDP, DEFAULT 00000000 ................................................................................. 25
REGISTER 0X15-SDP, DEFAULT 00011111 ................................................................................. 25
REGISTER 0X16-ANALOG, DEFAULT 11111011 ......................................................................... 25
REGISTER 0X17-ANALOG,DEFAULT11111000 ........................................................................... 26
REGISTER 0X18-ANALOG, DEFAULT 00000000 ......................................................................... 26
REGISTER 0X19-ANALOG,DEFAULT 00000000 .......................................................................... 26
REGISTER 0X1A-ANALOG, DEFAULT 00000000 ......................................................................... 26
REGISTER 0X1B-ANALOG, DEFAULT 01000000 ......................................................................... 27
REGISTER 0X1C-ANALOG, DEFAULT 01111100 ......................................................................... 27
REGISTER 0X1D-ANALOG, DEFAULT 00001010 ......................................................................... 27
REGISTER 0X1E-ANALOG, DEFAULT 10001000.......................................................................... 27
REGISTER 0X1F-ANALOG, DEFAULT 10001000 .......................................................................... 28
REGISTER 0X20 -ANALOG, DEFAULT 10001000......................................................................... 29
REGISTER 0X21-ANALOG, DEFAULT 10001000 ......................................................................... 30
REGISTER 0X22-ANALOG, DEFAULT 00001100 ......................................................................... 30
REGISTER 0X23-ANALOG, DEFAULT 00000000 ......................................................................... 31
REGISTER 0X24-ANALOG, DEFAULT 00001111 ......................................................................... 31
REGISTER 0X25-ANALOG, DEFAULT 00010001 ......................................................................... 31
REGISTER 0X26-ANALOG, DEFAULT 00000000 ......................................................................... 32
REGISTER 0X27-ANALOG, DEFAULT 00000000 ......................................................................... 32
REGISTER 0X28-ANALOG, DEFAULT 10000111 ......................................................................... 33
REGISTER 0X29-ADC CONTROL, DEFAULT 00000000 ................................................................ 33
REGISTER 0X2A-ADC CONTROL, DEFAULT 00000000 ................................................................ 33
REGISTER 0X2B-ADC CONTROL, DEFAULT 00000000 ................................................................ 34
REGISTER 0X2C-ADC CONTROL, DEFAULT 10111111 ................................................................ 34
REGISTER 0X2D-ADC CONTROL, DEFAULT 1011 1111 ............................................................... 34
REGISTER 0X2E-ADC CONTROL, DEFAULT 00000000 ................................................................ 35
REGISTER 0X2F –NOT USED, DEFAULT 00000000 ..................................................................... 35
REGISTER 0X30 - NOT USED, DEFAULT 00000000 ..................................................................... 35
REGISTER 0X31- NOT USED, DEFAULT 00000000 ...................................................................... 35
REGISTER 0X32-ADC CONTROL, DEFAULT 00000000 ................................................................ 35
REGISTER 0X33-ADC CONTROL, DEFAULT 00000000 ................................................................ 36
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REGISTER 0X34-ADC CONTROL, DEFAULT 00101100 ................................................................ 36
REGISTER 0X35-ADC CONTROL, DEFAULT 00001100 ................................................................ 36
REGISTER 0X36-ADC CONTROL, DEFAULT 00000000 ................................................................ 36
REGISTER 0X37-ADC CONTROL, DEFAULT 00000000 ................................................................ 37
REGISTER 0X38-ADC CONTROL, DEFAULT 00000000 ................................................................ 37
REGISTER 0X39-ADC CONTROL, DEFAULT 00000000 ................................................................ 37
REGISTER 0X3A-ADC CONTROL, DEFAULT 00000000 ................................................................ 37
REGISTER 0X3B-ADC CONTROL, DEFAULT 00000000 ................................................................ 37
REGISTER 0X3C-ADC CONTROL, DEFAULT 00000000 ................................................................ 37
REGISTER 0X3D-ADC CONTROL, DEFAULT 00000000................................................................ 37
REGISTER 0X3E-ADC CONTROL, DEFAULT 00000000 ................................................................ 37
REGISTER 0X3F-ADC CONTROL, DEFAULT 00000000 ................................................................ 37
REGISTER 0X40 -ADC CONTROL, DEFAULT 00000000 ............................................................... 37
REGISTER 0X41-ADC CONTROL, DEFAULT 00000000 ................................................................ 37
REGISTER 0X42-ADC CONTROL, DEFAULT 00000000 ................................................................ 37
REGISTER 0X43-ADC CONTROL, DEFAULT 00000000 ................................................................ 38
REGISTER 0X44-ADC CONTROL, DEFAULT 00000000 ................................................................ 38
REGISTER 0X45-ADC CONTROL, DEFAULT 00000000 ................................................................ 38
REGISTER 0X46-ADC CONTROL, DEFAULT 00000000 ................................................................ 38
REGISTER 0X47-ADC CONTROL, DEFAULT 00000000 ................................................................ 38
REGISTER 0X48-ADC CONTROL, DEFAULT 00000000 ................................................................ 38
REGISTER 0X49-ADC CONTROL, DEFAULT 00000000 ................................................................ 38
REGISTER 0X4A-DAC CONTROL, DEFAULT 00000000 ................................................................ 38
REGISTER 0X4B-DAC CONTROL, DEFAULT 00000000 ................................................................ 39
REGISTER 0X4C-DAC CONTROL, DEFAULT 00000000 ................................................................ 39
REGISTER 0X4D-DAC CONTROL, DEFAULT 00001000................................................................ 39
REGISTER 0X4E-DAC CONTROL, DEFAULT 00100000 ................................................................ 39
REGISTER 0X4F-DAC CONTROL, DEFAULT 00010101 ................................................................ 40
REGISTER 0X50 -DAC CONTROL,DEFAULT10111111 ................................................................. 41
REGISTER 0X53-DAC CONTROL, DEFAULT 00000000 ................................................................ 41
REGISTER 0X54-DAC CONTROL, DEFAULT 00000000 ................................................................ 41
REGISTER 0X56-GPIO, DEFAULT 00000000 ............................................................................... 42
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REGISTER 0X57-GPIO, DEFAULT 01010100 ............................................................................... 42
REGISTER 0X58-GPIO, DEFAULT 00000000 ............................................................................... 43
REGISTER 0X59-GPIO, DEFAULT 01000000 ............................................................................... 43
REGISTER 0X5A-GPIO, DEFAULT 10010000 ............................................................................... 43
REGISTER 0X5B-N/A, DEFAULT 00000000 ................................................................................. 44
REGISTER 0X5C-GPIO, DEFAULT 00000000 ............................................................................... 44
REGISTER 0XF9-TEST MODE, DEFAULT 11111010 ..................................................................... 45
REGISTER 0XFD-CHIP ID, DEFAULT 10000011 ........................................................................... 45
REGISTER 0XFE-CHIP ID, DEFAULT 00100110 ............................................................................ 45
REGISTER 0XFF-CHIP ID, DEFAULT 00000000 ............................................................................ 45
9. PACKAGE (UNIT: MM) .......................................................................................................... 46
10.
CORPORATE INFORMATION .......................................................................................... 47
11.
IMPORTANT NOTICE AND DISCLAIMER........................................................................ 47
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1. BLOCK DIAGRAM
Headset
INTOUT
GMS0
GMS1
CDATA
CCLK
CE
MCLK
2
IC
Clock Mgr
Headset Detect/OMTP CTIA Auto Switch
MIC1P
PGA
MIC1N
Mono
ADC
ALC
EQ
I2S
PCM
TDM
Interface
MIC2P
MIC2N
LOUT
ROUT
HP Driver
Analog Reference
Power Supply
DVDD
PVDD
DGND
AVDD
AGND
CPVDD
CPGND
CPTOP
CPBOT
CPVSSP
Revision 2.0
DRC
ADCVREF
DACVREF
VMID
Mic Bias
Charge
Pump
Stereo
DAC
SDOUT
SCLK
LRCK
SDIN
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2. PIN OUT AND DESCRIPTION
MIC1N
MIC1P
MIC2N
MIC2P
SDINOUT1/DMIC_SCL
CE
CDATA
CCLK
25
26
27
28
29
30
31
32
MCLK/DMIC_SDA
DVDD
PVDD
DGND
SCLK
SDIN
LRCK
SDOUT
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ES8327
VMID
ADCVREF
AGND
AVDD
DACVREF
LOUT
ROUT
CPVSSP
16
15
14
13
12
11
10
9
CPBOT
GMS1
CPGND
GMS0
CPTOP
CPVDD
INTOUT
HEADSET
Pin Name
CCLK, CDATA, CE
MCLK/DMIC_SDA
SCLK
SDIN
LRCK
SDOUT
SDINOUT1/DMIC_SCL
MIC2P
MIC2N
MIC1P
MIC1N
HEADSET, INTOUT
GMS0, GMS1
LOUT, ROUT
PVDD
DVDD, DGND
AVDD, AGND
CPVDD, CPGND
CPTOP, CPBOT
CPVSSP
VMID
ADCVREF, DACVREF
Revision 2.0
Pin number
32, 31, 30
1
5
6
7
8
29
28
27
26
25
9, 10
13, 15
19, 18
3
2, 4
21, 22
11, 14
12, 16
17
24
23, 20
Input or Output
I, I/O, I
I
I/O
I
I/O
O
O
I
I
I/O
O
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Pin Description
I2C clock, data, address
Master clock or DMIC input
Serial data bit clock
DAC serial data input
Serial data left and right channel frame clock
ADC serial data output
SDOUT1 from SDIN (TDM) or DMIC bit clock
Analog mic 2 input P
Analog mic 2 input N
Analog mic 1 input P
Analog mic 1 input N
Headset detect and interrupt
OMTP and CTIA auto switch
DAC stereo analog output
Power supply for the digital input and output
Digital power supply
Analog power supply
Charge pump power supply
Charge pump capacitor top and bottom
Charge pump filtering capacitor connection
Filtering capacitor connection
Filtering capacitor connection
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3. TYPICAL APPLICATION CIRCUIT
AVDD(1.8V TO 3.3V)
DVDD(1.8V TO 3.3V)
1
FB6
2
C39
0.1uF
C38
0.1uF
AGND
DGND
ADCVREF
R29
220R
CPVDD(1.8V)
1
IOVDD
C41
0.1uF
R59
NC
FB4
R58
2K
C24
4.7uF
IOVDD(1.8V TO 3.3V)
2
AGND
1
C40
0.1uF
P
2
N
2K
R32
2K
21
11
AVDD
MIC2P
MIC2N
30
32
31
DGND
I2C_SCL
I2C_SDA
MIC1P
MIC1N
CE
CCLK
CDATA
LO UT
1
5
6
7
8
I2S MCLK
I2S SCLK
I2S DACDAT
I2S LRCK
I2S ADCDAT
29
I2S TDMO UT
ROUT
U11
MCLK
SCLK
SDIN
LRCK
SDOUT
ES8327
HEADSET
GMS0
GMS1
INTOUT
SDINOUT1
CPVSSP
28
27
C18
C19
1uF
1uF
26
25
C15
C16
1uF
1uF
R27
10K
AGND
19
18
9
13
15
10
R28
17
C25
1uF
12
C26
1uF
16
C17
4.7uF
R16
33R
R26
33R
220R
VSPK
C34
1uF
C35
1uF
2
DGND
DGND
AGND
INP
HEADSET_EVT_INTERRUPT
VDD
GND
INN
1
2
OUTP
SHUTDOWN
ADCVREF
FB7
J2
HeadSet
U14
R30
10K
AGND
1
5 L/TIP
4
4
3
R
6
6
2 GND
7
7
1
M
8
8
IOVDD
AGND
AGND
VMID
ADCVREF
DACVREF
CPBOT
R66
2K
IOVDD
24
AGND
CPGND
PAD
23
20
4
33
22
14
DGND
CPTOP
AGND
MICRO PHO NE
AGND
CPVDD
PVDD
R31
DVDD
IOVDD
R60
10K
2
3
DGND
P
N
SPEAKER
OUTN
Analog Audio PA
U15
C28
1uF
C27
1uF
C33
1uF
C36
1uF
C37
1uF
INP
VDD
GND
INN
1
2
OUTP
SHUTDOWN
AGND
AGND
P
N
OUTN
SPEAKER
Analog Audio PA
AGND
PA_SHUTDOWN
VSPK
IOVDD
GND
MCLK
SCLK
LRCK
DAT
VCC
U16
I2S MCLK
I2S SCLK
I2S LRCK
I2S TDMO UT
DVDD
OUTP
1
2
OUTN
Digital Audio PA
P
N
SPEAKER
AVDD
CPVDD
AGND
ES8327 PIN29 (SDINOUT1) can be used to connect digital audio PA with I2S interface.
IO Power Supply, 1.8V to 3.3V. Please refer to ES8327 Datasheet
Digital Power Supply, 1.8V to 3.3V. Please refer to ES8327 Datasheet
Analog Power Supply, 1.8V to 3.3V. Please refer to ES8327 Datasheet
Charge Pump Power Supply, must be 1.8V.
One 1.8V LDO is recommended for CPVDD power supply
Please refer to ES8327 Datasheet
pulled up to PVDD, I2C Chip Address = 0x19
CE
I2C Chip Address.
pulled down to GND, I2C Chip Address = 0x18
HEADSET_EVT_INTERRUPT
ADCVREF
Revision 2.0
An Interrupt Signal to Host SOC / CPU
ADCVREF can be used as Microphone Power Supply.
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4. CLOCK MODES AND SAMPLING FREQUENCIES
The device supports standard audio clocks (32Fs, 64Fs, 128Fs, 256Fs, 384Fs, 512Fs, etc), USB
clocks (12/24 MHz), and some common non standard audio clocks (16 MHz, 25 MHz, 26 MHz,
etc).
The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and
SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the
system clock with specific rates. In master mode, LRCK and SCLK are derived internally from
device master clock.
5. MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard I2C micro-controller configuration interface. External microcontroller can completely configure the device through writing to internal configuration
registers.
I2C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock
line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in
Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on
a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being
transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull
the CDATA low. The transfer rate of this interface can be up to 400 kbps.
A master controller initiates the transmission by sending a “start” signal, which is defined as a
high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address.
It is a seven-bit chip address followed by a RW bit. The chip address must be 0011 00x, where x
equals CE. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is
received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by
the RW bit. The master can terminate the communication by generating a “stop” signal, which is
defined as a low-to-high transition at CDATA while CCLK is high.
In I2C interface mode, the registers can be written and read. The formats of “write” and “read”
instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you
must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the
register.
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Table 1 Write Data to Register in I2C Interface Mode
start
Chip Address
0011 00 CE
R/W
0
ACK
Chip Addr
CDATA
Register Address
RAM
Write ACK
bit 1 to 7
Reg Addr
ACK
ACK
bit 1 to 8
Data to be written
DATA
Write Data
ACK
ACK
bit 1 to 8
CCLK
START
STOP
Figure 1a I2C Write Timing
Table 2 Read Data from Register in I2C Interface Mode
Start
Start
Chip Address
0011 00 CE
Chip Address
0011 00 CE
R/W
0
R/W
1
Chip Addr
Reg Addr
CDATA
bit 1 to 7
Write ACK
ACK
ACK
ACK
bit 1 to 8
Register Address
RAM
Data to be read
Data
Chip Addr
bit 1 to 7
Read ACK
ACK
NACK
Stop
Read Data NO ACK
bit 1 to 8
CCLK
START
START
STOP
Figure 1b I2C Read Timing
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6. DIGITAL AUDIO INTERFACE
The device provides many formats of serial audio data interface to the input of the DAC or
output from the ADC through LRCK, SCLK and SDIN or SDOUT pins. These formats are I2S, left
justified, DSP/PCM and TDM. DAC input SDIN is sampled by the device on the rising edge of SCLK.
ADC data is out at SDOUT on the falling edge of SCLK. The relationship of SDATA (SDIN/SDOUT),
SCLK and LRCK with these formats are shown through Figure 2a to Figure 2h.
SDIN 6-ch TDM data can directly output to 2-ch SDINOUT1, 2-ch SDINOUT2 and 2-ch SDINOUT3.
1 SCLK
1 SCLK
L Channel
LRCK
R Channel
SCLK
SDATA
MSB
LSB
LSB
MSB
Figure 2a I2S Serial Audio Data Format
LRCK
L Channel
R Channel
SCLK
SDATA
LSB
MSB
MSB
LSB
Figure 2b Left Justified Serial Audio Data Format
1 SCLK
LRCK
R Channel
L Channel
SCLK
SDATA
MSB
LSB MSB
LSB
Figure 2c DSP/PCM Mode A Serial Audio Data Format
LRCK
R Channel
L Channel
SCLK
SDATA
MSB
LSB MSB
LSB
Figure 2d DSP/PCM Mode B Serial Audio Data Format
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1 SCLK
ES8327
1 SCLK
Channel 3
Channel 1
LRCK
Channel 4
Channel 2
SCLK
SDATA
MSB
LSB
LSB MSB
MSB
LSB
LSB MSB
Figure 2e TDM I2S Serial Audio Data Format
LRCK
Channel 3
Channel 1
Channel 4
Channel 2
SCLK
SDATA
MSB
LSB
LSB MSB
MSB
LSB
LSB MSB
Figure 2f TDM Left Justified Serial Audio Data Format
1 SCLK
LRCK
Channel 4
Channel 3
Channel 2
Channel 1
SCLK
SDATA
MSB
LSB MSB
LSB MSB
LSB
LSB MSB
Figure 2g TDM DSP/PCM Mode A Serial Audio Data Format
LRCK
Channel 4
Channel 3
Channel 2
Channel 1
SCLK
SDATA
MSB
LSB MSB
LSB MSB
LSB MSB
LSB
Figure 2h TDM DSP/PCM Mode B Serial Audio Data Format
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7. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Continuous operation at or beyond these conditions may permanently damage the device.
PARAMETER
Analog Supply Voltage Level
Digital Supply Voltage Level
Analog Input Voltage Range
Digital Input Voltage Range
Operating Temperature Range
Storage Temperature
MIN
-0.3V
-0.3V
AGND-0.3V
DGND-0.3V
-40°C
-65°C
MAX
+3.6V
+3.6V
AVDD+0.3V
PVDD+0.3V
+105°C
+150°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
AVDD
1.7
1.8/3.3 3.6
V
CPVDD (Note 1)
1.6
1.8
2.0
V
DVDD (Note 2)
1.6
1.8/3.3 3.6
V
PVDD
1.6
1.8/3.3 3.6
V
Note 1: recommend an option to add a LDO in PCB for CPVDD, in case CPVDD supply is noisy.
Note 2: for 96 kHz sampling frequency, DVDD must be 3.3V (±10%).
ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS
Test conditions are as the following unless otherwise specify: AVDD=3.3V, DVDD=3.3V,
AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, MCLK/LRCK=256.
PARAMETER
ADC Performance
Signal to Noise ratio (A-weigh)
THD+N
Gain Error
Filter Frequency Response
Passband
Stopband
Passband Ripple
Stopband Attenuation
Analog Input
Full Scale Input Level (±: differential P/N)
Input Impedance
Revision 2.0
MIN
TYP
MAX
UNIT
97
-93
102
-90
104
-87
±5
dB
dB
%
0.4535
Fs
Fs
dB
dB
0
0.5465
±0.05
70
±AVDD/3.3
6
±Vrms
KΩ
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DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS
Test conditions are as the following unless otherwise specify: AVDD=3.3V, DVDD=3.3V,
AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, MCLK/LRCK=256.
PARAMETER
DAC Performance
Signal to Noise ratio (A-weigh)
THD+N
Gain Error
Filter Frequency Response
Passband
Stopband
Passband Ripple
Stopband Attenuation
Analog Output
Full Scale Output Level
MIN
TYP
MAX
UNIT
95
-88
100
-85
102
-82
±5
dB
dB
%
0.4535
Fs
Fs
dB
dB
0
0.5465
±0.05
53
AVDD/3.3
Vrms
DC CHARACTERISTICS
PARAMETER
MIN
TYP
MAX
UNIT
Normal Operation Mode
DVDD=1.8V, PVDD=1.8V, AVDD=3.3V
TBD
mW
DVDD=1.8V, PVDD=1.8V, AVDD=1.8V
Power Down Mode (Note 3)
DVDD=1.8V, PVDD=1.8V, AVDD=3.3V
0
uA
DVDD=1.8V, PVDD=1.8V, AVDD=1.8V
Digital Voltage Level
Input High-level Voltage
0.7*PVDD
V
Input Low-level Voltage
0.5
V
Output High-level Voltage
PVDD
V
Output Low-level Voltage
0
V
Note 3: recommend all power supply on, entering low power through control register setting,
then stopping input clock.
Revision 2.0
14
October 2021
Latest datasheet: www.everest-semi.com or info@everest-semi.com
Everest Semiconductor
Confidential
ES8327
SERIAL AUDIO PORT SWITCHING SPECIFICATIONS
PARAMETER
Symbol
MCLK frequency
MCLK duty cycle
LRCK frequency
LRCK duty cycle (Note 4)
SCLK frequency
SCLK pulse width low
TSLKL
SCLK Pulse width high
TSCLKH
SCLK falling to LRCK edge (master mode only)
TSLR
LRCK edge to SCLK rising (slave mode only)
TLSR
SCLK falling to SDOUT valid
VDDD=3.3V
T
VDDD=1.8V SDO
LRCK edge to SDOUT valid (Note 5)
VDDD=3.3V
T
VDDD=1.8V LDO
SDIN valid to SCLK rising setup time
TSDIS
SCLK rising to SDIN hold time
TSDIH
Note 4: one SCLK period of high time in DSP/PCM modes.
MIN
40
40
16
16
10
10
10
MAX
49.2
60
100
60
26
10
16
39
11
25
UNIT
MHz
%
KHz
%
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Note 5: only apply to MSB of Left Justified or DSP/PCM mode B.
LRCK
TSLR
TSCLKH
TLSR
TSCLKL
SCLK
TSDO
TLDO
SDOUT
TSDIS
TSDIH
SDIN
Figure 3 Serial Audio Port Timing
Revision 2.0
15
October 2021
Latest datasheet: www.everest-semi.com or info@everest-semi.com
Everest Semiconductor
Confidential
ES8327
I2C SWITCHING SPECIFICATIONS (SLOW SPEED MODE/HIGH SPEED MODE)
PARAMETER
CCLK Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
CDATA Hold Time from CCLK Falling
CDATA Setup time to CCLK Rising
Rise Time of CCLK
Fall Time CCLK
Symbol
FCCLK
TTWID
TTWSTH
TTWCL
TTWCH
TTWSTS
TTWDH
TTWDS
TTWR
TTWF
MIN
4.7/1.3
4.0/0.6
4.7/1.3
4.0/0.6
4.7/0.6
0.25/0.1
MAX
100/400
3.45/0.9
1.0/0.3
1.0/0.3
UNIT
KHz
us
us
us
us
us
us
us
us
us
Figure 4 I2C Timing
Revision 2.0
16
October 2021
Latest datasheet: www.everest-semi.com or info@everest-semi.com
Everest Semiconductor
Confidential
ES8327
8. CONFIGURATION REGISTER DEFINITION
REGISTER 0X00 -RESET, DEFAULT 00011111
Bit Name
CSM_ON
Bit
7
MSC
6
SEQ_DIS
5
RST_DIG
4
RST_CMG
3
RST_MST
2
RST_ADCDIG
1
RST_DACDIG
0
Description
Chip Current State Machine ON/OFF control
0 - CSM power down(default)
1 - CSM power up
Master/Slave select for SDP
0 - Slave mode(default)
1 - Master mode
Power up sequence enable control
0 - Power up sequence enable(default)
1 - Power up sequence disable
Digital circuits reset (except control port)
0 - Not reset
1 - Reset(default)
Clock manager circuit reset
0 - Not reset
1 - Reset(default)
Master circuit reset
0 - Not reset
1 - Reset(default)
ADC digital circuit reset
0 - Not reset
1 - Reset(default)
DAC digital circuit reset
0 - Not reset
1 - Reset(default)
REGISTER 0X01 -CLOCK MANAGER, DEFAULT 00000000
Bit Name
CPCLK_ON
Bit
6
MCLK_ON
5
BCLK_ON
4
CLK1_ON
3
CLK3_ON
2
CLK8_ON
1
CLK9_ON
0
Revision 2.0
Description
Charge Pump clock CPCLK control
0 - CPCLK off(default)
1 - CPCLK on
MCLK in ON/OFF control
0 - MCLK off (default)
1 - MCLK on
BCLK in ON/OFF control
0 - BCLK off (default)
1 - BCLK on
clk1 ON/OFF control
0 - clk1 off (default)
1 - clk1 on
clk3 ON/OFF control
0 - clk3 off (default)
1 - clk3 on
clk8 ON/OFF control
0 - clk8 off (default)
1 - clk8 on
clk9 ON/OFF control
17
October 2021
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ES8327
0 - clk9 off (default)
1 - clk9 on
REGISTER 0X02-CLOCK MANAGER, DEFAULT 00000000
Bit Name
MSTCLK_SEL
Bit
7:6
DMIC_SCL_SEL
4
MAINCLK_SEL
3
BITCLK_SEL
2
MAINCLK_INV
1
BITCLK_INV
0
Description
Master BCLK/LRCK divider source clock selection
0 - from main_clk(main_clk refer to MAINCLK_SEL)(default)
1 - from adc_cfclk(adc_cfclk refer to ADC_CFCLK_SEL)
2 - from adc_mclk(adc_mclk refer to ADC_MCLK_SEL)
3 - from dac_mclk (dac_mclk refer to DAC_MCLK_SEL)
DMIC clock select
0 - from ADC OSR clock，ES8327 provides DMIC_SCL to DMIC. (default)
1 - from MCLK in, system provides DMIC clock from DMIC_SCL to ES8327, and ES8327 synchronize
with DMIC_SCL as ADC OSR clock. “adc_mclk” should be 4 times frequency of DMIC_SCL.
Internalclock “main_clk”select
0 - from MCLK PAD(default)
1 - from BCLK PAD
Slave bit clock “bit_clk”select
0 - from BCLK PAD(default)
1 - from MCLK PAD
Main clock“main_clk”invert
0 - normal(default)
1 - invert
Bit clock “bit_clk”invert
0 - normal(default)
1 - invert
REGISTER 0X03-CLOCK MANAGER, DEFAULT 00000010
Bit Name
RATIO_RESAMPLE
Bit
6:4
INTCLK_SEL
3:2
OSC_EN
1:0
Revision 2.0
Description
Clock cycles justify for ratio sync.
0 -no sync（default）
1 - 1/512，sync 1 cycle per 512 cycles for adc_ratio
