3-Axis Single Chip Magnetic Sensor
QMC5883P
The QMC5883P is a three-axis magnetic sensor, which integrates magnetic
sensors and signal condition ASIC into one silicon chip. This Land Grid Array package
(LGA) is targeted for applications such as e-compass, map rotation, gaming and
personal navigation in mobile and wearable devices.
The QMC5883P is based on state-of-the-art, high resolution, magneto-resistive
technology. Along with the custom-designed 16-bit ADC ASIC, it offers the
advantages of low noise, high accuracy, low power consumption, offset cancellation
and temperature compensations. QMC5883P enables 1°to 2°compass heading
accuracy. The I²C serial bus allows for easy interface.
The QMC5883P is in a 3.0x3.0x0.9mm3 surface mount 16-pin LGA package.
FEATURES
BENEFIT
3-Axis Magneto-Resistive Sensors in a 3.0x3.0x0.9
Small Size for Highly Integrated Products. Signals Have
Been Digitized and Calibrated.
16 Bit ADC With Low Noise AMR Sensors Achieves
Enables 1°To 2°Degree Compass Heading Accuracy,
Allows for Pedestrian Navigation and LBS Applications
Wide Magnetic Field Range (±30 Gauss)
Maximizes Sensor’s Full Dynamic Range and Resolution
Temperature Compensated Data Output
Automatically Maintains Sensor’s Sensitivity Under Wide
Operating Temperature Range
I2C Interface with Standard and Fast Modes
High-Speed Interfaces for Fast Data Communications.
Maximum 1.5KHz Data Output Rate
Built-In Self-Test
Enables Low-Cost Functionality Test After Assembly in
Production
Wide Range Operation Voltage (2.5V to 3.6V) and
Compatible with Battery Powered Applications
mm3 LGA, Guaranteed to Operate Over an Extended
Temperature Range of -40 °C to +85 °C.
2 milli-Gauss Field Resolution
Low Power Consumption (35A)
Lead Free Package Construction
RoHS Compliance
Software and Algorithm Support Available
Compassing Heading, Hard Iron, Soft Iron, and Auto
Calibration Libraries Available
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
2 / 18
矽睿
Document #: 13-52-19 Title: QMC5883P Datasheet
Rev: A
CONTENTS
CONTENTS....................................................................................................................................................................................... 3
1
INTERNAL SCHEMATIC DIAGRAM ................................................................................................................................... 4
1.1
Internal Schematic Diagram ..................................................................................................................................... 4
2
SPECIFICATIONS AND I/O CHARACTERISTICS .............................................................................................................. 5
2.1
Product Specifications .............................................................................................................................................. 5
2.2
Absolute Maximum Ratings ..................................................................................................................................... 6
2.3
I/O Characteristics .................................................................................................................................................... 6
3
PACKAGE PIN CONFIGURATIONS ..................................................................................................................................... 6
3.1
Package 3-D View .................................................................................................................................................... 6
3.2
Package Outlines ...................................................................................................................................................... 7
4
EXTERNAL CONNECTION ................................................................................................................................................... 8
4.1
Recommended External Connection ........................................................................................................................ 8
4.2
Mounting Considerations ......................................................................................................................................... 8
4.3
Layout Considerations .............................................................................................................................................. 9
5
BASIC DEVICE OPERATION ................................................................................................................................................ 9
5.1
Anisotropic Magneto-Resistive Sensors ................................................................................................................... 9
5.2
Power Management ................................................................................................................................................ 10
5.3
Power On/Off Time ................................................................................................................................................ 10
5.4
Communication Bus Interface I2C and Its Addresses ............................................................................................. 11
5.5
Internal Clock ......................................................................................................................................................... 11
5.6
Temperature Compensation .................................................................................................................................... 11
6
MODES OF OPERATION ..................................................................................................................................................... 11
6.1
Modes Transition .................................................................................................................................................... 11
6.2
Description of Modes ............................................................................................................................................. 11
7
APPLICATION EXAMPLES ................................................................................................................................................. 12
7.1
Normal Mode Setup Example ................................................................................................................................ 12
7.2
Continuous Mode Setup Example .......................................................................................................................... 12
7.3
Self-test Example.................................................................................................................................................... 12
7.4
Suspend Mode Example ......................................................................................................................................... 12
7.5
Measurement Example ........................................................................................................................................... 12
7.6
Soft Reset Example ................................................................................................................................................ 12
8
I2C COMMUNICATION PROTOCOL .................................................................................................................................. 13
8.1
I2C Timings ............................................................................................................................................................ 13
8.2
I2C R/W Operation ................................................................................................................................................. 14
9
REGISTERS ........................................................................................................................................................................... 15
9.1
Register Map .......................................................................................................................................................... 15
9.2
Register Definition ................................................................................................................................................. 15
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
3 / 18
矽睿
Document #: 13-52-19 Title: QMC5883P Datasheet
1
INTERNAL SCHEMATIC DIAGRAM
1.1
Internal Schematic Diagram
AMR
bridge
Rev: A
QMC5883P
X
MUX
PGA
Y
Z
ADC
Selftest
Reference
POR
Set-reset
Driver
CLKGEN
NVM
C1
Signal
conditioning
Register
I2C
VDD
GND
SCK
SDA
Figure 1. Block Diagram
Table 1. Block Function
Block
AMR bridge
MUX
PGA
ADC
Signal conditioning
I2C
NVM
Register
Self test
Set-reset Driver
Reference
CLKGEN.
POR
Function
3-axis magnetic sensor
Multiplexer for sensor channels
Programmable gain amplifier for sensor signals
Analog-to-Digital converter
Digital blocks for magnetic signal calibration and compensations
Interface logic data I/O
Non-volatile memory
Internal register
Internal driver to generate self-test stimulus
Internal driver to initialize magnetic sensor
Voltage/current reference for internal biasing
Internal oscillator for internal operation
Power on reset
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
4 / 18
2
SPECIFICATIONS AND I/O CHARACTERISTICS
2.1
Product Specifications
Table 2. Specifications (Tested and specified at 25°C except stated otherwise.)
Parameter
Conditions
Min
Typ
Max
Supply Voltage
VDD
2.5
3.6
Suspend Mode
Total Current on VDD
22
Current
ODR=10Hz
35/78
Low power
ODR=50Hz
85/310
Normal Mode
and high
Current [1]
ODR=100Hz
150/600
power mode
ODR=200Hz
280/1180
Continuous Mode
Maximum ODR: 1500Hz
2200
Current
Sensor Field
Full Scale
-30
+30
Range
Field Range = ±30G
1000
Sensitivity
[2]
Linearity
Hysteresis
Offset
Sensitivity
Tempco
Digital Resolution
Field Resolution
X-Y-Z
Orthogonality
Operating
Temperature
ESD
Unit
V
μA
uA
uA
Gauss
LSB/G
Field Range = ±12G
2500
LSB/G
Field Range = ±8G
3750
LSB/G
Field Range = ±2G
Field Range = ±30G
Happlied= ±15G
3 sweeps across ±30G
15000
LSB/G
Ta = -40°C~85°C
±0.05
0.03
±10
Field Range = ±30G
Standard
deviation
%FS
mG
%/°C
1.0
X/Y axis
2
Z axis
3
mGauss
mGauss
Sensitivity Directions
90±1
-40
HBM
CDM
%FS
0.5
4000
1000
Degree
85
°C
V
Note [1]: The Normal Mode Current differs at different OSR1 setting. The value of low power mode is measured at
OSR1=1 setting， and the value of high power mode is measured at OSR1=8.
Note [2]: Sensitivity is calibrated at zero field; it is slightly decreased at high fields.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
5 / 18
矽睿
2.2
Document #: 13-52-19 Title: QMC5883P Datasheet
Rev: A
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings (Tested at 25°C except stated otherwise.)
Parameter
MIN.
MAX.
Units
VDD
-0.3
5.4
V
Storage Temperature
-40
125
°C
Exposed to Magnetic Field (all directions)
50000
Gauss
Reflow Classification
MSL 1, 260 C Peak Temperature
2.3
I/O Characteristics
Table 4. I/O Characteristics（VDDIO=3.3V）
Symbol Parameter(Units)
VIH
High Level Input Voltage(V)
VIL
Low Level Input Voltage(V)
VHYS
Hysteresis of Schmitt Trigger Input(V)
IIL
Input Leakage, ALL Inputs(uA)
VOH
High Level output Voltage(V)
VOL
Low Level output Voltage(V)
3
PACKAGE PIN CONFIGURATIONS
3.1
Package 3-D View
Minimum
0.7*VDDIO
Typical
Maximum
0.3*VDDIO
0.1
-10
0.8*VDDIO
10
0.2*VDDIO
Arrow indicates direction of magnetic field that generates a positive output reading in normal measurement
configuration.
Figure 2. Package 3-D View
Figure 3. Package Top View
Table 5. Pin Configurations
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
6 / 18
PIN
No.
1
2
3~8
9
10
11
12~15
16
PIN
NAME
SCK
VDD
NC
GND
C1
GND
NC
SDA
3.2
Package Outlines
3.2.1
Package Type
I/O
TYPE
Function
I
CMOS
Power
NC
VSS
CMOS
VSS
NC
CMOS
I2C clock
Supply Power
Not connected
Ground
Reservoir capacitor connection
Ground
Not connected
I2C data
I/O
LGA 16-pin
3.2.2
Package Size:
3.0mm (Length)*3.0mm (Width)*0.9mm (Height)
Figure 4. Package Size
3.2.3
Marking:
H: supplier code; P:Fixed code, to denote QMC5883P
3rd line text: mass production trace-code
●= Pin1 Identifier
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
7 / 18
矽睿
Document #: 13-52-19 Title: QMC5883P Datasheet
Rev: A
Figure 5. Chip Marking
4
EXTERNAL CONNECTION
4.1
Recommended External Connection
Figure 6. External Connection
Note: R1/R2 selection guide: 2.7Kohm for a short I2C bus length (less than 10 cm), and 4.7Kohm for a bus length less
than 5 cm.
4.2
Mounting Considerations
The following is the recommend printed circuit board (PCB) footprint for the QMC5883P. Due to the fine pitch of
the pads, the footprint should be properly centered in the PCB.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
8 / 18
Figure 7. QMC5883P PCB footprint
4.3
Layout Considerations
Besides keeping all components that may contain ferrous materials (nickel, etc.) away from the sensor on both
sides of the PCB, it is also recommended that there is no conducting copper line under/near the sensor in any of
the PCB layers.
4.3.1
Solder Paste
A 4-mil stencil and 100% paste coverage is recommended for the electrical contact pads.
4.3.2
Reflow Assembly
This device is classified as MSL 3 with 260C peak reflow temperature. As specified by JEDEC, parts with an
MSL 3 rating require baking prior to soldering, if the part is not kept in a continuously dry(>10% RH) enviroment
before assembly. Reference IPC/JEDEC standard J-STD-033 for additional information.
No special reflow profile is required for QMC5883P, which is compatible with lead eutectic and lead-free solder
paste reflow profiles. QST recommends adopting solder paste manufacturer’s guidelines. Hand soldering is not
recommended.
4.3.3
External Capacitors
The external capacitors C1 should be ceramic type with low ESR characteristics. The exact ESR value is not
critical, but values less than 200 milli-ohms are recommended. Reservoir capacitor C1 is nominally 4.7 µF in
capacitance. Low ESR characteristics may not be in many small SMT ceramic capacitors (0402), so be prepared
to up-size the capacitors to gain low ESR characteristics.
5
BASIC DEVICE OPERATION
5.1
Anisotropic Magneto-Resistive Sensors
The QMC5883P magneto-resistive sensor circuit consists of tri-axial sensors and application specific support
circuits to measure magnetic fields. With a DC power supply is applied to the sensor two terminals, the sensor
converts any incident magnetic field in the sensitive axis directions to a differential voltage output.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
9 / 18
矽睿
Document #: 13-52-19 Title: QMC5883P Datasheet
Rev: A
The device has an offset cancellation function to eliminate sensor and ASIC offsets. It also applies a self-aligned
magnetic field to restore magnetic state before each measurement to ensure high accuracy. Because of these
features, the QMC5883P doesn’t need to calibrate every time in most of application situations. It may need to be
calibrated once in a new system or a system changes a new battery.
5.2
Power Management
There are only one power supply pins to the device. VDD provides power for all the internal analog and digital
functional blocks and I/O.
When the device is powered on, all registers are reset by POR (Power-On-Reset), then the device transits to the
suspend mode and waits for further commands.
Table 6 provides references for two power states.
Table 6: Power States
Power State
1
2
5.3
VDD
0V
2.5V~3.6V
Power State description
Device Off, No Power Consumption
Device On, Enters Suspend Mode after POR, waiting
for further commands
Power On/Off Time
After the device is powered on, some time periods are required for the device fully functional. The external power
supply requires a time period for voltage to ramp up (PSUP), it is typically 50 milli-second. However, it isn’t
controlled by the device. The Power-On-Reset time period (PORT) includes time to reset all the logics, load
values in NVM to proper registers, enter the standby mode and get ready for analogy measurements. The power
on/off time related to the device is in Table 7.
Table 7. Time Required for Power On/Off
Parameter
Symbol Condition
POR
PORT
Time Period After VDD at
Completion
Operating Voltage to Ready for
Time
I2C Command
Power off
SDV
Voltage that Device
Voltage
Considered to be Power
Down.
Power on
PINT
Time Period Required for
Interval
Voltage Lower Than SDV to
Enable Next POR
Min.
Typ.
100
Max.
250
Unit
uS
0.2
V
uS
Figure 8. Power On/Off Timing
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
10 / 18
5.4
Communication Bus Interface I2C and Its Addresses
This device will be connected to a serial interface bus as a slave device under the control of a master device,
such as the processor. Control of this device is carried out via I²C.
This device is compliant with I²C Bus Specification. As an I²C compatible device, this device has a 7-bit serial
address and supports I²C protocols. This device supports standard and fast speed modes, 100kHz and 400kHz,
respectively. External pull-up resistors are required to support all these modes.
The default I2C address for QMC5883P is 2CH.
If more I2C address options are required, please contact factory.
5.5
Internal Clock
The device has an internal clock for internal digital logic functions and timing management. This clock is not
available to external usage.
5.6
Temperature Compensation
The Device has built-in Temperature compensation function. The compensated magnetic sensor data is placed in
the Output Data Registers automatically.
6
MODES OF OPERATION
6.1
Modes Transition
The device has three different modes, controlled by register (0x0A), mode bits Mode. The main purpose of
these modes is for power management. The modes can be transited from one to another, as shown below,
through I2C commands of changing mode bits. The default mode is Suspend Mode.
Figure 9. Modes Transition
6.2
Description of Modes
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
11 / 18
矽睿
Document #: 13-52-19 Title: QMC5883P Datasheet
Rev: A
6.2.1
Normal Mode
During the Normal mode (MODE bits= 2’b01), the magnetic sensor continuously makes measurements and
places measured data in data output registers. The field range register is controlled by RNG in register 0BH
and data output rate is controlled by ODR in register 0AH. They should be set up properly for your
applications in the normal mode.
6.2.2
Single Mode
During the Single Mode (MODE bits=2’b10), the whole chip runs only once and enter in the suspend mode after 1
measurement is finished.
6.2.3
Continuous Mode
During the Continuous Mode (MODE bits=2’b11), the whole chip runs all the time without sleep time, so the
maximum ODR can be got at this mode. The self-test function can only be enabled in Continuous Mode and
enters in Suspend Mode after the data is updated.
6.2.4
Suspend Mode
Suspend mode is the default magnetometer state upon POR and soft reset. Only few function blocks are
activated in this mode which keeps power consumption as low as possible. In this state, register values are hold
on by a lower power LDO, I2C interface is active and all register read and write are allowed. There is no
magnetometer measurement in this Mode.
7
APPLICATION EXAMPLES
7.1
Normal Mode Setup Example
Write Register 29H by 0x06 (Define the sign for X Y and Z axis)
Write Register 0BH by 0x08 (Define Set/Reset mode, with Set/Reset On, Field Range 8Guass)
Write Register 0AH by 0xCD (set normal mode, set ODR=200Hz)
7.2
Continuous Mode Setup Example
Write Register 29H by 0x06 (Define the sign for X Y and Z axis)
Write Register 0BH by 0x08 (Define Set/Reset mode, with Set/Reset On, Field Range 8Guass)
Write Register 0AH by 0xC3 (set continuous mode)
7.3
Self-test Example
7.4
Write Register 29H by 0x06 (Define the sign for X Y and Z axis)
Write Register 0AH by 0x03 (set continuous mode)
Check status register 09H[0] ,”1” means ready
Read data Register 01H ~ 06H, recording as datax1/datay1/dataz1
Write Register 0BH by 0x40(enter self-test function)
Waiting 5 millisecond until measurement ends
Read data Register 01H ~ 06H, recording as datax2/datay2/dataz2
Calculate the delta (datax1-datax2), (datay2-datay1), (dataz2-dataz1)
Suspend Mode Example
Write Register 0AH by 0x00
7.5
Measurement Example
Check status register 09H[0] ,”1” means ready
Read data register 01H ~ 06H
7.6
Soft Reset Example
Write Register 0BH by 0x80
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
12 / 18
8
I2C COMMUNICATION PROTOCOL
8.1
I2C Timings
Below table and graph describe the I2C communication protocol times
Table 8. I2C Timings
Symbol Parameter
Conditions
Standard-mode
Min
fSCL
tHD;STA
SCL clock frequency
hold time (repeated) START
condition
tLOW
tHIGH
tSU;STA
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for a repeated START
condition
data hold time
data set-up time
rise time of both SDA and SCL
signals
fall time of both SDA and SCL
signals
set-up time for STOP condition
bus free time between a STOP and
START condition
capacitive load for each bus line
data valid time
data valid acknowledge time
tHD;DAT
tSU;DAT
tr
tf
tSU;STO
tBUF
Cb
tVD;DAT
tVD;ACK
After this period, the
first
clock pulse is
generated.
0
4.0
Max
100
Fast-mode
Min
0
0.6
Unit
Max
400
kHz
uS
4.7
4.0
4.7
1.3
0.6
0.6
uS
uS
uS
0
250
0
100
300
300
uS
nS
nS
300
300
nS
4.0
4.7
0.6
1.3
200
0.8
0.8
uS
uS
200
0.8
0.8
Figure 10. I2C Timing Diagram
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
13 / 18
pF
uS
uS
矽睿
Document #: 13-52-19 Title: QMC5883P Datasheet
8.2
I2C R/W Operation
8.2.1
Abbreviation
Rev: A
Table 9. Abbreviation
SACK
Acknowledged by slave
MACK
Acknowledged by master
NACK
Not acknowledged by master
RW
Read/Write
8.2.2
Start/Stop/Ack
START: Data transmission begins with a high to transition on SDA while SCL is held high. Once I 2C transmission
starts, the bus is considered busy.
STOP: STOP condition is a low to high transition on SDA line while SCL is held high.
ACK: Each byte of data transferred must be acknowledged. The transmitter must release the SDA line during the
acknowledge pulse while the receiver must then pull the SDA line low so that it remains stable low during the high
period of the acknowledge clock cycle.
NACK: If the receiver doesn’t pull down the SDA line during the high period of the acknowledge clock cycle, it’s
recognized as NACK by the transmitter.
8.2.3
I2C Write
I2C write sequence begins with start condition generated by master followed by 7 bits slave address and a write
bit (R/W=0). The slave sends an acknowledge bit (ACK=0) and releases the bus. The master sends the one-byte
register address. The slave again acknowledges the transmission and waits for 8 bits data which shall be written
to the specified register address. After the slave acknowledges the data byte, the master generates a stop signal
and terminates the writing protocol.
STOP
Data
(0x03)
0 0 0 0 0 0 1 1
SACK
SACK
8.2.4
SACK
START
Table 10. I2C Write for QMC5883P
Slave Address
R
Register Address
W
(0x0A)
0 1 0 1 1 0 0 0
0 0 0 0 1 0 1 0
I2C Read
I2C read sequence consists of a one-byte I2C write phase followed by the I2C read phase. A start condition must
be generated between two phases. The I2C write phase addresses the slave and sends the register address to be
read. After slave acknowledges the transmission, the master generates again a start condition and sends the
slave address together with a read bit (R/W=1). Then master releases the bus and waits for the data bytes to be
read out from slave. After each data byte, the master has to generate an acknowledge bit (ACK = 0) to enable
further data transfer. A NACK from the master stops the data being transferred from the slave. The slave releases
the bus so that the master can generate a STOP condition and terminate the transmission.
Slave Address
STOP
Data
(0x80)
1 0 0 0 0 0 0 0
NACK
0 1 0 1 1 0 0 1
SACK
START
R
W
0 1 0 1 1 0 0 1
SACK
SACK
START
Table 12. I2C Read for QMC5883P
Slave Address
R
Register Address
W
(0x00)
0 1 0 1 1 0 0 0
0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
14 / 18
9
REGISTERS
9.1
Register Map
The table below provides a list of the 8-bit registers embedded in the device and their respective function and
addresses
Table 14. Register Map
Addr.
7
00H
01H
02H
03H
04H
05H
06H
09H
0AH
0BH
CHIPID[7:0]
Data Output X LSB Register XOUT[7:0]
Data Output X MSB Register XOUT[15:8]
Data Output Y LSB Register YOUT[7:0]
Data Output Y MSB Register YOUT[15:8]
Data Output Z LSB Register ZOUT[7:0]
Data Output Z MSB Register ZOUT[15:8]
RFU
OSR2
OSR1
ODR
SOFT_ SELF_
RFU
RNG
RST
TEST
6
5
4
3
2
9.2
Register Definition
9.2.1
Output Data Register
Register 00H stores the chip ID. The default value is 80H.
1
0
Access
OVFL DRDY
MODE
SET/RESET
MODE
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Read/Write
Read/Write
Registers 01H ~ 06H store the measurement data from each axis magnetic sensor in each working mode. In the
normal mode, the output data is refreshed periodically based on the data update rate ODR setup in control
registers 0AH. The data stays the same, regardless of reading status through I 2C, until new data replaces them.
Each axis has 16-bit data width in 2’s complement, i.e., MSB of 02H/04H/06H indicates the sign of each axis. The
output data of each channel saturates at -32768 and 32767.
Table 15.
Addr.
00H
01H
02H
03H
04H
05H
06H
9.2.2
Output Data Register
7
6
5
CHIPID[7:0]
Data Output X LSB Register
Data Output X MSB Register
Data Output Y LSB Register
Data Output Y MSB Register
Data Output Z LSB Register
Data Output Z MSB Register
4
3
2
1
0
XOUT[7:0]
XOUT[15:8]
YOUT[7:0]
YOUT[15:8]
ZOUT[7:0]
ZOUT[15:8]
Status Register
There is one status register located in address 09H.
Register 09H has two bits indicating for status flags, the rest are reserved for factory use. The status registers are
read only bits.
Table 16. Status Register 1
Addr.
7
6
5
09H
4
3
2
1
OVFL
0
DRDY
Data Ready Register (DRDY), it is set when all three-axis data is ready and loaded to the output data registers in
each mode. It is reset to “0” by reading the status register through I2C commands
DRDY: “0”: no new data, “1”: new data is ready
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
15 / 18
矽睿
Document #: 13-52-19 Title: QMC5883P Datasheet
Rev: A
OVFL bit set high when either axis code output exceeds the range of [-30000,30000] LSB and reset to “0” after
this bit is read.
OVFL: “0”: no data overflow occurs, “1”: data overflow occurs.
9.2.3
Control Registers
Two 8-bits registers are used to control the device configurations.
Control register 1 is located in address 0AH, it sets the operational modes (MODE) and over sampling rate (OSR).
Control register 2 is located in address 0BH. It controls soft reset, self-test and set/reset mode.
Two bits of MODE registers can transfer mode of operations in the device, the four modes are Suspend Mode,
Normal mode, Single Mode and Continuous Mode. The default mode after Power-On-Reset (POR) is Suspend
Mode. Suspend Mode should be added in the middle of mode shifting between Continuous Mode、Single Mode
and Normal Mode.
The Output data rate is controlled by ODR registers. Four data update frequencies can be selected: 10Hz, 50Hz,
100Hz or 200Hz.
Over sample Rate (OSR1) registers are used to control bandwidth of an internal digital filter. Larger OSR value
leads to smaller filter bandwidth, less in-band noise and higher power consumption. It could be used to reach a
good balance between noise and power. Four over sample ratios can be selected, 8,4,2 or 1.
Another filter is added for better noise performance; the depth can be adjusted through OSR2.
Table 17. Control Register 1
Addr
7
6
0AH
OSR2
5
4
OSR1
Reg.
Mode
Definition
Mode Control
00
Suspend
ODR
Output Data
Rate
Over
sample
Ratio1
Down
sampling
rate
OSR1
OSR2
3
2
ODR
1
0
MODE
10
Single
10Hz
01
Normal
Mode
50Hz
100Hz
11
Continuous
Mode
200Hz
8
4
2
1
1
2
4
8
Set/Reset Mode can be control by the register SET/RESET MODE. There are 3 modes for selection：SET AND
RESET ON， SET ONLY ON and SET AND RESET OFF. In SET ONLY ON or SET AND RESET OFF mode, the
offset is not renewed during measuring.
Field ranges of the magnetic sensor can be selected through the register RNG. The full-scale range is determined
by the application environments. The lowest field range has the highest sensitivity, therefore, higher resolution.
Self-test function is added for verification of the signal-chain. When the function is enabled through the bit
SELF_TEST, an inner-built current is generated and an additional signal is added to the sensor, generating a
difference in the 3 axis’ value. User should record the value before and after the self-test and compare with
threshold value.
Soft Reset can be done by changing the register SOFT_RST. Soft reset can be invoked at any time of any mode.
Table 18. Control Register 2
Addr.
7
6
0BH
SOFT_RST SELF_TEST
Reg.
Definition
5
-
00
4
-
3
RNG
01
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
2
10
1
0
SET/RESET
MODE
11
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SET/RESET
MODE
RNG
SELF_TEST
SOFT_RST
Set and reset mode
ctrl
Full Range
Self_test
Soft reset
Set and reset
Set only on
Set and reset
Set and reset
on
off
off
30Guass
12Guass
8Guass
2Guass
1: self_test enable, auto clear after the data is updated
1：Soft reset, restore default value of all registers，0: no reset
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
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矽睿
Document #: 13-52-19 Title: QMC5883P Datasheet
Rev: A
ORDERING INFORMATION
Ordering Number
Operating
Temperature
Package
Packaging
QMC5883P-TR
-40°C ~ 85°C
LGA-16
Tape and Reel: 3k pieces/reel
FIND OUT MORE
For more information on QST’s Magnetic Sensors contact us at 86-21-69517300.
The application circuits herein constitute typical usage and interface of QST product. QST does not provide warranty or assume
liability of customer-designed circuits derived from this description or depiction.
QST reserves the right to make changes to improve reliability, function or design. QST does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of
others.
U.S. Patents 4,441,072, 4,533,872, 4,569,742, 4,681,812, 4,847,584 and 6,529,114 apply to the technology described.
China Patents 201210563667.3, 201210563956.3, 201210563952.5, 201210563687.0, 201310403912.9, 201410027189.3,
201410027240.0, 201410027085.2 and 201410085278.3 apply to the technology described.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
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