ME2N7002DKW-G

⚫ ME2N7002DKW-G Dual N - Channel 60V (D-S) MOSFET, ESD Protection Protected GENERAL DESCRIPTION FEATURES The ME2N7002DKW-G is the Dual N-Channel logic enhancement ● RDS(ON)≦3Ω@VGS=10V mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management and other battery powered circuits , and low in-line power loss are needed in a very small outline surface mount package. ● RDS(ON)≦4Ω@VGS=4.5V ● RDS(ON)≦4.5Ω@VGS=3V ● ESD Protection HBM >2KV ● Super high density cell design for extremely low RDS(ON) ● Exceptional on-resistance and maximum DC current capability APPLICATIONS ● Power Management in Note book ● DC/DC Converter PIN CONFIGURATION ● Load Switch ● LCD Display inverter (SOT-363) Top View Th Ordering Information: ME2N7002DKW-G (Green product-Halogen free) Absolute Maximum Ratings (TA=25℃ Unless Otherwise Noted) Symbol Maximum Ratings Unit Drain-Source Voltage VDS 60 V Gate-Source Voltage VGS ±20 V TA=25℃ ID 0.3 TA=70℃ ID 0.2 IDM 1.1 TA=25℃ PD 0.3 TA=70℃ PD 0.2 TJ -55 to 150 ℃ Thermal Resistance-Junction to Ambient (Note 1) RθJA 375 ℃/W Thermal Resistance, Junction to Ambient (Note 2) RθJA 318 ℃/W Thermal Resistance, Junction to Case (Note 2) RθJC 135 ℃/W Parameter Continuous Drain A Pulsed Drain Current Maximum Power Dissipation A W Operating Junction Temperature 2 Note1.The device mounted on 1in FR4 board with 2 oz copper 2 2 Note2. The device mounted on 1in FR4 board with 2 oz copper, with thermal vias to bottom layer 1in copper plate Apr, 2024-Ver2.0 www.force-mos.com 01 ME2N7002DKW-G Dual N - Channel 60V (D-S) MOSFET, ESD Protection Protected Electrical Characteristics (TA =25℃ Unless Otherwise Specified) Symbol Parameter Limit Min BVDSS Drain-Source Breakdown Voltage VGS=0V, ID=250μA 60 VGS(th) Gate Threshold Voltage VDS=VGS, ID=250μA 1 IGSS Gate-Body Leakage IDSS Zero Gate Voltage Drain Current Typ Max Unit STATIC V 2.5 V VDS=0V, VGS=±20V ±10 μA VDS=60V, VGS=0V 1 μA VGS=10V, ID=500mA 2 3 VGS=4.5V, ID=200mA 2.4 4 VGS=3V, ID=10mA 3.9 4.5 Diode Forward Voltage * IS=200mA, VGS=0V 0.82 1.2 Qg Total Gate Charge VDS=30V,VGS=10V,ID=200mA 4.5 Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge 0.4 Ciss Input Capacitance 21 Coss Output Capacitance Crss Reverse Transfer Capacitance td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time RDS(ON) VSD Drain-Source On-Resistance* Ω V DYNAMIC 1.4 nC VDS=30V,VGS=4.5V,ID=200mA VDS=30V, VGS=0V, f=1MHz 2.6 3 pF 1 VDS=30V, RL =150Ω VGS=10V,RGS=10Ω ID=200mA 6.8 2.4 ns 15 27.3 Notes: a, pulse test: pulse width≦ 300us, duty cycle≦ 2%, Guaranteed by design, not subject to production testing. b. Force mos reserves the right to improve product design, functions and reliability without notice. Apr, 2024-Ver2.0 www.force-mos.com 02 ME2N7002DKW-G Dual N - Channel 60V (D-S) MOSFET, ESD Protection Protected Typical Characteristics (TJ =25℃ Noted) Apr, 2024-Ver2.0 www.force-mos.com 03 ME2N7002DKW-G Dual N - Channel 60V (D-S) MOSFET, ESD Protection Protected Typical Characteristics (TJ =25℃ Noted) Apr, 2024-Ver2.0 www.force-mos.com 04 ME2N7002DKW-G Dual N - Channel 60V (D-S) MOSFET, ESD Protection Protected SOT-363 Package Outline TO-252-3L Package Outline Apr, 2024-Ver2.0 www.force-mos.com 05 ME2N7002DKW-G Dual N - Channel 60V (D-S) MOSFET, ESD Protection Protected Device name: ME2N7002DKW-G Package: SOT-363 Marking Code: D76:DeviceMarkingCode M:Date code Apr, 2024-Ver2.0 www.force-mos.com 06