74HC595PW

74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Product datasheet, Rev. 1.0 Aug 08, 2024 1.General Description The 74HC595; 74HCT595 are 8-bit serial-in/serial or parallel-out shift registers with storage registers and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.Features and Benefits  Wide operating voltage 2.7 V to 6.0 V  High noise immunity  CMOS low power dissipation  8-bit serial input  8-bit serial or parallel output  Storage register with 3-state outputs  Shift register with direct clear  Latch-up performance exceeds 250 mA  Complies with JEDEC standard: • JESD8C(2.7 V to 3.6 V) • JESD7A(2.7 V to 6.0 V)  Input levels: • For 74HC595: CMOS level • For 74HCT595: TTL level  ESD protection: Rev. 1.0 – Aug 08, 2024 1 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Product datasheet, Rev. 1.0 • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 3500 V • CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V Aug 08, 2024  Multiple package options  Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3.Applications  Serial-to-parallel data conversion  Remote control holding register Rev. 1.0 – Aug 08, 2024 2 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 4.Ordering Information Table 1. Ordering information Type number 74HC595D 74HCT595D 74HC595PW 74HCT595PW 74HC595DB 74HCT595DB Package Name Description Quantity SOP-16L plastic small outline package; 16 leads; body width 3.9 mm 2500 TSSOP-16L plastic thin shrink small outline package; 16 leads; body width 4.4 mm 2500 SSOP-16L plastic small outline package; 16 leads; body width 5.3 mm 2500 5.Function Diagram Fig. 1. Functional diagram Rev. 1.0 – Aug 08, 2024 3 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Fig. 2. Logic symbol Fig. 3. IEC logic symbol Fig. 4. Logic diagram Rev. 1.0 – Aug 08, 2024 4 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 6.Pinning Information 6.1. Pinning Fig. 5. Top view pin configuration SOP, SSOP and TSSOP 6.2. Pin description Table 2. Pin description Symbol Pin Description Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 Parallel data output GND 8 Ground (0V) Q7S 9 Serial data output MR 10 Master reset (active LOW) SHCP 11 Shift register clock input STCP 12 Storage register clock input OE 13 Output enable input (active LOW) DS 14 Serial data input VCC 16 Supply voltage Rev. 1.0 – Aug 08, 2024 5 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 7.Functional Description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state. Control SHCP STCP X X X ↑ MR L L Input DS X X Output Q7S Qn L NC L L OE L L X X H L X L Z ↑ X L H H Q6S NC X ↑ L H X NC QnS ↑ ↑ L H X Q6S QnS Function a LOW-level on MR only affects the shift registers empty shift register loaded into storage register shift register clear; parallel outputs in high-impedance OFFstate logic HIGH-level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages Fig. 6. Timing diagram Rev. 1.0 – Aug 08, 2024 6 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 8.Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Table 4. Absolute Maximum Ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND. Symbol Parameter VCC supply voltage IIK input clamping current IOK output clamping current IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Conditions Min Max Unit -0.5 7.0 V ±20 mA ±20 mA ±35 mA 70 mA VO < -0.5 V or VO > VCC + 0.5 V [1] VO < -0.5 V or VO > VCC + 0.5 V [1] -0.5 V < VO < VCC + 0.5 V -70 Tamb = -40 °C to + 125 °C -65 mA 500 mW 150 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 9.Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. MDD does not recommend exceeding them or designing to Absolute Maximum Ratings. Table 5. Recommended Operating Conditions Symbol Parameter VCC Conditions 74HC595 74HCT595 Unit Min Typ Max Min Typ Max supply voltage 2.7 5.0 6.0 2.7 5.0 5.5 V VI input voltage 0 VCC 0 VCC V VO output voltage 0 VCC 0 VCC V Tamb ambient temperature +125 -40 +125 °C 371 ns/V Δt/ΔV input transition rise and fall rate 139 ns/V Rev. 1.0 – Aug 08, 2024 -40 +25 VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V +25 371 1.67 139 83 1.67 ns/V 7 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 10. Static Characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to +85 °C Min Typ[1] -40 °C to +125 °C Max Min Max Unit 74HC595 VIH VIL HIGH-level input voltage LOW-level input voltage VCC = 3.0 V 2.0 2.0 V VCC = 4.5 V 3.15 3.15 V VCC = 6.0 V 4.2 4.2 V VCC = 3.0 V 0.6 0.6 V VCC = 4.5 V 1.35 1.35 V VCC = 6.0 V 1.8 1.8 V VI = VIH or VIL all outputs VOH HIGH-level output voltage IO = -20μA; VCC = 3.0 V 2.9 2.9 V IO = -20μA; VCC = 4.5 V 4.4 4.4 V IO = -20μA; VCC = 6.0 V 5.9 5.9 V IO = -4.0 mA; VCC = 4.5 V 3.84 3.7 V IO = -5.2 mA; VCC = 6.0 V 5.34 5.2 V IO = -6.0 mA; VCC = 4.5 V 3.84 3.7 V IO = -7.8 mA; VCC = 6.0 V 5.34 5.2 V Q7S output Qn bus driver outputs VI = VIH or VIL all outputs VOL LOW-level output voltage IO = 20μA; VCC = 3.0 V 0.1 0.1 V IO = 20μA; VCC = 4.5 V 0.1 0.1 V IO = 20μA; VCC = 6.0 V 0.1 0.1 V IO = 4.0 mA; VCC = 4.5 V 0.33 0.4 V IO = 5.2 mA; VCC = 6.0 V 0.33 0.4 V IO = 6.0 mA; VCC = 4.5 V 0.33 0.4 V IO = 7.8 mA; VCC = 6.0 V 0.33 0.4 V Q7S output Qn bus driver outputs Rev. 1.0 – Aug 08, 2024 8 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state -40 °C to +85 °C -40 °C to +125 °C Symbol Parameter Conditions II input leakage current VI = VCC or GND ; VCC = 6.0 V ±1 ±1 μA VI = VIH or VIL ; VCC = 6.0V ; VO = VCC or GND ±5 ±10 μA VI = VCC or GND ; IO = 0A ; VCC = 6.0 V 20 40 μA IOZ ICC CI 74HCT595 VIH VIL OFF-state output current supply current input capacitance HIGH-level input voltage LOW-level input voltage Min Typ[1] Max Min Max 6.5 Unit pF VCC = 3.0 V 2.0 2.0 V VCC = 4.5 V 2.0 2.0 V VCC = 5.5 V 2.0 2.0 V VCC = 3.0 V 0.6 0.6 V VCC = 4.5 V 0.8 0.8 V VCC = 5.5 V 0.8 0.8 V VI = VIH or VIL all outputs VOH HIGH-level output voltage IO = -20μA; VCC = 3.0 V 2.9 2.9 V IO = -20μA; VCC = 4.5 V 4.4 4.4 V 3.84 3.7 V 3.84 3.7 V Q7S output IO = -4.0 mA; VCC = 4.5 V Qn bus driver outputs IO = -6.0 mA; VCC = 4.5 V VI = VIH or VIL all outputs VOL LOW-level output voltage IO = 20μA; VCC = 3.0 V 0.1 0.1 V IO = 20μA; VCC = 4.5 V 0.1 0.1 V 0.33 0.4 V 0.33 0.4 V ±1 ±1 μA Q7S output IO = 4.0 mA; VCC = 4.5 V Qn bus driver outputs IO = 6.0 mA; VCC = 4.5 V II input leakage current Rev. 1.0 – Aug 08, 2024 VI = VCC or GND ; VCC = 5.5 V 9 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state -40 °C to +85 °C Symbol Parameter Conditions IOZ OFF-state output current VI = VIH or VIL ; VCC = 5.5 V ; VO = VCC or GND ICC ΔICC CI supply current additional supply current input capacitance Min Typ[1] -40 °C to +125 °C Max VI = VCC or GND ; IO = 0 A ; VCC = 5.5 V per pin ; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V Min Max Unit ±5 ±10 μA 20 40 μA 450 490 μA 6.5 pF [1]All typical values are measured at Tamb = 25°C. 11. Dynamic Characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 12. Symbol Parameter -40 °C to +85 °C Conditions Min Typ[1] -40 °C to +125 °C Max Min Max Unit 74HC595 SHCP to Q7S; see Fig. 7 tpd tPHL ten propagation delay HIGH to LOW propagation delay enable time Rev. 1.0 – Aug 08, 2024 [2] VCC = 3.0 V 30 35 ns VCC = 4.5 V 20 25 ns VCC = 6.0 V 15 18 ns VCC = 3.0 V 45 50 ns VCC = 4.5 V 25 30 ns VCC = 6.0 V 20 25 ns VCC = 3.0 V 30 35 ns VCC = 4.5 V 19 22 ns VCC = 6.0 V 16 19 ns 22 14 13 25 17 16 ns ns ns STCP to Qn; see Fig. 8 [2] MR to Q7S; see Fig. 10 OE to Qn; see Fig. 11 VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V [3] 10 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Symbol tdis tW tSU th Parameter disable time pulse width set up time hold time Conditions OE to Qn; see Fig. 11 [4] VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V SHCP HIGH or LOW; see Fig. 7 VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V STCP HIGH or LOW; see Fig. 8 VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V MR LOW; see Fig.10 VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V DS to SHCP; see Fig.9 VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V SHCP to STCP; see Fig.9 VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V DS to SHCP; see Fig.9 VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V -40 °C to +85 °C Min Typ[1] -40 °C to +125 °C Max Min 22 15 13 Max 25 18 15 Unit ns ns ns 25 19 16 30 22 19 ns ns ns 25 19 16 30 22 19 ns ns ns 25 19 16 30 22 19 ns ns ns 16 13 11 20 15 13 ns ns ns 25 19 16 30 22 19 ns ns ns 3 3 3 3 3 3 ns ns ns VCC = 3.0 V 16 20 ns VCC = 4.5 V 13 15 ns VCC = 6.0 V 11 13 ns MR to SHCP; see Fig. 10 trec recovery time Rev. 1.0 – Aug 08, 2024 11 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Symbol Parameter -40 °C to +85 °C Conditions Min Typ[1] -40 °C to +125 °C Max Min Max Unit SHCP or STCP; see Fig. 7 and Fig. 8 fmax CPD 74HCT595 maximum frequency power dissipation capacitance VCC = 3.0 V 20 16 MHz VCC = 4.5 V 24 20 MHz VCC = 6.0 V 28 24 MHz fi = 1 MHz; VI = GND to VCC ; SHCP to Q7S; see Fig. 7 tpd propagation delay 115 [5][6] [2] VCC = 4.5 V STCP to Qn; see Fig. 8 tPHL ten enable time tdis disable time tW tSU th trec pulse width set up time hold time recovery time Rev. 1.0 – Aug 08, 2024 25 30 ns 25 30 ns 25 30 ns 20 25 ns 20 25 ns [2] VCC = 4.5 V HIGH to LOW propagation delay pF MR to Q7S; see Fig. 10 VCC = 4.5 V OE to Qn; see Fig. 11 [3] VCC = 4.5 V OE to Qn; see Fig. 11 [4] VCC = 4.5 V SHCP HIGH or LOW; see Fig. 7 VCC = 4.5 V STCP HIGH or LOW; see Fig. 8 VCC = 4.5 V MR LOW; see Fig.10 VCC = 4.5 V DS to SHCP; see Fig.9 VCC = 4.5 V SHCP to STCP; see Fig.9 VCC = 4.5 V DS to SHCP; see Fig.9 VCC = 4.5 V 19 22 ns 19 22 ns 19 22 ns 13 15 ns 19 22 ns 3 3 ns 13 15 ns MR to SHCP; see Fig. 10 VCC = 4.5 V 12 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Symbol Parameter fmax maximum frequency CPD power dissipation capacitance -40 °C to +85 °C Conditions Min Typ[1] Max -40 °C to +125 °C Min Max Unit SHCP or STCP; see Fig. 7 and Fig. 8 VCC = 4.5 V fi = 1 MHz; VI = GND to VCC ; 24 [5][6] 20 115 MHz pF [1] Typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL. [3] ten is the same as tPZL and tPZH. [4] tdis is the same as tPLZ and tPHZ. [5] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. [6] All 9 outputs switching. Rev. 1.0 – Aug 08, 2024 13 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 11.1. Waveforms and test circuit Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 7. Shift clock pulse, maximum frequency and input to output propagation delays Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 8. Storage clock to output propagation delays Rev. 1.0 – Aug 08, 2024 14 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 9. Data set up and hold times Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 10. Master reset to output propagation delays Rev. 1.0 – Aug 08, 2024 15 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 11. Enable and disable times Table 8. Measurement points Input Output VM VM 74HC595 0.5VCC 0.5VCC 74HCT595 1.3 V 1.3 V Type Rev. 1.0 – Aug 08, 2024 16 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 12. Test circuit for measuring switching times Table 9. Test data Type Input Load VEXT VI tr = tf CL RL tPZL, tPLZ tPHL, tPLH tPZH, tPHZ 74HC595 VCC 2.5 ns 15 pF 500Ω VCC Open GND 74HCT595 3V 2.5 ns 15pF 500Ω VCC Open GND Rev. 1.0 – Aug 08, 2024 17 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 12. Package Outline SOP-16L Symbol A A1 A2 b c D e E E1 L θ Rev. 1.0 – Aug 08, 2024 Dimensions In Millimeters Min. Max. 1.750 —— 0.150 0.250 1.400 1.500 0.330 0.510 0.170 0.250 9.800 10.000 1.270(BSC) 5.900 6.100 3.800 4.000 0.400 1.270 0° 8° Dimensions In Inches Min. Max. 0.069 —— 0.006 0.010 0.055 0.059 0.013 0.020 0.007 0.010 0.386 0.394 0.050(BSC) 0.232 0.240 0.150 0.157 0.016 0.050 0° 8° 18 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state TSSOP-16L Symbol A A1 A2 b c D e E E1 L θ Rev. 1.0 – Aug 08, 2024 Dimensions In Millimeters Min. Max. 1.200 —— 0.020 0.100 0.800 1.000 0.190 0.300 0.090 0.200 4.900 5.100 0.650(BSC) 6.250 6.550 4.300 4.500 0.500 0.700 1° 7° Dimensions In Inches Min. Max. 0.047 —— 0.001 0.004 0.031 0.039 0.007 0.012 0.004 0.008 0.193 0.201 0.026(BSC) 0.252(BSC) 0.169 0.177 0.020 0.028 1° 7° 19 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state SSOP-16L Symbol A A1 A2 A3 B B1 B2 C C1 C2 Dimensions In Millimeters Min. Max. 6.15 6.25 0.30TYP 0.65TYP 0.675TYP 5.25 5.35 7.65 7.95 0.60 0.80 1.70 1.80 1.75 1.95 0.799 Rev. 1.0 – Aug 08, 2024 Symbol C3 C4 H θ θ1 θ2 θ3 R R1 Dimensions In Millimeters Min. Max. 0.152 0.172 0.05 0.15 12 TYP4 12 TYP4 10 TYP 0 ~ 8 0.20TYP 0.15TYP 20 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model CDM Charged Device Model TTL Transistor-Transistor Logic 14. Revision History Table 11. Revision history Document ID Release Date Data sheet status 74HC_HCT595 Rev. 1.0 Apr 28, 2025 Product datasheet Rev. 1.0 – Aug 08, 2024 Change notice Supersedes 21