74HC165PW

74HC165 8-bit parallel-in/serial out shift register Draft datasheet, Rev. 1.0 Aug 08, 2024 1.General Description The 74HC165is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.Features and Benefits  Wide supply voltage range from 2.0 V to 6.0 V  High noise immunity  CMOS low power dissipation  Asynchronous 8-bit parallel load  Synchronous serial input  Latch-up performance exceeds 250 mA  Complies with JEDEC standard: • JESD8C(2.7 V to 3.6 V) • JESD7A(2.0 V to 6.0 V)  ESD protection: • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 3500 V • CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V  Multiple package options  Specified from -40 °C to +85 °C and from -40 °C to +125 °C Rev. 1.0 – Aug 08, 2024 1 74HC165 8-bit parallel-in/serial out shift register Draft datasheet, Rev. 1.0 Aug 08, 2024 3.Ordering Information Table 1. Ordering information Type number Package Name 74HC165D SOP-16L 74HC165PW TSSOP-16L Rev. 1.0 – Aug 08, 2024 Description plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Quantity 2500 2500 2 74HC165 8-bit serial-in/serial-out shift register 4.Function Diagram Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram Rev. 1.0 – Aug 08, 2024 3 74HC165 8-bit serial-in/serial-out shift register 5.Pinning Information 5.1. Pinning Fig. 4. Top view pin configuration SOP and TSSOP 5.2. Pin description Table 2. Pin description Symbol Pin Description PL 1 asynchronous parallel load input (active LOW) CP 2 clock input (LOW-to-HIGH edge-triggered) Q7 7 complementary output from the last stage GND 8 ground(0V) Q7 9 serial output from the last stage DS 10 serial data input D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn) CE 15 clock enable input (active LOW) VCC 16 supply voltage Rev. 1.0 – Aug 08, 2024 4 74HC165 8-bit serial-in/serial-out shift register 6.Functional Description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; q = state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care ↑ = LOW-to-HIGH transition; Inputs Qn registers Operating modes CP DS D0 to D7 Q0 Q1 to Q6 PL CE parallel load serial shift Hold“do nothing” Outputs Q7 Q7 L X X X L L L to L L H L X X X H H H to H H L H L ↑ I X L q0 to q5 q6 q6 H L ↑ h X H q0 to q5 q6 q6 H ↑ L I X L q0 to q5 q6 q6 H ↑ L h X H q0 to q5 q6 q6 H H X X X q0 q1 to q6 q7 q7 H X H X X q0 q1 to q6 q7 q7 Fig. 5. Timing diagram Rev. 1.0 – Aug 08, 2024 5 74HC165 8-bit serial-in/serial-out shift register 7.Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Table 4. Absolute Maximum Ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND. Symbol Parameter VCC supply voltage IIK input clamping current IOK output clamping current IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Conditions Min Max Unit -0.5 7.0 V ±20 mA ±20 mA ±25 mA 50 mA VI < -0.5 V or VI > VCC + 0.5 V [1] VO < -0.5 V or VO > VCC + 0.5 V [1] -0.5 V < VO < VCC + 0.5 V -50 mA Tamb = -40 °C to + 125 °C -65 500 mW 150 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 8.Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. MDD does not recommend exceeding them or designing to Absolute Maximum Ratings. Table 5. Recommended Operating Conditions Symbol Parameter VCC Conditions 74HC165 Unit Min Typ Max supply voltage 2.0 5.0 6.0 V VI input voltage 0 VCC V VO output voltage 0 VCC V Tamb ambient temperature +125 °C 625 ns/V 139 ns/V 83 ns/V -40 +25 VCC = 3.0 V Δt/ΔV input transition rise and fall rate VCC = 4.5 V VCC = 6.0 V Rev. 1.0 – Aug 08, 2024 1.67 6 74HC165 8-bit serial-in/serial-out shift register 9.Static Characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage VIL LOW-level input voltage Conditions -40 °C to +85 °C -40 °C to +125 °C Max Min Max Unit Min Typ[1] VCC = 2.0 V 1.5 1.2 1.5 V VCC = 4.5 V 3.15 2.4 3.15 V VCC = 6.0 V 4.2 3.5 4.2 V VCC = 2.0 V 0.8 0.5 0.5 V VCC = 4.5 V 2.1 1.35 1.35 V VCC = 6.0 V 2.8 1.8 1.8 V VI = VIH or VIL VOH HIGH-level output voltage IO = -20μA; VCC = 2.0 V 1.9 2.0 1.9 V IO = -20μA; VCC = 4.5 V 4.4 4.5 4.4 V IO = -20μA; VCC = 6.0 V 5.9 6.0 5.9 V IO = -4.0 mA; VCC = 4.5 V 3.84 4.4 3.7 V IO = -5.2 mA; VCC = 6.0 V 5.34 5.9 5.2 V VI = VIH or VIL IO = 20μA; VCC = 2.0 V VOL II ICC CI LOW-level output voltage input leakage current supply current input capacitance 0 0.1 0.1 V V IO = 20μA; VCC = 4.5 V 0 0.1 0.1 IO = 20μA; VCC = 6.0 V 0 0.1 0.1 V IO = 4.0 mA; VCC = 4.5 V 0.04 0.33 0.4 V IO = 5.2 mA; VCC = 6.0 V 0.05 0.33 0.4 V 0.1 ±1 ±1 μA 11 20 40 μA VI = VCC or GND ; VCC = 6.0 V VI = VCC or GND ; IO = 0A ; VCC = 6.0 V Pin PL,DS 4.3 pF Pin CP, CE 7.0 pF Pin D0 to D7 8.6 pF [1]All typical values are measured at Tamb = 25°C. Rev. 1.0 – Aug 08, 2024 7 74HC165 8-bit serial-in/serial-out shift register 10. Dynamic Characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 11. Symbol Parameter tpd VCC = 2.0 V 25 37 40 ns VCC = 4.5 V 12.5 17 20 ns VCC = 5.0 V 11.7 15 18 ns VCC = 6.0 V 10.4 13 15 ns VCC = 2.0 V 25 37 40 ns VCC = 4.5 V 11.8 17 20 ns VCC = 5.0 V 10.7 15 18 ns VCC = 6.0 V 9.7 13 15 ns VCC = 2.0 V 25 37 40 ns VCC = 4.5 V 12.4 17 20 ns VCC = 5.0 V 11.5 15 18 ns VCC = 6.0 V 10.1 13 15 ns VCC = 2.0 V 4 9 11 ns VCC = 4.5 V 2.2 7 9 ns VCC = 6.0 V 1.9 7 9 ns D7 to Q7, Q7; see Fig. 8 Min Max Unit Max PL to Q7, Q7; see Fig. 7 Min -40 °C to +125 °C Typ[1] CP or CE to Q7, Q7; see Fig. 6 propagation delay -40 °C to +85 °C Conditions [2] [2] [2] Q7, Q7 output; see Fig. 6 [3] tt transition time CP HIGH or LOW;see Fig. 6 tW pulse width Rev. 1.0 – Aug 08, 2024 VCC = 2.0 V 30 36 ns VCC = 4.5 V 20 24 ns VCC = 6.0 V 17 20 ns VCC = 2.0 V 25 30 ns VCC = 4.5 V 15 18 ns VCC = 6.0 V 13 15 ns PL LOW; see Fig. 7 8 74HC165 8-bit serial-in/serial-out shift register Symbol Parameter Conditions -40 °C to +85 °C Min Typ[1] -40 °C to +125 °C Max Min Max Unit PL to CP, CE; see Fig. 7 trec recovery time VCC = 2.0 V 25 28 ns VCC = 4.5 V 15 18 ns VCC = 6.0 V 13 15 ns VCC = 2.0 V 30 35 ns VCC = 4.5 V 20 24 ns VCC = 6.0 V 17 20 ns VCC = 2.0 V 30 35 ns VCC = 4.5 V 20 24 ns VCC = 6.0 V 17 20 ns VCC = 2.0 V 30 35 ns VCC = 4.5 V 20 24 ns VCC = 6.0 V 17 20 ns VCC = 2.0 V 5 5 ns VCC = 4.5 V 5 5 ns VCC = 6.0 V 5 5 ns VCC = 2.0 V 5 5 ns VCC = 4.5 V 5 5 ns VCC = 6.0 V 5 5 ns VCC = 2.0 V 16 12 MHz VCC = 4.5 V 24 20 MHz VCC = 6.0 V 28 24 MHz DS to CP, CE; see Fig. 9 CE to CP and CP to CE; see Fig. 9 tSU set up time Dn to PL; see Fig. 10 DS to CP, CE and Dn to PL; see Fig. 9 th hold time CE to CP and CP to CE; see Fig. 9 for CP; see Fig. 6 fmax maximum frequency Rev. 1.0 – Aug 08, 2024 9 74HC165 8-bit serial-in/serial-out shift register Symbol Parameter Conditions CPD power dissipation capacitance per package ; VI = GND to VCC ; -40 °C to +85 °C Min [4] Typ[1] 26 -40 °C to +125 °C Max Min Max Unit pF [1] Typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL. [3] tt is the same as tTHL and tTHL. [4] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. Rev. 1.0 – Aug 08, 2024 10 74HC165 8-bit serial-in/serial-out shift register 11. Waveforms and test circuit Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the maximum clock frequency and the output transition times Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 7. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) recovery time Rev. 1.0 – Aug 08, 2024 11 74HC165 8-bit serial-in/serial-out shift register Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 8. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. (1) CE may change only from HIGH-to-LOW while CP is LOW, see Section 1. Fig. 9. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE) Rev. 1.0 – Aug 08, 2024 12 74HC165 8-bit serial-in/serial-out shift register Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 10. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL) Table 8. Measurement points Type 74HC165 Rev. 1.0 – Aug 08, 2024 Input Output VI VM VX VY 0.5VCC 0.5VCC 0.1VCC 0.9VCC 13 74HC165 8-bit serial-in/serial-out shift register Test data is given in Table 9. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig. 11. Test circuit for measuring switching times Table 9. Test data Type 74HC165 Rev. 1.0 – Aug 08, 2024 Input Load VI tr = tf CL VCC 2.5 ns 50 pF Test tPHL, tPLH 14 74HC165 8-bit serial-in/serial-out shift register 12. Package Outline SOP-16L Symbol A A1 A2 b c D e E E1 L θ Rev. 1.0 – Aug 08, 2024 Dimensions In Millimeters Min. Max. 1.750 —— 0.150 0.250 1.400 1.500 0.330 0.510 0.170 0.250 9.800 10.000 1.270(BSC) 5.900 6.100 3.800 4.000 0.400 1.270 0° 8° Dimensions In Inches Min. Max. 0.069 —— 0.006 0.010 0.055 0.059 0.013 0.020 0.007 0.010 0.386 0.394 0.050(BSC) 0.232 0.240 0.150 0.157 0.016 0.050 0° 8° 15 74HC165 8-bit serial-in/serial-out shift register TSSOP-16L Symbol A A1 A2 b c D e E E1 L θ Rev. 1.0 – Aug 08, 2024 Dimensions In Millimeters Min. Max. 1.200 —— 0.020 0.100 0.800 1.000 0.190 0.300 0.090 0.200 4.900 5.100 0.650(BSC) 6.250 6.550 4.300 4.500 0.500 0.700 1° 7° Dimensions In Inches Min. Max. 0.047 —— 0.001 0.004 0.031 0.039 0.007 0.012 0.004 0.008 0.193 0.201 0.026(BSC) 0.252(BSC) 0.169 0.177 0.020 0.028 1° 7° 16 74HC165 8-bit serial-in/serial-out shift register 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model CDM Charged Device Model 14. Revision History Table 11. Revision history Document ID Release Date Data sheet status 74HC165 Rev. 1.0 Feb 20, 2025 Draft datasheet Rev. 1.0 – Aug 08, 2024 Change notice Supersedes 17