74HC164
8-bit serial-in, parallel-out shift register
Draft datasheet, Rev. 1.0
Aug 08, 2024
1.General Description
The 74HC164is an 8-bit serial-in/parallel-out shift register. The device features two serial data
inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through
DSA or DSB and either input can be used as an active HIGH enable for data entry through the
other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input. A LOW on
the master reset input (MR) clears the register and forces all outputs LOW, independently of
otherinputs. Inputs include clamp diodes. This enables the use of current limiting resistors to
interface inputs to voltages in excess of VCC.
2.Features and Benefits
Wide supply voltage range from 2.0 V to 6.0 V
High noise immunity
CMOS low power dissipation
Gated serial data inputs
Asynchronous master reset
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
•
JESD8C(2.7 V to 3.6 V)
•
JESD7A(2.0 V to 6.0 V)
ESD protection:
•
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 3500 V
•
CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Rev. 1.0 – Aug 08, 2024
1
74HC164
8-bit serial-in, parallel-out shift register
Draft datasheet, Rev. 1.0
Aug 08, 2024
3.Ordering Information
Table 1. Ordering information
Type number
Package
Name
74HC164D
SOP-14L
74HC164PW
TSSOP-14L
Rev. 1.0 – Aug 08, 2024
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
Quantity
2500
2500
2
74HC164
8-bit serial-in, parallel-out shift register
4.Function Diagram
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram
Rev. 1.0 – Aug 08, 2024
3
74HC164
8-bit serial-in, parallel-out shift register
Fig. 4. Functional diagram
5.Pinning Information
5.1. Pinning
Fig. 5. Top view pin configuration SOP and TSSOP
Rev. 1.0 – Aug 08, 2024
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74HC164
8-bit serial-in, parallel-out shift register
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
DSA
1
data input
DSB
2
data input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
3, 4, 5, 6, 10, 11, 12, 13
output
CP
8
clock input (LOW-to-HIGH, edge-triggered)
MR
9
master reset input (active LOW)
VCC
14
supply voltage
GND
7
ground
6.Functional Description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock
transition; ↑ = LOW-to-HIGH transition; X = don’t care
Operating modes
Reset(clear)
Shift
Input
Output
MR
CP
DSA
DSB
Q0
Q1 to Q7
L
X
X
X
L
L to L
H
↑
l
l
L
q0 to q6
H
↑
l
h
L
q0 to q6
H
↑
h
l
L
q0 to q6
H
↑
h
h
H
q0 to q6
Rev. 1.0 – Aug 08, 2024
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74HC164
8-bit serial-in, parallel-out shift register
7.Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not
recommended. In addition, extended exposure to stresses above the recommended operating conditions may
affect device reliability. The absolute maximum ratings are stress ratings only.
Table 4. Absolute Maximum Ratings
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND.
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
IOK
output clamping current
IO
output current
ICC
supply current
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
Conditions
Min
Max
Unit
-0.5
7.0
V
±20
mA
±20
mA
±25
mA
50
mA
VO < -0.5 V or VO > VCC + 0.5 V
[1]
VO < -0.5 V or VO > VCC + 0.5 V
[1]
-0.5 V < VO < VCC + 0.5 V
-50
mA
Tamb = -40 °C to + 125 °C
-65
500
mW
150
°C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
8.Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. MDD does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Table 5. Recommended Operating Conditions
Symbol
Parameter
VCC
Conditions
74HC164
Unit
Min
Typ
Max
supply voltage
2.0
5.0
6.0
V
VI
input voltage
0
VCC
V
VO
output voltage
0
VCC
V
Tamb
ambient temperature
+125
°C
625
ns/V
139
ns/V
83
ns/V
-40
+25
VCC = 2.0 V
Δt/ΔV
input transition rise and fall rate
VCC = 4.5 V
VCC = 6.0 V
Rev. 1.0 – Aug 08, 2024
1.67
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74HC164
8-bit serial-in, parallel-out shift register
9.Static Characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VIH
HIGH-level
input
voltage
VIL
LOW-level
input voltage
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Max
Min
Max
Unit
Min
Typ[1]
VCC = 2.0 V
1.5
1.2
1.5
V
VCC = 4.5 V
3.15
2.7
3.15
V
VCC = 6.0 V
4.2
3.5
4.2
V
VCC = 2.0 V
0.8
0.5
0.5
V
VCC = 4.5 V
2.68
1.35
1.35
V
VCC = 6.0 V
3.5
1.8
1.8
V
VI = VIH or VIL
VOH
HIGH-level
output
voltage
IO = -20μA; VCC = 2.0 V
1.9
2.0
1.9
V
IO = -20μA; VCC = 4.5 V
4.4
4.5
4.4
V
IO = -20μA; VCC = 6.0 V
5.9
6.0
5.9
V
IO = -4.0 mA; VCC = 4.5 V
3.84
4.45
3.7
V
IO = -5.2 mA; VCC = 6.0 V
5.34
5.95
5.2
V
VI = VIH or VIL
VOL
II
ICC
CI
LOW-level
output
voltage
input
leakage
current
supply
current
input
capacitance
IO = 20μA; VCC = 2.5 V
0
0.1
0.1
V
IO = 20μA; VCC = 4.5 V
0
0.1
0.1
V
IO = 20μA; VCC = 6.0 V
0
0.1
0.1
V
V
IO = 4.0 mA; VCC = 4.5 V
0.04
0.33
0.4
IO = 5.2 mA; VCC = 6.0 V
0.05
0.33
0.4
V
VI = VCC or GND ;
VCC = 6.0 V
0.001
±1
±1
μA
7.7
20
40
μA
VI = VCC or GND ; IO = 0A ;
VCC = 6.0 V
Pin DSA, DSB
7
pF
Pin CP
8
pF
Pin MR
3
pF
[1]All typical values are measured at Tamb = 25°C.
Rev. 1.0 – Aug 08, 2024
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74HC164
8-bit serial-in, parallel-out shift register
10. Dynamic Characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 9.
Symbol
Parameter
tpd
Min
-40 °C to +125 °C
Min
Max
Unit
Typ[1]
Max
VCC = 2.0 V
28.5
60
65
ns
VCC = 4.5 V
13.5
17
20
ns
VCC = 5.0 V
11.8
15
18
ns
VCC = 6.0 V
9.9
13
15
ns
VCC = 2.0 V
30.8
60
65
ns
VCC = 4.5 V
13.2
17
20
ns
VCC = 5.0 V
12.3
15
18
ns
VCC = 6.0 V
11.4
13
15
ns
VCC = 2.0 V
1.3
8
10
ns
VCC = 4.5 V
2.3
7
9
ns
VCC = 6.0 V
2.1
7
9
ns
CP to Qn; see Fig. 6
propagation
delay
-40 °C to +85 °C
Conditions
[2]
MR to Qn; see Fig. 7
tPHL
HIGH to
LOW
propagation
delay
see Fig. 6
tt
transition
time
[3]
CP HIGH or LOW;
see Fig. 6
tW
pulse width
VCC = 2.0 V
100
120
ns
VCC = 4.5 V
20
24
ns
VCC = 6.0 V
17
20
ns
VCC = 2.0 V
75
90
ns
VCC = 4.5 V
15
18
ns
VCC = 6.0 V
13
15
ns
VCC = 2.0 V
75
90
ns
VCC = 4.5 V
15
18
ns
VCC = 6.0 V
13
15
ns
MR LOW; see Fig. 7
MR to CP; see Fig. 7
trec
recovery
time
Rev. 1.0 – Aug 08, 2024
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74HC164
8-bit serial-in, parallel-out shift register
Symbol
Parameter
-40 °C to +85 °C
Conditions
Min
Typ[1]
-40 °C to +125 °C
Max
Min
Max
Unit
DSA and DSB to CP;
see Fig. 8
tSU
set up time
VCC = 2.0 V
75
90
ns
VCC = 4.5 V
15
18
ns
VCC = 6.0 V
13
15
ns
VCC = 2.0 V
4
4
ns
VCC = 4.5 V
4
4
ns
VCC = 6.0 V
4
4
ns
VCC = 2.0 V
5
4
MHz
VCC = 4.5 V
24
20
MHz
VCC = 6.0 V
28
24
MHz
DSA and DSB to CP;
see Fig. 8
th
hold time
for CP; see Fig. 6
fmax
maximum
frequency
CPD
power
dissipation
capacitance
per package ;
VI = GND to VCC ;
[4]
68
pF
[1] Typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTHL and tTHL.
[4] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
Rev. 1.0 – Aug 08, 2024
9
74HC164
8-bit serial-in, parallel-out shift register
10.1. Waveforms and test circuit
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width,
the output transition times and the maximum clock frequency
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 7. Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn)
propagation delays and the master reset to clock (CP) removal time
Rev. 1.0 – Aug 08, 2024
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74HC164
8-bit serial-in, parallel-out shift register
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 8. Waveforms showing the data set-up and hold times for Dn inputs
Table 8. Measurement points
Type
74HC164
Rev. 1.0 – Aug 08, 2024
Input
Output
VI
VM
VX
VY
0.5VCC
0.5VCC
0.1VCC
0.9VCC
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74HC164
8-bit serial-in, parallel-out shift register
Test data is given in Table 9.
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig. 9. Test circuit for measuring switching times
Table 9. Test data
Type
74HC164
Rev. 1.0 – Aug 08, 2024
Input
Load
VI
tr = tf
CL
VCC
2.5 ns
50 pF
Test
tPHL, tPLH
12
74HC164
8-bit serial-in, parallel-out shift register
11. Package Outline
SOP-14L
Rev. 1.0 – Aug 08, 2024
13
74HC164
8-bit serial-in, parallel-out shift register
TSSOP-14L
Rev. 1.0 – Aug 08, 2024
14
74HC164
8-bit serial-in, parallel-out shift register
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
CDM
Charged Device Model
13. Revision History
Table 11. Revision history
Document ID
Release Date
Data sheet status
74HC164 Rev. 1.0
Jun 26, 2025
Product datasheet
Rev. 1.0 – Aug 08, 2024
Change notice
Supersedes
15
