74AHC1G08GW

74AHC1G08; 74AHCT1G08 Single 2-input AND gate Product datasheet, Rev. 1.0 Aug 8, 2024 1.General Description The 74AHC1G08 and 74AHCT1G08 are single 2-input AND gates. Inputs are overvoltage tolerant.This feature allows the use of these devices as translators in mixed voltage environments. 2.Features and Benefits  Wide supply voltage range from 2.0 V to 5.5 V  Overvoltage tolerant inputs to 5.5 V  High noise immunity  CMOS low power dissipation  Latch-up performance exceeds 200 mA  Symmetrical output impedance  Balanced propagation delays  Input levels: • For 74AHC1G08: CMOS level • For 74AHCT1G08: TTL level  ESD protection: • HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 7000 V • CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V  Multiple package options Rev. 1.0 – Aug 8, 2024 1 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate 3.Ordering Information Table 1. Ordering information Type number 74AHC1G08GV 74AHCT1G08GV 74AHC1G08GW 74AHCT1G08GW 74AHC1G08DRL 74AHCT1G08DRL Package Name Description Quantity SOT23-5L SOT23 package, 5 pins 2.92 mm × 1.6 mm; 1.25 mm (Max) height 3000 SOT353 SOT353 package, 5 pins 2.1 mm × 1.25 mm; 1.1 mm (Max) height 3000 SOT553 SOT553 package, 5 pins 1.6 mm × 1.2 mm; 0.6 mm (Max) height 3000 4.Function Diagram Fig. 1. Logic symbol Rev. 1.0 – Aug 8, 2024 Fig. 2. IEC logic symbol Fig. 3. Logic diagram 2 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate 5.Pinning Information 5.1. Pinning Fig. 4. Top view pin configuration SOT23-5L, SOT353 and SOT553 5.2. Pin description Table 2. Pin description Symbol Pin Description B 1 Data input A 2 Data input GND 3 Ground (0V) Y 4 Data output VCC 5 Supply voltage 6.Functional Description Table 3. Function table H = HIGH voltage level; L = LOW voltage level. Input Output A B Y L L L L H L H L L H H H Rev. 1.0 – Aug 8, 2024 3 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate 7.Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Table 4. Absolute Maximum Ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND. Symbol Parameter VCC Conditions Min Max Unit supply voltage -0.5 7.0 V VI input voltage -0.5 7.0 V IIK input clamping current IOK output clamping current IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature VI < -0.5 V VO < -0.5 V or VO > VCC + 0.5 V [1] -0.5 V < VO < VCC + 0.5 V -20 mA ±20 mA ±25 mA 75 mA -75 mA Tamb = -40 °C to + 125 °C -65 250 mW 150 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 8.Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. MDD does not recommend exceeding them or designing to Absolute Maximum Ratings. Table 5. Recommended Operating Conditions Symbol Parameter VCC Conditions 74AHC1G08 74AHCT1G08 Unit Min Typ Max Min Typ Max supply voltage 2.0 5.0 5.5 2.0 5.0 5.5 V VI input voltage 0 5.5 0 5.5 V VO output voltage 0 VCC 0 VCC V Tamb ambient temperature 125 -40 125 °C Δt/ΔV input transition rise and fall rate Rev. 1.0 – Aug 8, 2024 -40 25 25 VCC = 3.3 V ± 0.3 V 100 100 ns/V VCC = 5.0 V ± 0.5 V 20 20 ns/V 4 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate 9.Static Characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to +85 °C Min Typ[1] -40 °C to +125 °C Max Min Max Unit 74AHC1G08 VIH VIL HIGH-level input voltage LOW-level input voltage VCC = 2.0 V 1.5 1.5 V VCC = 3.0 V 2.1 2.1 V VCC = 5.5 V 3.85 3.85 V VCC = 2.0 V 0.5 0.5 V VCC = 3.0 V 0.9 0.9 V VCC = 5.5 V 1.65 1.65 V VI = VIH or VIL VOH HIGH-level output voltage IO = -50 μA; VCC = 2.0 V 1.9 2.0 1.9 V IO = -50 μA; VCC = 3.0 V 2.9 3.0 2.9 V IO = -50 μA; VCC = 4.5 V 4.4 4.5 4.4 V IO = -4.0 mA; VCC = 3.0 V 2.48 2.93 2.40 V IO = -8.0 mA; VCC = 4.5 V 3.80 4.39 3.70 V VI = VIH or VIL VOL II ICC CI LOW-level output voltage input leakage current supply current input capacitance Rev. 1.0 – Aug 8, 2024 IO = 50 μA; VCC = 2.0 V 0 0.1 0.1 V IO = 50 μA; VCC = 3.0 V 0 0.1 0.1 V IO = 50 μA; VCC = 4.5 V 0 0.1 0.1 V IO = 4.0 mA; VCC = 3.0 V 0.05 0.44 0.55 V IO = 8.0 mA; VCC = 4.5 V 0.07 0.44 0.55 V VI = 5.5 V or GND ; VCC = 0 V to 5.5 V ±0.01 ±1.0 ±2.0 μA VI = VCC or GND ; IO = 0 A ; VCC = 5.5 V 0.01 10 40 μA 3.5 pF 5 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate Symbol Parameter Conditions -40 °C to +85 °C Min Typ[1] -40 °C to +125 °C Max Min Max Unit 74AHCT1G08 VIH VIL HIGH-level input voltage LOW-level input voltage VCC = 2.0 V 1.0 1.0 V VCC = 3.3 V 1.5 1.5 V VCC = 4.5 V to 5.5 V 2.0 2.0 V VCC = 2.0 V 0.3 0.3 V VCC = 3.3 V 0.55 0.55 V VCC = 4.5 V to 5.5 V 0.8 0.8 V VI = VIH or VIL; VOH HIGH-level output voltage IO = -50 μA; VCC = 2.0 V 1.9 2.0 1.9 V IO = -50 μA; VCC = 3.0 V 2.9 3.0 2.9 V IO = -50 μA; VCC = 4.5 V 4.4 4.5 4.4 V IO = -4.0 mA; VCC = 3.0 V 2.48 2.93 2.4 V IO = -8.0 mA; VCC = 4.5 V 3.80 4.39 3.70 V VI = VIH or VIL; VOL LOW-level output voltage II input leakage current ICC supply current ΔICC additional supply current CI input capacitance IO = 50 μA; VCC = 2.0 V 0 0.1 0.1 V IO = 50 μA; VCC = 3.0 V 0 0.1 0.1 V IO = 50 μA; VCC = 4.5 V 0 0.1 0.1 V IO = 4.0 mA; VCC = 3.0 V 0.05 0.44 0.55 V IO = 8.0 mA; VCC = 4.5 V 0.07 0.44 0.55 V ±0.01 ±1.0 ±2.0 μA 0.01 10 40 μA 0.23 1.35 1.35 mA VI = 5.5 V or GND ; VCC = 0 V to 5.5 V VI = VCC or GND ; IO = 0 A ; VCC = 5.5 V per input pin ; VI = 3.4 V; other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V 3.5 pF [1]All typical values are measured at Tamb = 25°C. Rev. 1.0 – Aug 8, 2024 6 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate 10. Dynamic Characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6. Symbol Parameter -40 °C to +85 °C Conditions -40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 3.0 V to 3.6 V, CL = 15 pF 1.0 4.3 9.5 1.0 10.0 ns VCC = 4.5 V to 5.5 V, CL = 15 pF 1.0 3.1 6.5 1.0 7.0 ns 74AHC1G08 tpd CPD propagation delay power dissipation capacitance A and B to Y; see Fig. 5 [2] CL = 15 pF ; f = 1MHz ; VI = GND to VCC [3] ; 26 pF 74AHCT1G08 A and B to Y; see Fig. 5 [2] tpd CPD propagation delay power dissipation capacitance VCC = 2.0 V, CL = 15 pF 46.5 VCC = 3.3 V, CL = 15 pF 3.0 9.3 12.5 3.0 13.0 VCC = 4.5 V to 5.5 V, CL = 15 pF 1.0 4.3 8.0 1.0 8.5 CL = 15 pF ; f = 1MHz ; VI = GND to VCC [3] ; 22 ns pF [1] Typical values are measured at Tamb = 25 °C and VCC =2.0 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. Rev. 1.0 – Aug 8, 2024 7 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate 10.1. Waveforms and test circuit Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. The input A, B to output Y propagation delays Table 8. Measurement points Type 74AHC1G08 74AHCT1G08 Rev. 1.0 – Aug 8, 2024 Supply Voltage Input Output VCC VI VM VM 3.0 V ~ 5.5 V GND to VCC 0.5 x VCC 0.5 x VCC 2.0 V GND to VCC 0.5 x VCC 0.5 x VCC 3.3 V GND to 3.0 V 1.5 V 0.5 x VCC 4.5 V ~ 5.5 V GND to 3.0 V 1.5 V 0.5 x VCC 8 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 6. Test circuit for measuring switching times Table 9. Test data Input Load VEXT tr = tf CL tPLH, tPHL 74AHC1G08 ≤ 2.5 ns 15 pF open 74AHCT1G08 ≤ 2.5 ns 15 pF open Type Rev. 1.0 – Aug 8, 2024 9 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate 11. Package Outline SOT23-5L Rev. 1.0 – Aug 8, 2024 10 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate SOT353 Rev. 1.0 – Aug 8, 2024 11 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate SOT553 Rev. 1.0 – Aug 8, 2024 12 74AHC1G08; 74AHCT1G08 Single 2-input NAND gate 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model CDM Charged Device Model TTL Transistor-Transistor Logic 13. Revision History Table 11. Revision history Document ID Release Date Data sheet status 74AHC_AHCT1G08 Rev. 1.0 Mar 08, 2024 Product datasheet Rev. 1.0 – Aug 8, 2024 Change notice Supersedes 13