74HC259; 74HCT259
8-bit addressable latch
Product datasheet, Rev. 1.0
Aug 08, 2024
1.General Description
The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of
operation. In the addressable latch mode, data on the D input is written into the latch
addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed
latches will retain their previous states. In memory mode, all latches retain their previous states
and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing
mode, the addressed output follows the D input and all other outputs are LOW. In the reset
mode, all outputs are forced LOW and unaffected by the data or address inputs. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
2.Features and Benefits
Wide supply voltage range from 2.0 V to 6.0 V
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
•
JESD8C (2.7 V to 3.6 V)
•
JESD7A (2.0 V to 6.0 V)
Combined demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Input levels:
•
For 74HC259: CMOS level
•
For 74HCT259: TTL level
Rev. 1.0 – Aug 08, 2024
74HC259; 74HCT259
8-bit addressable latch
Product datasheet, Rev. 1.0
Aug 08, 2024
ESD protection:
•
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 3500 V
•
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3.Ordering Information
Table 1. Ordering information
Type number
74HC259D
74HCT259D
74HC259PW
74HCT259PW
Rev. 1.0 – Aug 08, 2024
Package
Name
Description
Quantity
SOP-16L
plastic small outline package; 16 leads;
body width 3.9 mm
2500
TSSOP-16L
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
2500
74HC259; 74HCT259
8-bit addressable latch
4.Function Diagram
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Fig. 3. Functional diagram
Rev. 1.0 – Aug 08, 2024
74HC259; 74HCT259
8-bit addressable latch
5.Pinning Information
5.1. Pinning
Fig. 4. Top view pin configuration SOP and TSSOP
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
A0, A1, A2
1, 2, 3
Address input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
4, 5, 6, 7, 9, 10, 11, 12
Latch output
GND
8
Ground (0 V)
D
13
Data input
LE
14
Latch enable input (active LOW)
MR
15
Conditional reset input (active LOW)
VCC
16
Supply voltage
Rev. 1.0 – Aug 08, 2024
74HC259; 74HCT259
8-bit addressable latch
6.Functional Description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-toHIGH transition.
Operating
mode
Reset(clear)
Demultiplexer
(active HIGH
8-channel)
decoder
(when D = H)
Memory (no
action)
Addressable
latch
Input
MR
L
L
L
L
L
L
L
L
L
A2
X
L
L
L
L
H
H
H
H
Output
Q0
Q1
L
L
Q=d L
L
Q=d
L
L
L
L
L
L
L
L
L
L
L
L
LE
H
L
L
L
L
L
L
L
L
D
X
d
d
d
d
d
d
d
d
A0
X
L
H
L
H
L
H
L
H
A1
X
L
L
H
H
L
L
H
H
Q2
L
L
L
Q=d
L
L
L
L
L
Q3
L
L
L
L
Q=d
L
L
L
L
Q4
L
L
L
L
L
Q=d
L
L
L
Q5
L
L
L
L
L
L
Q=d
L
L
Q6
L
L
L
L
L
L
L
Q=d
L
Q7
L
L
L
L
L
L
L
L
Q=d
H
H
X
X
X
X
q0
q1
q2
q3
q4
q5
q6
q7
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
d
d
d
d
d
d
d
d
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
Q=d
q0
q0
q0
q0
q0
q0
q0
q1
Q=d
q1
q1
q1
q1
q1
q1
q2
q2
Q=d
q2
q2
q2
q2
q2
q3
q3
q3
Q=d
q3
q3
q3
q3
q4
q4
q4
q4
Q=d
q4
q4
q4
q5
q5
q5
q5
q5
Q=d
q5
q5
q6
q6
q6
q6
q6
q6
Q=d
q6
q7
q7
q7
q7
q7
q7
q7
Q=d
Table 4. Operating mode select table
H = HIGH voltage level; L = LOW voltage level.
LE
L
H
L
H
Rev. 1.0 – Aug 08, 2024
MR
H
H
L
L
Mode
Addressable latch mode
Memory mode
Demultiplexer mode
Reset mode
74HC259; 74HCT259
8-bit addressable latch
7.Absolute Maximum Ratings
Stresses exceeding the absolut`e maximum ratings may damage the device. The device may not function
or be operable above the recommended operating conditions and stressing the parts to these levels is
not recommended. In addition, extended exposure to stresses above the recommended operating
conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Table 4. Absolute Maximum Ratings
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND.
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
IOK
Conditions
Min
Max
Unit
-0.5
7
V
VI < -0.5 V or VI > VCC + 0.5 V
±20
mA
output clamping current
VO < -0.5 V or VO > VCC + 0.5 V
±20
mA
IO
output current
VO = -0.5 V to (VCC + 0.5 V)
±25
mA
ICC
supply current
70
mA
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
-70
mA
Tamb = -40 °C to + 125 °C
-65
500
mW
150
°C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
8.Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation.
Recommended operating conditions are specified to ensure optimal performance to the datasheet
specifications. MDD does not recommend exceeding them or designing to Absolute Maximum Ratings.
Table 5. Recommended Operating Conditions
Symbol
Parameter
VCC
Conditions
74HC259
74HCT259
Unit
Min
Typ
Max
Min
Typ
Max
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
VCC
0
VCC
V
VO
output voltage
0
VCC
0
VCC
V
Tamb
ambient temperature
125
-40
125
°C
Δt/ΔV
Input transition rise
and fall rate
Rev. 1.0 – Aug 08, 2024
-40
25
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
25
625
1.67
139
83
ns/V
1.67
139
ns/V
ns/V
74HC259; 74HCT259
8-bit addressable latch
9.Static Characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
-40 °C to +85 °C
Min
Typ
-40 °C to +125 °C
Max
Min
Max
Unit
74HC259
VIH
VIL
HIGH-level
input
voltage
LOW-level
input
voltage
VCC = 2.0 V
1.5
1.5
V
VCC = 4.5 V
3.15
3.15
V
VCC = 6.0 V
4.2
4.2
V
VCC = 2.0 V
0.5
0.5
V
VCC = 4.5 V
1.35
1.35
V
VCC = 6.0 V
1.8
1.8
V
VI = VIH or VIL
VOH
HIGH-level
output
voltage
IO = -20 μA; VCC = 2.0 V
1.9
1.9
V
IO = -20 μA; VCC = 4.5 V
4.4
4.4
V
IO = -20 μA; VCC = 6.0 V
5.9
5.9
V
IO = -4.0 mA; VCC = 4.5 V
3.84
3.7
V
IO = -5.2 mA; VCC = 6.0 V
5.34
5.2
V
VI = VIH or VIL
VOL
LOW-level
output
voltage
IO = 20 μA; VCC = 2.0 V
0.1
0.1
V
IO = 20 μA; VCC = 4.5 V
0.1
0.1
V
IO = 20 μA; VCC = 6.0 V
0.1
0.1
V
IO = 4.0 mA; VCC = 4.5 V
0.33
0.4
V
IO = 5.2 mA; VCC = 6.0 V
0.33
0.4
V
II
input
leakage
current
VI = VCC or GND ;
VCC = 6.0 V
±1
±1
μA
ICC
supply
current
VI = VCC or GND ; IO = 0
A;
VCC = 6.0 V
20
40
μA
CI
input
capacitance
Rev. 1.0 – Aug 08, 2024
6.5
pF
74HC259; 74HCT259
8-bit addressable latch
Symbol
Parameter
Conditions
-40 °C to +85 °C
Min
Typ
-40 °C to +125 °C
Max
Min
Max
Unit
74HCT259
VIH
VIL
VOH
HIGH-level
input
voltage
LOW-level
input
voltage
HIGH-level
output
voltage
VOL
LOW-level
output
voltage
II
input
leakage
current
ICC
supply
current
ΔICC
additional
supply
current
CI
input
capacitance
Rev. 1.0 – Aug 08, 2024
VCC = 4.5 V to 5.5 V
2.0
2.0
VCC = 4.5 V to 5.5 V
0.8
V
0.8
V
VI = VIH or VIL; VCC = 4.5 V
IO = -20 μA
4.4
4.4
V
IO = -4.0 mA
3.84
3.7
V
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA
0.1
0.1
V
IO = 4.0 mA
0.33
0.4
V
±1
±1
μA
20
40
μA
450
490
μA
VI = VCC or GND ;
VCC = 5.5 V
VI = VCC or GND ; IO = 0
A;
VCC = 5.5 V
VI = VCC - 2.1 V; other
inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
6.5
pF
74HC259; 74HCT259
8-bit addressable latch
10. Dynamic Characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 11.
Symbol
Parameter
-40 °C to +85 °C
Conditions
Min
Typ[1]
-40 °C to +125 °C
Max
Min
Max
Unit
74HC259
D to Qn; see Fig. 5
VCC = 2.0 V
55
60
ns
VCC = 4.5 V
17
20
ns
VCC = 6.0 V
13
15
ns
VCC = 2.0 V
55
60
ns
VCC = 4.5 V
17
20
ns
VCC = 6.0 V
13
15
ns
VCC = 2.0 V
55
60
ns
VCC = 4.5 V
17
20
ns
VCC = 6.0 V
13
15
ns
VCC = 2.0 V
55
60
ns
VCC = 4.5 V
17
20
ns
VCC = 6.0 V
13
15
ns
VCC = 2.0 V
8
10
ns
VCC = 4.5 V
7
9
ns
VCC = 6.0 V
7
9
ns
An
[2]
tpd
propagation
delay
LE
[2]
tPHL
HIGH to
LOW
propagation
delay
to
to
transition
time
Rev. 1.0 – Aug 08, 2024
Qn;
Qn;
see
see
Fig.
Fig.
6
7
MR to Qn; see Fig. 8
see Fig. 7
tt
[2]
[3]
74HC259; 74HCT259
8-bit addressable latch
Symbol
Parameter
-40 °C to
+125 °C
-40 °C to +85 °C
Conditions
Min
Typ[1]
Max
Min
Max
Unit
LE HIGH or LOW; see Fig. 7
tW
pulse width
VCC = 2.0 V
100
120
ns
VCC = 4.5 V
20
24
ns
VCC = 6.0 V
17
20
ns
VCC = 2.0 V
75
90
ns
VCC = 4.5 V
15
18
ns
VCC = 6.0 V
13
15
ns
VCC = 2.0 V
75
90
ns
VCC = 4.5 V
15
18
ns
VCC = 6.0 V
13
15
ns
VCC = 2.0 V
5
5
ns
VCC = 4.5 V
5
5
ns
VCC = 6.0 V
5
5
ns
VCC = 2.0 V
5
5
ns
VCC = 4.5 V
5
5
ns
VCC = 6.0 V
5
5
ns
MR LOW; see Fig. 8
D, An to LE;
see Fig. 9 and Fig. 10
tSU
set-up time
D to LE; see Fig. 9 and Fig. 10
th
CPD
hold time
power
dissipation
capacitance
An to LE; see Fig. 9 and Fig. 10
f = 1 MHz; VI = GND to VCC [4]
26
pF
74HCT259
D to Qn; see Fig. 5
[2]
VCC = 4.5 V
tpd
propagation
delay
An to Qn; see Fig. 6
VCC = 4.5 V
Rev. 1.0 – Aug 08, 2024
20
ns
17
20
ns
17
20
ns
[2]
VCC = 4.5 V
LE to Qn; see Fig. 7
17
[2]
74HC259; 74HCT259
8-bit addressable latch
Symbol
Parameter
Conditions
MR to Qn; see Fig. 8
tPHL
HIGH to
LOW
propagation
delay
tt
transition
time
see Fig. 7
-40 °C to +85 °C
Min
Typ
VCC = 4.5 V
-40 °C to +125 °C
Max
Min
Max
Unit
17
20
ns
7
9
ns
[3]
VCC = 4.5 V
LE HIGH or LOW; see Fig. 7
tW
pulse width
VCC = 4.5 V
set-up time
24
ns
31
38
ns
15
18
ns
5
5
ns
5
5
ns
MR LOW; see Fig. 8
VCC = 4.5 V
tsu
20
D, An to LE;
see Fig. 9 and Fig. 10
VCC = 4.5 V
D to LE; see Fig. 9 and Fig. 10
th
hold time
VCC = 4.5 V
An to LE; see Fig. 9 and Fig. 10
VCC = 4.5 V
CPD
power
dissipation
capacitance
f = 1 MHz;
VI = GND to VCC - 1.5 V
[4]
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTHL and tTLH.
[4] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
Rev. 1.0 – Aug 08, 2024
28
pF
74HC259; 74HCT259
8-bit addressable latch
10.1. Waveforms and test circuit
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 5. Data input to output propagation delays
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6. Address input to output propagation delays
Rev. 1.0 – Aug 08, 2024
74HC259; 74HCT259
8-bit addressable latch
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 7. Enable input to output propagation delays and pulse width
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 8. Master reset input to output propagation delays
Rev. 1.0 – Aug 08, 2024
74HC259; 74HCT259
8-bit addressable latch
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 9. Data input to latch enable input set-up and hold times
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 10. Address input to latch enable input set-up and hold times
Rev. 1.0 – Aug 08, 2024
74HC259; 74HCT259
8-bit addressable latch
Table 8. Measurement points
Input
Output
VM
VM
VX
VY
74HC259
0.5VCC
0.5VCC
0.1VCC
0.9 VCC
74HCT259
1.3 V
1.3 V
0.1 VCC
0.9 VCC
Type
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 11. Test circuit for measuring switching times
Table 9. Test data
Type
Input
Load
VEXT
VI
tr = tf
CL
RL
tPLH, tPHL
74HC259
VCC
2.0 ns
50 pF
500 Ω
open
74HCT259
3V
2.0 ns
50 pF
500 Ω
open
Rev. 1.0 – Aug 08, 2024
74HC259; 74HCT259
8-bit addressable latch
11. Package Outline
SOP-16L
Rev. 1.0 – Aug 08, 2024
74HC259; 74HCT259
8-bit addressable latch
TSSOP-16L
Rev. 1.0 – Aug 08, 2024
74HC259; 74HCT259
8-bit addressable latch
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
CDM
Charged Device Model
TTL
Transistor-Transistor Logic
13. Revision History
Table 11. Revision history
Document ID
Release Date
Data sheet status
74HC_HCT259 Rev. 1.0
Apr 28, 2025
Product datasheet
Rev. 1.0 – Aug 08, 2024
Change notice
Supersedes
