74LVC8T245PW

74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state Draft datasheet, Rev. 1.0 Aug 08, 2024 1.General Description The 74LVC8T245; 74LVCH8T245 is an 8-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated. The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a valid logic level. 2.Features and Benefits  Wide supply voltage range • VCC(A): 1.2 V to 5.5 V • VCC(B): 1.2 V to 5.5 V  High noise immunity  Complies with JEDEC standards: • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • JESD36 (4.5 V to 5.5 V)  Suspend mode Rev. 1.0 – Aug 08, 2024 1 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state Draft datasheet, Rev. 1.0 Aug 08, 2024  Latch-up performance exceeds 250 mA  ±24 mA output drive (VCC = 3.0 V)  Inputs accept voltages up to 5.5 V  Low power consumption: 30 μA maximum ICC  IOFF circuitry provides partial Power-down mode operation  ESD protection:  • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2500 V • CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V Multiple package options Rev. 1.0 – Aug 08, 2024 2 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state 3.Ordering Information Table 1. Ordering information Type number 74LVC8T245PW 74LVCH8T245PW Package Name Description Quantity TSSOP-24L plastic thin shrink small outline package; 24 leads; body width 4.4 mm 2500 4.Function Diagram Fig. 1. Logic symbol Fig. 2. Logic diagram (one channel) Rev. 1.0 – Aug 08, 2024 3 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state 5.Pinning Information 5.1. Pinning Fig. 3. Top view pin configuration TSSOP 5.2. Pin description Table 2. Pin description Symbol Pin Description VCC(A) 1 Supply voltage A (An inputs/outputs, OE and DIR inputs are referenced to VCC(A)) DIR 2 Direction control A1, A2, A3, A4, A5, A6, A7, A8 3, 4, 5, 6, 7, 8, 9, 10 Data input or output GND [1] 11, 12, 13 Ground (0 V) B1, B2, B3, B4, B5, B6, B7, B8 21, 20, 19, 18, 17, 16, 15, 14 Data input or output OE 22 Output enable input (active LOW) VCC(B) 23, 24 Supply voltage B (Bn inputs/outputs are referenced to VCC(B)) [1] All GND pins must be connected to ground (0V). Rev. 1.0 – Aug 08, 2024 4 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state 6.Functional Description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Supply voltage Input Input/output VCC(A), VCC(B) OE [2] DIR [2] An [2] Bn [2] 1.2 V to 5.5 V L L A=B input 1.2 V to 5.5 V L H input B=A 1.2 V to 5.5 V H X Z Z GND [1] X X Z Z [1] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. [2] The An inputs/outputs, DIR and OE input circuit is referenced to VCC(A); The Bn inputs/outputs circuit is referenced to VCC(B). 7.Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Table 4. Absolute Maximum Ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND. Symbol Parameter VCC(A) Conditions Min Max Unit supply voltage A -0.5 6.5 V VCC(B) supply voltage B -0.5 6.5 V IIK input clamping current VI input voltage IOK output clamping current VO output voltage IO VI < 0 V -50 [1] -0.5 VO < 0 V mA 6.5 -50 V mA [1][2][3] -0.5 VCCO + 0.5 V Suspend or 3-state mode [1] -0.5 6.5 V output current VO = 0 V to VCCO [2] ±50 mA ICC supply current ICC(A) or ICC(B); per VCC pin 100 mA IGND ground current per GND pin Ptot total power dissipation Tstg storage temperature Active mode -100 -65 mA 500 mW 150 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] VCCO is the supply voltage associated with the output port. [3] VCCO + 0.5 V should not exceed 6.5 V. Rev. 1.0 – Aug 08, 2024 5 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state 8.Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. MDD does not recommend exceeding them or designing to Absolute Maximum Ratings. Table 5. Recommended Operating Conditions Symbol Parameter VCC(A) Min Max Unit supply voltage A 1.2 5.5 V VCC(B) supply voltage B 1.2 5.5 V VI input voltage 0 5.5 V 0 VCCO V 0 5.5 V -40 125 °C 20 ns/V VCCI = 1.4 V to 1.95 V 20 ns/V VCCI = 2.3 V to 2.7 V 20 ns/V VCCI = 3 V to 3.6 V 10 ns/V VCC = 4.5 V to 5.5 V 5 ns/V VO output voltage Tamb ambient temperature Conditions Active [1] Suspend or 3-state mode VCCI [2] Δt/ΔV input transition rise and fall rate mode = 1.2 V [1] VCCO is the supply voltage associated with the output port. [2] VCCI is the supply voltage associated with the input port. Rev. 1.0 – Aug 08, 2024 6 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state 9.Static Characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Typical values measured at Tamb = 25°C (unless otherwise noted). Symbol Parameter -40 °C to +85 °C Conditions Min data input VIH HIGH-level input voltage Max Unit 0.8VCCI 0.8VCCI V VCCI = 1.4 V to 1.95 V 0.65VCCI 0.65VCCI V VCCI = 2.3 V to 2.7 V 1.7 1.7 V VCCI = 3 V to 3.6 V 2.2 2.2 V 0.7VCCI 0.7VCCI V VCCI = 1.2 V 0.8VCC(A) 0.8VCC(A) V VCCI = 1.4 V to 1.95 V 0.65VCC(A) 0.65VCC(A) V VCCI = 2.3 V to 2.7 V 1.7 1.7 V VCCI = 3 V to 3.6 V 2.0 2.0 V 0.7VCC(A) 0.7VCC(A) V VCCI = 4.5 V to 5.5 V DIR, OE input [1] VCCI = 1.2 V 0.2VCCI 0.2VCCI V VCCI = 1.4 V to 1.95 V 0.35 VCCI 0.35 VCCI V VCCI = 2.3 V to 2.7 V 0.7 0.7 V VCCI = 3 V to 3.6 V 0.8 0.8 V 0.3VCCI 0.3VCCI V 0.2VCC(A) 0.2VCC(A) V VCCI = 1.4 V to 1.95 V 0.35 VCC(A) 0.35 VCC(A) V VCCI = 2.3 V to 2.7 V 0.7 0.7 V VCCI = 3 V to 3.6 V 0.8 0.8 V 0.3VCC(A) 0.3VCC(A) V VCCI = 4.5 V to 5.5 V DIR, OE input VCCI = 1.2 V VCCI = 4.5 V to 5.5 V Rev. 1.0 – Aug 08, 2024 Min VCCI = 1.2 V data input LOW-level input voltage Max [1] VCCI = 4.5 V to 5.5 V VIL Typ -40 °C to +125 °C 7 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state Symbol Parameter Conditions -40 °C to +85 °C Min Typ -40 °C to +125 °C Max Min Max Unit VI = VIH IO = -100 μA; VCCO = 1.2 V to 4.5 V IO = -3 mA; VCCO = 1.4 V VOH HIGH-level output voltage IO V IO V IO V IO V = -8 mA; VCCO = 1.65 = -12 mA; VCCO = 2.3 = -24 mA; VCCO = 3.0 = -32 mA; VCCO = 4.5 VCCO - 0.1 VCCO - 0.1 V 1.0 1.0 V 1.2 1.2 V 1.9 1.9 V 2.4 2.4 V 3.8 3.8 V VI = VIL VOL II IOZ IOFF LOW-level output voltage input leakage current OFF-state output current power-off leakage current Rev. 1.0 – Aug 08, 2024 IO = 100 μA; VCCO = 1.2 V to 4.5 V 0.1 0.1 V IO = 3 mA; VCCO = 1.4 V 0.3 0.3 V IO = 8 mA; VCCO = 1.65 V 0.45 0.45 V IO = 12 mA; VCCO = 2.3 V 0.3 0.3 V IO = 24 mA; VCCO = 3.0 V 0.55 0.55 V IO = 32 mA; VCCO = 4.5 V 0.55 0.55 V ±2 ±10 μA ±2 ±10 μA ±2 ±10 μA ±2 ±10 μA ±2 ±10 μA ±2 ±10 μA DIR, OE input; VI = 0V to 5.5V ; VCCI = 1.2V to 5.5V A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V [2] suspend mode A port; VO = 0 V or VCCO; VCC(A) = 5.5 V; VCC(B) = 0 V [2] suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V; VCC(B) = 5.5 V [2] A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V B port; VI or VO = 0 V to 5.5 V; 8 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V Symbol IBHL IBHH Parameter bus hold LOW current bus hold HIGH current IBHLO IBHHO Rev. 1.0 – Aug 08, 2024 Typ -40 °C to +125 °C Max Min Max Unit 25 20 μA VI = 0.70 V; VCCI = 2.3 V 45 45 μA VI = 0.80 V; VCCI = 3.0 V 100 80 μA VI = 1.35 V; VCCI = 4.5 V 100 100 μA -1 -1 μA VI = 1.70 V; VCCI = 2.3 V -7 -7 μA VI = 2.00 V; VCCI = 3.0 V -35 -35 μA VI = 3.15 V; VCCI = 4.5 V -95 -95 μA VCCI = 1.6 V 125 125 μA VCCI = 1.95 V 200 200 μA VCCI = 2.7 V 300 300 μA VCCI = 3.6 V 500 500 μA VCCI = 5.5 V 900 900 μA VCCI = 1.6 V -125 -125 μA VCCI = 1.95 V -200 -200 μA VCCI = 2.7 V -300 -300 μA VCCI = 3.6 V -500 -500 μA VCCI = 5.5 V -900 -900 μA A or B port [1] VI = 1.07 V; VCCI = 1.65 V A or B port bus hold HIGH overdrive current Min A or B port [1] VI = 0.58 V; VCCI = 1.65 V A or B port bus hold LOW overdrive current -40 °C to +85 °C Conditions [1][3] [1][3] 9 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state Symbol Parameter Conditions -40 °C to +85 °C Min Typ -40 °C to +125 °C Max Min Max Unit A port; VI = 0 V or VCCI; IO = 0 A [1] VCC(A), VCC(B)=1.2V to 5.5V 15 20 μA VCC(A) = 5.5V; VCC(B) = 0V 15 20 μA VCC(A) = 0V; VCC(B) = 5.5V ICC supply current -2 -4 μA B port; VI = 0 V or VCCI; IO = 0 A VCC(A), VCC(B)=1.2V to 5.5V VCC(B) = 0V; VCC(A) = 5.5V VCC(B) = 5.5V; VCC(A) = 0V 15 -2 20 -4 μA μA 15 20 μA 25 30 μA 50 75 μA 50 75 μA 50 75 μA A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI VCC(A), VCC(B)=1.2V to 5.5V ΔICC additional supply current per input; VCC(A), VCC(B) = 3.0V to 5.5V DIR and OE input; DIR or OE input at VCC(A) 0.6V; A port at VCC(A) or GND; B port = open A port; A port at VCC(A) 0.6 V; DIR at VCC(A); B port = open [4] B port; B port at VCC(B) 0.6 V; DIR at VCC(B); A port = open [4] [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. [3] To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH. [4] For non bus hold parts only (74LVC8T245). Rev. 1.0 – Aug 08, 2024 10 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state 10. Dynamic Characteristics Table 7. Dynamic characteristics for temperature range -40 °C to +85 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6. for waveforms see Fig. 3 and Fig. 4. [1] Symbol Parameter Conditions VCC(B) Unit 1.5V±0.1V 1.8V±0.15V 2.5V±0.2V 3.3V±0.3V 5.0V±0.5V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.5 V ± 0.1 V tpd propagation An to Bn 0.9 43.2 0.9 39.2 0.8 36.3 0.7 35.1 0.7 35.1 ns time Bn to An 0.9 43.2 0.9 39.2 0.8 36.3 0.7 35.1 0.7 35.1 ns tdis disable time OE to An 1.5 72.5 1.5 72.5 1.5 72.5 1.5 72.5 1.4 72.5 ns 1.5 72.5 1.5 72.5 1.5 72.5 1.5 72.5 1.4 72.5 ns OE to Bn ten enable time OE to An 0.4 92.2 0.4 92.2 0.4 92.2 0.4 92.2 0.4 92.2 ns 0.4 92.2 0.4 92.2 0.4 92.2 0.4 92.2 0.4 92.2 ns OE to Bn VCC(A) = 1.8 V ± 0.15 V tpd propagation An to Bn 0.9 38.6 0.9 30.5 0.8 26.9 0.7 26.3 0.7 25.8 ns time Bn to An 0.9 38.6 0.9 30.5 0.8 26.9 0.7 26.3 0.7 25.8 ns tdis disable time OE to An 1.5 46.3 1.5 46.3 1.5 46.3 1.5 46.3 1.4 46.3 ns 1.5 46.3 1.5 46.3 1.5 46.3 1.5 46.3 1.4 46.3 ns OE to Bn ten enable time OE to An 0.4 63.2 0.4 58.1 0.4 54.6 0.4 54.1 0.4 53.1 ns 0.4 63.2 0.4 58.1 0.4 54.6 0.4 54.1 0.4 53.1 ns OE to Bn VCC(A) = 2.5 V ± 0.2 V tpd propagation An to Bn 1.2 33.0 1.2 24.7 1.0 19.7 1.0 18.3 0.9 17.1 ns time Bn to An 1.2 33.0 1.2 24.7 1.0 19.7 1.0 18.3 0.9 17.1 ns tdis disable time OE to An 1.4 25.1 1.4 25.1 1.4 25.1 1.4 25.1 1.4 25.1 ns 1.4 25.1 1.4 25.1 1.4 25.1 1.4 25.1 1.4 25.1 ns OE to Bn ten enable time OE to An 1.0 38.3 1.0 33.1 1.0 29.5 1.0 28.0 1.0 27.0 ns 1.0 38.3 1.0 33.1 1.0 29.5 1.0 28.0 1.0 27.0 ns OE to Bn VCC(A) = 3.3 V ± 0.3 V tpd propagation An to Bn 0.8 31.2 0.8 22.6 0.8 16.2 0.7 14.5 0.6 13.6 ns time Bn to An 0.8 31.2 0.8 22.6 0.8 16.2 0.7 14.5 0.6 13.6 ns tdis disable time OE to An 1.6 20.2 1.6 20.2 1.6 20.2 1.6 20.2 1.6 20.2 ns 1.6 20.2 1.6 20.2 1.6 20.2 1.6 20.2 1.6 20.2 ns OE to Bn ten enable time OE to An 0.8 31.5 0.8 25.8 0.8 22.4 0.8 21.1 0.8 20.8 ns 1.8 31.5 0.8 25.8 0.8 22.4 0.8 21.1 0.8 20.8 ns OE to Bn VCC(A) = 5.0 V ± 0.5 V tpd propagation An to Bn 0.7 29.8 0.7 21.3 0.4 14.8 0.3 12.6 0.3 11.2 ns time Bn to An 0.7 29.8 0.7 21.3 0.4 14.8 0.3 12.6 0.3 11.2 ns tdis disable time OE to An 0.3 15.6 0.3 15.6 0.3 15.6 0.3 15.6 0.3 15.6 ns 0.3 15.6 0.3 15.6 0.3 15.6 0.3 15.6 0.3 15.6 ns OE to Bn ten enable time OE to An 0.7 29.1 0.7 21.2 0.7 18.5 0.7 16.8 0.7 15.9 ns 0.7 29.1 0.7 21.2 0.7 18.5 0.7 16.8 0.7 15.9 ns OE to Bn [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Rev. 1.0 – Aug 08, 2024 11 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state Table 8. Dynamic characteristics for temperature range -40 °C to +125 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6. for waveforms see Fig. 3 and Fig. 4. [1] Symbol Parameter Conditions VCC(B) Unit 1.5V±0.1V 1.8V±0.15V 2.5V±0.2V 3.3V±0.3V 5.0V±0.5V Min Max Min Max Min Max Min Max Min Max VCC(A) = 1.5 V ± 0.1 V tpd propagation An to Bn 0.9 43.3 0.9 38.9 0.8 36.3 0.7 35.1 0.7 35.1 ns time Bn to An 0.9 43.3 0.9 38.9 0.8 36.3 0.7 35.1 0.7 35.1 ns tdis disable time OE to An 1.5 74.5 1.5 74.5 1.5 74.5 1.5 74.5 1.4 74.5 ns 1.5 74.5 1.5 74.5 1.5 74.5 1.5 74.5 1.4 74.5 ns OE to Bn ten enable time OE to An 0.4 94.2 0.4 94.2 0.4 94.2 0.4 94.2 0.4 94.2 ns 0.4 94.2 0.4 94.2 0.4 94.2 0.4 94.2 0.4 94.2 ns OE to Bn VCC(A) = 1.8 V ± 0.15 V tpd propagation An to Bn 0.9 38.4 0.9 30.8 0.8 27.8 0.7 26.4 0.7 25.3 ns time Bn to An 0.9 38.4 0.9 30.8 0.8 27.8 0.7 26.4 0.7 25.3 ns tdis disable time OE to An 1.5 50.3 1.5 50 1.5 50.2 1.5 50.4 1.4 50.3 ns 1.5 50.3 1.5 50 1.5 50.2 1.5 50.4 1.4 50.3 ns OE to Bn ten enable time OE to An 0.4 67.2 0.4 61.8 0.4 58.5 0.4 58.2 0.4 57.1 ns 0.4 67.2 0.4 61.8 0.4 58.5 0.4 58.2 0.4 57.1 ns OE to Bn VCC(A) = 2.5 V ± 0.2 V tpd propagation An to Bn 1.2 33.4 1.2 25.4 1.0 19.7 1.0 18.5 0.9 17.3 ns time Bn to An 1.2 33.4 1.2 25.4 1.0 19.7 1.0 18.5 0.9 17.3 ns tdis disable time OE to An 1.4 29.1 1.4 28.8 1.4 29 1.4 29.2 1.4 29.1 ns 1.4 29.1 1.4 28.8 1.4 29 1.4 29.2 1.4 29.1 ns OE to Bn ten enable time OE to An 1.0 42.3 1.0 36.8 1.0 33.4 1.0 32.1 1.0 31.0 ns 1.0 42.3 1.0 36.8 1.0 33.4 1.0 32.1 1.0 31.0 ns OE to Bn VCC(A) = 3.3 V ± 0.3 V tpd propagation An to Bn 0.8 32.2 0.8 23.2 0.8 16.8 0.7 15.5 0.6 14.6 ns time Bn to An 0.8 32.2 0.8 23.2 0.8 16.8 0.7 15.5 0.6 14.6 ns tdis disable time OE to An 1.6 24.2 1.6 23.9 1.6 24.1 1.6 24.3 1.6 24.2 ns 1.6 24.2 1.6 23.9 1.6 24.1 1.6 24.3 1.6 24.2 ns OE to Bn ten enable time OE to An 0.8 35.5 0.8 29.5 0.8 26.3 0.8 25.2 0.8 24.8 ns 0.8 35.5 0.8 29.5 0.8 26.3 0.8 25.2 0.8 24.8 ns OE to Bn VCC(A) = 5.0 V ± 0.5 V tpd propagation An to Bn 0.7 30.4 0.7 22.1 0.4 15.5 0.3 13.4 0.3 11.9 ns time Bn to An 0.7 30.4 0.7 22.1 0.4 15.5 0.3 13.4 0.3 11.9 ns tdis disable time OE to An 0.3 19.6 0.3 19.3 0.3 19.5 0.3 19.7 0.3 19.6 ns 0.3 19.6 0.3 19.3 0.3 19.5 0.3 19.7 0.3 19.6 ns OE to Bn ten enable time OE to An 0.7 33.1 0.7 24.9 0.7 22.4 0.7 20.9 0.7 19.9 ns 0.7 33.1 0.7 24.9 0.7 22.4 0.7 20.9 0.7 19.9 ns OE to Bn [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. Rev. 1.0 – Aug 08, 2024 12 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state Table 9. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V). [1][2] Symbol Parameter Conditions CPD power dissipation capacitance A port: (direction A to B); B port: (direction B to A) A port: (direction B to A); B port: (direction A to B) VCC(A) and VCC(B) Unit 1.8 V 2.5 V 3.3 V 5.0 V 1 1 1 1 pF 16 16 17 18 pF [1] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. [2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. Rev. 1.0 – Aug 08, 2024 13 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state 10.1. Waveforms and test circuit Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 4. The input An, Bn to output Bn, An propagation delays Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. 3-state enable and disable times Table 10. Measurement points Supply voltage Input [1] Output [2] VCC(A), VCC(B) VM VM VX VY 1.2 V to 1.6 V 0.5VCCI 0.5VCCO VOL + 0.1 V VOH - 0.1 V 1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL + 0.15 V VOH - 0.15 V 3.0 V to 5.5 V 0.5VCCI 0.5VCCO VOL + 0.3 V VOH - 0.3 V [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. Rev. 1.0 – Aug 08, 2024 14 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 6. Test circuit for measuring switching times Table 11. Test data Supply voltage Input Load VEXT VCC(A), VCC(B) VI [1] tr = tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ [2] 1.2 V to 5.5 V VCCI ≤ 2.5 ns 15 pF 2kΩ open GND 2VCCO [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. Rev. 1.0 – Aug 08, 2024 15 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state 11. Package Outline TSSOP-24L Symbol A A1 A2 A3 b b1 c c1 D E1 Rev. 1.0 – Aug 08, 2024 Dimensions In Millimeters Min. Max. 1.20 0.05 0.15 0.80 1.05 0.39 0.49 0.20 0.28 0.19 0.25 0.13 0.17 0.12 0.14 6.40 6.60 4.30 4.50 Dimensions In Millimeters Min. Max. 6.20 6.60 0.65BSC 0.45 0.75 1.00REF 0° 8° 16 74LVC8T245; 74LVCH8T245 8-bit dual supply translating transceiver; 3-state 12. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model CDM Charged Device Model 13. Revision History Table 13. Revision history Document ID Release Date Data sheet status 74LVC_LVCH8T245 Rev. 1.0 Feb 10, 2025 Product datasheet Rev. 1.0 – Aug 08, 2024 Change notice Supersedes 17