74LVC1G57GW

74LVC1G57 Low-power configurable multiple function gate Product datasheet, Rev. 1.0 Aug 08, 2024 1.General Description The 74LVC1G57 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2.Features and Benefits  Wide supply voltage range from 1.65 V to 5.5 V  Overvoltage tolerant inputs to 5.5 V  High noise immunity  ±24 mA output drive (VCC = 3.0 V)  CMOS low power dissipation  Latch-up performance exceeds 200 mA  Direct interface with TTL levels  IOFF circuitry provides partial Power-down mode operation  Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8B/JESD36 (2.7 V to 3.6 V)  ESD protection: • HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V • CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V  Multiple package options Rev. 1.0 – Aug 08, 2024 1 74LVC1G57 Low-power configurable multiple function gate 3.Ordering Information Table 1. Ordering information Type number Topside marking Package 74LVC1G57GV VHYW SOT23-6L 74LVC1G57GW VHYW SOT363 Name Description Quantity SOT23 package, 6 pins 2.92 mm × 1.6 mm; 1.25 mm (Max) height SOT363 package, 6 pins 2.1 mm × 1.25 mm; 1.1 mm (Max) height 3000 3000 MARKING INFORMATION NOTE: YW = Data Code. VH Y W Data Code -Week Data Code -Year Serial Number 4.Function Diagram A 3 4 B 1 Y C 6 Fig. 1. Logic symbol Rev. 1.0 – Aug 08, 2024 2 74LVC1G57 Low-power configurable multiple function gate 5.Pinning Information 5.1. Pinning 6 C 2 5 VCC 3 4 Y B 1 GND A Fig. 2. Top view pin configuration SOT23-6 and SOT363 5.2. Pin description Table 2. Pin description Symbol Pin Description B 1 Data input GND 2 Ground (0V) A 3 Data input Y 4 Data output VCC 5 Supply voltage C 6 Data input Rev. 1.0 – Aug 08, 2024 3 74LVC1G57 Low-power configurable multiple function gate 6.Functional Description Table 3. Function table H = HIGH voltage level; L = LOW voltage level. Input Output C B A Y L L L H L L H L L H L H L H H L H L L L H L H L H H L H H H H H 6.1. Logic configurations Table 4. Function selection table Logic function Figure 2-input AND see Fig. 3 2-input AND with both inputs inverted see Fig. 6 2-input NAND with inverted input see Fig. 4 and Fig. 5 2-input OR with inverted input see Fig. 4 and Fig. 5 2-input NOR see Fig. 6 2-input NOR with both inputs inverted see Fig. 3 2-input XNOR see Fig. 7 Inverter see Fig. 8 Buffer see Fig. 9 Rev. 1.0 – Aug 08, 2024 4 74LVC1G57 Low-power configurable multiple function gate VCC B C Y B C Y B 1 2 6 5 C 3 4 Y Fig. 3. 2-input AND gate or 2-input NOR gate with both inputs inverted VCC B C Y B C Y B 1 2 6 5 C 3 4 Y Fig. 4. 2-input NAND gate with input B inverted or 2-input OR gate with inverted C input VCC VCC A C Y A C Y A 1 2 6 5 C 3 4 Y Fig. 5. 2-input NAND gate with input C inverted or 2-input OR gate with inverted A input A C Y A C Y A 1 2 6 5 C 3 4 Y Fig. 6. 2-input NOR gate or 2-input AND gate with both inputs inverted VCC VCC B C Y B 1 2 6 5 C 3 4 Y Y A Fig. 7. 2-input XNOR gate A 1 2 6 5 3 4 Y Fig. 8. Inverter VCC B Y B 1 2 6 5 3 4 Y Fig. 9. Buffer Rev. 1.0 – Aug 08, 2024 5 74LVC1G57 Low-power configurable multiple function gate 7.Absolute Maximum Ratings Stresses exceeding the absolut`e maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Table 5. Absolute Maximum Ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND. Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Conditions VI < 0 V Min Max Unit -0.5 6.5 V -50 [1] -0.5 VO > VCC or VO < 0 V mA 6.5 V ±50 mA Active mode [1] -0.5 6.5 V Power-down mode; VCC = 0 V [1] -0.5 6.5 V ±50 mA 100 mA VO = 0 V to VCC -100 Tamb = -40 °C to + 125 °C -65 mA 250 mW 150 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 8.Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. EnergyMath does not recommend exceeding them or designing to Absolute Maximum Ratings. Table 6. Recommended Operating Conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Rev. 1.0 – Aug 08, 2024 Conditions Min Typ Max Unit 1.65 5.5 V 0 5.5 V Active mode 0 VCC V Power-down mode; VCC = 0V 0 5.5 V -40 125 °C 6 74LVC1G57 Low-power configurable multiple function gate 9.Static Characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to +85 °C Min Typ[1] -40 °C to +125 °C Max Min Max Unit VI = VT+ or VTIO = -100μA; VCC = 1.65 V to 5.5 V VOH HIGH-level output voltage VCC - 0.1 VCC - 0.1 V IO = -4 mA; VCC = 1.65 V 1.2 1.6 0.95 V IO = -8 mA; VCC = 2.3 V 1.9 2.2 1.7 V IO = -12 mA; VCC = 2.7 V 2.2 2.5 1.9 V V V IO = -24 mA; VCC = 3.0 V 2.3 2.7 2.0 IO = -32 mA; VCC = 4.5 V 3.8 4.2 3.4 VI = VT+ or VTIO = 100μA; VCC = 1.65 V to 5.5 V VOL II IOFF ICC ΔICC CI LOW-level output voltage input leakage current power-off leakage current supply current additional supply current input capacitance 0.10 0.10 V IO = 4 mA; VCC = 1.65 V 0.02 0.45 0.70 V IO = 8 mA; VCC = 2.3 V 0.06 0.30 0.45 V IO = 12 mA; VCC = 2.7 V 0.12 0.40 0.60 V IO = 24 mA; VCC = 3.0 V 0.28 0.55 0.80 V IO = 32 mA; VCC = 4.5 V 0.34 0.55 0.80 V VI = 5.5 V or GND ; VCC = 0 V to 5.5 V ±0.1 ±1 ±1 μA VCC = 0V ; VI or VO = 5.5 V ±0.1 ±2 ±2 μA 0.1 4 4 μA per pin ; VCC = 2.3V to 5.5V ; VI = VCC -0.6V ; IO = 0A 5 500 500 μA VCC = 3.3V ; VI = GND to VCC 5 VI = 5.5V or GND ; IO = 0A ; VCC = 5.5V pF [1]All typical values are measured at Tamb = 25℃. Rev. 1.0 – Aug 08, 2024 7 74LVC1G57 Low-power configurable multiple function gate 10. Dynamic Characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 11. Symbol Parameter tpd CPD power dissipation capacitance -40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.65 V to 1.95 V 4.0 15.7 26 4.0 26.5 ns VCC = 2.3 V to 2.7 V 2.5 9.5 14 2.5 14.5 ns VCC = 3.0 V to 3.6 V 2.0 7.1 9 2.0 9.5 ns VCC = 4.5 V to 5.5 V 1.5 2.9 5 1.5 5.5 ns A, B, C to Y; see Fig. 10 propagation delay -40 °C to +85 °C Conditions VCC = 3.3 V VI = GND to VCC [2] [3] 25 pF [1] Typical values are measured at norminal at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. Rev. 1.0 – Aug 08, 2024 8 74LVC1G57 Low-power configurable multiple function gate 10.1. Waveforms and test circuit VI A, B, C input VM VM GND tPHL tPLH VOH Y output VM VOL VOH Y output VM tPLH tPHL VM VM VOL Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 10. Input A, B and C to output Y propagation delays Table 9. Measurement points Supply Voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5VCC 0.5VCC 2.3 V to 2.7 V 0.5VCC 0.5VCC 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5VCC 0.5VCC Rev. 1.0 – Aug 08, 2024 9 74LVC1G57 Low-power configurable multiple function gate VEXT VCC G VI RL VO DUT RT CL Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 11. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VCC VI tr = tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC ≤ 2.0 ns 15 pF 500 Ω open 2.3 V to 2.7 V VCC ≤ 2.0 ns 15 pF 500 Ω open 3.0 V to 3.6 V 3V ≤ 2.5 ns 15 pF 500 Ω open 4.5 V to 5.5 V VCC ≤ 2.5 ns 15 pF 500 Ω open Rev. 1.0 – Aug 08, 2024 Load VEXT 10 74LVC1G57 Low-power configurable multiple function gate 11. Transfer Characteristics Table 11. Transfer characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.8 V 0.70 1.09 1.20 0.67 1.20 V VCC = 2.3 V 1.11 1.36 1.60 1.08 1.60 V VCC = 3.0 V 1.50 1.69 2.00 1.47 2.00 V VCC = 4.5 V 2.16 2.39 2.74 2.13 2.74 V VCC = 5.5 V 2.61 2.86 3.33 2.58 3.33 V VCC = 1.8 V 0.30 0.6 0.72 0.30 0.75 V VCC = 2.3 V 0.58 0.77 1.00 0.58 1.03 V VCC = 3.0 V 0.80 1.09 1.30 0.80 1.33 V VCC = 4.5 V 1.21 1.62 1.90 1.21 1.93 V VCC = 5.5 V 1.45 1.99 2.29 1.45 2.32 V VCC = 1.8 V 0.30 0.49 0.62 0.23 0.62 V VCC = 2.3 V 0.40 0.58 0.80 0.34 0.80 V VCC = 3.0 V 0.50 0.6 1.00 0.44 1.00 V VCC = 4.5 V 0.71 0.76 1.20 0.65 1.20 V VCC = 5.5 V 0.71 0.86 1.40 0.65 1.40 V see Fig. 12, Fig. 13, Fig. 14 and Fig. 15 VT+ positivegoing threshold voltage see Fig. 12, Fig. 13, Fig. 14 and Fig. 15 VT- negativegoing threshold voltage see Fig. 12, Fig. 13, Fig. 14 and Fig. 15 VH hysteresis voltage [1]All typical values are measured at Tamb = 25℃. Rev. 1.0 – Aug 08, 2024 11 74LVC1G57 Low-power configurable multiple function gate 11.1. Waveforms transfer characteristics VO VT+ VI VI VH VTFig. 12. VT- VH VO VT+ and VT- limits at 70% and 20%. VT+ Transfer characteristic Fig. 13. Definition of VT+, VT- and VH VO VT+ VI VI VH VT- VH VO VT+ Fig. 14. Transfer characteristic Rev. 1.0 – Aug 08, 2024 VT- Fig. 15. Definition of VT+, VT- and VH 12 74LVC1G57 Low-power configurable multiple function gate 12. Package Outline SOT23-6L D b L1 E E1 L 0.2 e A A1 A2 b c D E1 E e e1 L L1 θ Rev. 1.0 – Aug 08, 2024 1.050 0.000 1.050 0.300 0.100 2.820 1.500 2.650 1.800 0.300 0° 0.950(BSC) 0.600REF. A A1 A2 e1 1.250 0.100 1.150 0.500 0.200 3.020 1.700 2.950 0.041 0.000 0.041 0.012 0.004 0.111 0.059 0.104 2.000 0.600 0.071 0.012 8° 0° 0.037(BSC) 0.024REF. 0.049 0.004 0.045 0.020 0.008 0.119 0.067 0.116 0.079 0.024 8° 13 74LVC1G57 Low-power configurable multiple function gate SOT363 Symbol A A1 A2 b c D E E1 e e1 L L1 Rev. 1.0 – Aug 08, 2024 Dimensions In Millimeters Min. Max. 0.900 1.100 0.000 0.100 1.000 0.900 0.150 0.350 0.110 0.175 2.000 2.200 1.150 1.350 2.150 2.450 0.650 TYP. 1.200 1.400 0.525 REF. 0.260 0.460 0° 8° Dimensions In Inches Min. Max. 0.035 0.043 0.000 0.004 0.035 0.039 0.006 0.014 0.004 0.007 0.079 0.087 0.045 0.053 0.085 0.096 0.026 TYP. 0.047 0.055 0.021 REF. 0.010 0.018 0° 8° 14 74LVC1G57 Low-power configurable multiple function gate 13. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model CDM Charged Device Model TTL Transistor-Transistor Logic 14. Revision History Table 13. Revision history Document ID Release Date Data sheet status 74LVC1G57Rev. 1.0 Aug 08, 2024 Product datasheet Rev. 1.0 – Aug 08, 2024 Change notice Supersedes 15