74AHC1G125;74AHCT1G125
Bus buffer/line driver; 3-state
Product datasheet, Rev. 1.0
Aug 08, 2024
1.General Description
The 74AHC1G125 and 74AHCT1G125 are single buffer/line drivers with 3-state outputs. Inputs
are overvoltage tolerant.This feature allows the use of these devices as translators in mixed
voltage environments.
2.Features and Benefits
Wide supply voltage range from 2.0 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
Latch-up performance exceeds 200 mA
Symmetrical output impedance
Balanced propagation delays
Input levels:
•
For 74AHC1G125: CMOS level
•
For 74AHCT1G125: TTL level
ESD protection:
•
HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 7000 V
•
CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
Multiple package options
Rev. 1.0 – Aug 08, 2024
1
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
3.Ordering Information
Table 1. Ordering information
Type number
74AHC1G125GV
74AHCT1G125GV
74AHC1G125GW
74AHCT1G125GW
74AHC1G125DRL
74AHCT1G125DRL
Package
Name
Description
Quantity
SOT23-5L
SOT23 package, 5 pins 2.92 mm × 1.6 mm; 1.25 mm
(Max) height
3000
SOT353
SOT353 package, 5 pins 2.1 mm × 1.25 mm; 1.1 mm
(Max) height
3000
SOT553
SOT553 package, 5 pins
1.6 mm × 1.2 mm; 0.6 mm (Max) height
3000
4.Function Diagram
Fig. 1. Logic symbol
Rev. 1.0 – Aug 08, 2024
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram
2
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
5.Pinning Information
5.1. Pinning
Fig. 4. Top view pin configuration SOT23-5L, SOT353 and SOT553
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
OE
1
Output enable input
A
2
Data input
GND
3
Ground (0V)
Y
4
Data output
VCC
5
Supply voltage
6.Functional Description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state
Input
Output
OE
A
Y
L
L
L
L
H
H
H
X
Z
Rev. 1.0 – Aug 08, 2024
3
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
7.Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not
recommended. In addition, extended exposure to stresses above the recommended operating conditions may
affect device reliability. The absolute maximum ratings are stress ratings only.
Table 4. Absolute Maximum Ratings
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND.
Symbol
Parameter
VCC
Conditions
Min
Max
Unit
supply voltage
-0.5
7.0
V
VI
input voltage
-0.5
7.0
V
IIK
input clamping current
IOK
output clamping current
IO
output current
ICC
supply current
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
VI < -0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
[1]
-0.5 V < VO < VCC + 0.5 V
-20
mA
±20
mA
±25
mA
75
mA
-75
mA
Tamb = -40 °C to + 125 °C
-65
250
mW
150
°C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
8.Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. MDD does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Table 5. Recommended Operating Conditions
Symbol
Parameter
VCC
Conditions
74AHC1G125
74AHCT1G125
Unit
Min
Typ
Max
Min
Typ
Max
supply voltage
2.0
5.0
5.5
2.0
5.0
5.5
V
VI
input voltage
0
5.5
0
5.5
V
VO
output voltage
0
VCC
0
VCC
V
Tamb
ambient temperature
125
-40
125
°C
Δt/ΔV
input transition rise and fall
rate
Rev. 1.0 – Aug 08, 2024
-40
25
25
VCC = 3.3 V ± 0.3 V
100
100
ns/V
VCC = 5.0 V ± 0.5 V
20
20
ns/V
4
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
9.Static Characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
-40 °C to +85 °C
Min
Typ[1]
-40 °C to +125 °C
Max
Min
Max
Unit
74AHC1G125
VIH
VIL
HIGH-level
input
voltage
LOW-level
input
voltage
VCC = 2.0 V
1.5
1.5
V
VCC = 3.0 V
2.1
2.1
V
VCC = 5.5 V
3.85
3.85
V
VCC = 2.0 V
0.5
0.5
V
VCC = 3.0 V
0.9
0.9
V
VCC = 5.5 V
1.65
1.65
V
VI = VIH or VIL
VOH
HIGH-level
output
voltage
IO = -50 μA; VCC = 2.0 V
1.9
2.0
1.9
V
IO = -50 μA; VCC = 3.0 V
2.9
3.0
2.9
V
IO = -50 μA; VCC = 4.5 V
4.4
4.5
4.4
V
IO = -4.0 mA; VCC = 3.0 V
2.48
2.93
2.40
V
IO = -8.0 mA; VCC = 4.5 V
3.80
4.39
3.70
V
VI = VIH or VIL
VOL
IOZ
II
ICC
CI
LOW-level
output
voltage
OFF-state
output
current
input
leakage
current
supply
current
input
capacitance
Rev. 1.0 – Aug 08, 2024
IO = 50 μA; VCC = 2.0 V
0
0.1
0.1
V
IO = 50 μA; VCC = 3.0 V
0
0.1
0.1
V
IO = 50 μA; VCC = 4.5 V
0
0.1
0.1
V
IO = 4.0 mA; VCC = 3.0 V
0.05
0.44
0.55
V
IO = 8.0 mA; VCC = 4.5 V
0.07
0.44
0.55
V
VCC = 5.5 V; VI = VCC or GND
0.01
2.5
10
μA
VI = 5.5 V or GND ;
VCC = 0 V to 5.5 V
±0.01
±1.0
±2.0
μA
VI = VCC or GND ; IO = 0 A ;
VCC = 5.5 V
0.01
10
40
μA
3.5
pF
5
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Symbol
Parameter
Conditions
-40 °C to +85 °C
Min
Typ[1]
-40 °C to +125 °C
Max
Min
Max
Unit
74AHCT1G125
VIH
VIL
HIGH-level
input voltage
LOW-level
input voltage
VCC = 2.0 V
1.0
1.0
V
VCC = 3.3 V
1.5
1.5
V
VCC = 4.5 V to 5.5 V
2.0
2.0
V
VCC = 2.0 V
0.3
0.3
V
VCC = 3.3 V
0.55
0.55
V
VCC = 4.5 V to 5.5 V
0.8
0.8
V
VI = VIH or VIL;
VOH
HIGH-level
output voltage
IO = -50 μA; VCC = 2.0 V
1.9
2.0
1.9
V
IO = -50 μA; VCC = 3.0 V
2.9
3.0
2.9
V
IO = -50 μA; VCC = 4.5 V
4.4
4.5
4.4
V
IO = -4.0 mA; VCC = 3.0 V
2.48
2.93
2.4
V
IO = -8.0 mA; VCC = 4.5 V
3.80
4.39
3.70
V
VI = VIH or VIL;
VOL
IOZ
II
LOW-level
output voltage
OFF-state
output current
input leakage
current
ICC
supply current
ΔICC
additional
supply current
CI
input
capacitance
IO = 50 μA; VCC = 2.0 V
0
0.1
0.1
V
IO = 50 μA; VCC = 3.0 V
0
0.1
0.1
V
IO = 50 μA; VCC = 4.5 V
0
0.1
0.1
V
IO = 4.0 mA; VCC = 3.0 V
0.05
0.44
0.55
V
IO = 8.0 mA; VCC = 4.5 V
0.07
0.44
0.55
V
0.01
2.5
10
μA
±0.01
±1.0
±2.0
μA
0.01
10
40
μA
0.23
1.35
1.35
mA
VCC = 5.5 V; VI = VCC or
GND
VI = 5.5 V or GND ;
VCC = 0 V to 5.5 V
VI = VCC or GND ; IO = 0 A ;
VCC = 5.5 V
per input pin ; VI = 3.4 V;
other inputs at VCC or
GND;
IO = 0 A; VCC = 5.5 V
3.5
pF
[1]All typical values are measured at Tamb = 25°C.
Rev. 1.0 – Aug 08, 2024
6
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
10. Dynamic Characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7.
Symbol
Parameter
-40 °C to +85 °C
Conditions
-40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
VCC = 3.0 V to 3.6 V, CL = 15 pF
1.0
5.7
8.5
1.0
9.0
ns
VCC = 4.5 V to 5.5 V, CL = 15 pF
1.0
3.9
5.5
1.0
6.0
ns
VCC = 3.0 V to 3.6 V, CL = 15 pF
1.0
6.3
10.0
1.0
11.0
ns
VCC = 4.5 V to 5.5 V, CL = 15 pF
1.0
4.5
6.5
1.0
7.0
ns
VCC = 3.0 V to 3.6 V, CL = 15 pF
1.0
4.7
14.0
1.0
14.5
ns
VCC = 4.5 V to 5.5 V, CL = 15 pF
1.0
3.9
7.5
1.0
8.0
ns
74AHC1G125
tpd
ten
tdis
CPD
propagation
delay
enable time
disable time
power
dissipation
capacitance
A
[2]
to
OE
[2]
Y;
to
OE
[2]
see
Y;
to
Y;
see
see
CL = 15 pF ; f = 1MHz ;
VI
=
GND
to
[3]
Fig.
Fig.
Fig.
VCC
5
6
6
;
20
pF
44
ns
74AHCT1G125
A
[2]
tpd
propagation
delay
tdis
enable time
disable time
Y;
see
5
VCC = 3.3 V, CL = 15 pF
2.0
5.5
12.5
2.0
13.0
ns
VCC = 4.5 V to 5.5 V, CL = 15 pF
1.0
5.0
7.5
1.0
8.0
ns
to
Y;
see
Fig.
6
VCC = 2.0 V, CL = 15 pF
79
ns
VCC = 3.3 V, CL = 15 pF
7.0
12.9
17.0
7.0
17.5
ns
VCC = 4.5 V to 5.5 V, CL = 15 pF
4.0
8.1
11
4.0
11.5
ns
OE
[2]
to
Y;
see
Fig.
6
VCC = 2.0 V, CL = 15 pF
VCC = 3.3 V, CL = 15 pF
Rev. 1.0 – Aug 08, 2024
Fig.
VCC = 2.0 V, CL = 15 pF
OE
[2]
ten
to
12
3.0
6.4
ns
9.5
3.0
10.0
ns
7
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
VCC = 4.5 V to 5.5 V, CL = 15 pF
CPD
power
dissipation
capacitance
CL = 15 pF ; f = 1MHz ;
VI
=
GND
to
[3]
VCC
2.0
;
4.1
6.5
21
2.0
7.0
ns
pF
[1] Typical values are measured at Tamb = 25 °C and VCC = 2.0 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
10.1. Waveforms and test circuit
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 5. The input A to output Y propagation delays
Rev. 1.0 – Aug 08, 2024
8
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6. 3-state enable and disable times
Table 8. Measurement points
Type
74AHC1G125
74AHCT1G125
Supply Voltage
Input
VCC
VI
VM
VM
VX
VY
3.0 V - 5.5 V
GND to VCC
0.5 x VCC
0.5 x VCC
VOL + 0.3 V
VOH - 0.3 V
2.0 V
GND to VCC
0.5 x VCC
0.5 x VCC
VOL + 0.15 V
VOH - 0.15 V
3.3 V
GND to 3.0 V
1.5 V
0.5 x VCC
VOL + 0.3 V
VOH - 0.3 V
4.5 V - 5.5 V
GND to 3.0 V
1.5 V
0.5 x VCC
VOL + 0.3 V
VOH - 0.3 V
Rev. 1.0 – Aug 08, 2024
Output
9
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 7. Test circuit for measuring switching times
Table 9. Test data
Input
Load
tr = tf
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
74AHC1G125
≤ 2.5 ns
15 pF
500 Ω
open
GND
VCC
74AHCT1G125
≤ 2.5 ns
15 pF
500 Ω
open
GND
VCC
Type
VEXT
11. Package Outline
SOT23-5L
Rev. 1.0 – Aug 08, 2024
10
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
SOT353
Rev. 1.0 – Aug 08, 2024
11
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
SOT553
Rev. 1.0 – Aug 08, 2024
12
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Rev. 1.0 – Aug 08, 2024
13
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
CDM
Charged Device Model
TTL
Transistor-Transistor Logic
13. Revision History
Table 11. Revision history
Document ID
Release Date
Data sheet status
74AHC_AHCT1G125 Rev. 1.0
Apr 20, 2024
Product datasheet
Rev. 1.0 – Aug 08, 2024
Change notice
Supersedes
14
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