74LVC1G32GV

74LVC1G32 Single 2-input OR gate Product datasheet, Rev1.0 Aug 08, 2024 1. General Description The 74LVC1G32is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2.Features and Benefits  Wide supply voltage range from 1.65 V to 5.5 V  Overvoltage tolerant inputs to 5.5 V  High noise immunity  CMOS low power dissipation  IOFF circuitry provides partial Power-down mode operation  ±24 mA output drive (VCC = 3.0 V)  Latch-up performance exceeds 100 mA  Direct interface with TTL levels  Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8-B/JESD36 (2.7 V to 3.6 V)  ESD protection: • HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V • MM JESD22-A115C Class C exceeds 550 V • CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V  Multiple package options Rev1.0– Aug 08, 2024 1 74LVC1G32 Single 2-input OR gate 3.Ordering Information Table 1. Ordering information Type number Topside Package marking Name 74LVC1G32GV VEYW 74LVC1G32GW Description Quantity SOT23-5L SOT23 package, 5 pins 2.92 mm × 1.6 mm; 1.25 mm (Max) height 3000 VEYW SOT353 SOT353 package, 5 pins 2.1 mm × 1.25 mm; 1.1 mm (Max) height 3000 74LVC1G32GS VE DFN1x1-6L DFN1×1 package, 6 pins 1 mm × 1 mm; 0.42 mm (Max) height 3000 74LVC1G32GM VEYW DFN1x1.45- DFN1.45×1 package, 6 pins 6L 1.45 mm × 1 mm; 0.6 mm (Max) height 3000 74LVC1G32GX VE DFN0.8x0.8- DFN0.8×0.8 package, 5pins 4L 0.8 mm × 0.8 mm; 0.4 mm (Max) height 3000 4.Function Diagram 1 2 B A Fig 1. Y Logic symbol Rev1.0– Aug 08, 2024 4 1 2 ≥1 B 4 Y A Fig 2. IEC logic symbol Fig 3. Logic diagram 2 74LVC1G32 Single 2-input OR gate 5.Pinning Information 5.1. Pin map B 1 A 2 GND 3 5 VCC 4 Y Fig 4. Top view pin configuration SOT23-5 and SOT353 B 1 B 1 6 VCC A 2 5 NC GND 3 4 Y Fig 5. Top view pin configuration DFN6L 5 VCC 3 GND A 4 Y 2 Fig 6. Top view pin configuration DFN4L 5.2. Pin description Table 2. Pin description Symbol Pin Description SOT23-5, SOT353 and DFN4L DFN6L B 1 1 Data input A 2 2 Data input GND 3 3 Ground (0V) Y 4 4 Data output NC - 5 Not connected VCC 5 6 Supply voltage Rev1.0– Aug 08, 2024 3 74LVC1G32 Single 2-input OR gate 6.Functional Description Table 3. Function table H = HIGH voltage level; L = LOW voltage level. Input Output A B Y L L L L H H H L H H H H 7.Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Table 4. Absolute Maximum Ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND. Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Conditions Min Max Unit -0.5 6.5 V VI < 0 V -50 [1] -0.5 VO > VCC or VO < 0 V mA 6.5 V ±50 mA Active mode [1] -0.5 VCC + 0.5 V Power-down mode; VCC = 0 V [1] -0.5 6.5 V ±50 mA 100 mA VO = 0 V to VCC -100 Tamb = -40 °C to + 125 °C -65 mA 250 mW 150 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Rev1.0– Aug 08, 2024 4 74LVC1G32 Single 2-input OR gate 8. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. EnergyMath does not recommend exceeding them or designing to Absolute Maximum Ratings. Table 5. Recommended Operating Conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV Input transition rise and fall rate Rev1.0– Aug 08, 2024 Conditions Min Typ Max Unit 1.65 5.5 V 0 5.5 V Active mode 0 VCC V Power-down mode; VCC = 0 V 0 5.5 V -40 125 °C VCC = 1.65 V to 2.7 V 20 ns/V VCC = 2.7 V to 5.5 V 10 ns/V 5 74LVC1G32 Single 2-input OR gate 9.Static Characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC = 1.65 V to 1.95 V VIH HIGH-level input VCC = 2.3 V to 2.7 V voltage VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V -40 °C to +85 °C Min Typ[1] LOW-level input voltage Max Min Max Unit 0.65VCC 0.65VCC V 1.7 1.7 V 2.0 2.0 V 0.7VCC 0.7VCC V VCC = 1.65 V to 1.95 V VIL -40 °C to +125 °C 0.35VCC 0.35VCC V VCC = 2.3 V to 2.7 V 0.7 0.7 V VCC = 2.7 V to 3.6 V 0.8 0.8 V VCC = 4.5 V to 5.5 V 0.3VCC 0.3VCC V VI = VIH or VIL IO = -100μA; VCC = 1.65 V to 5.5 V VOH HIGH-level output voltage VCC - 0.1 VCC - 0.1 V IO = -4 mA; VCC = 1.65 V 1.2 0.95 V IO = -8 mA; VCC = 2.3 V 1.9 1.7 V IO = -12 mA; VCC = 2.7 V 2.2 1.9 V IO = -24 mA; VCC = 3.0 V 2.3 2.0 V IO = -32 mA; VCC = 4.5 V 3.8 3.4 V VI = VIH or VIL VOL LOW-level output voltage IO = 100μA; VCC = 1.65 V to 5.5 V 0.10 0.10 V IO = 4 mA; VCC = 1.65 V 0.45 0.70 V IO = 8 mA; VCC = 2.3 V 0.30 0.45 V IO = 12 mA; VCC = 2.7 V 0.40 0.60 V IO = 24 mA; VCC = 3.0 V 0.55 0.80 V IO = 32 mA; VCC = 4.5 V 0.55 0.80 V II Input leakage current VI = 5.5 V or GND ; VCC = 0 V to 5.5 V ±0.1 ±1 ±1 μA IOFF power-off leakage current VCC = 0V ; VI or VO = 5.5 V ±0.1 ±2 ±2 μA Rev1.0– Aug 08, 2024 6 74LVC1G32 Single 2-input OR gate ICC supply current ΔICC CI VI = 5.5V or GND ; IO = 0A ; VCC = 1.65V to 5.5V 0.1 4 4 μA additional supply per pin ; VCC = 2.3V to 5.5V ; current VI = VCC -0.6V ; IO = 0A 5 500 500 μA input capacitance 5 VCC = 3.3V ; VI = GND to VCC pF [1]All typical values are measured at VCC = 3.3V and Tamb = 25℃. 10. Dynamic Characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8. Symbol Parameter CPD propagation delay power dissipation capacitance -40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.65 V to 1.95 V 3.4 9.4 15.9 3.4 16.3 ns VCC = 2.3 V to 2.7 V 2.4 5.0 8.6 2.4 9.1 ns VCC = 3.0 V to 3.6 V 1.8 3.9 6.0 1.8 6.3 ns VCC = 4.5 V to 5.5 V 1.4 2.6 3.6 1.4 3.8 ns A to Y; see Fig. 7 tpd -40 °C to +85 °C Conditions [2] VI = GND to VCC ; VCC = 3.3V [3] 24 pF [1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. Rev1.0– Aug 08, 2024 7 74LVC1G32 Single 2-input OR gate 10.1. Waveforms and test circuit VI A,B input VM VM GND tPHL tPLH VOH Y output VM VM VOL Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The input A, B to output Y propagation delays Table 8. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5VCC 0.5VCC 2.3 V to 2.7 V 0.5VCC 0.5VCC 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5VCC 0.5VCC Rev1.0– Aug 08, 2024 8 74LVC1G32 Single 2-input OR gate VEXT VCC G VI DUT RL VO RT CL RL Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr = tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 3.0 V to 3.6 V 3V ≤ 2.5 ns 50 pF 500 Ω open 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open Rev1.0– Aug 08, 2024 Load VEXT 9 74LVC1G32 Single 2-input OR gate 11. Package Outline SOT23-5L Rev1.0– Aug 08, 2024 10 74LVC1G32 Single 2-input OR gate SOT353 Rev1.0– Aug 08, 2024 11 74LVC1G32 Single 2-input OR gate DFN1x1-6L Rev1.0– Aug 08, 2024 12 74LVC1G32 Single 2-input OR gate DFN1x1.45-6L Rev1.0– Aug 08, 2024 13 74LVC1G32 Single 2-input OR gate DFN0.8x0.8-4L Rev1.0– Aug 08, 2024 14 74LVC1G32 Single 2-input OR gate 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision History Table 11. Revision history Document ID Release Date Data sheet status 74LVC1G32 Rev1.0 Aug 08, 2024 Product datasheet Rev1.0– Aug 08, 2024 Change notice Supersedes 15