74HCT138PW

74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Draft datasheet, Rev. 1.0 Aug 08, 2024 1.General Description The 74HC138 and 74HCT138 decode three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '138 ICs and one inverter. The '138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.Features and Benefits  Wide operating voltage 2.0 V to 6.0 V  High noise immunity  CMOS low power dissipation  Latch-up performance exceeds 250 mA  Demultiplexing capability  Multiple input enable for easy expansion  Ideal for memory chip select decoding  Active LOW mutually exclusive outputs  Input levels: • For 74HC138: CMOS level • For 74HCT138: TTL level  ESD protection: • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 3500 V • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2000 V  Multiple package options  Specified from -40 °C to +85 °C and from -40 °C to +125 °C Rev. 1.0 – Aug 08, 2024 1 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting 3.Ordering Information Table 1. Ordering information Type number 74HC138D 74HCT138D 74HC138PW 74HCT138PW Rev. 1.0 – Aug 08, 2024 Package Name Description Quantity SOP-16L plastic small outline package; 16 leads; body width 3.9 mm 2500 TSSOP-16L plastic thin shrink small outline package; 16 leads; body width 4.4 mm 2500 2 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting 4.Functional diagram Fig. 1. Logic symbol Fig. 2. Functional diagram Fig. 3. Logic diagram Rev. 1.0 – Aug 08, 2024 3 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting 5.Pinning Information 5.1. Pinning Fig. 4. Top view pin configuration SOP-20L and TSSOP-20L 5.2. Pin description Table 2. Pin description Symbol Pin Description A0, A1, A2 1, 2, 3 address input E1, E2 4, 5 enable input (active LOW) E3 6 enable input (active HIGH) Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 15, 14, 13, 12, 11, 10, 9, 7 output GND 8 ground (0 V) VCC 16 supply voltage Rev. 1.0 – Aug 08, 2024 4 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting 6.Functional Description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Control E1 H X X L Input E2 X H X L Output E3 A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X X L X X X H H H H H H H H H L L L L H H H H L L H H L L H H L H L H L H L H H H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H H Rev. 1.0 – Aug 08, 2024 5 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting 7.Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Table 4. Absolute Maximum Ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND. Symbol Parameter VCC supply voltage IIK input clamping current IOK Conditions Min Max Unit -0.5 7 V VI < -0.5 V or VI > VCC + 0.5 V ±20 mA output clamping current VO < -0.5 V or VO > VCC + 0.5 V ±20 mA IO output current -0.5V < VO < VCC + 0.5 V ±25 mA ICC supply current 50 mA IGND ground current Ptot total power dissipation Tstg storage temperature -50 mA Tamb = -40 °C to + 125 °C -65 500 mW +150 °C 8.Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. MDD does not recommend exceeding them or designing to Absolute Maximum Ratings. Table 5. Recommended Operating Conditions Symbol Parameter VCC Conditions 74HC138 74HCT138 Unit Min Min Typ Min Min Typ supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 VCC 0 VCC V VO output voltage 0 VCC 0 VCC V Tamb ambient temperature +125 -40 +125 °C Δt/ΔV input transition rise and fall rate Rev. 1.0 – Aug 08, 2024 -40 +25 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V +25 625 1.67 139 83 ns/V 1.67 139 ns/V ns/V 6 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting 9.Static Characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Typical values measured at Tamb = 25°C (unless otherwise noted). Symbol Parameter Conditions -40 °C to +85 °C Min Typ Max -40 °C to +125 °C Min Max Unit 74HC138 VIH VIL HIGH-level input voltage LOW-level input voltage VCC = 2.0 V 1.5 1.5 V VCC = 4.5 V 3.15 3.15 V VCC = 6.0 V 4.2 4.2 V VCC = 2.0 V 0.5 0.5 V VCC = 4.5 V 1.35 1.35 V VCC = 6.0 V 1.8 1.8 V VI = VIH or VIL VOH HIGH-level output voltage IO = -20 μA; VCC = 2.0 V 1.9 1.9 V IO = -20 μA; VCC = 4.5 V 4.4 4.4 V IO = -20 μA; VCC = 6.0 V 5.9 5.9 V IO = -4.0 mA; VCC = 4.5 V 3.84 3.7 V IO = -5.2 mA; VCC = 6.0 V 5.34 5.2 V VI = VIH or VIL VOL LOW-level output voltage II input leakage current ICC supply current CI input capacitance Rev. 1.0 – Aug 08, 2024 IO = 20 μA; VCC = 2.0 V 0.1 0.1 V IO = 20 μA; VCC = 4.5 V 0.1 0.1 V IO = 20 μA; VCC = 6.0 V 0.1 0.1 V IO = 4.0 mA; VCC = 4.5 V 0.33 0.4 V IO = 5.2 mA; VCC = 6.0 V 0.33 0.4 V ±1 ±1 μA 20 40 μA VI = VCC or GND ; VCC = 6.0 V VI = VCC or GND ; IO = 0 A ; VCC = 6.0 V 4.0 pF 7 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Symbol Parameter Conditions -40 °C to +85 °C Min Typ Max -40 °C to +125 °C Min Max Unit 74HCT138 VIH VIL VOH VOL II ICC ΔICC CI HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current supply current additional supply current input capacitance Rev. 1.0 – Aug 08, 2024 VCC = 4.5 V to 5.5 V 2.0 2.0 VCC = 4.5 V to 5.5 V 0.8 V 0.8 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V 4.4 4.4 V IO = -4.0 mA; VCC = 4.5 V 3.84 3.7 V VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V 0.1 0.1 V IO = 4.0 mA; VCC = 4.5 V 0.33 0.4 V ±1 ±1 μA 20 40 μA 400 490 μA VI = VCC or GND ; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per pin ; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V 4.0 pF 8 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting 10. Dynamic Characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7. Typical values measured at Tamb = 25°C (unless otherwise noted). Symbol Parameter -40 °C to +85 °C Conditions Min Typ -40 °C to +125 °C Max Min Max Unit 74HC138 An to Yn; see Fig. 5 VCC = 2.0 V 35 40 ns VCC = 4.5 V 20 25 ns VCC = 6.0 V 15 20 ns VCC = 2.0 V 35 40 ns VCC = 4.5 V 20 25 ns VCC = 6.0 V 15 20 ns VCC = 2.0 V 35 40 ns VCC = 4.5 V 20 25 ns VCC = 6.0 V 15 20 ns VCC = 2.0 V 9 11 ns VCC = 4.5 V 6 8 ns VCC = 6.0 V 4 5 ns E3 to Yn; see Fig. 5 tpd propagation delay En to Yn; see Fig. 6 Yn; see Fig. 5 and Fig. 6 tt transition time CPD power dissipation capacitance Rev. 1.0 – Aug 08, 2024 [1] CL = 50pF ; f = 1 MHz ; VI = GND to [3] [1] [1] [2] VCC 67 pF 9 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Symbol Parameter -40 °C to +85 °C Conditions Min Typ -40 °C to +125 °C Max Min Max Unit 74HCT138 tpd propagation delay tt transition time CPD power dissipation capacitance An to Yn; VCC = 4.5V; see Fig. [1] E3 to Yn; VCC = 4.5V; see Fig. [1] En to Yn; VCC = 4.5V see Fig. [1] Yn; VCC=4.5V; see Fig. 5 and [2] Fig. CL = 50pF ; f = 1 MHz ; VI = GND to VCC – 1.5 V [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. Rev. 1.0 – Aug 08, 2024 10 5 20 25 ns 5 20 25 ns 6 20 25 ns 6; 6 8 ns [3] 67 pF 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting 10.1. Waveforms and test circuit Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. Propagation delay input (An) and enable input (E3) to output (Yn) and transition time output (Yn) Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. Propagation delay enable input (En) to output (Yn) and transition time output (Yn) Table 8. Measurement points Type 74HC245 Rev. 1.0 – Aug 08, 2024 11 Input Output VM VM VX VY 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting 74HCT245 1.3 V 1.3 V 0.1VCC 0.9VCC Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 7. Test circuit for measuring switching times Table 9. Test data Type Input Load VEXT VI tr = tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 74HC245 VCC ≤ 2.5 ns 50 pF 500Ω open GND 2VCC 74HCT245 3V ≤ 2.5 ns 50 pF 500Ω open GND 2VCC Rev. 1.0 – Aug 08, 2024 12 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting 11. Package Outline SOP-16L Symbol A A1 A2 b c D e E E1 L θ Rev. 1.0 – Aug 08, 2024 13 Dimensions In Millimeters Min. Max. 1.750 —— 0.150 0.250 1.400 1.500 0.330 0.510 0.170 0.250 9.800 10.000 1.270(BSC) 5.900 6.100 3.800 4.000 0.400 1.270 0° 8° Dimensions In Inches Min. Max. 0.069 —— 0.006 0.010 0.055 0.059 0.013 0.020 0.007 0.010 0.386 0.394 0.050(BSC) 0.232 0.240 0.150 0.157 0.016 0.050 0° 8° 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting TSSOP-16L Symbol A A1 A2 b c D e E E1 L θ Rev. 1.0 – Aug 08, 2024 14 Dimensions In Millimeters Min. Max. 1.200 —— 0.020 0.100 0.800 1.000 0.190 0.300 0.090 0.200 4.900 5.100 0.650(BSC) 6.250 6.550 4.300 4.500 0.500 0.700 1° 7° Dimensions In Inches Min. Max. 0.047 —— 0.001 0.004 0.031 0.039 0.007 0.012 0.004 0.008 0.193 0.201 0.026(BSC) 0.252(BSC) 0.169 0.177 0.020 0.028 1° 7° 74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model CDM Charged Device Model TTL Transistor-Transistor Logic 13. Revision History Table 11. Revision history Document ID Release Date Data sheet status 74AHC_HCT138 Rev. 1.0 Apr 24, 2024 Draft datasheet Rev. 1.0 – Aug 08, 2024 15 Change notice Supersedes