74HCT00PW

74HC00; 74HCT00 Quad 2-input NAND gate Product datasheet, Rev. 1.0 Aug 08, 2024 1.General Description The 74HC00; 74HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.Features and Benefits  Wide supply voltage range from 2.0 V to 6.0 V  High noise immunity  CMOS low power dissipation  Latch-up performance exceeds 250 mA  Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V)  Input levels: • For 74HC00: CMOS level • For 74HCT00: TTL level  ESD protection:  • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 3500 V • CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V Multiple package options Rev. 1.0 – Aug 08, 2024 1 74HC00; 74HCT00 Quad 2-input NAND gate 3.Ordering Information Table 1. Ordering information Type number 74HC00D 74HCT00D 74HC00PW 74HCT00PW Package Name Description Quantity SOP-14L plastic small outline package; 14 leads; body width 3.9 mm 2500 TSSOP-14L plastic thin shrink small outline package; 14 leads; body width 4.4 mm 2500 4.Function Diagram Fig. 1. Logic symbol Rev. 1.0 – Aug 08, 2024 Fig. 2. IEC logic symbol Fig. 3. Logic diagram(one gate) 2 74HC00; 74HCT00 Quad 2-input NAND gate 5.Pinning Information 5.1. Pinning Fig. 4. Top view pin configuration SOP and TSSOP 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 Data input 1B, 2B, 3B, 4B 2, 5, 10, 13 Data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 Data output GND 7 Ground (0V) VCC 14 Supply voltage 6.Functional Description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Control Output nA nB nY L X H X L H H H L Rev. 1.0 – Aug 08, 2024 3 74HC00; 74HCT00 Quad 2-input NAND gate 7.Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Table 4. Absolute Maximum Ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND. Symbol Parameter Conditions VCC supply voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V IO output current VO = -0.5 V to (VCC + 0.5 V) ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Min Max Unit -0.5 7.0 V [1] ±20 mA [1] ±20 mA ±25 mA 50 mA -50 mA -65 500 mW 150 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 8.Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. MDD does not recommend exceeding them or designing to Absolute Maximum Ratings. Table 5. Recommended Operating Conditions Symbol Parameter VCC Conditions 74HC00 74HCT00 Unit Min Typ Max Min Typ Max supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 VCC 0 VCC V VO output voltage 0 VCC 0 VCC V Tamb ambient temperature -40 125 -40 125 °C Δt/ΔV input transition rise and fall rate Rev. 1.0 – Aug 08, 2024 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 625 1.67 139 83 ns/V 1.67 139 ns/V ns/V 4 74HC00; 74HCT00 Quad 2-input NAND gate 9.Static Characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Typical values measured at Tamb = 25°C (unless otherwise noted). Symbol Parameter Conditions -40 °C to +85 °C Min Typ Max -40 °C to +125 °C Min Max Unit 74HC00 VIH VIL HIGH-level input voltage LOW-level input voltage VCC = 2.0 V 1.5 1.5 V VCC = 4.5 V 3.15 3.15 V VCC = 6.0 V 4.2 4.2 V VCC = 2.0 V 0.5 0.5 V VCC = 4.5 V 1.35 1.35 V VCC = 6.0 V 1.8 1.8 V VI = VIH or VIL VOH HIGH-level output voltage IO = -20 μA; VCC = 2.0 V 1.9 1.9 V IO = -20 μA; VCC = 4.5 V 4.4 4.4 V IO = -20 μA; VCC = 6.0 V 5.9 5.9 V IO = -4.0 mA; VCC = 4.5 V 3.84 3.7 V IO = -5.2 mA; VCC = 6.0 V 5.34 5.2 V VI = VIH or VIL VOL II ICC CI LOW-level output voltage input leakage current supply current input capacitance Rev. 1.0 – Aug 08, 2024 IO = 20 μA; VCC = 2.0 V 0.1 0.1 V IO = 20 μA; VCC = 4.5 V 0.1 0.1 V IO = 20 μA; VCC = 6.0 V 0.1 0.1 V IO = 4.0 mA; VCC = 4.5 V 0.33 0.4 V IO = 5.2 mA; VCC = 6.0 V 0.33 0.4 V VI = VCC or GND ; VCC = 6.0 V ±1 ±1 μA VI = VCC or GND ; IO = 0 A ; VCC = 6.0 V 20 40 μA 7 pF 5 74HC00; 74HCT00 Quad 2-input NAND gate Symbol Parameter Conditions -40 °C to +85 °C Min Typ Max -40 °C to +125 °C Min Max Unit 74HCT00 VIH VIL VOH VOL II ICC ΔICC CI HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current supply current additional supply current input capacitance Rev. 1.0 – Aug 08, 2024 VCC = 4.5 V to 5.5 V 2.0 2.0 VCC = 4.5 V to 5.5 V 0.8 V 0.8 V VI = VIH or VIL; VCC = 4.5 V IO = -20 μA; 4.4 4.4 V IO = -4.0 mA; 3.84 3.7 V VI = VIH or VIL; VCC = 4.5 V IO = 20 μA; 0.1 0.1 V IO = 4.0 mA; 0.33 0.4 V ±1 ±1 μA 20 40 μA 1.55 1.85 mA VI = VCC or GND ; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per pin ; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V 10 pF 6 74HC00; 74HCT00 Quad 2-input NAND gate 10. Dynamic Characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6. Typical values measured at Tamb = 25°C (unless otherwise noted). Symbol Parameter -40 °C to +85 °C Conditions Min Typ -40 °C to +125 °C Max Min Max Unit 74HC00 nA, nB to nY; see Fig. 5 tpd propagation delay VCC = 2.0 V 35 40 ns VCC = 4.5 V 20 25 ns VCC = 6.0 V 15 20 ns VCC = 2.0 V 9 11 ns VCC = 4.5 V 6 8 ns VCC = 6.0 V 4 5 ns see Fig. 5 tt CPD transition time power dissipation capacitance [1] [2] CL = 15 pF; f = 1 MHz; VI = GND to VCC [3] nA, nB to nY; VCC = 4.5 V; see Fig. 5 [1] VCC = 4.5 V; see Fig. 5 [2] CL = 15 pF; f = 1 MHz; VI = GND to (VCC -1.5 V) [3] 18 pF 74HCT00 tpd tt CPD propagation delay transition time power dissipation capacitance 37 16 19 ns 6 8 ns pF [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of outputs. Rev. 1.0 – Aug 08, 2024 7 74HC00; 74HCT00 Quad 2-input NAND gate 10.1. Waveforms and test circuit Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. The input to output propagation delays Table 8. Measurement points Input Output VM VM VX VY 74HC00 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT00 1.3 V 1.3 V 0.1VCC 0.9VCC Type Rev. 1.0 – Aug 08, 2024 8 74HC00; 74HCT00 Quad 2-input NAND gate Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 6. Test circuit for measuring switching times Table 9. Test data Type Input Load VEXT VI tr = tf CL RL tPLH, tPHL 74HC00 VCC ≤ 2.5 ns 15 pF 500Ω open 74HCT00 3V ≤ 2.5 ns 15 pF 500Ω open Rev. 1.0 – Aug 08, 2024 9 74HC00; 74HCT00 Quad 2-input NAND gate 11. Package Outline SOP-14L Rev. 1.0 – Aug 08, 2024 10 74HC00; 74HCT00 Quad 2-input NAND gate TSSOP-14L Rev. 1.0 – Aug 08, 2024 11 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 1.0 – Aug 08, 2024 12 74HC00; 74HCT00 Quad 2-input NAND gate 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model CDM Charged Device Model TTL Transistor-Transistor Logic 13. Revision History Table 11. Revision history Document ID Release Date Data sheet status 74HC_HCT00 Rev. 1.0 Aug 30, 2024 Product datasheet Rev. 1.0 – Aug 08, 2024 13 Change notice Supersedes