74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Draft datasheet, Rev. 1.0
Aug 08, 2024
1.General Description
The 74HC574 and 74HCT574 are 8-bit D-type transparent latches with 3-state outputs. The
device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of
their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH
clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state.
Operation of the OE input does not affect the state of the flip-flops. Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2.Features and Benefits
Wide operating voltage 2.7 V to 6.0 V
High noise immunity
CMOS low power dissipation
Latch-up performance exceeds 250 mA
Input levels:
•
For 74HC574: CMOS level
•
For 74HCT574: TTL level
Inputs and outputs on opposite sides of package allowing easy interface with
microprocessors
Useful as input or output port for microprocessors and microcomputers
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
Complies with JEDEC standards:
•
JESD8C (2.7 V to 3.6 V)
•
JESD7A (2.7 V to 6.0 V)
ESD protection:
•
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 3500 V
•
CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Rev. 1.0 – Aug 08, 2024
1
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
3.Ordering Information
Table 1. Ordering information
Type number
74HC574D
74HCT574D
74HC574PW
74HCT574PW
Package
Name
Description
Quantity
SOP-20L
plastic small outline package; 20 leads;
body width 7.5 mm
2000
TSSOP-20L
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
2000
4.Function Diagram
Fig. 1. Functional diagram
Rev. 1.0 – Aug 08, 2024
2
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Fig. 2. Logic diagram
Fig. 3. Logic symbol
Rev. 1.0 – Aug 08, 2024
Fig. 4. IEC logic symbol
3
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
5.Pinning Information
5.1. Pinning
Fig. 5. Top view pin configuration SOP-20L and TSSOP-20L
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
OE
1
3-state output enable input (active LOW)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
19,18,17,16,15,14,13,12
3-state flip-flop outputs
D0, D1, D2, D3, D4, D5, D6, D7
2, 3, 4, 5, 6, 7, 8, 9
data inputs
GND
10
ground (0 V)
CP
11
clock input (LOW-to-HIGH, edge triggered)
VCC
20
supply voltage
Rev. 1.0 – Aug 08, 2024
4
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
6.Functional Description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition.
Operating modes
Load and read register
Load register and disable output
Rev. 1.0 – Aug 08, 2024
Input
Outputs
OE
CP
Dn
Internal
flip-flop
L
↑
I
L
L
L
↑
h
H
H
H
↑
l
L
Z
H
↑
h
H
Z
Qn
5
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
7.Absolute Maximum Ratings
Stresses exceeding the absolut`e maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not
recommended. In addition, extended exposure to stresses above the recommended operating conditions may
affect device reliability. The absolute maximum ratings are stress ratings only.
Table 5. Absolute Maximum Ratings
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND.
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
IOK
Conditions
Min
Max
Unit
-0.5
7
V
VI < -0.5 V or VI > VCC + 0.5 V
±20
mA
output clamping current
VO < -0.5 V or VO > VCC + 0.5 V
±20
mA
IO
output current
-0.5V < VO < VCC + 0.5 V
±35
mA
ICC
supply current
70
mA
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
-70
mA
Tamb = -40 °C to + 125 °C
-65
500
mW
+150
°C
8.Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. MDD does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Table 6. Recommended Operating Conditions
Symbol
Parameter
VCC
Conditions
74HC574
74HCT574
Unit
Min
Min
Typ
Min
Min
Typ
supply voltage
2.7
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
VCC
0
VCC
V
VO
output voltage
0
VCC
0
VCC
V
Tamb
ambient temperature
+125
-40
+125
°C
△t/△V
input transition rise and
fall rate
Rev. 1.0 – Aug 08, 2024
-40
+25
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
+25
625
1.67
139
83
ns/V
1.67
139
ns/V
ns/V
6
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
9.Static Characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
-40 °C to +85 °C
Min
Typ[1]
-40 °C to +125 °C
Max
Min
Max
Unit
74HC574
VIH
VIL
HIGH-level
input
voltage
LOW-level
input
voltage
VCC = 3.0 V
2.0
2.0
V
VCC = 4.5 V
3.15
3.15
V
VCC = 6.0 V
4.2
4.2
V
VCC = 3.0 V
0.6
0.6
V
VCC = 4.5 V
1.35
1.35
V
VCC = 6.0 V
1.8
1.8
V
VI = VIH or VIL
VOH
HIGH-level
output
voltage
IO = -20μA; VCC = 3.0 V
2.9
2.9
V
IO = -20μA; VCC = 4.5 V
4.4
4.4
V
IO = -20μA; VCC = 6.0 V
5.9
5.9
V
IO = -6.0 mA; VCC = 4.5 V
3.84
3.7
V
IO = -7.8 mA; VCC = 6.0 V
5.34
5.2
V
VI = VIH or VIL
VOL
II
IOZ
ICC
CI
LOW-level
output
voltage
input
leakage
current
OFF-state
output
current
supply
current
input
capacitance
Rev. 1.0 – Aug 08, 2024
IO = 20μA; VCC = 3.0 V
0.1
0.1
V
IO = 20μA; VCC = 4.5 V
0.1
0.1
V
IO = 20μA; VCC = 6.0 V
0.1
0.1
V
IO = 6.0 mA; VCC = 4.5 V
0.33
0.4
V
IO = 7.8 mA; VCC = 6.0 V
0.33
0.4
V
VI = VCC or GND ;
VCC = 6.0 V
±1
±1
μA
VI = VIH or VIL ; VCC = 6.0V ;
VO = VCC or GND
±5
±10
μA
VI = VCC or GND ; IO = 0A ;
VCC = 6.0 V
20
40
μA
6.5
pF
7
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Symbol
74HCT574
VIH
VIL
VOH
VOL
II
IOZ
Parameter
HIGH-level
input
voltage
LOW-level
input
voltage
HIGH-level
output
voltage
LOW-level
output
voltage
input
leakage
current
OFF-state
output
current
ICC
supply
current
ΔICC
additional
supply
current
CI
input
capacitance
Conditions
VCC = 4.5 V to 5.5 V
-40 °C to +85 °C
Min
Typ[1]
-40 °C to +125 °C
Max
2.0
Min
Max
2.0
VCC = 4.5 V to 5.5 V
0.8
Unit
V
0.8
V
VI = VIH or VIL; VCC = 4.5 V
IO = -20μA
4.4
4.4
V
IO = -6.0 mA
3.84
3.7
V
VI = VIH or VIL; VCC = 4.5 V
IO = 20μA
0.1
0.1
V
IO = 6.0 mA
0.33
0.4
V
VI = VCC or GND ;
VCC = 5.5 V
±1
±1
μA
VI = VIH or VIL ; VCC = 5.5 V ;
VO = VCC or GND
±5
±10
μA
20
40
μA
450
490
μA
VI = VCC or GND ; IO = 0 A ;
VCC = 5.5 V
per pin ; VI = VCC – 2.1 V ; IO =
0 A ; other inputs at VCC or
GND ;
VCC = 4.5 V to 5.5 V
6.5
pF
[1]All typical values are measured at Tamb = 25°C.
Rev. 1.0 – Aug 08, 2024
8
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
10. Dynamic Characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 9.
Symbol
Parameter
-40 °C to +85 °C
Conditions
Min
Typ[1]
-40 °C to +125 °C
Max
Min
Max
Unit
74HC574
CP to Qn; see Fig. 6
tpd
propagation
delay
VCC = 3.0 V
30
35
ns
VCC = 4.5 V
20
25
ns
VCC = 6.0 V
15
18
ns
VCC = 3.0 V
22
25
ns
VCC = 4.5 V
14
17
ns
VCC = 6.0 V
13
16
ns
VCC = 3.0 V
22
25
ns
VCC = 4.5 V
15
18
ns
VCC = 6.0 V
13
15
ns
VCC = 3.0 V
8
10
ns
VCC = 4.5 V
7
9
ns
VCC = 6.0 V
7
9
ns
OE to Qn; see Fig. 8
ten
enable time
[2]
[3]
OE to Qn; see Fig. 8
tdis
disable time
[4]
Qn; see Fig. 6
tt
transition
time
CP HIGH or LOW; see Fig. 7
tW
pulse width
VCC = 3.0 V
25
30
ns
VCC = 4.5 V
20
24
ns
VCC = 6.0 V
17
20
ns
VCC = 3.0 V
16
20
ns
VCC = 4.5 V
15
18
ns
VCC = 6.0 V
13
15
ns
VCC = 3.0 V
5
5
ns
VCC = 4.5 V
5
5
ns
VCC = 6.0 V
5
5
ns
Dn to CP; see Fig.7
tSU
set up time
Dn to CP; see Fig.7
th
hold time
Rev. 1.0 – Aug 08, 2024
9
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Symbol
Parameter
-40 °C to +85 °C
Conditions
Min
Typ[1]
-40 °C to +125 °C
Unit
Max
CP; see Fig. 6
fmax
CPD
maximum
frequency
power
dissipation
capacitance
VCC = 3.0 V
20
16
MHz
VCC = 4.5 V
24
20
MHz
VCC = 6.0 V
28
24
MHz
fi = 1 MHz;
VI = GND to VCC ;
[6]
[2]
30
pF
74HCT574
tpd
propagation
delay
CP to Qn; see Fig. 6
tt
transition
time
Qn; see Fig. 6
ten
enable time
tdis
disable time
tW
pulse width
tSU
set up time
th
hold time
fmax
maximum
frequency
CPD
power
dissipation
capacitance
VCC = 4.5 V
7
9
ns
20
25
ns
20
25
ns
[4]
VCC = 4.5 V
CP HIGH or LOW; see Fig. 7
VCC = 4.5 V
20
24
ns
15
18
ns
5
5
ns
24
20
ns
Dn to CP; see Fig.7
VCC = 4.5 V
Dn to CP; see Fig.7
VCC = 4.5 V
CP; see Fig.6
VCC = 4.5 V
fi = 1 MHz;
VI = GND to VCC – 1.5 V ;
[6]
[1] Typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL.
[3] ten is the same as tPZL and tPZH.
[4] tdis is the same as tPLZ and tPHZ.
[5] tt is the same as tTHL and tTLH.
[6] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
Rev. 1.0 – Aug 08, 2024
10
ns
[3]
VCC = 4.5 V
OE to Qn; see Fig. 8
30
[5]
VCC = 4.5 V
OE to Qn; see Fig. 8
25
30
pF
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
10.1. Waveforms and test circuit
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 6. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width
and the maximum frequency (CP)
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 7. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold
times
Rev. 1.0 – Aug 08, 2024
11
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 8.
Enable and disable times
Table 8. Measurement points
Input
Output
VM
VM
VX
VY
74HC574
0.5VCC
0.5VCC
0.1VCC
0.9VCC
74HCT574
1.3 V
1.3 V
0.1VCC
0.9VCC
Type
Rev. 1.0 – Aug 08, 2024
12
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 9. Test circuit for measuring switching times
Table 9. Test data
Type
Input
Load
VEXT
VI
tr = tf
CL
RL
tPZL, tPLZ
tPHL, tPLH
tPZH, tPHZ
74HC574
VCC
2.5 ns
50 pF
500Ω
VCC
Open
GND
74HCT574
3V
2.5 ns
50 pF
500Ω
VCC
Open
GND
Rev. 1.0 – Aug 08, 2024
13
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 1.0 – Aug 08, 2024
14
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
11. Package Outline
SOP-20L
Symbol
A
A1
A2
A3
B
B1
C
C1
C2
C3
Dimensions In Millimeters
Min.
Max.
12.600
12.900
0.381
0.431
1.240
1.300
0.450
0.460
7.400
7.600
10.206
10.406
2.150
2.300
0.938
1.038
0.938
1.2038
0.145
0.205
Rev. 1.0 – Aug 08, 2024
15
Symbol
C4
D
D1
D2
R1
R2
θ1
θ2
θ3
Dimensions In Millimeters
Min.
Max.
0.246
0.262
1.353
1.453
0.764
0.964
0.18TYP
0.30TYP
0.20TYP
12° TYP
12° TYP
0° ~ 8°
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
TSSOP-20L
Symbol
A
A1
A2
A3
b
b1
c
c1
D
E1
Dimensions In Millimeters
Min.
Max.
1.20
0.05
0.15
0.80
1.05
0.39
0.49
0.20
0.28
0.19
0.25
0.13
0.17
0.12
0.14
6.40
6.60
4.30
4.50
Rev. 1.0 – Aug 08, 2024
16
Symbol
E
e
L
L1
θ
Dimensions In Millimeters
Min.
Max.
6.20
6.60
0.65BSC
0.45
0.75
1.00REF
0°
8°
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
CDM
Charged Device Model
TTL
Transistor-Transistor Logic
13. Revision History
Table 11. Revision history
Document ID
Release Date
Data sheet status
74HC_HCT574 Rev. 1.0
Apr 24, 2025
Draft datasheet
Rev. 1.0 – Aug 08, 2024
17
Change notice
Supersedes
