74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Product datasheet, Rev. 1.0
Aug 08, 2024
1.General Description
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual
data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs.
Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH
clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in
the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs
include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of VCC.
2.Features and Benefits
Wide operating voltage 2.0 V to 6.0 V
High noise immunity
CMOS low power dissipation
Input levels:
• For 74HC74: CMOS level
• For 74HCT74: TTL level
Symmetrical output impedance
Balanced propagation delays
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
•
JESD8C (2.7 V to 3.6 V)
•
JESD7A (2.0 V to 6.0 V)
ESD protection:
•
HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 3500 V
•
CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
Multiple package options
Rev. 1.0 – Aug 08, 2024
1
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
3.Ordering Information
Table 1. Ordering information
Type number
74HC74D
74HCT74D
74HC74PW
74HCT74PW
Package
Name
Description
Quantity
SOP-14L
plastic small outline package; 14 leads;
body width 3.9 mm
2500
TSSOP14L
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
2500
4.Function Diagram
Fig. 1. Logic symbol
Rev. 1.0 – Aug 08, 2024
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram
2
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Fig. 4. Logic diagram for one flip-flop
5.Pinning Information
5.1. Pinning
Fig. 5. Top view pin configuration SOP-14L and TSSOP14L
Rev. 1.0 – Aug 08, 2024
3
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
1RD, 2RD
1, 13
asynchronous reset-direct input (active LOW)
1D, 2D
2, 12
data output
1CP, 2CP
3,11
clock input (LOW-to-HIGH, edge-triggered)
1SD, 2SD
4,10
asynchronous set-direct input (active LOW)
1Q, 2Q
5,9
output
1Q, 2Q
6,8
complement output
GND
7
ground (0 V)
VCC
14
supply voltage
6.Functional Description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input
Output
nSD
nRD
nCP
nD
nQ
nQ
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑ = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition.
Input
Output
nSD
nRD
nCP
nD
nQn+1
nQn+1
H
H
↑
L
L
H
H
H
↑
H
H
L
Rev. 1.0 – Aug 08, 2024
4
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
7.Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function
or be operable above the recommended operating conditions and stressing the parts to these levels is
not recommended. In addition, extended exposure to stresses above the recommended operating
conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Table 5. Absolute Maximum Ratings
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND.
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
IOK
Conditions
Min
Max
Unit
-0.5
7
V
VI < -0.5 V or VI > VCC + 0.5 V
±20
mA
output clamping current
VO < -0.5 V or VO > VCC + 0.5 V
±20
mA
IO
output current
-0.5V < VO < VCC + 0.5 V
±25
mA
ICC
supply current
100
mA
IGND
ground current
Ptot
total power dissipation
Tstg
storage temperature
-100
mA
Tamb = -40 °C to + 125 °C
-65
500
mW
+150
°C
8.Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation.
Recommended operating conditions are specified to ensure optimal performance to the datasheet
specifications. MDD does not recommend exceeding them or designing to Absolute Maximum Ratings.
Table 6. Recommended Operating Conditions
Symbol
Parameter
VCC
VI
Conditions
74HC74
74HCT74
Unit
Min
Typ
Max
Min
Typ
Max
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
input voltage
0
VCC
0
VCC
V
VO
output voltage
0
VCC
0
VCC
V
Tamb
ambient temperature
+125
-40
+25
+125
°C
Δt/ΔV
input transition rise and
fall rate
1.67
139
Rev. 1.0 – Aug 08, 2024
-40
+25
625
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.67
139
83
ns/V
ns/V
ns/V
5
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
9.Static Characteristics
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
-40 °C to +85 °C
Max
-40 °C to +125 °C
Min
Max
Unit
Min
Typ[1]
VCC = 2.0 V
1.5
1.2
1.5
V
VCC = 4.5 V
3.15
2.5
3.15
V
VCC = 6.0 V
4.2
3.3
4.2
V
74HC74
VIH
VIL
VOH
VOL
II
ICC
CI
HIGH-level
input
voltage
LOW-level
input
voltage
HIGH-level
output
voltage
LOW-level
output
voltage
Input
leakage
current
supply
current
input
capacitance
Rev. 1.0 – Aug 08, 2024
VCC = 2.0 V
0.8
0.5
0.5
V
VCC = 4.5 V
2.1
1.35
1.35
V
VCC = 6.0 V
2.8
1.8
1.8
V
VI = VIH or VIL
IO = -4.0 mA; VCC = 4.5 V
3.84
4.4
3.7
V
IO = -5.2 mA; VCC = 6.0 V
5.34
5.9
5.2
V
VI = VIH or VIL
IO = 4.0 mA; VCC = 4.5 V
0.03
0.33
0.4
V
IO = 5.2 mA; VCC = 6.0 V
0.04
0.33
0.4
V
VI = VCC or GND ;
VCC = 6.0 V
0.01
±1
±1
μA
VI = VCC or GND ; IO = 0A ;
VCC = 6.0 V
0.01
20
40
μA
7
pF
6
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Symbol
Parameter
Conditions
-40 °C to +85 °C
Min
Typ[1]
-40 °C to +125 °C
Max
Min
Max
Unit
74HCT74
VIH
VIL
VOH
VOL
II
ICC
ΔICC
CI
HIGH-level
input
voltage
LOW-level
input
voltage
HIGH-level
output
voltage
LOW-level
output
voltage
Input
leakage
current
supply
current
additional
supply
current
input
capacitance
VCC = 4.5 V to 5.5 V
2.0
VCC = 4.5 V to 5.5 V
1.7
2.0
V
1.3
0.8
0.8
V
4.4
-
IO = 4.0 mA
0.03
0.33
0.4
V
VI = VCC or GND ;
VCC = 5.5 V
0.01
±1
±1
μA
0.01
20
40
μA
350
500
550
μA
640
850
950
μA
1130
1550
1650
μA
VI = VIH or VIL; VCC = 4.5 V
IO = -4.0 mA
3.84
3.7
V
VI = VIH or VIL; VCC = 4.5 V
VI = VCC or GND ; IO = 0A ;
VCC = 5.5 V
VI = VCC - 2.1 V; IO = 0 A; other
inputs at VCC or GND;VCC = 4.5
V to 5.5 V
per input pin;
nD,nRD inputs
per input pin;
nSD inputs
per input pin;
nCP inputs
7
pF
[1]All typical values are measured at Tamb = 25℃.
Rev. 1.0 – Aug 08, 2024
7
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
10. Dynamic Characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8.
Symbol
Parameter
-40 °C to +85 °C
Conditions
Min
Typ[1]
-40 °C to +125 °C
Max
Min
Max
Unit
74HC74
nCP to nQ, nQ; see Fig. 6
VCC = 2.0 V
30
33
ns
VCC = 4.5 V
16
19
ns
VCC = 6.0 V
12
14
ns
VCC = 2.0 V
30
33
ns
VCC = 4.5 V
16
19
ns
VCC = 6.0 V
12
14
ns
VCC = 2.0 V
30
33
ns
VCC = 4.5 V
16
19
ns
VCC = 6.0 V
12
14
ns
VCC = 2.0 V
9
11
ns
VCC = 4.5 V
6
8
ns
VCC = 6.0 V
4
5
ns
nSD to nQ, nQ; see Fig. 7
tpd
propagation
delay
nRD to nQ, nQ; see Fig. 7
nQ, nQ;see Fig. 6
tt
transition
time
[2]
[2]
[2]
[3]
nCP HIGH or LOW; see Fig. 6
tw
pulse width
Rev. 1.0 – Aug 08, 2024
VCC = 2.0 V
100
120
ns
VCC = 4.5 V
20
24
ns
VCC = 6.0 V
17
20
ns
VCC = 2.0 V
100
120
ns
VCC = 4.5 V
20
24
ns
VCC = 6.0 V
17
20
ns
nSD, nRD LOW;see Fig. 7
8
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Symbol
Parameter
-40 °C to +85 °C
Conditions
Min
Typ[1]
-40 °C to +125 °C
Max
Min
Max
Unit
nSD, nRD;see Fig. 7
trec
recovery
time
VCC = 2.0 V
40
45
ns
VCC = 4.5 V
8
9
ns
VCC = 6.0 V
7
8
ns
VCC = 2.0 V
75
90
ns
VCC = 4.5 V
15
18
ns
VCC = 6.0 V
13
15
ns
VCC = 2.0 V
3
3
ns
VCC = 4.5 V
3
3
ns
VCC = 6.0 V
3
3
ns
VCC = 2.0 V
4.8
4.0
MHz
VCC = 4.5 V
24
20
MHz
VCC = 6.0 V
28
24
MHz
nD to nCP; see Fig. 6
tsu
set-up time
nD to nCP; see Fig. 6
th
hold time
nCP; see Fig. 6
fmax
CPD
maximum
frequency
power
dissipation
capacitance
VI = GND
[4]
f = 1MHz
to
VCC
;
23
pF
74HCT74
nCP to nQ, nQ; see Fig. 6
[2]
VCC = 4.5 V
tpd
propagation
delay
16
19
ns
16
19
ns
16
19
ns
6
8
ns
nSD to nQ, nQ ; see Fig. 7
[2]
VCC = 4.5 V
nRD to nQ, nQ ; see Fig. 7
[2]
VCC = 4.5 V
tt
transition
time
nQ,
[3]
nQ
;see
Fig.
6
VCC = 4.5 V
nCP HIGH or LOW; see Fig. 6
tw
pulse width
VCC = 4.5 V
23
27
ns
nSD, nRD LOW;see Fig. 7
Rev. 1.0 – Aug 08, 2024
9
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
VCC = 4.5 V
20
24
-40 °C to +85 °C
Symbol
Parameter
Conditions
trec
recovery
time
nSD, nRD;see Fig. 7
tsu
set-up time
th
hold time
fmax
maximum
frequency
nCP; see Fig. 6
CPD
power
dissipation
capacitance
VI = GND
[4]
f = 1MHz
Min
VCC = 4.5 V
Typ[1]
Max
ns
-40 °C to +125 °C
Min
Max
Unit
8
9
ns
15
18
ns
3
3
ns
22
18
MHz
nD to nCP; see Fig. 6
VCC = 4.5 V
nD to nCP; see Fig. 6
VCC = 4.5 V
VCC = 4.5 V
to
VCC
;
24
pF
[1] Typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTHL and tTLH.
[4] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
Rev. 1.0 – Aug 08, 2024
10
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
10.1. Waveforms and test circuit
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6. The Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse
width and the maximum frequency (CP)
Rev. 1.0 – Aug 08, 2024
11
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 7. The set (nSD) and reset (nRD) input to output (nQ,nQ) propagation delays, set and reset pulse
widths and the nSD, nRD to nCP recovery time
Table 9. Measurement points
Input
Output
VM
VM
74HC74
0.5VCC
0.5VCC
74HCT74
1.3V
1.3V
Type
Rev. 1.0 – Aug 08, 2024
12
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator..
Fig. 8. Test circuit for measuring switching times
Table 10. Test data
Type
Input
Load
Test
VI
tr = tf
CL
74HC74
VCC
≤ 2.5 ns
15 pF
tPLH, tPHL
74HCT74
3V
≤ 2.5 ns
15 pF
tPLH, tPHL
Rev. 1.0 – Aug 08, 2024
13
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
11. Package Outline
SOP-14L
Rev. 1.0 – Aug 08, 2024
14
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
TSSOP-14L
Rev. 1.0 – Aug 08, 2024
15
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
12. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
CDM
Charged Device Model
TTL
Transistor-Transistor Logic
13. Revision History
Table 12. Revision history
Document ID
Release Date
Data sheet status
74HC74_HCT74 Rev. 1.0
Aug 28, 2024
Product datasheet
Rev. 1.0 – Aug 08, 2024
Change notice
Supersedes
16
