ZB25VQ32DSJG

ZB25VQ32D_DTR 3V 32M-BIT SERIAL NOR FLASH WITH DUAL AND QUAD SPI, QPI&DTR Zbit Semiconductor, Inc. 1 ZB25VQ32D_DTR Contents FEATURES ................................................................................................................................................ 5 GENERAL DESCRIPTION ........................................................................................................................ 6 1 ORDERING INFORMATION ............................................................................................................... 7 2 BLOCK DIAGRAM .............................................................................................................................. 8 3 CONNECTION DIAGRAMS................................................................................................................ 9 4 SIGNAL DESCRIPTIONS ................................................................................................................. 10 4.1 Serial Data Input (DI) / IO0 ................................................................................................. 10 4.2 Serial Data Output (DO) / IO1 ............................................................................................ 10 4.3 Serial Clock (CLK) .............................................................................................................. 10 4.4 Chip Select (CS#) ............................................................................................................... 10 4.5 Write Protect (WP#) / IO2 ................................................................................................... 10 4.6 HOLD (HOLD#) / IO3 ..........................................................................................................11 4.7 RESET (RESET#) / IO3 ......................................................................................................11 5 MEMORY ORGANIZATION .............................................................................................................. 12 5.1 5Flash Memory Array ......................................................................................................... 12 5.2 Security Registers .............................................................................................................. 12 5.2.1 Security Register 0 ........................................................................................................... 12 5.2.2 Serial Flash Discoverable Parameters (SFDP) Address Map ......................................... 13 5.2.3 SFDP Header Field Definitions......................................................................................... 14 5.2.4 JEDEC SFDP Basic SPI Flash Parameter ....................................................................... 15 6 FUNCTION DESCRIPTION .............................................................................................................. 21 6.1 SPI Operations ................................................................................................................... 21 6.1.1 SPI Modes ........................................................................................................................ 21 6.1.2 Dual SPI Modes ................................................................................................................ 21 6.1.3 Quad SPI Modes .............................................................................................................. 21 6.1.4 QPI Function ..................................................................................................................... 22 6.1.5 SPI / QPI DTR Read Function .......................................................................................... 22 6.1.6 Hold Function.................................................................................................................... 22 6.1.7 Software Reset & Hardware RESET# pin ........................................................................ 22 6.2 Status Register ................................................................................................................... 23 6.2.1 BUSY ................................................................................................................................ 24 6.2.2 Write Enable Latch (WEL) ................................................................................................ 25 6.2.3 Block Protect Bits (BP2, BP1, BP0) ................................................................................. 25 6.2.4 Top / Bottom Block Protect (TB) ....................................................................................... 25 6.2.5 Sector / Block Protect (SEC) ............................................................................................ 25 6.2.6 Complement Protect (CMP) ............................................................................................. 25 6.2.7 The Status Register Protect (SRP1, SRP0) ..................................................................... 25 6.2.8 Erase / Program Suspend Status (SUS1, SUS2) ............................................................ 26 6.2.9 Security Register Lock Bits (LB3, LB2, LB1).................................................................... 26 6.2.10 Quad Enable (QE) .......................................................................................................... 26 6.2.11 HOLD# or RESET# Pin Function (HRSW) ..................................................................... 26 6.2.12 Output Driver Strength (DRV1, DRV0) ........................................................................... 26 6.2.13 High Frequency Mode Enable Bit (HFM) ....................................................................... 26 6.2.14 Dummy Configuration (DC) ............................................................................................ 26 7 INSTRUCTIONS ............................................................................................................................... 31 7.1 Configuration and Status Commands ................................................................................ 36 7.1.1 Read Status Register (05h/35h/15h) ................................................................................ 36 7.1.2 Write Enable (06h) ............................................................................................................ 37 7.1.3 Write Enable for Volatile Status Register (50h) ................................................................ 37 7.1.4 Write Disable (04h) ........................................................................................................... 38 7.1.5 Write Status Register (01h/31h/11h) ................................................................................ 38 Zbit Semiconductor, Inc. 2 ZB25VQ32D_DTR 7.2 8 9 Program and Erase Commands ......................................................................................... 40 7.2.1 Page Program (PP) (02h) ................................................................................................. 40 7.2.2 Quad Input Page Program (32h) ...................................................................................... 41 7.2.3 Sector Erase (SE) (20h) ................................................................................................... 42 7.2.4 Block Erase (BE) (D8h) and Half Block Erase (52h) ........................................................ 43 7.2.5 Chip Erase (CE) (C7h or 60h) .......................................................................................... 44 7.2.6 Erase / Program Suspend (75h) ....................................................................................... 44 7.2.7 Erase / Program Resume (7Ah) ....................................................................................... 46 7.3 Read Commands................................................................................................................ 47 7.3.1 Read Data (03h) ............................................................................................................... 47 7.3.2 Fast Read (0Bh) ............................................................................................................... 47 7.3.3 DTR Fast Read (0Dh) ....................................................................................................... 48 7.3.4 Fast Read Dual Output (3Bh) ........................................................................................... 49 7.3.5 Fast Read Quad Output (6Bh).......................................................................................... 49 7.3.6 Fast Read Dual I/O (BBh)................................................................................................. 50 7.3.7 DTR Fast Read Dual I/O (BDh) ........................................................................................ 51 7.3.8 Fast Read Quad I/O (EBh) ............................................................................................... 52 7.3.9 DTR Fast Read Quad I/O (EDh)....................................................................................... 54 7.3.10 Set Burst with Wrap (77h) .............................................................................................. 56 7.4 Reset Commands ............................................................................................................... 57 7.4.1 Software Reset Enable (66h) ........................................................................................... 58 7.4.2 Software Reset (99h) ........................................................................................................ 58 7.5 ID and Security Commands ............................................................................................... 58 7.5.1 Deep Power-down (DP) (B9h) .......................................................................................... 58 7.5.2 Release Power-down / Device ID (ABh) .......................................................................... 58 7.5.3 Read Manufacturer / Device ID (90h)............................................................................... 60 7.5.4 Read Identification (RDID) (9Fh/AFh) .............................................................................. 61 7.5.5 Read SFDP Register (5Ah) .............................................................................................. 62 7.5.6 Erase Security Registers (44h)......................................................................................... 62 7.5.7 Program Security Registers (42h) .................................................................................... 63 7.5.8 Read Security Registers (48h) ......................................................................................... 63 7.5.9 Read Manufacturer / Device ID Dual I/O (92h) ................................................................ 64 7.5.10 Read Manufacturer / Device ID Quad I/O (94h) ............................................................. 65 7.5.11 Read Unique ID Number (4Bh)....................................................................................... 65 7.5.12 Set Read Parameters (C0h) ........................................................................................... 66 7.5.13 Burst Read with Wrap (0Ch)........................................................................................... 67 7.5.14 DTR Burst Read with Wrap (0Eh) .................................................................................. 67 7.5.15 Enter QPI Mode (38h) .................................................................................................... 68 7.5.16 Exit QPI Mode (FFh) ....................................................................................................... 68 7.6 Write Protection .................................................................................................................. 27 7.6.1 Write Protect Features ...................................................................................................... 27 7.6.2 Block Protection Maps ...................................................................................................... 28 7.7 Page Program .................................................................................................................... 29 7.8 Sector Erase, Block Erase and Chip Erase ....................................................................... 29 7.9 Active Power, Stand-by Power and Deep Power-Down Modes ........................................ 29 7.10 Polling during a Write, Program or Erase Cycle ................................................................ 30 ELECTRICAL CHARACTERISTIC ................................................................................................... 70 8.1 Power-Up Power-Down Timing and Requirements ........................................................... 70 8.2 Absolute Maximum Ratings................................................................................................ 70 8.3 Recommended Operating Ranges..................................................................................... 71 8.4 DC Characteristics.............................................................................................................. 72 8.5 AC Measurement Conditions ............................................................................................. 73 8.6 AC Electrical Characteristics .............................................................................................. 74 PACKAGE MECHANICAL ................................................................................................................ 78 9.1 SOP8 - 150mil .................................................................................................................... 78 9.2 SOP8 - 208mil .................................................................................................................... 79 Zbit Semiconductor, Inc. 3 ZB25VQ32D_DTR 9.3 DFN8 (4*3*0.55mm) ........................................................................................................... 80 9.4 TFBGA24 (5*5 Ball Array) .................................................................................................. 82 9.5 TFBGA24 (6*4 Ball Array) .................................................................................................. 83 REVISION LIST........................................................................................................................................ 84 Zbit Semiconductor, Inc. 4 ZB25VQ32D_DTR FEATURES ◼ Power Supply Voltage - Single 2.3V-3.6V supply ◼ 32M bit Serial Flash - 32 M-bit/4M-Byte/16,384 pages - 256 Bytes per programmable page - Uniform 4K-Byte Sectors, 32K/64K-Byte Blocks ◼ New Family of SpiFlash Memories - Standard SPI: CLK, CS#, DI, DO, WP#, HOLD# / RESET# - Dual SPI: CLK, CS#, DI, DO, WP#, HOLD# / RESET# - Quad SPI: CLK, CS#, IO0, IO1, IO2, IO3 - QPI: CLK, CS#, IO0, IO1, IO2, IO3 - SPI / QPI DTR (Double Transfer Rate) Read - Software & Hardware Reset - Auto-increment Read capability ◼ Temperature Ranges - Industrial (-40°C to 85°C) - Industrial (-40°C to 105°C) instruction overhead ◼ ◼ ◼ Low power consumption - 1 μA typical standby current, HFM =0 - 15 μA typical standby current, HFM =1 - 1 μA typical power down current Efficient “Continuous Read” and QPI Mode - Continuous Read with 8/16/32/64-Byte Wrap - As few as 8 clocks to address memory - Quad Peripheral Interface (QPI) reduces Zbit Semiconductor, Inc. ◼ Flexible Architecture with 4KB sectors Sector Erase (4K-Byte) Block Erase (32K/64K-Byte) Page Program up to 256 Bytes More than 100K erase/program cycles More than 20-year data retention Advanced Security Feature - Software and Hardware Write-Protect - Power Supply Lock-Down and OTP protection - Top/Bottom, Complement array protection - 128-Bit Unique ID for each device - Serial Flash Discoverable Parameters (SFDP) Register - 3X1024-Byte Security Registers with OTP locks - Volatile & Non-volatile Status Register Bits ◼ - High performance program/erase speed Page program time: 500us typical Sector erase time: 45ms typical Block erase time: 250ms typical Chip erase time: 12s typical - Package Options SOP8 - 150mil / 208mil DFN8 (2*3*0.55mm) DFN8 (4*3*0.55mm) TFBGA24 All Pb-free packages are RoHS compliant ◼ 5 ZB25VQ32D_DTR GENERAL DESCRIPTION The ZB25VQ32D_DTR of non-volatile flash memory device supports the standard Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (quad I/O or QIO) serial protocols. This multiple width interface is called SPI Multi-I/O or MIO. The SPI protocols use only 4 to 6 signals: ◆ Chip Select (CS#) ◆ Serial Clock (CLK) ◆ Serial Data - IO0 (DI) - IO1 (DO) - IO2 (WP#) - IO3 (HOLD# / RESET#) The ZB25VQ32D_DTR support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-clocks instruction cycle Quad Peripheral Interface (QPI) as well as Double Transfer Rate (DTR): Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (WP#), and I/O3 (HOLD# / RESET#). SPI clock frequencies of up to 133MHz are supported allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP Register, a 128-bit Unique Serial Number and three 1024-Byte Security Registers. The ZB25VQ32D_DTR provides an ideal storage solution for systems with limited space, signal connections, and power. These memories’ flexibility and performance is better than ordinary serial flash devices. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data. Zbit Semiconductor, Inc. 6 ZB25VQ32D_DTR 1 ORDERING INFORMATION The ordering part number is formed by a valid combination of the following: ZB 25 VQ 32 D X X X X Packing Type T: Tube R: Tape & Reel Y: Tray Green Code P: Pb free only green package G: Pb free and halogen free Temperature Range J: Industrial+ (-40℃ to 85℃) K: Industrial++ (-40℃ to 85℃) H: Industrial (-40℃ to 105℃) Package Type S:SOP8 208mil T:SOP8 150mil D:DFN8 2*3mm, THK 0.55mm N:DFN8 4*3mm, THK 0.55mm B:TFBGA24 (6*4 Ball Array) Z:TFBGA24 (5*5 Ball Array) Version D: D Version Device Density 32: 32Mbit Series VQ: 2.5V extended, 4KB uniform sector, Quad Mode Product Family 25: SPI Interface Flash Zbit Semiconductor Figure 1.1 Ordering Information Zbit Semiconductor, Inc. 7 ZB25VQ32D_DTR 2 BLOCK DIAGRAM X-Decoder Flash Memory Address Buffers and Latches Y-Decoder I/O Buffers and Data Latches Control Logic Serial Interface CS# CLK DI DO WP# HOLD#/ RESET# Figure 2.1 Block Diagram Zbit Semiconductor, Inc. 8 ZB25VQ32D_DTR 3 CONNECTION DIAGRAMS CS# 1 8 VCC DO 2 7 HOLD#/ RESET# WP# 3 6 CLK GND 4 5 DI Figure 3.1 SOP8 (208mil) CS# 1 8 VCC DO 2 7 HOLD# / RESET# WP# 3 6 CLK GND 4 5 DI Figure 3.2 DFN8 Zbit Semiconductor, Inc. 9 ZB25VQ32D_DTR 4 SIGNAL DESCRIPTIONS Table 4.1 Pin Descriptions Symbol CLK DI(IO0) DO(IO1) CS# WP#(IO2)(3) HOLD# / RESET#(3)(IO3) VCC GND Pin Name Serial Clock Input Serial Data Input(Data input output 0) (1) Serial Data Output(Data input output 1) (1) Chip Enable Write Protect (Data input output 2) (2) Hold or Reset input(Data input output 3) (2) Power Supply (2.3-3.6V) Ground Notes: (1) IO0 and IO1 are used for Standard and Dual SPI instructions. (2) IO0—IO3 are used for QUAD SPI / QPI instructions. (3) WP# and HOLD# / RESET# functions are only available for Standard and Dual SPI. 4.1 Serial Data Input (DI) / IO0 The SPI Serial Data Input (DI) pin is used to transfer data serially into the device. It receives instructions, address and data to be programmed. Data is latched on the rising edge of the Serial Clock (CLK) input pin. The DI pin becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, address, and data to be programmed (values latched on rising edge of serial CLK clock signal) as well as shifting out data (on the falling edge of CLK). 4.2 Serial Data Output (DO) / IO1 The SPI Serial Data Output (DO) pin is used to transfer data serially out of the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin. DO becomes IO1 - an input and output during Dual and Quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial CLK clock signal) as well as shifting out data (on the falling edge of CLK). 4.3 Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. (“See SPI Mode”) 4.4 Chip Select (CS#) The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is deselected and the Serial Data Output pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When CS# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. 4.5 Write Protect (WP#) / IO2 The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP0, BP1 and BP2, TB, SEC, CMP) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. Zbit Semiconductor, Inc. 10 ZB25VQ32D_DTR The WP# function is not available when the Quad mode is enabled. The WP# function is replaced by IO2 for input and output during Quad mode for receiving addresses and data to be programmed (values are latched on rising edge of the CLK signal) as well as shifting out data (on the falling edge of CLK). 4.6 HOLD (HOLD#) / IO3 The HOLD# pin allows the device to be paused while it is actively selected. When HRSW bit is ‘0’ (factory default is ‘0’), the HOLD# pin is enabled. When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device operation can resume. The HOLD# function can be useful when multiple devices are sharing the same SPI signals. The HOLD# pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the HOLD# pin function is not available since this pin is used for IO3. 4.7 RESET (RESET#) / IO3 The RESET# pin allows the device to be reset by the controller. When HRSW bit is ‘1’ (factory default is ‘0’), the RESET# pin is enabled. Drive RESET# low for a minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the status of other SPI signals (CS#, CLK, DI, DO, WP# and/or HOLD#). The Hardware Reset function is only available for standard SPI and Dual SPI operation, when QE=0, the IO3 pin can be configured either as a HOLD# pin or as a RESET# pin depending on Status Register setting, when QE=1, this pin is the Serial Data IO (IO3) for Quad I/O operation. Zbit Semiconductor, Inc. 11 ZB25VQ32D_DTR 5 MEMORY ORGANIZATION 5.1 5Flash Memory Array The memory is organized as: - 4,194,304 Bytes - 64 blocks of 64K-Byte - 1,024 sectors of 4K-Byte - 16,384 pages (256 Bytes each) Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, Block or Chip Erasable but not Page Erasable. Table 5.1 (1) Memory Organization(ZB25VQ32D_DTR) Block/ Security Register/SFDP Security Register 3 Security Register 2 Security Register 1 Security Register 0 (SFDP) Block 63 Block 62 ...... ...... Block 2 Block 1 Block 0 Sector Address range - 003000H 002000H 001000H 0033FFH 0023FFH 0013FFH - 000000H 0000FFH 1023 ...... 1008 1007 ...... 992 ...... ...... ...... ...... ...... ...... 47 ...... 32 31 ...... 16 15 ...... 0 3FF000H ...... 3F0000H 3EF000H ...... 3E0000H ...... ...... ...... ...... ...... ...... 02F000H ...... 020000H 01F000H ...... 010000H 00F000H ...... 000000H 3FFFFFH ...... 3F0FFFH 3EFFFFH ...... 3E0FFFH ...... ...... ...... ...... ...... ...... 02FFFFH ...... 020FFFH 01FFFFH ...... 010FFFH 00FFFFH ...... 000FFFH Note: (1) These are condensed tables that use a couple of sectors as references. There are address ranges that are not explicitly listed. All 4-kB sectors have the pattern XXX000h-XXXFFFh. 5.2 Security Registers The ZB25VQ32D_DTR provides three 1024-Byte Security Registers. Each register can be used to store information that can be permanently protected by programming One Time Programmable (OTP) lock bits in Status Register-2. Register 0 is used by Zbit to store and protect the Serial Flash Discoverable Parameters (SFDP) information that is also accessed by the Read SFDP command. See Table 5.1. The three additional Security Registers can be erased, programmed, and protected individually. These registers may be used by system manufacturers to store and permanently protect security or other important information separate from the main memory array. 5.2.1 Security Register 0 Zbit Semiconductor, Inc. 12 ZB25VQ32D_DTR Serial Flash Discoverable Parameters (SFDP — JEDEC JESD216D): This document defines the Serial Flash Discoverable Parameters (SFDP) revision D data structure for ZB25VQ32D_DTR family. The Read SFDP (RSFDP) command (5Ah) reads information from a separate flash memory address space for device identification, feature, and configuration information, in accord with the JEDEC JESD216D standard for Serial Flash Discoverable Parameters. The SFDP data structure consists of a header table that identifies the revision of the JESD216 header format that is supported and provides a revision number and pointer for each of the SFDP parameter tables that are provided. The parameter tables follow the SFDP header. However, the parameter tables may be placed in any physical location and order within the SFDP address space. The tables are not necessarily adjacent nor in the same order as their header table entries. The SFDP header points to the following parameter tables: ◼ Basic Flash – This is the original SFDP table. The physical order of the tables in the SFDP address space is: SFDP Header, and Basic Flash. The SFDP address space is programmed by Zbit and read-only for the host system. 5.2.2 Serial Flash Discoverable Parameters (SFDP) Address Map The SFDP address space has a header starting at address zero that identifies the SFDP data structure and provides a pointer to each parameter. One Basic Flash parameter is mandated by the JEDEC JESD216D standard. Table 5.2 SFDP Overview Map — Security Register 0 Byte Address 0000h 0020h 0030h ... 007Bh 007Ch to 00FFh Zbit Semiconductor, Inc. Description Location zero within JEDEC JESD216D SFDP space – start of SFDP header Undefined space reserved for future SFDP header Start of SFDP parameter Remainder of SFDP JEDEC parameter followed by undefined space End of SFDP space Reserved space 13 ZB25VQ32D_DTR 5.2.3 SFDP Header Field Definitions Table 5.3 SFDP Signature and Parameter Identification Data Value SFDP Byte Address SFDP Dword Name 00h 01h 02h 03h 53h SFDP Header 1st DWORD 04h 05h Data 46h 44h 50h 08h SFDP Header 2nd DWORD 01h 06h 07h 01h FFh 08h 00h 09h Parameter Header 0 1st DWORD 07h 0Ah 01h 0Bh 10h 0Ch 0Dh 0Eh 0Fh 10h 11h 12h Parameter Header 0 2nd DWORD Parameter Header 1 1st DWORD 13h 14h 15h 16h 17h 30h 00h 00h FFh 5Eh 00h 01h 03h Parameter Header 1 2nd DWORD Zbit Semiconductor, Inc. 70h 00h 00h FFh Description This is the entry point for Read SFDP (5Ah) command i.e. location zero within SFDP space.ASCII “S” ASCII “F” ASCII “D” ASCII “P” SFDP Minor Revision Number This 8-bit field indicates the minor revision number of this standard. The value in this field is 08h for devices which implement the JESD216D revision SFDP Major Revision Number This 8-bit field indicates the major revision number of this standard. The value in this field is 01h for devices which implement the JESD216D revision Number of Parameter Headers (zero based, 00h = 1 parameters) SFDP Access Protocol field Parameter ID LSB The JEDEC Basic Flash Parameter Table is assigned the ID LSB of 00h. Parameter Table Minor Revision Number This 8-bit field indicates the minor revision number of the JEDEC Basic Flash Parameter table. The value in this field is 07h for this table defined by JESD216D revision Parameter Table Major Revision Number This 8-bit field indicates the major revision number of the parameter table. The value in this field is 01h for this table defined by JESD216D revision Parameter Table Length (in double words = Dwords = 4-Byte units) 10h = 16 Dwords Parameter Table Pointer Byte 0 (Dword = 4-Byte aligned) JEDEC Basic SPI Flash parameter Byte offset = 30h Parameter Table Pointer Byte 1 Parameter Table Pointer Byte 2 Parameter ID MSB (FFh = JEDEC defined legacy Parameter ID) ID Number.It indicates Zbit manufacture ID Parameter Table Minor Revision Number Starts from 00h Parameter Table Major Revision Number Starts from 01h Parameter Table Length, 0 based Parameter Table Pointer Byte 0 (Dword = 4-Byte aligned) Zbit Flash parameter Byte offset = 70h Parameter Table Pointer Byte 1 Parameter Table Pointer Byte 2 Unused 14 ZB25VQ32D_DTR 5.2.4 JEDEC SFDP Basic SPI Flash Parameter Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev D (Sheet 1 of 5) SFDP Parameter Relative Byte Address SFDP Dword Name 30h 31h E5h JEDEC Basic Flash Parameter Dword-1 32h 33h 34h 35h 36h 37h 3Ah JEDEC Basic Flash Parameter Dword-2 3Dh 3Eh 41h 42h 43h 44h 45h 46h 47h EBh 08h 6Bh JEDEC Basic Flash Parameter Dword-4 3Fh 40h FFh FFh FFh FFh 01h 44h JEDEC Basic Flash Parameter Dword-3 3Bh 3Ch 20h F9h 38h 39h Data 08h 3Bh 80h BBh JEDEC Basic Flash Parameter Dword-5 JEDEC Basic Flash Parameter Dword-6 Zbit Semiconductor, Inc. FEh FFh FFh FFh FFh FFh FFh FFh Description Start of SFDP JEDEC parameter Bits 7:5 = unused = 111b Bit 4:3 = 05h is volatile status register write instruction and status register is default non-volatile= 00b Bit 2 = Program Buffer > 64 Bytes = 1 Bits 1:0 = Uniform 4-KB erase is supported throughout the device = 01b Bits 15:8 = Uniform 4-KB erase instruction = 20h Bit 23 = Unused = 1b Bit 22 = Supports QOR Read (1-1-4), Yes = 1b Bit 21 = Supports QIO Read (1-4-4),Yes =1b Bit 20 = Supports DIO Read (1-2-2), Yes = 1b Bit19 = Supports DTR, YES= 1b Bit 18:17 = Number of Address Bytes 3 only = 00b Bit 16 = Supports SIO and DIO Yes = 1b Binary Field: 1-1-1-1-1-00-1 Nibble Format: 1111_1001 Hex Format: F9 Bits 31:24 = Unused = FFh Density in bits, zero based, 32 Mb = 01FFFFFFh 64 Mb = 03FFFFFFh 128 Mb = 07FFFFFFh Bits 7:5 = number of QIO (1-4-4)Mode cycles = 010b Bits 4:0 = number of Fast Read QIO Dummy cycles = 00100b for default latency code Fast Read QIO (1-4-4)instruction code Bits 23:21 = number of Quad Out (1-1-4) Mode cycles = 000b Bits 20:16 = number of Quad Out Dummy cycles = 01000b for default latency code Quad Out (1-1-4)instruction code Bits 7:5 = number of Dual Out (1-1-2)Mode cycles = 000b Bits 4:0 = number of Dual Out Dummy cycles = 01000b for default latency code Dual Out (1-1-2) instruction code Bits 23:21 = number of Dual I/O Mode cycles = 100b Bits 20:16 = number of Dual I/O Dummy cycles = 00000b for default latency code Dual I/O instruction code Bits 7:5 RFU = 111b Bit 4 = QPI (4-4-4) fast read commands supported = 1b Bits 3:1 RFU = 111b Bit 0 = Dual All not supported = 0b Bits 15:8 = RFU = FFh Bits 23:16 = RFU = FFh Bits 31:24 = RFU = FFh Bits 7:0 = RFU = FFh Bits 15:8 = RFU = FFh Bits 23:21 = number of Dual All Mode cycles = 111b Bits 20:16 = number of Dual All Dummy cycles = 11111b Dual All instruction code 15 ZB25VQ32D_DTR Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev D (Sheet 2 of 5) SFDP Parameter Relative Byte Address 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h SFDP Dword Name JEDEC Basic Flash Parameter Dword-7 JEDEC Basic Flash Parameter Dword-8 JEDEC Basic Flash Parameter Dword-9 JEDEC Basic Flash Parameter Dword-10 Zbit Semiconductor, Inc. Data Description FFh FFh Bits 7:0 = RFU = FFh Bits 15:8 = RFU = FFh Bits 23:21 = number of QPI Mode cycles = 010b Bits 20:16 = number of QPI Dummy cycles = 00100b for default latency code QPI instruction code Erase Type 1 size 2N Bytes = 4 KB = 0Ch (for Uniform 4 KB) Erase Type 1 instruction Erase Type 2 size 2N Bytes = 32 KB = 0Fh (for Uniform 32 KB) Erase Type 2 instruction Erase Type 3 size 2N Bytes =64 KB = 10h(for Uniform 64 KB) Erase Type 3 instruction Erase Type 4 size 2N Bytes = not supported = 00h Erase Type 4 instruction = not supported = FFh Bits 31:30 = Erase Type 4 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b:1 s) = RFU = 11b Bits 29:25 = Erase Type 4 Erase, Typical time count = RFU = 11111b (typ erase time = (count+1) * units) = RFU =11111 Bits 24:23 = Erase Type 3 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b:1 s) = RFU = 01b Bits 22:18 = Erase Type 3 Erase, Typical time count = 01001b (typ erase time = (count +1) *units) = 10*16 ms =150ms Bits 17:16 = Erase Type 2 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b:1 s) = 16 ms = 01b Bits 15:11 = Erase Type 2 Erase, Typical time count = 00111b (typ erase time = (count +1) *units) = 8*16 ms = 120 ms Bits 10:9 = Erase Type 1 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1s) = 16ms = 01b Bits 8:4 = Erase Type 1 Erase, Typical time count = 00001b (typ erase time = (count +1) *units) = 2*16 ms = 30 ms Bits 3:0 = Count = (Max Erase time / (2 * Typical Erase time))- 1 = 0001b Multiplier from typical erase time to maximum erase time = 8x multiplier Max Erase time = 2*(Count +1)*Typ Erase time Binary Fields: 1111111_0101001_0100111_0100001_0001 Nibble Format: 1111_1110_1010_0101_0011_1010_0001_0001 Hex Format: FE_A5_3A_11 44h EBh 0Ch 20h 0Fh 52h 10h D8h 00h FFh 11h 3Ah A5h FEh 16 ZB25VQ32D_DTR Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev D (Sheet 3 of 5) SFDP Parameter Relative Byte Address 58h 59h 5Ah SFDP Dword Name JEDEC Basic Flash Parameter Dword-11 Data Description 82h 67h Bits 23 = Byte Program Typical time, additional Byte units (0b:1 μs, 1b:8 μs) = 1 μs = 0b Bits 22:19 = Byte Program Typical time, additional Byte count, (count+1)*units, count = 0010b,(typ Program time = (count +1) * units) = 3*1 μs =3 μs Bits 18 = Byte Program Typical time, first Byte units (0b:1 μs, 1b:8 μs) = 8 μs = 1b Bits 17:14 = Byte Program Typical time, first Byte count, (count+1)*units, count = 0001b, (typ Program time = (count +1) * units) = 2*8 μs = 16 μs Bits 13 = Page Program Typical time units (0b:8 μs, 1b:64 μs) = 64 μs = 1b Bits 12:8 = Page Program Typical time count, (count+1)*units, count = 00111b, (typ Program time = (count +1) * units) = 8*64 μs = 500 μs Bits 7:4 = N = 1000b, Page size= 2N = 256B page Bits 3:0 = Count = 0010b = (Max Page Program time / (2 * Typ Page Program time))1 Multiplier from typical Page Program time to maximum Page Program time = 2x multiplier Max Page Program time = 2*(Count +1)*Typ Page Program time Binary Fields: 0-0010-1-0001-1-00111-1000-0010 Nibble Format: 0001_0100_0110_0111_1000_0010 Hex Format: 14_67_82 32 Mb = 1100_0010b = C2h Bit 31 Reserved = 1b Bits 30:29 = Chip Erase, Typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) = 4s= 10b Bits 28:24 = Chip Erase, Typical time count, (count+1)*units, count = 00010b, (typ Program time = (count +1) * units) = 3*4s = 12s Bit 31 = Suspend and Resume supported = 0b Bits 30:29 = Suspend in-progress erase max latency units (00b: 128ns, 01b: 1us, 10b: 8 μs,11b: 64 μs) = 1 μs= 01b Bits 28:24 = Suspend in-progress erase max latency count = 10011b, max erase suspend latency = (count +1) * units = 20*1 μs = 20 μs Bits 23:20 = Erase resume to suspend interval count = 0001b, interval = (count +1) * 64 μs = 2* 64 μs = 128 μs Bits 19:18 = Suspend in-progress program max latency units (00b: 128ns, 01b: 1us, 10b: 8 μs,11b: 64 μs) = 1 μs= 01b Bits 17:13 = Suspend in-progress program max latency count = 10011b, max erase suspend latency = (count +1) * units = 20*1 μs = 20 μs Bits 12:9 = Program resume to suspend interval count = 0001b, interval = (count +1) * 64 μs =2 * 64 μs = 128 μs Bit 8 = RFU = 1b Bits 7:4 = Prohibited operations during erase suspend = xxx0b: May not initiate a new erase anywhere (erase nesting not permitted) + xx1xb: May not initiate a page program in the erase suspended sector size + x1xxb: May not initiate a read in the erase suspended sector size + 1xxxb: The erase and program restrictions in bits 5:4 are sufficient= 1110b Bits 3:0 = Prohibited Operations During Program Suspend = xxx0b: May not initiate a new erase in the program suspended page size + xx0xb: May not initiate a new page program anywhere (program nesting not permitted) + x1xxb: May not initiate a read in the program suspended page size + 1xxxb: The erase and program restrictions in bits 1:0 are sufficient= 1101b Binary Fields: 0-01-10011-0001-01-10011-0001-1-1110-1100 Nibble Format: 0011_0011_0001_0110_0110_0011_1110_1100 Hex Format: 33_16_63_EC 14h 5Bh C2h 5Ch 5Dh 5Eh ECh 63h 16h 5Fh JEDEC Basic Flash Parameter Dword-12 Zbit Semiconductor, Inc. 33h 17 ZB25VQ32D_DTR Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev D (Sheet 4 of 5) SFDP Parameter Relative Byte Address 60h 61h 62h 63h 64h 65h 66h 67h SFDP Dword Name JEDEC Basic Flash Parameter Dword-13 JEDEC Basic Flash Parameter Dword-14 68h 69h 6Ah 6Bh Data Description 7Ah 75h 7Ah 75h F7h A2h D5h Bits 31:24 = Erase Suspend Instruction = 75h Bits 23:16 = Erase Resume Instruction = 7Ah Bits 15:8 = Program Suspend Instruction = 75h Bits 7:0 = Program Resume Instruction = 7Ah Bit 31 = Deep Power-Down Supported = 0 Bits 30:23 = Enter Deep Power-Down Instruction = B9h Bits 22:15 = Exit Deep Power-Down Instruction = ABh Bits 14:13 = Exit Deep Power-Down to next operation delay units = (00b: 128 ns, 01b: 1 μs, 10b: 8 μs, 11b: 64 μs) = 1 μs = 01b Bits 12:8 = Exit Deep Power-Down to next operation delay count = 00010b, Exit Deep Power-Down to next operation delay = (count+1)*units = 3*1 μs=3 μs Bits 7:4 = RFU = 1111b Bit 3:2 = Status Register Polling Device Busy = 01b: Legacy status polling supported = Use legacy polling by reading the Status Register with 05h instruction and checking BUSY bit (0=ready; 1=busy). Bits 1:0 = RFU = 11b Binary Fields: 0-10111001-10101011-01-00010-1111-01-11 Nibble Format: 0101_1100_1101_0101_1010_0010_1111_0111 Hex Format: 5C_D5_A2_F7 Bits 31:24 = RFU = FFh Bit 23 = Hold and WP Disable = set QE(bit 1 of SR2) high = 1b Bits 22:20 = Quad Enable Requirements = 101b: QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction 05h. Status register 2 is read using instruction 35h. QE is set via Write Status instruction 01h with two data Bytes where bit 1 of the second Byte is one. It is cleared via Write Status with two data Bytes where bit 1 of the second Byte is zero. Bits 19:16 0-4-4 Mode Entry Method = xxx1b: Mode Bits[7:0] = A5h Note: QE must be set prior to using this mode + x1xxb: Mode Bits[7:0] = Axh + 1xxxb: RFU = 1101b Bits 15:10 0-4-4 Mode Exit Method = xx_xxx1b: Mode Bits[7:0] = 00h will terminate this mode at the end of the current read operation + xx_1xxxb: Input Fh (mode bit reset) on DQ0-DQ3 for 8 clocks. This will terminate the mode prior to the next read operation. + 11_x1xx: RFU= 111101b Bit 9 = 0-4-4 mode supported = 1 Bits 8:4 = 4-4-4 mode enable sequences = 0_0001b: set QE per QER description above, then issue instruction 38h Bits 3:0 = 4-4-4 mode disable sequences = xxx1b: issue FFh instruction + 1xxxb: issue the Soft Reset 66/99 sequence= 1001b Binary Fields: 11111111-1-101-1101-111101-1-00001-1001 Nibble Format: 1111_1111-1101-1101-1111_0110_0001-1001 Hex Format: FF_DD_F6_19 5Ch 19h F6h DDh JEDEC Basic Flash Parameter Dword-15 Zbit Semiconductor, Inc. FFh 18 ZB25VQ32D_DTR Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev D (Sheet 5 of 5) SFDP Parameter Relative Byte Address 6Ch 6Dh 6Eh 6Fh SFDP Dword Name JEDEC Basic Flash Parameter Dword-16 Zbit Semiconductor, Inc. Data Description E8h 30h C0h Bits 31:24 = Enter 4-Byte Addressing = xxxx_xxx1b:issue instruction B7 (preceding write enable not required + xx1x_xxxxb: Supports dedicated 4-Byte address instruction set. Consult vendor data sheet for the instruction set definition or look for 4-Byte Address Parameter Table. + 1xxx_xxxxb: Reserved = 10000000b not supported Bits 23:14 = Exit 4-Byte Addressing = xx_xxxx_xxx1b:issue instruction E9h to exit 4-Byte address mode (Write enable instruction 06h is not required) + xx_xx1x_xxxxb: Hardware reset + xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD) + xx_1xxx_xxxxb: Power cycle + x1_xxxx_xxxxb: Reserved + 1x_xxxx_xxxxb: Reserved = 11_0000_0000b not supported Bits 13:8 = Soft Reset and Rescue Sequence Support = x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h. The reset enable, reset sequence may be issued on 1,2, or 4 wires depending on the device operating mode + 1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences above if the device may be operating in this mode. = 11_0000b Bit 7 = RFU = 1 Bits 6:0 = Volatile or Non-Volatile Register and Write Enable Instruction for Status Register 1 = xxx_1xxxb: Non-Volatile/Volatile status register 1 powers-up to last written value in the nonvolatile status register, use instruction 06h to enable write to non-volatile status register. Volatile status register may be activated after power-up to override the non-volatile status register, use instruction 50h to enable write and activate the volatile status register. + x1x_xxxxb: Reserved + 1xx_xxxxb: Reserved = 1101000b Binary Fields: 10000000-1100000000-110000-1-1101000 Nibble Format: 1000_0000_1100_0000_0011_0000_1110_1000 Hex Format: 80_C0_30_E8 80h 19 ZB25VQ32D_DTR Table 5.5 Zbit flash parameter SFDP Parameter Relative Byte Address 70h 71h 72h 73h SFDP Dword Name Zbit flash parameter Dword-1 74h Data Description 00h 36h 00h Bits 15:0 = VCC Supply Maximum Voltage 2000h = 2.000 V 2700h = 2.700 V 3600h = 3.600 V Bits 31:16 = VCC Supply Minimum Voltage 1650h = 1.650V 2250h = 2.250V 2300h = 2.300V 2700h = 2.700V Bit 0 = HW Reset# pin ( 0=not support, 1=support ) = 1b Bit 1 = HW Hold# pin ( 0=not support, 1=support ) = 1b Bit 2 = Deep Power Down Mode ( 0=not support, 1=support ) = 1b Bit 3 = SW Reset ( 0=not support, 1=support ) = 1b Bits 11:4 = SW Reset Opcode: Should be issue Reset Enable(66H) before Reset cmd = 10011001b Bit 12 = Program Suspend/Resume ( 0=not support, 1=support ) = 1b Bit 13 = Erase Suspend/Resume ( 0=not support, 1=support ) = 1b Bit 14 = Unused = 1b Bit 15 = Wrap-Around Read mode ( 0=not support, 1=support ) = 1b Binary Fields: 1111_10011001_1111 Nibble Format: 1111_1001_1001_1111 Hex Format: F9_9F Wrap-Around Read mode Opcode Wrap-Around Read data length 08H:support 8B wrap-around read 16H:8B&16B 32H:8B&16B&32B 64H:8B&16B&32B&64B Bit 0 = Individual block lock ( 0=not support, 1=support ) = 0b Bit 1 = Individual block lock bit (Volatile/Nonvolatile) ( 0=Volatile, 1=Nonvolatile ) = 0b Bits 9:2 = Individual block lock Opcode = 11111111b Bit 10 = Individual block lock Volatile protect bit default protect status ( 0=protect, 1=unprotect ) = 0b Bit 11 = Secured OTP ( 0=not support, 1=support ) = 1b Bit 12 = Read Lock ( 0=not support, 1=support ) = 0b Bit 13 = Permanent Lock ( 0=not support, 1=support ) = 0b/1b(1) Bits 15:14 = Unused = 11b Binary Fields: 110(1)010_11111111_00 Nibble Format: 110(1)0_1011_1111_1100 Hex Format: C(E)B_FC Unused Unused 23h 9Fh 75h Zbit flash parameter Dword-2 F9h 76h 77h 77h 64h 78h FCh Zbit flash parameter Dword-3 79h 7Ah 7Bh C(E)Bh FFh FFh NOTE: (1) ZB25VQ32D support Permanent Lock. Please contact Zbit for details. Zbit Semiconductor, Inc. 20 ZB25VQ32D_DTR 6 FUNCTION DESCRIPTION 6.1 SPI Operations 6.1.1 SPI Modes The ZB25VQ32D_DTR can be driven by an embedded microcontroller (bus master) in either of the two following clocking modes. ◆ Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0 ◆ Mode 3 with CPOL = 1 and, CPHA = 1 For these two modes, input data is always latched in on the rising edge of the CLK signal and the output data is always available on the falling edge of the CLK clock signal. The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring any data. ◆ CLK will stay at logic low state with CPOL = 0, CPHA = 0 ◆CLK will stay at logic high state with CPOL = 1, CPHA = 1 CS# CPOL=0_CPHA=0_CLK CPOL=1_CPHA=1_CLK DI MSB DO MSB Figure 6.1 SPI Modes Timing diagrams throughout the rest of the document are generally shown as both mode 0 and 3 by showing CLK as both high and low at the fall of CS#. In some cases a timing diagram may show only mode 0 with CLK low at the fall of CS#. In such case, mode 3 timing simply means clock is high at the fall of CS# so no CLK rising edge set up or hold time to the falling edge of CS# is needed for mode 3. CLK cycles are measured (counted) from one falling edge of CLK to the next falling edge of CLK. In mode 0 the beginning of the first CLK cycle in a command is measured from the falling edge of CS# to the first falling edge of CLK because CLK is already low at the beginning of a command. 6.1.2 Dual SPI Modes The ZB25VQ32D_DTR supports Dual SPI Operation when using the Fast Read Dual Output (3Bh) and Fast Dual I/O (BBh) instruction. These features allow data to be transferred from the device at twice the rate possible with the standard SPI. These instructions are ideal for quickly downloading code to RAM upon Power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP). When using Dual SPI commands, the DI and DO pins become bidirectional I/O pins: IO0 and IO1. 6.1.3 Quad SPI Modes Zbit Semiconductor, Inc. 21 ZB25VQ32D_DTR The ZB25VQ32D_DTR supports Quad SPI operation when using the Fast Read Quad Output (6Bh) and Fast Read Quad I/O (EBh) instruction. These instructions allow data to be transferred to or from the device four times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions, the DI and DO pins become bidirectional IO0 and IO1, and the WP# and HOLD# / RESET# pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. 6.1.4 QPI Function The ZB25VQ32D_DTR supports Quad Peripheral Interface (QPI) operations when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI protocol requires that the Byte-long instruction code being shifted into the device only via DI pin in eight serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks are required. This can significantly reduce the SPI instruction overhead and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to switch between these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction, the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and DO pins become bidirectional IO0 and IO1, and the WP# and HOLD# / RESET# pins become IO2 and IO3 respectively. 6.1.5 SPI / QPI DTR Read Function To effectively improve the read operation throughput without increasing the serial clock frequency, ZB25VQ32D_DTR introduces multiple DTR (Double Transfer Rate) Read instructions that support Standard/ Dual/ Quad SPI and QPI modes. The Byte-long instruction code is still latched into the device on the rising edge of the serial clock similar to all other SPI/QPI instructions. Once a DTR instruction code is accepted by the device, the address input and data output will be latched on both rising and falling edges of the serial clock. 6.1.6 Hold Function For Standard SPI and Dual SPI operations, the HOLD# / RESET# (IO3) signal allows the device interface operation to be paused while it is actively selected (when CS# is low). The Hold function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, if the page buffer is only partially written when a priority interrupt requires use of the SPI bus, the Hold function can save the state of the interface and the data in the buffer so programming command can resume where it left off once the bus is available again. The Hold function is only available for standard SPI and Dual SPI operation, not during Quad SPI. To initiate a Hold condition, the device must be selected with CS# low. A Hold condition will activate on the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold condition will activate after the next falling edge of CLK. The Hold condition will terminate on the rising edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold condition will terminate after the next falling edge of CLK. During a Hold condition, the Serial Data Output, (DO) or IO0 and IO1, are high impedance and Serial Data Input, (DI) or IO0 and IO1, and Serial Clock (CLK) are ignored. The Chip Select (CS#) signal should be kept active (low) for the full duration of the Hold operation to avoid resetting the internal logic state of the device. 6.1.7 Software Reset & Hardware RESET# pin The ZB25VQ32D_DTR can be reset to the initial power-on state by a software Reset sequence, either in SPI mode or QPI mode. This sequence must include two consecutive commands: Enable Reset Zbit Semiconductor, Inc. 22 ZB25VQ32D_DTR (66h) & Reset (99h). If the command sequence is successfully accepted, the device will take approximately the time of tRST (see Table 8.6) to reset. No command will be accepted during the reset period. ZB25VQ32D_DTR can also be configured to utilize a hardware RESET# pin. The HRSW bit in the Status Register-3 is the configuration bit for HOLD# pin function or RESET# pin function. When HRSW=0 (factory default), the pin acts as a HOLD# pin as described above; when HRSW =1, the pin acts as a RESET# pin. Drive the RESET# pin low for a minimum period of ~1us (t RESET(1)) will reset the device to its initial power-on state. Any on-going Program/Erase operation will be interrupted and data corruption may happen. While RESET# is low, the device will not accept any command input. If QE bit is set to 1, the HOLD# or RESET# function will be disabled, the pin will become one of the four data I/O pins. Hardware RESET# pin has the highest priority among all the input signals. Drive RESET# low for a minimum period of ~1us (tRESET(1)) will interrupt any on-going external/internal operations, regardless the status of other SPI signals (CS#, CLK, DI, DO, WP# and/or HOLD#). Note: (1) While a faster RESET# pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended to ensure reliable operation. 6.2 Status Register The Read and Write Status Registers commands can be used to provide status and control of the flash memory device. Status Register-1 (SR1) and Status Register-2 (SR2) can be used to provide status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, and Erase / Program Suspend status. SR1 and SR2 contain non-volatile bits in locations SR1[7:2] and SR2[6:3,1,0] that control sector protection, OTP Register Protection, Status Register Protection, and Quad mode. Bits located in SR2[7], SR2[2], SR1[1], and SR1[0] are read only volatile bits for suspend, write enable, and busy status. These are updated by the memory control logic. The SR1[1] write enable bit is set only by the Write Enable (06h/50h) command and cleared by the memory control logic when an embedded operation is completed. Write access to the non-volatile Status Register bits is controlled by the state of the non-volatile Status Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the Write Enable command (06h) preceding a Write Status Registers command, and while Quad mode is not enabled, the WP# pin. A volatile version of bits SR2[6], SR2[1], and SR1[7:2] that control sector protection and Quad Mode is used to control the behavior of these features after power up. During power up or software reset, these volatile bits are loaded from the non-volatile version of the Status Register bits. The Write Enable for Volatile Status Register (50h) command can be used to write these volatile bits when the command is followed by a Write Status Registers (01h) command. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. Status Register-3 (SR3) is used to configure and provide status on the variable HOLD# or RESET# function, Output Driver Strength, High Frequency Mode Enable Bit, Write Protect Selection and Dummy Configuration. Zbit Semiconductor, Inc. 23 ZB25VQ32D_DTR Table 6.1 Status Register-1 (SR1) Bits Field Function 7 SRP0 Status Register Protect 0 6 SEC Sector / Block Protect Top / Bottom protect Type Default State 0 Non-volatile and volatile versions 0 5 TB 4 3 2 BP2 BP1 BP0 0 Block Protect Bits 1 WEL Write Enable Latch Volatile, Read only 0 0 BUSY Embedded Operation Status Volatile, Read only 0 Bits Field 7 SUS1 6 CMP 5 4 3 0 0 0 Description Controls Status Register Protection configuration with SRP1.See details in Table 6.4 Status Register Protect. 0 = BP2-BP0 protect 64-KB blocks 1 = BP2-BP0 protect 4-KB sectors 0 = BP2-BP0 protect from the Top down 1 = BP2-BP0 protect from the Bottom up 000b = No protection 0 = Not Write Enabled, no embedded operation can start 1 = Write Enabled, embedded operation can start 0 = Not Busy, no embedded operation in progress 1 = Busy, embedded operation in progress Table 6.2 Status Register-2 (SR2) Function Erase Suspend Status Complement Protect Type Volatile, Read Only Non-volatile and volatile versions Default State LB3 LB2 LB1 Security Register Lock Bits OTP 0 0 0 2 SUS2 Program Suspend Status Volatile, Read Only 0 1 QE Quad Enable 0 0 0 Non-volatile and volatile versions 0 SRP1 Status Register Protect 1 0 Description 0 = Erase not suspended 1 = Erase suspended 0 = Normal Protection Map 1 = Complementary Protection Map OTP Lock Bits 3:1 for Security Registers 3:1 0 = Security Register not protected 1 = Security Register protected 0 = Program not suspended 1 = Program suspended 0 = Quad Mode Not Enabled, the WP# pin and HOLD# / RESET# are enabled 1 = Quad Mode Enabled, the IO2 and IO3 pins are enabled, and WP# and HOLD# / RESET# functions are disabled Controls Status Register Protection configuration with SRP0.See details in Table 6.4 Status Register Protect. Note: (1) Reserved bit should be considered don’t care for read. Table 6.3 Status Register-3 (SR3) Bits Field 7 HRSW 6 DRV1 5 DRV0 4 HFM 3 2 1 Reserved Reserved Reserved 0 DC Function HOLD# or RESET# function Output Driver Strength High Frequency Mode Enable Bit Reserved Reserved Reserved Dummy Configuration Type Default State 0 Non-volatile and volatile versions N/A N/A N/A Non-volatile and volatile versions 0 0 Description When HRSW=0, the pin acts as HOLD#; when HRSW=1, the pin acts as RESET#. HRSW functions are only available when QE=0. The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations. 1 0 =Low Standby Mode 1 =High Frequency Mode 0 0 0 N/A N/A N/A 0 Selects the number of dummy cycles. 6.2.1 BUSY BUSY is a read only bit in the status register (SR1[0]) which is set to a “1” state when the device is executing a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During this time the device will ignore further instructions except for the Read Status Register instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register Zbit Semiconductor, Inc. 24 ZB25VQ32D_DTR instruction has completed, the BUSY bit will be cleared to a “0” state indicating the device is ready for further instructions. 6.2.2 Write Enable Latch (WEL) Write Enable Latch (WEL) is a read only bit in the status register (SR1[1]) which is set to a 1 after executing a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is written disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register. 6.2.3 Block Protect Bits (BP2, BP1, BP0) The Block Protect Bits (BP2, BP1, BP0) are non-volatile read / write bits in the Status Register (SR1[4:2]) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Registers Command (see tW in Section 8.6). All, none or a portion of the memory array can be protected from Program and Erase commands (see Section 6.3.2, Block Protection Maps). The factory default setting for the Block Protection Bits is 0 (none of the array is protected.) 6.2.4 Top / Bottom Block Protect (TB) The non-volatile Top / Bottom bit (TB SR1[5]) controls whether the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in Section 6.3.2, Block Protection Maps. The factory default setting is TB=0. The TB bit can be set with the Write Status Registers Command depending on the state of the SRP0, SRP1 and WEL bits. 6.2.5 Sector / Block Protect (SEC) The non-volatile Sector / Block Protect bit (SEC SR1[6]) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4-KB Sectors (SEC=1) or 64-KB Blocks (SEC=0) of the array as shown in Section 6.3.2, Block Protection Maps. The default setting is SEC=0. 6.2.6 Complement Protect (CMP) The Complement Protect bit (CMP SR2[6]) is a non-volatile read / write bit in the Status Register (SR2[6]). It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, a top 4-KB sector can be protected while the rest of the array is not; when CMP=1, the top 4-KB sector will become unprotected while the rest of the array become read-only. Refer to Section 6.3.2, Block Protection Maps for details. The default setting is CMP=0. 6.2.7 The Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read / write bits in the Status Register (SR2[0] and SR1[7]). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down, or one time programmable (OTP) protection. Table 6.4 Status Register Protect SRP1 SRP0 WP# Status Register 0 0 X Software Protection 0 1 0 Hardware Protected 0 1 1 Hardware Unprotected 1 0 X 1 1 X Power Supply Lock Down One Time Program (2) Description WP# pin has no control. SR1, SR2 and SR3 can be written to after a Write Enable command, WEL=1. [Factory Default] When WP# pin is low the SR1, SR2 and SR3 are locked and cannot be written. When WP# pin is high SR1, SR2 and SR3 are unlocked and can be written to after a Write Enable command, WEL=1. SR1, SR2 and SR3 are protected and cannot be written to again until the next power-down, power-up cycle. (1) SR1, SR2 and SR3 are permanently protected and cannot be written. Notes: Zbit Semiconductor, Inc. 25 ZB25VQ32D_DTR (1) When SRP1, SRP0 = (1, 0), a power-down, power-up, or Software Reset cycle will change SRP1, SRP0 to (0, 0) state. (2) The One-Time Program feature is available upon special order. Contact Zbit for details. (3) Busy, WEL, SUS1 and SUS2 (SR1[1:0], SR2[2] and SR2[7]) are volatile read only status bits that are never affected by the Write Status Registers command. 6.2.8 Erase / Program Suspend Status (SUS1, SUS2) The Suspend Status bit is a read only bit in the status register (SR2[7] and SR2[2]) that is set to 1 after executing an Erase / Program Suspend (75h) command. The SUS status bits are cleared to 0 by Erase / Program Resume (7Ah) command as well as a power-down, power-up cycle. 6.2.9 Security Register Lock Bits (LB3, LB2, LB1) The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status Register (SR2[5:3]) that provide the write protect control and status to the Security Registers. The default state of LB[3:1] is 0, Security Registers 1 to 3 are unlocked. LB[3:1] can be set to 1 individually using the Write Status Registers command. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the corresponding 1024-Byte Security Register will become read-only permanently. 6.2.10 Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read / write bit in the Status Register (SR2[1]) that allows Quad SPI operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# / RESET# are enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and WP# and HOLD# / RESET# functions are disabled. Note: (1) If the WP# or HOLD# / RESET# pins are tied directly to the power supply during standard SPI or Dual SPI operation, the QE bit should never be set to a 1. 6.2.11 HOLD# or RESET# Pin Function (HRSW) The HRSW bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware pin for 8-pin packages. When HRSW=0, the pin acts as #HOLD; when HRSW=1, the pin acts as RESET#. However, HOLD# or RESET# functions are only available when QE=0. If QE is set to 1, the HOLD# and RESET# functions are disabled, the pin acts as a dedicated data I/O pin. 6.2.12 Output Driver Strength (DRV1, DRV0) The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations. DRV1, DRV0 0, 0 0, 1 1, 0 1, 1 Driver Strength 50% 25% 75% 100% 6.2.13 High Frequency Mode Enable Bit (HFM) The HFM bit is used to determine whether the device is in High Frequency Mode. When HFM bit sets to 1(default), it means the device is in High Frequency Mode, when HFM bit sets 0, it means the device is in Low Standby Mode. 6.2.14 Dummy Configuration (DC) Zbit Semiconductor, Inc. 26 ZB25VQ32D_DTR The Dummy Configuration (DC) bit is non-volatile, which selects the number of dummy cycles between the end of address and the start of read data output. Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array before data can be returned to the host system. Some read commands require additional dummy cycles as the SCLK frequency increases. The following dummy cycle tables provide different dummy cycle settings that are configured. Command BBh EBh DC bit 0 (default) 1 0 (default) 1 Numbers of Dummy Cycles 4 8 6 10 Frequency (MHz) 104 133 104 133 6.3 Write Protection Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the ZB25VQ32D_DTR provides the following data protection mechanisms: 6.3.1 Write Protect Features ◆ Device resets when VCC is below threshold ◆ Time delay write disable after Power-Up ◆ Write enable / disable commands and automatic write disable after erase or program ◆ Command length protection - All commands that Write, Program or Erase must complete on a Byte boundary (CS# driven high after a full 8 bits have been clocked) otherwise the command will be ignored. ◆ Software and Hardware write protection using Status Register control - WP# input protection - Lock Down write protection until next power-up or Software Reset - One-Time Program (OTP) write protection ◆ Write Protection using the Deep Power-Down command Upon power-up or at power-down, the ZB25VQ32D_DTR will maintain a reset condition while VCC is below the threshold value of VWI, (see Figure 8.1).While reset, all operations are disabled and no commands are recognized. During power-up and after the VCC voltage exceeds VCC(min), all commands are further disabled for a time delay of tVSL. Note that the chip select pin (CS#) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up resistor on CS# can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable command must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Registers command will be accepted. After completing a program, erase or write command the Write Enable Latch (WEL) is automatically cleared to a write-disabled state of 0. Software controlled main flash array write protection is facilitated using the Write Status Registers command to write the Status Register (SR1,SR2) and Block Protect (SEC, TB, BP2, BP1 and BP0) bits. Zbit Semiconductor, Inc. 27 ZB25VQ32D_DTR The BP method allows a portion as small as 4-KB sector or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register can be enabled or disabled under hardware control. See the Table 6.4 for further information. Additionally, the Deep Power-Down (DPD) command offers an alternative means of data protection as all commands are ignored during the DPD state, except for the Release from Deep-Power-Down (RES ABh) command. Thus, preventing any program or erase during the DPD state. 6.3.2 Block Protection Maps Table 6.5 ZB25VQ32D_DTR Block Protection (CMP = 0) Status Register (1) SEC TB BP2 BP1 BP0 X 0 0 0 0 0 0 0 0 0 0 0 0 X X 0 0 0 0 0 0 1 1 1 1 1 1 X 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 0 1 X 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 X 0 ZB25VQ32D_DTR(32 Mbit) Block Protection (CMP=0) (2) Protected Protected Protected Block(s) Protected Addresses Density Portion None None None None 63 3F0000h – 3FFFFFh 64 KB Upper 1/64 62 and 63 3E0000h – 3FFFFFh 128 KB Upper 1/32 60 thru 63 3C0000h – 3FFFFFh 256 KB Upper 1/16 56 thru 63 380000h – 3FFFFFh 512 KB Upper 1/8 48 thru 63 300000h – 3FFFFFh 1 MB Upper 1/4 32 thru 63 200000h – 3FFFFFh 2MB Upper 1/2 0 000000h – 00FFFFh 64 KB Lower 1/64 0 and 1 000000h – 01FFFFh 128 KB Lower 1/32 0 thru 3 000000h – 03FFFFh 256 KB Lower 1/16 0 thru 7 000000h – 07FFFFh 512 KB Lower 1/8 0 thru 15 000000h – 0FFFFFh 1 MB Lower 1/4 0 thru 31 000000h – 1FFFFFh 2 MB Lower 1/2 0 thru 63 000000h – 3FFFFFh 4 MB All Upper 63 3FF000h – 3FFFFFh 4 KB 1/1024 63 3FE000h – 3FFFFFh 8 KB Upper 1/512 63 3FC000h – 3FFFFFh 16 KB Upper 1/256 63 3F8000h – 3FFFFFh 32 KB Upper 1/128 63 3F8000h – 3FFFFFh 32 KB Upper 1/128 Lower 0 000000h – 000FFFh 4 KB 1/1024 0 000000h – 001FFFh 8 KB Lower 1/512 0 000000h – 003FFFh 16 KB Lower 1/256 0 000000h – 007FFFh 32 KB Lower 1/128 0 000000h – 007FFFh 32 KB Lower 1/128 Notes: (1) X = don’t care. (2) If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. Zbit Semiconductor, Inc. 28 ZB25VQ32D_DTR Table 6.6 ZB25VQ32D_DTR Block Protection (CMP = 1) Status Register (1) SEC TB BP2 BP1 BP0 X 0 0 0 0 0 0 0 0 0 0 0 0 X X 0 0 0 0 0 0 1 1 1 1 1 1 X 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 X 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 X 1 1 1 1 0 ZB25VQ32D_DTR(32 Mbit) Block Protection (CMP=1) (2) Protected Protected Protected Block(s) Protected Addresses Density Portion 0 thru 63 000000h – 3FFFFFh 4 MB All 0 thru 62 000000h – 3EFFFFh 4032 KB Lower 63/64 0 thru 61 000000h – 3DFFFFh 3986 KB Lower 31/32 0 thru 59 000000h – 3BFFFFh 3840 KB Lower 15/16 0 thru 55 000000h – 37FFFFh 3584 KB Lower 7/8 0 thru 47 000000h – 2FFFFFh 3 MB Lower 3/4 0 thru 31 000000h – 1FFFFFh 2 MB Lower 1/2 1 thru 63 010000h – 3FFFFFh 4032 KB Upper 63/64 2 thru 63 020000h – 3FFFFFh 3986 KB Upper 31/32 4 thru 63 040000h – 3FFFFFh 3840 KB Upper 15/16 8 thru 63 080000h – 3FFFFFh 3584 KB Upper 7/8 16 thru 63 100000h – 3FFFFFh 3 MB Upper 3/4 32 thru 63 200000h – 3FFFFFh 2 MB Upper 1/2 None None None None Lower 0 thru 63 000000h – 3FEFFFh 4092 KB 1023/1024 Lower 0 thru 63 000000h – 3FDFFFh 4088 KB 511/512 Lower 0 thru 63 000000h – 3FBFFFh 4080 KB 255/256 Lower 0 thru 63 000000h – 3F7FFFh 4064 KB 127/128 Lower 0 thru 63 000000h – 3F7FFFh 4064 KB 127/128 Upper 0 thru 63 001000h – 3FFFFFh 4092 KB 1023/1024 Upper 0 thru 63 002000h – 3FFFFFh 4088 KB 511/512 Upper 0 thru 63 004000h – 3FFFFFh 4080 KB 255/256 Upper 0 thru 63 008000h – 3FFFFFh 4064 KB 127/128 Upper 0 thru 63 008000h – 3FFFFFh 4064 KB 127/128 Notes: (1) X = don’t care. (2) If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. 6.4 Page Program To program one data Byte, two instructions are required: Write Enable (WREN), which is one Byte, and a Page Program (PP) sequence, which consists of four Bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 Bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. 6.5 Sector Erase, Block Erase and Chip Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the Bytes of memory need to be erased to all 1s (FFh). This can be achieved a sector at a time, using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration tSE tBE or tCE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. 6.6 Active Power, Stand-by Power and Deep Power-Down Modes When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal Zbit Semiconductor, Inc. 29 ZB25VQ32D_DTR cycles have completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI) instruction) is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Program or Erase instructions. 6.7 Polling during a Write, Program or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or CE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE or tCE). The Write In Progress (BUSY) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. Zbit Semiconductor, Inc. 30 ZB25VQ32D_DTR 7 INSTRUCTIONS The instruction set of the ZB25VQ32D_DTR consists of 38 basic instructions that are fully controlled through the SPI bus. Instructions are initiated with the falling edge of Chip Select (CS#). The first Byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. The QPI instruction set of the ZB25VQ32D_DTR consists of 31 basic instructions that are fully controlled through the SPI bus (see Instruction Set Table 7.5). Instructions are initiated with the falling edge of Chip Select (CS#). The first Byte of data clocked through IO[3:0] pins provides the instruction code. Data on all four IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI instructions, addresses, data and dummy Bytes are using all four IO pins to transfer every Byte of data with every two serial clocks (CLK). For SPI/QPI DTR Read instructions, the address input is sampled on both rising and falling edges of the clock; the data output is also ready on both edges of the clock. Instructions vary in length from a single Byte to several Bytes and may be followed by address Bytes, data Bytes, dummy Bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising edge of edge CS#. Clock relative timing diagrams for each instruction are included in figures 7.1 through 7.41. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a Byte boundary (CS# driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register and Erase/Program Suspend will be ignored until the program or erase cycle completes. Zbit Semiconductor, Inc. 31 ZB25VQ32D_DTR Table 7.1 Command Set (Configuration, Status, Erase, Program Instructions (1), SPI Mode) Command Name Read Status Register-1 Read Status Register-2 Read Status Register-3 Write Enable Write Enable for Volatile Status Register Write Disable Write Status Registers-1 Write Status Registers-2 Write Status Registers-3 Set Burst with Wrap Page Program Quad Page Program Sector Erase (4 KB) Block Erase (32 KB) Block Erase (64 KB) Chip Erase Erase/Program Suspend Erase/Program Resume Enter QPI Mode Enable Reset Reset Device BYTE 1 (Instruction) 05h 35h 15h 06h BYTE 2 BYTE 3 BYTE 4 SR2[7:0] SR3[7:0] xxh A15—A8 A15—A8 A15—A8 A15—A8 A15—A8 xxh A7—A0 A7—A0 A7—A0 A7—A0 A7—A0 BYTE 5 BYTE 6 SR1[7:0](2) SR2[7:0](2) SR3[7:0](2) 50h 04h 01h 31h 11h 77h 02h 32h 20h 52h D8h C7h/60h 75h 7Ah 38h 66h 99h SR1[7:0](5) SR2[7:0] SR3[7:0] xxh A23—A16 A23—A16 A23—A16 A23—A16 A23—A16 W[7:0](3) D7—D0 D7—D0(4) Notes: (1) Data Bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device on the DO pin. (2) Status Register contents will repeat continuously until CS# terminates the command. (3) Set Burst with Wrap Input format. IO0 = x, x, x, x, x, x, W4, x IO1 = x, x, x, x, x, x, W5, x IO2 = x, x, x, x, x, x, W6 x IO3 = x, x, x, x, x, x, x,x (4) Quad Page Program Input Data: IO0 = ( D4,D0,...) IO1 = ( D5,D1,...) IO2 = ( D6,D2,...) IO3 = ( D7,D3,...) (5) The 01h command could continuously write up to three Bytes to registers SR1, SR2, SR3. Zbit Semiconductor, Inc. 32 ZB25VQ32D_DTR Table 7.2 Command Set (Read Instructions, SPI Mode) Command Name Read Data Fast Read Fast Read Dual Output Fast Read Quad Output Fast Read Dual I/O Fast Read Quad I/O BYTE 1 (Instruction) 03h 0Bh BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 A23—A16 A23—A16 A15—A8 A15—A8 A7—A0 A7—A0 (D7—D0,…) dummy (D7—D0,…) 3Bh A23—A16 A15—A8 A7—A0 dummy (D7—D0,…)(1) 6Bh A23—A16 A15—A8 A7—A0 dummy (D7—D0,…)(3) BBh A23—A8(2) A7—A0,M7—M0(2) (D7—D0,…)(1) EBh A23—A0,M7—M0(4) (x,x,x,x,D7—D0,...) (D7—D0,…)(3) Notes: (1) Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) (2) Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1 (3) Quad Output Data IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3, …..) (4) Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 Zbit Semiconductor, Inc. 33 ZB25VQ32D_DTR Table 7.3 Command Set (Read ID Command Name Deep Power-down Release Power down / Device ID Manufacturer/ Device ID(2) Manufacturer/ Device ID by Dual I/O Manufacturer/ Device ID by Quad I/O JEDEC ID Read SFDP Register Read Security Registers(3) Erase Security Registers(3) Program Security Registers(3) Read Unique ID BYTE 1 (Instruction) (1) , OTP Instructions, SPI Mode) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 ABh dummy dummy dummy Device ID(1) 90h dummy dummy 00h Manufacturer Device ID 92h A23—A8 A7—A0,M[7:0] (MF[7:0],ID[7:0]) 94h A23—A0,M[7:0] XXXX,(MF[7:0],ID[7:0]) (MF[7:0],ID[7:0]...) 9Fh Manufacturer Memory Type Capacity 5Ah 00h 00h A7—A0 dummy (D7—D0,…) 48h A23—A16 A15—A8 A7—A0 dummy (D7—D0,…) 44h A23—A16 A15—A8 A7—A0 42h A23—A16 A15—A8 A7—A0 D7—D0,… 4Bh A23—A16 A15—A8 A7—A0 dummy B9h (ID127-ID0) Notes: (1) The Device ID will repeat continuously until CS# terminates the command. (2) Legacy Device Identification Commands on page 58 for Device ID information. The 90h instruction is followed by an address. Address = 0 selects Manufacturer ID as the first returned data as shown in the table. Address = 1 selects Device ID as the first returned data followed by Manufacturer ID. (3) Security Register Address: Security Register 1: A23-16 = 00h; A15-10 = 000100b; A9-0 = Byte address Security Register 2: A23-16 = 00h; A15-10 = 001000b; A9-0 = Byte address Security Register 3: A23-16 = 00h; A15-10 = 001100b; A9-0 = Byte address Table 7.4 (1) Manufacturer and Device Identification(SPI and QPI Mode) OP Code ABh 90h/92h/94h 9Fh Data1 Device ID = 15h Manufacturer ID = 5E Manufacturer ID = 5E Data2 Device ID = 15h Memory Type =80h Data3 Capacity = 16h Notes: (1) Please contact sales for more information Zbit Semiconductor, Inc. 34 ZB25VQ32D_DTR Table 7.5 Command Set (QPI Instructions, QPI Mode) Command Name Clock Number Write Enable Write Enable for Volatile Status Register Write Disable Read Status Register-1 Write Status Register-1 Read Status Register-2 Write Status Register-2 Read Status Register-3 Write Status Register-3 Chip Erase Erase / Program Suspend Erase / Program Resume Deep Power-down Set Read Parameters Release Power down / ID Manufacturer/Device ID JEDEC ID Exit QPI Mode Enable Reset Reset Device Page Program Sector Erase (4KB) Block Erase (32KB) Block Erase (64KB) Fast Read Burst Read with Wrap(5) Fast Read Quad I/O BYTE 1 (Instruction) (0, 1) 06h BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 (2, 3) (4, 5) (6, 7) (8, 9) (10, 11) (S15-S8) (S23-S16) P7-P0 Dummy Dummy (MF7-MF0) Dummy Dummy (ID15-ID8) Dummy 00h (ID7-ID0) (ID7-ID0)(1) (MF7-MF0) (ID7-ID0) A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 D7-D0(3) D7-D0(2) Dummy(4) Dummy(4) M7-M0(4) D7-D0 D7-D0 D7-D0 50h 04h 05h 01h 35h 31h 15h 11h C7h/60h 75h 7Ah B9h C0h ABh 90h 9Fh/AFh FFh 66h 99h 02h 20h 52h D8h 0Bh 0Ch EBh (S7-S0)(1) (S7-S0)(6) (S15-S8)(1) (S15-S8) (S23-S16)(1) (S23-S16) Notes: (1) The Status Register contents and Device ID will repeat continuously until CS# terminates the instruction. (2) At least one Byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 1024 Bytes of data input. If more than 1024 Bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. (3) Quad SPI data input/output format: IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3, …..) (4) The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is controlled by read parameter P7 – P4. (5) The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0. (6) Write Status Register-1 (01h) can also be used to program Status Register-1&2&3, see section 7.1.5. Zbit Semiconductor, Inc. 35 ZB25VQ32D_DTR Table 7.6 Command Set (DTR Instructions, SPI Mode) Command Name Clock Number DTR Fast Read BYTE 1 (Instruction) (0 - 7) BYTE 3 BYTE 4 BYTE 5 BYTE 6 (8 - 11) (12 - 15) (16 - 19) (26 - 29) A23—A16 A15—A8 A7—A0 (0 - 7) (8, 9) (10, 11) (12, 13) (20 - 25) 6 - CLK dummy (14, 15) BDh A23—A16 A15—A8 A7—A0 M7—M0 (0 - 7) (8) (9) (10) (11) EDH A23—A16 A15—A8 A7—A0 M7—M0 0Dh Clock Number DTR Fast Read Dual I/O Clock Number DTR Fast Read Quad I/O BYTE 2 BYTE 7 (D7—D0,…) (16 - 19) 4 - CLK dummy (12 - 18) 7 - CLK dummy (20, 21) (D7—D0,…) (19) (D7—D0,…) Table 7.7 Command Set (DTR Instructions, QPI Mode) Command Name BYTE 1 (Instruction) (0, 1) BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 (2) (3) (4) (13) 0Eh A23—A16 A15—A8 A7—A0 DTR Fast Read 0Dh A23—A16 A15—A8 A7—A0 Clock Number DTR Fast Read Quad I/O (0, 1) (2) (3) (4) (5 - 12) 8 - CLK dummy 8 - CLK dummy (5) EDH A23—A16 A15—A8 A7—A0 M7—M0 Clock Number DTR Burst Read with Wrap BYTE 7 (D7—D0,…) (D7—D0,…) (6 - 12) 7 - CLK dummy (13) (D7—D0,…) 7.1 Configuration and Status Commands 7.1.1 Read Status Register (05h/35h/15h) The Read Status Register commands allow the 8-bit Status Registers to be read. The command is entered by driving CS# low and shifting the instruction code “05h” for Status Register-1, “35h” for Status Register-2, “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The Status Register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.1. The Status Register bits are shown in Section 6.2, Status Registers. The Read Status Register-1 (05h) command may be used at any time, even during a Program, Erase, or Write Status Registers cycle. This allows the BUSY status bit to be checked to determine when the operation is complete and if the device can accept another command. CS# Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Mode 0 DI Mode 3 05h/35h/15h DO S7-S0 out Instruction Status S7-S0 out Updated Status Figure 7.1a Read Status Register Instruction(SPI Mode) Zbit Semiconductor, Inc. 36 ZB25VQ32D_DTR CS# 0 Mode 3 CLK 1 2 3 4 5 Mode 0 IO0 4 0 S4 S0 S4 S0 S4 IO1 5 1 S5 S1 S5 S1 S5 IO2 6 2 S6 S2 S6 S2 S6 IO3 7 3 S7 S3 S7 S3 S7 Instruction SR-1/2/3 SR-1/2/3 05h/35h/15h out out Figure 7.1b Read Status Register Instruction(QPI Mode) 7.1.2 Write Enable (06h) The Write Enable instruction (Figure 7.2) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instruction. The Write Enable instruction is entered by driving CS# low, shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving CS# high. CS# Mode 3 CLK CS# Mode 3 CLK DI 0 1 2 3 4 Mode 0 5 6 7 0 1 Mode 0 Mode 3 Mode 0 Mode 3 Mode 0 06h DO IO0 4 0 IO1 5 1 IO2 6 2 7 3 Instruction IO3 Instruction 06h Figure 7.2 Write Enable Instruction (SPI or QPI Mode) 7.1.3 Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described in section 6.2 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h / 11h) instruction. Write Enable for Volatile Status Register instruction (Figure 7.3) will not set the Write Enable Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status Register bit values. Zbit Semiconductor, Inc. 37 ZB25VQ32D_DTR CS# Mode 3 CLK CS# Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 0 1 Mode 3 Mode 0 Mode 3 Mode 0 50h DI 0 Mode 0 DO IO0 4 0 IO1 5 1 IO2 6 2 7 3 Instruction IO3 Instruction 50h Figure 7.3 Write Enable for Volatile Status Register Instruction (SPI or QPI Mode) 7.1.4 Write Disable (04h) The Write Disable instruction (Figure 7.4) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving CS# low, shifting the instruction code “04h” into the DI pin and then driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. CS# Mode 3 CLK CS# Mode 3 CLK DI 0 1 2 3 4 Mode 0 5 6 7 DO 1 Mode 3 Mode 0 Mode 3 Mode 0 04h 0 Mode 0 IO0 4 0 IO1 5 1 IO2 6 2 7 3 Instruction IO3 Instruction 04h Figure 7.4 Write Disable Instruction(SPI or QPI Mode) 7.1.5 Write Status Register (01h/31h/11h) The Write Status Registers command allows the Status Registers to be written. Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (SR1[7:2]) CMP, LB3, LB2, LB1, QE, SRP1 (SR2[6:3,1,0]), and HRSW, DRV[1:0], HFM, DC (SR3[7:4,0]) can be written. All other Status Register bit locations are read-only and will not be affected by the Write Status Registers command. LB[3:1] are non-volatile OTP bits; once each is set to 1, it cannot be cleared to 0. The Status Register bits are shown in Section 6.2, Status Registers. Any reserved bits should only be written to their default value. To write non-volatile Status Register bits, a standard Write Enable (06h) command must previously have been executed for the device to accept the Write Status Registers Command (Status Register bit WEL must equal 1). Once write enabled, the command is entered by driving CS# low, sending the instruction code “01h”, and then writing the Status Register data Bytes as illustrated in Figure 7.5. To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) command must have been executed prior to the Write Status Registers command (Status Register bit WEL Zbit Semiconductor, Inc. 38 ZB25VQ32D_DTR remains 0). However, LB3, LB2, LB1 and SRP1 cannot be changed because of the OTP protection for these bits. Upon power-off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored when power on again. To complete the Write Status Registers command, the CS# pin must be driven high after the eighth bit of a data value is clocked in (CS# must be driven high on an 8-bit boundary). If this is not done the Write Status Registers command will not be executed. The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction must previously have been executed for the device to accept the Write Status Register Instruction (Status Register bit WEL must equal to 1). Once write enabled, the instruction is entered by driving CS# low, sending the instruction code “01h”, and then writing the status register data Byte as illustrated in Figure 7.5. During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after CS# is driven high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. During volatile Status Register write operation (50h combined with 01h/31h/11h), after CS# is driven high, the Status Register bits will be refreshed to the new values. BUSY bit will remain 0 during the Status Register bit refresh period. If CS# is driven high after the eighth clock, the Write Status Register-1 (01h) instruction will only program the Status Register-1, the Status Register-2 will not be affected. Note: (1) In QPI mode, QE bits will not be cleared to 0. CS# Mode 3 CLK DI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 0 Mode 3 Mode 0 01h/31h/11h S7-S0 in DO Instruction Input Status Register Figure 7.5a Write Status Register Instruction(SPI Mode) Zbit Semiconductor, Inc. 39 ZB25VQ32D_DTR CS# Mode 3 CLK 0 1 2 3 Mode 0 Mode 3 Mode 0 IO0 4 0 S4 S0 IO1 5 1 S5 S1 IO2 6 2 S6 S2 IO3 7 3 S7 S3 Instruction SR-1/2/3 01h/31h/11h in Figure 7.5b Write Status Register Instruction(QPI Mode) 7.2 Program and Erase Commands 7.2.1 Page Program (PP) (02h) The Page Program instruction allows up to 256 Bytes of data to be programmed at previously erased to all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one data Byte, into the DI pin. The CS# pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in Figure 7.6. If an entire 256 Byte page is to be programmed, the last address Byte (the 8 least significant address bits) should be set to 0. If the last address Byte is not zero, and the number of clocks exceeds the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 Bytes (a partial page) can be programmed without having any effect on other Bytes within the same page. One condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. If more than 256 Bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the last Byte has been latched. If this is not done the Page Program instruction will not be executed. After CS# is driven high, the self-timed Page Program instruction will commence for a time duration of tPP (See AC Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (TB, SEC, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Zbit Semiconductor, Inc. 40 ZB25VQ32D_DTR CS# Mode 3 CLK 0 1 2 3 4 5 6 7 8 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Mode 0 02h DI 24-bit 8-bit 8-bit DO Instruction Input Data 1 Address Input Data 2 Figure 7.6a Page Program Instruction (SPI Mode) CS# Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 512 513 514 515516 517518 519 Mode 0 Mode 3 Mode 0 IO0 4 0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 IO1 5 1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 IO2 6 2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 IO3 7 3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Instruction Address D1 D2 D3 D4 D253 D254 D255 D256 02h Figure 7.6b Page Program Instruction(QPI Mode) 7.2.2 Quad Input Page Program (32h) The Quad Input Page Program instruction allows up to 256 Byte of data to be programmed at previously erased (FFh) memory locations using four pins: IO0, IO1, IO2 and IO3. The Quad Input Page Program can improved performance for PROM Programmer and applications that have slow clock speeds