ESP32-C5-WROOM-1
ESP32-C5-WROOM-1U
Datasheet
Version 1.1
Module that supports 2.4 and 5 GHz dual-band Wi-Fi 6 (802.11ax), Bluetooth® 5 (LE),
Zigbee, and Thread (802.15.4)
Built around ESP32-C5 series of SoCs, 32-bit RISC-V single-core microprocessor
Flash up to 32 MB
Up to 22 GPIOs, rich set of peripherals
On-board PCB antenna or external antenna connector
ESP32-C5-WROOM-1
ESP32-C5-WROOM-1U
www.espressif.com
1 Module Overview
1 Module Overview
Note:
Check the link or the QR code to make sure that you use the latest version of this document:
https://espressif.com/documentation/esp32-c5-wroom-1_wroom-1u_datasheet_en.pdf
1.1 Features
– 20 MHz bandwidth
CPU and On-Chip Memory
– Downlink fullband MU-MIMO
• ESP32-C5 embedded, 32-bit RISC-V
• Fully compatible with IEEE 802.11b/g/n protocol
single-core microprocessor, up to 240 MHz
• ROM: 320 KB
– 20 MHz and 40 MHz bandwidth
• HP SRAM: 384 KB
– MCS0 ~ MCS7
• LP SRAM: 16 KB
– Wi-Fi Multimedia (WMM)
• PSRAM: Up to 8 MB (optional)
– TX/RX A-MPDU, TX/RX A-MSDU
– Immediate Block ACK
Wi-Fi
– Fragmentation and defragmentation
• 1T1R in 2.4 and 5 GHz dual band
– Transmit opportunity (TXOP)
• Operating frequency: 2412 ~ 2484 MHz, 5180 ~
– Automatic Beacon monitoring (hardware
5885 MHz
TSF)
• Data rate up to 150 Mbps
– Four virtual Wi-Fi interfaces
• IEEE 802.11ax-compliant
– Simultaneous support for Infrastructure
BSS in Station mode, SoftAP mode, Station
– 20 MHz-only non-AP mode
+ SoftAP mode, and promiscuous mode
– Uplink and downlink OFDMA to enhance
Note that when ESP32-C5 scans in Station
connectivity and performance in
mode, the SoftAP channel will change
congested environments for IoT
along with the Station channel
applications
– Antenna diversity
– Downlink MU-MIMO (multi-user, multiple
– 802.11mc FTM
input, multiple output) to increase network
capacity
Bluetooth®
– Beamformee that improves signal quality
• Bluetooth LE: Bluetooth Core 6.0 certified
– Spatial reuse to maximize parallel
• Bluetooth mesh 1.1
transmissions
• High power mode (20 dBm)
– Target wake time (TWT) that optimizes
• Direction finding (AoA/AoD)
power saving mechanisms
• IEEE 802.11ac-compliant
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• Periodic advertising with responses (PAwR)
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
1 Module Overview
• LE connection subrating
system timer, general-purpose timers, RTC
timer, watchdog timers, etc.
• LE power control
• Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps
Integrated Components on Module
• LE advertising extensions and multiple
• 48 MHz crystal oscillator
advertising sets
• Up to 32 MB SPI flash (optional)
• Allow devices to operate in Broadcaster,
• Dual-band diplexer
Observer, Central, and Peripheral roles
concurrently
Antenna Options
IEEE 802.15.4
• ESP32-C5-WROOM-1: On-board PCB antenna
• ESP32-C5-WROOM-1U: External antenna via a
• Compliant with IEEE 802.15.4-2015 protocol
connector or module pins
• OQPSK PHY in 2.4 GHz band
• Data rate: 250 Kbps
Operating Conditions
• Thread 1.4
• Operating voltage/Power supply: 3.0 ~ 3.6 V
• Zigbee 3.0
• Operating ambient temperature: –40 ~ 85 °C
Certification
Peripherals
• GPIO, SPI, parallel IO interface, UART, I2C, I2S,
• RF certification: See certificates
RMT (TX/RX), pulse counter, LED PWM, USB
• Green certification: RoHS/REACH
Serial/JTAG controller, MCPWM, GDMA, CAN FD
controller, SDIO slave controller, BitScrambler,
Test
event task matrix, ADC, temperature sensor,
• HTOL/HTSL/uHAST/TCT/ESD
brownout detector, analog voltage comparator,
1.2
Series Comparison
ESP32-C5-WROOM-1 and ESP32-C5-WROOM-1U are two general-purpose 2.4 and 5 GHz dual-band Wi-Fi 6
(802.11ax), Bluetooth® 5 (LE), Zigbee, and Thread (802.15.4) modules. The rich set of peripherals and high
performance make the module an ideal choice for smart homes, industrial automation, health care, consumer
electronics, etc.
ESP32-C5-WROOM-1 comes with a PCB antenna. ESP32-C5-WROOM-1U comes with a connector for an
external antenna.
A wide selection of module variants are available. The variant nomenclature is shown in Figure 1-1, and the
series comparisons are listed in Table 1-1 and Table 1-2.
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1 Module Overview
The nomenclature for the module variants is as follows:
ESP32-C5
-XX-XX
H/N
x
R
x
PSRAM size (MB)
PSRAM (optional)
Flash size (MB)
Ambient temperature (℃)
H：-40 ~ 105
N：-40 ~ 85
Module name
Figure 1-1. ESP32-C5 Module Variant Nomenclature
The series comparison for the two modules is as follows:
Table 1-1. ESP32-C5-WROOM-1 (ANT) Series Comparison1
Part Number2
Flash3,4
PSRAM
ESP32-C5-WROOM-1-N4
4 MB (Quad SPI)
-
ESP32-C5-WROOM-1-N8R8
8 MB (Quad SPI)
ESP32-C5-WROOM-1-N16R8
16 MB (Quad SPI)
ESP32-C5-WROOM-1-N32R8
32 MB (Quad SPI)
8 MB
(Quad SPI)
Embedded
Chip
Ambient
Temp.5 (°C)
Size6
(mm)
ESP32-C5HF4
ESP32-C5HR8
–40 ~ 85
18.0 × 27.5
× 3.3
1 This table shares the notes 3-6 presented in Table 1-2 below.
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1 Module Overview
Table 1-2. ESP32-C5-WROOM-1U (CONN)7 Series Comparison
Part Number2
Flash3,4
PSRAM
ESP32-C5-WROOM-1U-N4
4 MB (Quad SPI)
-
ESP32-C5-WROOM-1U-N8R8
8 MB (Quad SPI)
ESP32-C5-WROOM-1U-N16R8
16 MB (Quad SPI)
ESP32-C5-WROOM-1U-N32R8
32 MB (Quad SPI)
8 MB
(Quad SPI)
Embedded
Chip
Ambient
Temp.5 (°C)
Size6
(mm)
ESP32-C5HF4
ESP32-C5HR8
–40 ~ 85
18.0 × 21.2
× 3.3
2 Variants with special flash, PSRAM sizes, or ambient temperatures are not listed individually. For customization
requests, please contact us. For variants not listed above, refer to Figure 1-1 ESP32-C5 Module Variant Nomenclature for the detailed specifications.
3 For specifications, refer to Section 6.5 Memory Specifications.
4 By default, the SPI flash on the module operates at a maximum clock frequency of 80 MHz and does not support
the auto suspend feature. If you need the flash auto suspend feature, please contact us.
5 Ambient temperature specifies the recommended temperature range of the environment immediately outside
the Espressif module.
6 For details, refer to Section 10.1 Module Dimensions.
7 ESP32-C5-WROOM-1U uses ANT1 by default. To order a custom ANT2 model, append the suffix T2 to the
general part number, for example: ESP32-C5-WROOM-1U-N8R8T2.
At the core of the modules is ESP32-C5 *, a 32-bit RISC-V single-core microprocessor operates at up to 240
MHz. You can power off the CPU and make use of the low-power coprocessor to constantly monitor the
peripherals for changes or crossing of thresholds.
Note:
For more information on ESP32-C5, please refer to ESP32-C5 Series Datasheet.
1.3 Applications
• Smart Home
• Service Robot
• Industrial Automation
• Audio Devices
• Health Care
• Generic Low-power IoT Sensor Hubs
• Consumer Electronics
• Generic Low-power IoT Data Loggers
• Smart Agriculture
• POS Machines
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• Wi-Fi + Bluetooth Networking Card
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
Contents
Contents
1
Module Overview
2
1.1
Features
2
1.2
Series Comparison
3
1.3
Applications
5
2
Block Diagram
11
3
Pin Definitions
12
3.1
Pin Layout
12
3.2
Pin Description
13
4
Boot Configurations
16
4.1
Chip Boot Mode Control
17
4.2
SDIO Sampling and Driving Clock Edge Control
18
4.3
ROM Messages Printing Control
18
4.4
JTAG Signal Source Control
19
4.5
Chip Power-up and Reset
20
5
Peripherals
21
5.1
Peripheral Overview
21
5.2
Peripheral Description
21
5.2.1
21
5.2.2
Connectivity Interface
5.2.1.1
UART Controller
21
5.2.1.2
SPI Controller
22
5.2.1.3
I2C Controller
23
5.2.1.4
I2S Controller
23
5.2.1.5
USB Serial/JTAG Controller
24
5.2.1.6
CAN FD Controller
25
5.2.1.7
LED PWM Controller
25
5.2.1.8
Pulse Count Controller
26
5.2.1.9
Motor Control PWM
26
5.2.1.10
Remote Control Peripheral
27
5.2.1.11
Parallel IO Controller
28
5.2.1.12
BitScrambler
28
5.2.1.13
SDIO Slave Controller
29
Analog Signal Processing
30
5.2.2.1
Temperature Sensor
30
5.2.2.2
ADC Controller
30
5.2.2.3
Analog Voltage Comparator
31
6
Electrical Characteristics
32
6.1
Absolute Maximum Ratings
32
6.2
Recommended Operating Conditions
32
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Contents
6.3
DC Characteristics (3.3 V, 25 °C)
32
6.4
Current Consumption Characteristics
33
6.4.1
Current Consumption in Active Mode
33
6.4.2
Current Consumption in Other Modes
34
6.5
Memory Specifications
35
7
RF Characteristics
36
7.1
2.4 GHz Wi-Fi Radio
36
7.1.1
2.4 GHz Wi-Fi RF Transmitter (TX) Characteristics
36
7.1.2
2.4 GHz Wi-Fi RF Receiver (RX) Characteristics
37
7.2
7.3
7.4
5 GHz Wi-Fi Radio
39
7.2.1
5 GHz Wi-Fi RF Transmitter (TX) Characteristics
39
7.2.2
5 GHz Wi-Fi RF Receiver (RX) Characteristics
40
Bluetooth 5 (LE) Radio
42
7.3.1
Bluetooth LE RF Transmitter (TX) Characteristics
42
7.3.2
Bluetooth LE RF Receiver (RX) Characteristics
43
802.15.4 Radio
45
7.4.1
802.15.4 RF Transmitter (TX) Characteristics
46
7.4.2
802.15.4 RF Receiver (RX) Characteristics
46
8
Module Schematics
47
9
Peripheral Schematics
49
10 Physical Dimensions
51
10.1
Module Dimensions
51
10.2
Dimensions of External Antenna Connector
52
11 PCB Layout Recommendations
54
11.1
PCB Land Pattern
54
11.2
Module Placement for PCB Design
55
12 Product Handling
56
12.1
Storage Conditions
56
12.2
Electrostatic Discharge (ESD)
56
12.3
Reflow Profile
56
12.4
Ultrasonic Vibration
57
Datasheet Versioning
58
Related Documentation and Resources
59
Revision History
61
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
List of Tables
List of Tables
1-2
ESP32-C5-WROOM-1 (ANT) Series Comparison1
ESP32-C5-WROOM-1U (CONN)7 Series Comparison
3-1
ESP32-C5-WROOM-1 Pin Definitions 1
13
3-2 ESP32-C5-WROOM-1U Pin Definitions
14
4-1
16
1-1
4
5
Default Configuration of Strapping Pins
4-2 Description of Timing Parameters for the Strapping Pins
17
4-3 Boot Mode Control
18
4-4 SDIO Input Sampling Edge/Output Driving Edge Control
18
4-5 UART0 ROM Message Printing Control
19
4-6 USB Serial/JTAG ROM Message Printing Control
19
4-7 JTAG Signal Source Control
20
4-8 Description of Timing Parameters for Power-up and Reset
20
6-1 Absolute Maximum Ratings
32
6-2 Recommended Operating Conditions
32
6-3 DC Characteristics (3.3 V, 25 °C)
32
6-4 Current Consumption for Wi-Fi (2.4 GHz) in Active Mode
33
6-5 Current Consumption for Wi-Fi (5 GHz) in Active Mode
33
6-6 Current Consumption for Bluetooth LE in Active Mode
34
6-7 Current Consumption for 802.15.4 in Active Mode
34
6-8 Current Consumption in Modem-sleep Mode
34
6-9 Current Consumption in Low-Power Modes
35
6-10 Flash Specifications
35
6-11 PSRAM Specifications
35
7-1
36
2.4 GHz Wi-Fi RF Characteristics
7-2 2.4 GHz TX Power with Spectral Mask and EVM Meeting 802.11 Standards
7-3 2.4 GHz TX EVM Test1
36
7-4 2.4 GHz RX Sensitivity
37
7-5 2.4 GHz Maximum RX Level
38
7-6 2.4 GHz RX Adjacent Channel Rejection
38
7-7
39
5 GHz Wi-Fi RF Characteristics
36
7-8 5 GHz TX Power with Spectral Mask and EVM Meeting 802.11 Standards
7-9 5 GHz TX EVM Test1
39
7-10 5 GHz RX Sensitivity
40
7-11 5 GHz Maximum RX Level
41
7-12 5 GHz RX Adjacent Channel Rejection
41
7-13 Bluetooth LE RF Characteristics
42
7-14 Bluetooth LE - Transmitter Characteristics - 1 Mbps
42
7-15 Bluetooth LE - Transmitter Characteristics - 2 Mbps
42
7-16 Bluetooth LE - Transmitter Characteristics - 125 Kbps
43
7-17 Bluetooth LE - Transmitter Characteristics - 500 Kbps
43
7-18 Bluetooth LE - Receiver Characteristics - 1 Mbps
43
7-19 Bluetooth LE - Receiver Characteristics - 2 Mbps
44
7-20 Bluetooth LE - Receiver Characteristics - 125 Kbps
45
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39
ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
List of Tables
7-21 Bluetooth LE - Receiver Characteristics - 500 Kbps
45
7-22 802.15.4 RF Characteristics
45
7-23 802.15.4 Transmitter Characteristics - 250 Kbps
46
7-24 802.15.4 Receiver Characteristics - 250 Kbps
46
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
List of Figures
List of Figures
1-1
ESP32-C5 Module Variant Nomenclature
4
2-1
ESP32-C5-WROOM-1 Block Diagram
11
2-2 ESP32-C5-WROOM-1U Block Diagram
11
3-1
12
ESP32-C5-WROOM-1 Layout (Top View)
3-2 ESP32-C5-WROOM-1U Layout (Top View)
13
4-1
17
Visualization of Timing Parameters for the Strapping Pins
4-2 Visualization of Timing Parameters for Power-up and Reset
8-1
ESP32-C5-WROOM-1 Schematics
20
47
8-2 ESP32-C5-WROOM-1U Schematics
48
9-1
49
ESP32-C5-WROOM-1 Schematics
9-2 ESP32-C5-WROOM-1U Schematics
50
10-1 ESP32-C5-WROOM-1 Dimensions
51
10-2 ESP32-C5-WROOM-1U Dimensions
51
10-3 Dimensions of External Antenna Connector
52
11-1 ESP32-C5-WROOM-1 PCB Land Pattern
54
11-2 ESP32-C5-WROOM-1U PCB Land Pattern
55
12-1 Reflow Profile
56
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
2 Block Diagram
2 Block Diagram
3V3
48 MHz
Crystal
3V3
48 MHz
Crystal
ESP32-C5-WROOM-1
Antenna
ESP32-C5-WROOM-1
2.4G
ESP32-C5
EN
ESP32-C5
PSRAM(opt.)
5G
2.4G
RF
RF Matching
Matching
5G
RF Matching
SPICS0
SPICLK
SPID
SPIQ
SPIHD
SPIWP
VDD_SPI
EN
RF Matching
GND
Antenna
Diplexer
Diplexer
GPIOs
RF Matching
RF Matching
GPIOs
SPICS0
SPICLK
SPID
SPIQ
SPIHD
SPIWP
VDD_SPI
PSRAM(opt.)
QSPI Flash(opt.)
GND
QSPI Flash(opt.)
Figure 2-1. ESP32-C5-WROOM-1 Block Diagram
3V3
48 MHz
Crystal
3V3
48 MHz
Crystal
GND
GND
2.4G
ESP32-C5
PSRAM(opt.)
ESP32-C5
5G
2.4G
RF
RF Matching
Matching
5G
Antenna2
Antenna1
RF Matching
RF Matching
SPICS0
SPICLK
SPID
SPIQ
SPIHD
SPIWP
VDD_SPI
EN
ESP32-C5-WROOM-1U
Antenna2
Diplexer
Diplexer
GPIOs
RF Matching
Antenna1
RF Matching
GPIOs
PSRAM(opt.)
SPICS0
SPICLK
SPID
SPIQ
SPIHD
SPIWP
VDD_SPI
EN
ESP32-C5-WROOM-1U
QSPI Flash(opt.)
QSPI Flash(opt.)
Figure 2-2. ESP32-C5-WROOM-1U Block Diagram
Note:
For the pin mapping between the chip and the in-package flash/PSRAM, please refer to ESP32-C5 Series Datasheet
> Table Pin Mapping Between Chip and Flash/PSRAM.
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3 Pin Definitions
3
Pin Definitions
3.1
Pin Layout
The pin diagram below shows the approximate location of pins on the module. For the actual diagram drawn to
scale, please refer to Chapter 10.1 Module Dimensions.
Keepout Zone
GND
1
28
GND
3V3
2
27
IO26
EN
3
26
IO25
IO2
4
25
TX0
IO3
5
24
RX0
IO0
6
23
IO24
22
NC
21
IO23
20
NC
IO1
GND
GND
GND
GND
29
GND
GND
GND
GND
GND
7
IO6
8
IO7
9
IO8
10
19
NC/IO15
IO9
11
18
IO27
IO10
12
17
IO4
IO13
13
16
IO5
IO14
14
15
IO28
Figure 3-1. ESP32-C5-WROOM-1 Layout (Top View)
Pin Layout (Top View)
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GND
ANT2
GND
3 Pin Definitions
32
31
30
ANT1
28
GND
2
27
IO26
EN
3
26
IO25
IO2
4
25
TX0
IO3
5
24
RX0
IO0
6
23
IO24
22
NC
21
IO23
20
NC
GND
1
3V3
IO1
GND
GND
GND
GND
29
GND
GND
GND
GND
GND
7
IO6
8
IO7
9
IO8
10
19
NC/IO15
IO9
11
18
IO27
IO10
12
17
IO4
IO13
13
16
IO5
IO14
14
15
IO28
Figure 3-2. ESP32-C5-WROOM-1U Layout (Top View)
Pin Layout (Top View)
3.2
Pin Description
The module ESP32-C5-WROOM-1 has 29 pins, and module ESP32-C5-WROOM-1U has 32 pins. See pin
definitions in Table 3-1 ESP32-C5-WROOM-1 Pin Definitions 1 and Table 3-2 ESP32-C5-WROOM-1U Pin
Definitions.
For peripheral pin configurations, please refer to Section 5.2 Peripheral Description.
Table 3-1. ESP32-C5-WROOM-1 Pin Definitions 1
Name
No.
Type2
GND
1
P
Ground
3V3
2
P
Power Supply
EN
3
I
Function
High: on, enables the chip.
Low: off, the chip powers off.
Note: Do not leave the EN pin floating.
IO2
4
I/O/T
MTMS, GPIO2, LP_GPIO2, LP_UART_RTSN, LP_I2C_SDA, ADC1_CH1,
FSPIQ
Cont’d on next page
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3 Pin Definitions
Table 3-1 – cont’d from previous page
No.
Type2
Function
IO3
5
I/O/T
MTDI, GPIO3, LP_GPIO3, LP_UART_CTSN, LP_I2C_SCL, ADC1_CH2
IO0
6
I/O/T
GPIO0, XTAL_32K_P, LP_GPIO0, LP_UART_DTRN
IO1
7
I/O/T
GPIO1, XTAL_32K_N, LP_GPIO1, LP_UART_DSRN, ADC1_CH0
IO6
8
I/O/T
GPIO6, LP_GPIO6, ADC1_CH5, FSPICLK
IO7
9
I/O/T
GPIO7, FSPID, SDIO_DATA1
IO8
10
I/O/T
GPIO8, PAD_COMP0, SDIO_DATA0
IO9
11
I/O/T
GPIO9, PAD_COMP1, SDIO_CLK
IO10
12
I/O/T
GPIO10, FSPICS0, SDIO_CMD
IO13
13
I/O/T
GPIO13, USB_D-, SDIO_DATA3
IO14
14
I/O/T
GPIO14, USB_D+, SDIO_DATA2
IO28
15
I/O/T
GPIO28
IO5
16
I/O/T
MTDO, GPIO5, LP_GPIO5, LP_UART_TXD, ADC1_CH4, FSPIWP
IO4
17
I/O/T
MTCK, GPIO4, LP_GPIO4, LP_UART_RXD, ADC1_CH3, FSPIHD
IO27
18
I/O/T
GPIO27
NC/IO15
19
I/O/T
SPICS1, GPIO153
NC
20
-
IO23
21
I/O/T
NC
22
-
IO24
23
I/O/T
GPIO24
RX0
24
I/O/T
U0RXD, GPIO12
TX0
25
I/O/T
U0TXD, GPIO11
IO25
26
I/O/T
GPIO25
IO26
27
I/O/T
GPIO26
GND
28
P
Ground
EPAD
29
P
Ground
Name
NC
GPIO23
NC
1 This table shares the notes 2 and 3 presented in Table 3-2 below.
Table 3-2. ESP32-C5-WROOM-1U Pin Definitions
Name
No.
Type2
GND
1
P
Ground
3V3
2
P
Power Supply
EN
3
I
Function
High: on, enables the chip.
Low: off, the chip powers off.
Note: Do not leave the EN pin floating.
MTMS, GPIO2, LP_GPIO2, LP_UART_RTSN, LP_I2C_SDA, ADC1_CH1,
IO2
4
I/O/T
IO3
5
I/O/T
MTDI, GPIO3, LP_GPIO3, LP_UART_CTSN, LP_I2C_SCL, ADC1_CH2
IO0
6
I/O/T
GPIO0, XTAL_32K_P, LP_GPIO0, LP_UART_DTRN
IO1
7
I/O/T
GPIO1, XTAL_32K_N, LP_GPIO1, LP_UART_DSRN, ADC1_CH0
IO6
8
I/O/T
GPIO6, LP_GPIO6, ADC1_CH5, FSPICLK
FSPIQ
Cont’d on next page
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3 Pin Definitions
Table 3-2 – cont’d from previous page
No.
Type2
Function
IO7
9
I/O/T
GPIO7, FSPID, SDIO_DATA1
IO8
10
I/O/T
GPIO8, PAD_COMP0, SDIO_DATA0
IO9
11
I/O/T
GPIO9, PAD_COMP1, SDIO_CLK
IO10
12
I/O/T
GPIO10, FSPICS0, SDIO_CMD
IO13
13
I/O/T
GPIO13, USB_D-, SDIO_DATA3
IO14
14
I/O/T
GPIO14, USB_D+, SDIO_DATA2
IO28
15
I/O/T
GPIO28
IO5
16
I/O/T
MTDO, GPIO5, LP_GPIO5, LP_UART_TXD, ADC1_CH4, FSPIWP
IO4
17
I/O/T
MTCK, GPIO4, LP_GPIO4, LP_UART_RXD, ADC1_CH3, FSPIHD
IO27
18
I/O/T
GPIO27
NC/IO15
19
I/O/T
SPICS1, GPIO153
NC
20
-
IO23
21
I/O/T
NC
22
-
IO24
23
I/O/T
GPIO24
RX0
24
I/O/T
U0RXD, GPIO12
TX0
25
I/O/T
U0TXD, GPIO11
IO25
26
I/O/T
GPIO25
IO26
27
I/O/T
GPIO26
GND
28
P
Ground
EPAD
29
P
Ground
GND
30
P
Ground
ANT24
31
I/O
GND
32
P
Name
NC
GPIO23
NC
RF input and output
Ground
2 P: power supply; I: input; O: output; T: high impedance.
3 In modules with the in-package SPI PSRAM, this pin is used as SPICS1 for SPI PSRAM and cannot
be used for other functions; in modules without the in-package SPI PSRAM, this pin can be used
as GPIO15.
4 By default, ESP32-C5-WROOM-1U uses ANT1, and ANT2 is disabled. To use ANT2, please contact
us.
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4 Boot Configurations
4 Boot Configurations
Note:
The content below is excerpted from ESP32-C5 Series Datasheet > Section Boot Configurations. For the strapping
pin mapping between the chip and modules, please refer to Chapter 8 Module Schematics.
The chip allows for configuring the following boot parameters through strapping pins and eFuse parameters at
power-up or a hardware reset, without microcontroller interaction.
• Chip boot mode
– Strapping pin: GPIO26, GPIO27, and GPIO28
• SDIO sampling and driving clock edge
– Strapping pin: GPIO25 and MTDI
• ROM message printing
– Strapping pin: GPIO27
– eFuse parameter: EFUSE_UART_PRINT_CONTROL and
EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
• JTAG signal source
– Strapping pin: GPIO7
– eFuse parameter: EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG, and EFUSE_JTAG_SEL_ENABLE
The default values of all the above eFuse parameters are 0, which means that they are not burnt. Given that
eFuse is one-time programmable, once programmed to 1, it can never be reverted to 0. For how to program
eFuse parameters, please refer to ESP32-C5 Technical Reference Manual > Chapter eFuse Controller.
The default values of the strapping pins, namely the logic levels, are determined by pins’ internal weak
pull-up/pull-down resistors at reset if the pins are not connected to any circuit, or connected to an external
high-impedance circuit.
Table 4-1. Default Configuration of Strapping Pins
Strapping Pin
Default Configuration
Bit Value
GPIO25
Floating
–
GPIO26
Floating
–
GPIO27
Pull-up
1
GPIO28
Pull-up
1
GPIO7
Floating
–
MTMS
Floating
–
MTDI
Floating
–
To change the bit values, the strapping pins should be connected to external pull-down/pull-up
resistances.
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4 Boot Configurations
All strapping pins have latches. At Chip Reset, the latches sample the bit values of their respective strapping
pins and store them until the chip is powered down or shut down. The states of latches cannot be changed in
any other way. It makes the strapping pin values available during the entire chip operation, and the pins are
freed up to be used as regular IO pins after reset. For details on Chip Reset, see
ESP32-C5 Technical Reference Manual > Chapter Reset and Clock.
The timing of signals connected to the strapping pins should adhere to the setup time and hold time
specifications in Table 4-2 and Figure 4-1.
Table 4-2. Description of Timing Parameters for the Strapping Pins
Parameter
tSU
Description
Min (ms)
Setup time is the time reserved for the power rails to stabilize before the CHIP_PU pin is pulled high to activate the chip.
0
Hold time is the time reserved for the chip to read the strapping
tH
pin values after CHIP_PU is already high and before these pins
3
start operating as regular IO pins.
tSU
tH
VIH_nRST
CHIP_PU
VIH
Strapping pin
Figure 4-1. Visualization of Timing Parameters for the Strapping Pins
4.1
Chip Boot Mode Control
GPIO26, GPIO27 and GPIO28 control the boot mode after the reset is released. See Table 4-3 Boot Mode
Control.
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4 Boot Configurations
Table 4-3. Boot Mode Control
Boot Mode
SPI Boot1
GPIO26
GPIO27
Any value
Any value
GPIO28
11
Joint Download Boot 02
Any value
1
0
Joint Download Boot 13
0
0
0
1 Bold marks the default value and configuration.
2 Joint Download Boot 0 mode supports the following download methods:
• USB-Serial-JTAG Download Boot
• UART Download Boot
• SPI Slave Download Boot (chip revision v0.1 only)
3 Joint Download Boot 1 mode supports the following download methods:
• UART Download Boot
• SDIO Download Boot
In SPI Boot mode, the ROM bootloader loads and executes the program from SPI flash to boot the
system.
In Joint Download Boot 0 mode, users can download binary files into flash using UART0, USB, or SPI Slave
interfaces. It is also possible to download binary files into SRAM and execute it from SRAM.
In Joint Download Boot 1 mode, users can download binary files into flash using UART0 or SDIO interfaces. It is
also possible to download binary files into SRAM and execute it from SRAM.
4.2
SDIO Sampling and Driving Clock Edge Control
The strapping pin GPIO25 and MTDI can be used to decide on which clock edge to sample signals and drive
output lines. See Table 4-4 SDIO Input Sampling Edge/Output Driving Edge Control.
Table 4-4. SDIO Input Sampling Edge/Output Driving Edge Control
Edge behavior
GPIO25
MTDI
Falling edge sampling, falling edge output
0
0
Falling edge sampling, rising edge output
0
1
Rising edge sampling, falling edge output
1
0
Rising edge sampling, rising edge output
1
1
1 GPIO25 and MTDI are floating by default, so above are not
default configurations.
4.3
ROM Messages Printing Control
During the boot process, the messages by the ROM code can be printed to:
• (Default) UART0 and USB Serial/JTAG controller
• UART0
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• USB Serial/JTAG controller
To print ROM messages to UART0 or USB Serial/JTAG controller, see the description below.
EFUSE_UART_PRINT_CONTROL and GPIO27 control printing ROM messages to UART0 as shown in Table 4-5
UART0 ROM Message Printing Control.
Table 4-5. UART0 ROM Message Printing Control
Register2
UART0 ROM Message Printing
ROM messages are always printed to UART0 during boot
eFuse3
0 (0b00)
Print is enabled during boot
1 (0b01)
Print is disabled during boot
0
Print is disabled during boot
2 (0b10)
Print is enabled during boot
Print is disabled during boot
Print is disabled during boot
GPIO27
x4
0
1
0
1
3 (0b11)
x
x
x
1
1 Bold marks the default value and configuration.
2 Register: LP_AON_STORE4_REG[0]
3 eFuse: EFUSE_UART_PRINT_CONTROL
4 x: x indicates that the value has no effect on the result and can be ignored.
EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT controls the printing to USB Serial/JTAG controller as shown in
Table 4-6 USB Serial/JTAG ROM Message Printing Control.
Table 4-6. USB Serial/JTAG ROM Message Printing Control
USB Serial/JTAG
ROM Message
EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
Printing
Enabled
0
1
Disabled
Ignored
1 Bold marks the default value and configuration.
4.4
JTAG Signal Source Control
The strapping pin GPIO7 can be used to control the source of JTAG signals during the early boot process. This
pin does not have any internal pull resistors and the strapping value must be controlled by the external circuit
that cannot be in a high impedance state.
As Table 4-7 shows, GPIO7 is used in combination with EFUSE_DIS_PAD_JTAG, EFUSE_DIS_USB_JTAG, and
EFUSE_JTAG_SEL_ENABLE.
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Table 4-7. JTAG Signal Source Control
eFuse 12
JTAG Signal Source
eFuse 23
6
USB Serial/JTAG Controller
eFuse 34
0
0
0
JTAG pins MTDI, MTCK, MTMS, and MTDO
1
GPIO7
x5
1
0
x
1
USB Serial/JTAG Controller6
0
1
JTAG is disabled
x
x
x
1
1 Bold marks the default value and configuration.
2 eFuse 1: EFUSE_DIS_PAD_JTAG
3 eFuse 2: EFUSE_DIS_USB_JTAG
4 eFuse 3: EFUSE_JTAG_SEL_ENABLE
5 x: x indicates that the value has no effect on the result and can be ignored.
6 In Joint Download Boot 1 mode, the USB Serial/JTAG controller is forcibly disabled, and
the JTAG signal only comes from JTAG pins. If PAD_JTAG is also disabled, then JTAG is
disabled.
4.5 Chip Power-up and Reset
Once the power is supplied to the chip, its power rails need a short time to stabilize. After that, CHIP_PU – the
pin used for power-up and reset – should be pulled high to activate the chip. For information on CHIP_PU as
well as power-up and reset timing, see Figure 4-2 and Table 4-8.
tST BL
tRST
2.8 V
VDDPST1, VDDPST2, VDDPST3,
VDDA1, VDDA2, VDDA3,
VDDA4, VDDA5, VDDA6,
VDDA7, VDDA8
VIL_nRST
CHIP_PU
Figure 4-2. Visualization of Timing Parameters for Power-up and Reset
Table 4-8. Description of Timing Parameters for Power-up and Reset
Parameter
Description
Min (µs)
Time reserved for the power rails of VDDPST1, VDDPST2, VDtST BL
DPST3, VDDA1, VDDA2, VDDA3, VDDA4, VDDA5, VDDA6, VDDA7,
and VDDA8 to stabilize before the CHIP_PU pin is pulled high to
50
activate the chip
tRST
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chip (see Table 6-3)
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5 Peripherals
5 Peripherals
5.1
Peripheral Overview
ESP32-C5 integrates a rich set of peripherals including SPI, parallel IO interface, UART, I2C, I2S, RMT (TX/RX),
pulse counter, LED PWM, USB Serial/JTAG controller, MCPWM, GDMA, CAN FD controller, SDIO slave
controller, BitScrambler, event task matrix, ADC, temperature sensor, brownout detector, analog voltage
comparator, as well as up to 22 GPIOs, etc.
For detailed information about module peripherals, please refer to ESP32-C5 Series Datasheet > Section
Functional Description.
Note:
The content below is sourced from ESP32-C5 Series Datasheet > Section Peripherals. Some information may not be
applicable to ESP32-C5-WROOM-1 and ESP32-C5-WROOM-1U as not all the IO signals are exposed on the module.
To learn more about peripheral signals, please refer to ESP32-C5 Technical Reference Manual > Section Peripheral
Signal List.
5.2
Peripheral Description
This section describes the chip’s peripheral capabilities, covering connectivity interfaces and on-chip sensors
that extend its functionality.
5.2.1
Connectivity Interface
This subsection describes the connectivity interfaces on the chip that enable communication and interaction
with external devices and networks.
5.2.1.1
UART Controller
ESP32-C5 has three UART interfaces, i.e. UART0, UART1, and LP UART. All the three interfaces provide
hardware flow control (CTS and RTS signals) and software flow control (XON and XOFF).
Feature List
• programmable baud rates up to 5 MBaud
• RAM shared by TX FIFOs and RX FIFOs
• support for various lengths of data bits and stop bits
• parity bit support
• special character AT_CMD detection
• RS485 protocol support (not supported by LP UART)
• IrDA protocol support (not supported by LP UART)
• high-speed data communication using GDMA (not supported by LP UART)
• receive timeout feature
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• UART as the wake-up source
• software and hardware flow control
For details, see ESP32-C5 Technical Reference Manual > Chapter UART Controller (UART).
Pin Assignment
The pins connected to transmit and receive signals (U0TXD and U0RXD) for UART0 are multiplexed with
GPIO11 and GPIO12 via IO MUX. Other signals can be routed to any GPIOs via the GPIO matrix.
For LP UART, the pins used are multiplexed with LP_GPIO0 ~ LP_GPIO5 via LP IO MUX.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.1.2
SPI Controller
ESP32-C5 features three SPI interfaces (SPI0, SPI1, and SPI2). SPI0 and SPI1 can be configured to operate in
SPI memory mode, while SPI2 can be configured to operate in general-purpose SPI mode.
Feature List
• SPI Memory mode
In SPI memory mode, SPI0 and SPI1 interfaces are for external SPI memory. Data are transferred in unit of
byte. Up to four-line STR reads and writes are supported. The clock frequency is configurable to a
maximum of 120 MHz.
• SPI2 General-purpose SPI (GP-SPI) mode
SPI2 can operate in master and slave modes. SPI2 supports two-line full-duplex communication and
single/two/four-line half-duplex communication in both master and slave modes. The host’s clock
frequency is configurable. Data are transferred in unit of byte. The clock polarity (CPOL) and phase
(CPHA) are also configurable. The SPI2 interface can connect to GDMA.
– In master mode, the clock frequency is 80 MHz at most, and the four modes of SPI transfer format
are supported.
– In slave mode, the clock frequency is 40 MHz at most, and the four modes of SPI transfer format
are also supported.
For details, see ESP32-C5 Technical Reference Manual > Chapter SPI Controller (SPI).
Pin Assignment
For SPI0/1, the pins are multiplexed with GPIO15 ~ GPIO18 and GPIO20 ~ GPIO22 via the IO MUX.
For SPI2, the pins for data and clock signals are multiplexed with GPIO2 and GPIO4 ~ GPIO7 via the IO MUX.
The pins for chip select signals for multiplexed with GPIO10 via the IO MUX. SPI2 signals can also be routed to
any GPIOs via the GPIO matrix.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
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5.2.1.3 I2C Controller
ESP32-C5 has an I2C and an LP I2C bus interface. I2C is used for I2C master mode or slave mode, depending
on your configuration, while LP I2C is always in master mode.
Feature List
• standard mode (100 Kbit/s)
• fast mode (400 Kbit/s)
• up to 800 Kbit/s (constrained by SCL and SDA pull-up strength)
• 7-bit and 10-bit addressing mode
• double addressing mode
• 7-bit broadcast address
For details, see ESP32-C5 Technical Reference Manual > Chapter I2C Controller (I2C).
Pin Assignment
For regular I2C, the pins used can be chosen from any GPIOs via the GPIO Matrix.
For LP I2C, the pins used are multiplexed with LP_GPIO2 and LP_GPIO3 via LP IO MUX.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.1.4
I2S Controller
ESP32-C5 includes a standard I2S interface. This interface can operate as a master or a slave in full-duplex
mode or half-duplex mode, and supports 8-bit, 16-bit, 24-bit, or 32-bit serial communication. BCK clock
frequency, from 10 kHz up to 40 MHz, is supported.
The I2S interface supports TDM Philips, TDM MSB alignment, TDM PCM standard, PDM standard, and
PCM-to-PDM TX interface. It connects to the GDMA controller.
Feature List
• master mode and slave mode
• full-duplex and half-duplex communications
• separate TX and RX units that can work independently or simultaneously
• a variety of audio standards supported:
– TDM Philips standard
– TDM MSB alignment standard
– TDM PCM standard
– PDM standard
• various TX/RX modes
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– TDM TX mode, up to 16 channels supported
– TDM RX mode, up to 16 channels supported
– PDM TX mode
* raw PDM data transmission
* PCM-to-PDM data format conversion, up to 2 channels supported
– PDM RX mode
* raw PDM data reception
• configurable clock source with frequency up to 240 MHz
• configurable high-precision sample clock with a variety of sampling frequencies supported
• 8/16/24/32-bit data width
• synchronous counter in TX mode
• ETM feature
• direct memory access
• standard I2S interface interrupts
For details, see ESP32-C5 Technical Reference Manual > Chapter I2S Controller (I2S).
Pin Assignment
The pins for the I2S controller can be chosen from any GPIOs via the GPIO Matrix.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.1.5
USB Serial/JTAG Controller
ESP32-C5 contains a USB Serial/JTAG controller. This unit can be used to program the SoC’s flash, read
program output, as well as attach a debugger to the running program. All of these are possible for any
computer with a USB host without any active external components.
Feature List
• USB 2.0 full speed compliant, capable of up to 12 Mbit/s transfer speed (note that this controller does
not support the faster 480 Mbit/s high-speed transfer mode)
• CDC-ACM virtual serial port and JTAG adapter functionality
• programming the chip’s flash
• CPU debugging with compact JTAG instructions
• a full-speed USB PHY integrated in the chip
For details, see ESP32-C5 Technical Reference Manual > Chapter USB Serial/JTAG Controller
(USB_SERIAL_JTAG).
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Pin Assignment
The pins for the USB Serial/JTAG controller are multiplexed with GPIO13 ~ GPIO14 via IO MUX. GPIO13 ~ GPIO14
are also multiplexed with the pins for the SDIO Slave controller. The SDIO Slave controller can be used
together with the USB Serial/JTAG controller in single SPI mode, but not in quad SPI mode.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.1.6 CAN FD Controller
The Controller Area Network Flexible Data-Rate (CAN FD) is a multi-master, multi-cast communication protocol
designed for automotive applications. The CAN FD controller facilitates the communication based on this
protocol.
Feature List
• compliant with ISO11898-1:2015
• RX buffer FIFO with 32 - 4096 words (1 - 204 CAN FD frames with 64 byte of data)
• 2 - 8 TXT buffers (1 CAN FD frame in each TXT buffer)
• 32-bit slave memory interface (APB, AHB, RAM-like interface)
• support of ISO and non-ISO CAN FD protocol
• timestamping and time triggered transmission
• support interrupts
• loopback mode, bus monitoring mode, ACK forbidden mode, self-test mode, and restricted operation
mode
For details, see ESP32-C5 Technical Reference Manual > Chapter Controller Area Network Flexible Data-Rate.
Pin Assignment
The pins for the CAN FD Controller can be chosen from any GPIOs via the GPIO Matrix.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.1.7 LED PWM Controller
The LED PWM controller can generate independent digital waveform on six channels.
Feature List
• generating digital waveform with configurable periods and duty cycle. The resolution of duty cycle can
be up to 20 bits
• multiple clock sources, including 80 MHz PLL clock, external main crystal clock, and internal fast RC
oscillator
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• operation when the CPU is in Light-sleep mode
• gradual increase or decrease of duty cycle, which is useful for the LED RGB color-gradient generator
• up to 16 duty cycle ranges for gamma curve generation, each can be independently configured in terms
of duty cycle direction (increase or decrease), step size, the number of steps, and step frequency
For details, see ESP32-C5 Technical Reference Manual > Chapter LED PWM Controller.
Pin Assignment
The pins for the LED PWM controller can be chosen from any GPIOs via the GPIO Matrix.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.1.8 Pulse Count Controller
The Pulse Count controller (PCNT) in ESP32-C5 captures pulses and counts pulse edges in seven
modes.
Feature List
• four independent pulse counters (units) that count from 1 to 65535
• each unit consists of two independent channels sharing one pulse counter
• all channels have input pulse signals (e.g. sig_ch0_un) with their corresponding control signals (e.g.
ctrl_ch0_un)
• independently filter glitches of input pulse signals (sig_ch0_un and sig_ch1_un) and control signals
(ctrl_ch0_un and ctrl_ch1_un) on each unit
• each channel has the following parameters:
1. selection between counting on positive or negative edges of the input pulse signal
2. configuration to Increment, Decrement, or Disable counter mode for control of signal’s high and low
states
• support step counting
• maximum frequency of pulses: 40 MHz
For details, see ESP32-C5 Technical Reference Manual > Chapter Pulse Count Controller.
Pin Assignment
The pins for the Pulse Count controller can be chosen from any GPIOs via the GPIO Matrix.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.1.9 Motor Control PWM
ESP32-C5 integrates an MCPWM that can be used to drive digital motors and smart light.
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Feature List
• a clock divider (prescaler), three PWM timers, three PWM operators, and a dedicated capture
submodule. PWM timers are used to generate timing references. PWM operators generate desired
waveform based on the timing references
• a PWM operator can use the timing reference of any PWM timer
• a PWM operator can use the same timing reference with other PWM operators
• PWM operators can use different PWM timers’ values to produce independent PWM signals
• PWM timers can be synchronized
For details, see ESP32-C5 Technical Reference Manual > Chapter Motor Control PWM (MCPWM).
Pin Assignment
The pins for the Motor Control PWM can be chosen from any GPIOs via the GPIO Matrix.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.1.10
Remote Control Peripheral
The Remote Control Peripheral (RMT) supports two channels of infrared remote transmission and two
channels of infrared remote reception. By controlling pulse waveform through software, it supports various
infrared and other single wire protocols.
Feature List
• four channels:
– TX channels 0 ~ 1
– RX channels 2 ~ 3
– four channels share a 192 x 32-bit RAM
• the transmitter supports:
– normal TX mode
– wrap TX mode
– modulation on TX pulses
– continuous TX mode
– multiple channels (programmable) transmitting data simultaneously
• the receiver supports:
– normal RX mode
– wrap RX mode
– RX filtering
– demodulation on RX pulses
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For more details, see ESP32-C5 Technical Reference Manual > Chapter Remote Control Peripheral (RMT).
Pin Assignment
The pins for the Remote Control Peripheral can be chosen from any GPIOs via the GPIO Matrix.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.1.11 Parallel IO Controller
ESP32-C5 integrates a PARLIO controller for parallel data transfer. It has a transmitter and a receiver,
connected with the GDMA controller. In full-duplex mode the PARLIO controller supports up to 4-bit parallel
data transfer, while in half-duplex mode it supports up to 8-bit parallel data transfer.
Feature List
• multiple clock sources and clock division, with clock frequency up to 40 MHz
• receiver/transmitter supports input and output clock inverse
• 1/2/4/8-bit data transfer
• changeable sample sequence for data to be transmitted and received in 1-bit, 2-bit, and 4-bit mode
• support for multiple data sampling mode by the receiver
• support for multiple GDMA EOF signal generation modes by the receiver
• output external chip select signals with configurable delay cycles
• support for transmitter clock gating
For more details, see ESP32-C5 Technical Reference Manual > Chapter Parallel IO Controller.
Pin Assignment
The pins for the Parallel IO controller can be chosen from any GPIOs via the GPIO Matrix.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.1.12 BitScrambler
The ESP32-C5 has an extensive amount of DMA-capable peripherals. These can move data from memory to
an external device, and vice versa, without any interference from the CPU. This only works if the external
device needs or emits the data in question in the same format as the software expects it: if not, the CPU
needs to rewrite the format of the data. Examples include a need to swap bytes, reverse bytes, and shift the
data left or right.
As bitwise operations tend to be fairly CPU-expensive and the purpose of DMA is to not use the CPU in the
transfer, ESP32-C5 integrates one BitScrambler, which are dedicated peripherals to change the format of data
in between memory and the peripheral. The RX channel is dedicated to peripheral-to-memory transfers, and
the TX channel is dedicated to memory-to-peripheral transfers. The BitScrambler is capable of performing the
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aforementioned operations, but as a flexible programmable state machine, it is capable of more advanced
things as well.
Feature List
• one BitScrambler, one channel for RX (peripheral-to-memory), one channel for TX
(memory-to-peripheral). The two channels support only half-duplex communications, and cannot work
at the same time
• support for memory-to-memory transfers
• process up to 32 bits per DMA clock period
• data path controlled by a BitScrambler program stored in the instruction memory
• input registers able to read 0, 8, 16, or 32 bits per clock cycle
• output registers:
– able to write 0, 8, 16, or 32 bits per clock cycle
– data sources for output register bits: 64 bits of input data, two counters, LUT RAM data, data output
of last cycle, comparators
– with some restrictions, each of the 32 output register bits can come from any bit on the data
sources
• 8 x 257-bit instruction memory, for storing eight instructions, controlling control flow and the data path
• 2048 bytes of lookup table (LUT) memory, configurable as various word widths
For more details, see ESP32-C5 Technical Reference Manual > Chapter BitScrambler.
Pin Assignment
The BitScrambler does not directly interact with IOs, so it has no pins assigned.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.1.13 SDIO Slave Controller
The SDIO Slave controller in ESP32-C5 provides hardware support for the Secure Digital Input/Output (SDIO)
device interface. It allows an SDIO host to access ESP32-C5 via an SDIO bus protocol.
Feature List
• compatible with SDIO Physical Layer Specification V2.00 and SDIO Specifications V2.00
• support SPI, 1-bit SDIO, and 4-bit SDIO transfer modes
• clock range of 0 ~ 50 MHz
• configurable sample and drive clock edge
• integrated and SDIO-accessible registers for information interaction
• support SDIO interrupts
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• automatic padding data and discarding the padded data on the SDIO bus
• block size up to 512 bytes
• interrupt vector between the host and slave for bidirectional interrupt
• support DMA for data transfer
• support wake-up from sleep when connection is retained
For more details about the SDIO Slave controller, refer to the ESP32-C5 Technical Reference Manual > Chapter
SDIO Slave Controller (SDIO).
Pin Assignment
The pins for the SDIO Slave controller are multiplexed with GPIO7 ~ GPIO10, GPIO13, and GPIO14 via IO MUX.
GPIO13 ~ GPIO14 are also multiplexed with the pins for the USB serial/JTAG controller. The SDIO Slave controller
can be used together with the USB Serial/JTAG controller in single SPI mode, but not in quad SPI mode.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter IO MUX and GPIO Matrix.
Note:
This peripheral is not supported by chip revision v0.0 and v0.1.
5.2.2 Analog Signal Processing
This subsection describes components on the chip that sense and process real-world data.
5.2.2.1 Temperature Sensor
ESP32-C5 provides a temperature sensor to monitor temperature changes inside the chip in real time. The
sensor converts analog voltage to digital values and supports compensation for the temperature offset.
Feature List
• software-triggered temperature measurement. Once triggered, the sensor continuously measures
temperature. Software can read the data any time.
• hardware-triggered automatic temperature monitoring
• two modes for automatic monitoring of temperature and support for triggering interrupts
• configurable temperature offset based on the application scenario for improved accuracy
• configurable temperature measurement range
• support for several Event Task Matrix (ETM) related events and tasks
For more details, see ESP32-C5 Technical Reference Manual > Chapter Temperature Sensor.
5.2.2.2 ADC Controller
ESP32-C5 integrates One 12-bit successive approximation ADC (SAR ADC) for measuring analog signals from
up to six channels.
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Feature List
• 12-bit resolution
• analog inputs sampling from up to six pins
• one-shot sampling mode and multi-channel sampling mode
• multi-channel sampling mode supports:
– configurable channel sampling sequence
– two filters whose filter coefficients are configurable
– two threshold monitors that can trigger an interrupt when the filtered value is below a low threshold
or above a high threshold
– continuous transfer of converted data to memory via GDMA interface
• support for several Event Task Matrix (ETM) related events and tasks
For more details, see ESP32-C5 Technical Reference Manual > Chapter ADC Controller.
Pin Assignment
The pins for the ADC controller are multiplexed with GPIO1 ~ GPIO6.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
5.2.2.3 Analog Voltage Comparator
ESP32-C5 provides an analog voltage comparator which contains two special pads. This peripheral can be
used to compare the voltages of the two pads or compare the voltage of one pad with a stable internal
voltage that is adjustable.
Feature List
• internal or external reference voltage
• supported internal reference voltage ranging from 0 to 0.7 * VDD_PST
• support for ETM
• interrupt triggered when the measured voltage reaches the reference voltage
For more details, see ESP32-C5 Technical Reference Manual > Chapter Analog Voltage Comparator.
Pin Assignment
The analog voltage comparator has dedicated pads, GPIO8 and GPIO9. GPIO9 is the test pad, and GPIO8
serves as the reference pad when using an external reference voltage.
For more information about the pin assignment, see ESP32-C5 Series Datasheet > Section IO Pins and
ESP32-C5 Technical Reference Manual > Chapter GPIO Matrix and IO MUX.
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6 Electrical Characteristics
6 Electrical Characteristics
The values presented in this section are preliminary and may change with the final release of this
datasheet.
6.1
Absolute Maximum Ratings
Stresses above those listed in Table 6-1 Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions
beyond those indicated under Table 6-2 Recommended Operating Conditions is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 6-1. Absolute Maximum Ratings
6.2
Symbol
Parameter
VDD33
Power supply voltage
Min
Max
Unit
–0.3
3.6
V
Recommended Operating Conditions
Table 6-2. Recommended Operating Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDD33
Power supply voltage
3.0
3.3
3.6
V
IV DD
Current delivered by external power supply
0.6
—
—
A
TA
Operating ambient temperature
–40
—
85
°C
6.3 DC Characteristics (3.3 V, 25 °C)
Table 6-3. DC Characteristics (3.3 V, 25 °C)
Parameter
Description
CIN
Pin capacitance
VIH
Min
Typ
Unit
pF
High-level input voltage
—
0.75 × VDD 1
—
VIL
Low-level input voltage
–0.3
—
—
1
VDD + 0.3
0.25 × VDD 1
IIH
High-level input current
—
—
50
nA
Low-level input current
—
50
nA
—
V
IIL
2
Max
V
V
VOH
2
High-level output voltage
—
0.8 × VDD 1
VOL
2
Low-level output voltage
—
—
—
0.1 × VDD 1
—
40
—
mA
—
28
—
mA
IOH
IOL
High-level source current (VDD 1 = 3.3 V,
VOH >= 2.64 V, PAD_DRIVER = 3)
Low-level sink current (VDD 1 = 3.3 V, V
OL
=
0.495 V, PAD_DRIVER = 3)
V
RP U
Internal weak pull-up resistor
—
45
—
kΩ
RP D
Internal weak pull-down resistor
—
45
—
kΩ
Cont’d on next page
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6 Electrical Characteristics
Table 6-3 – cont’d from previous page
Parameter
VIH_nRST
VIL_nRST
Description
Min
Chip reset release voltage (CHIP_PU voltage
is within the specified range)
Typ
Max
Unit
0.75 × VDD 1
—
VDD 1 + 0.3
V
–0.3
—
0.25 × VDD 1
V
Chip reset voltage (CHIP_PU voltage is within
the specified range)
1 VDD – voltage from a power pin of a respective power domain.
2V
and V
are measured using high-impedance load.
OH
6.4
OL
Current Consumption Characteristics
6.4.1 Current Consumption in Active Mode
The current consumption measurements are taken with a 3.3 V supply at 25 °C ambient temperature.
TX current consumption is rated at a 100% duty cycle.
RX current consumption is rated when the peripherals are disabled and the CPU idle.
Table 6-4. Current Consumption for Wi-Fi (2.4 GHz) in Active Mode
Work Mode
RF Condition
TX
Active (RF working)
Description
Peak (mA)
802.11b, 1 Mbps, DSSS @ 19dBm
337
802.11g, 54 Mbps, OFDM @ 15.7dBm
272
802.11n, HT20, MCS7 @ 15.9dBm
272
802.11n, HT40, MCS7 @ 15dBm
265
802.11ax, MCS9 @ 14dBm
249
802.11b/g/n, HT20
RX
94
802.11n, HT40
102
802.11ax, HE20
94
Table 6-5. Current Consumption for Wi-Fi (5 GHz) in Active Mode
Work Mode
RF Condition
TX
Active (RF working)
RX
Espressif Systems
Description
Peak (mA)
802.11a, 6 Mbps, OFDM @ 17.5dBm
397
802.11n, HT20, MCS7 @ 14.6dBm
364
802.11n, HT40, MCS7 @ 14.4dBm
361
802.11ac, VHT20, MCS7 @ 14.4dBm
364
802.11ax, HE20, MCS7 @ 14.4dBm
365
802.11a/n, HT20
121
802.11n, HT40
128
802.11ac, VHT20
120
802.11ax, HE20
122
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Table 6-6. Current Consumption for Bluetooth LE in Active Mode
Work Mode
RF Condition
TX
Active (RF working)
Description
Peak (mA)
Bluetooth LE @ 19.7dBm
364
Bluetooth LE @ 7dBm
205
Bluetooth LE @ 0.5dBm
171
Bluetooth LE @ –16.7dBm
RX
105
Bluetooth LE
85
Table 6-7. Current Consumption for 802.15.4 in Active Mode
Work Mode
RF Condition
TX
Active (RF working)
RX
Description
Peak (mA)
802.15.4 @ 19.5dBm
360
802.15.4 @ 6.8dBm
206
802.15.4 @ 0dBm
180
802.15.4 @ –17dBm
105
802.15.4
85
Note:
The content below is excerpted from Section Power Consumption in Other Modes in ESP32-C5 Series Datasheet.
6.4.2
Current Consumption in Other Modes
Table 6-8. Current Consumption in Modem-sleep Mode
Typ (mA)
CPU Frequency
Mode
(MHz)
All Peripherals
All Peripherals
Clocks Disabled
Clocks Enabled1
WAITI
18
27
CPU while loop
26
35
Run CoreMark
34
43
WAITI
15
27
CPU while loop
20
32
Run CoreMark
26
37
WAITI
12
24
CPU while loop
15
26
Run CoreMark
18
29
8
18
CPU while loop
10
19
Run CoreMark
12
21
Description
240
160
Modem-sleep2,3
80
WAITI
40
1 In practice, the current consumption might be different depending on which peripherals
are enabled.
2 In Modem-sleep mode, Wi-Fi is clock gated.
3 In Modem-sleep mode, the consumption might be higher when accessing flash.
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Table 6-9. Current Consumption in Low-Power Modes
Mode
Description
Typ (mA)
CPU and wireless communication modules are powered down,
Light-sleep
0.25
peripheral clocks are disabled, and all GPIOs are high-impedance
CPU, wireless communication modules and peripherals are pow-
0.06
ered down, and all GPIOs are high-impedance
6.5
Deep-sleep
RTC timer and LP memory are powered on
0.012
Power off
CHIP_PU is set to low level, the chip is powered off
0.002
Memory Specifications
The data below is sourced from the memory vendor datasheet. These values are guaranteed through design
and/or characterization but are not fully tested in production. Devices are shipped with the memory
erased.
Table 6-10. Flash Specifications
Parameter
Description
Min
Typ
Max
Unit
Power supply voltage (1.8 V)
1.65
1.80
2.00
V
Power supply voltage (3.3 V)
2.7
3.3
3.6
V
FC
Maximum clock frequency
80
—
—
MHz
—
Program/erase cycles
100,000
—
—
cycles
TRET
Data retention time
20
—
—
years
TP P
Page program time
—
0.8
5
ms
TSE
Sector erase time (4 KB)
—
70
500
ms
TBE1
Block erase time (32 KB)
—
0.2
2
s
TBE2
Block erase time (64 KB)
—
0.3
3
s
Chip erase time (16 Mb)
—
7
20
s
Chip erase time (32 Mb)
—
20
60
s
Chip erase time (64 Mb)
—
25
100
s
Chip erase time (128 Mb)
—
60
200
s
Chip erase time (256 Mb)
—
70
300
s
VCC
TCE
Table 6-11. PSRAM Specifications
Parameter
VCC
FC
Espressif Systems
Description
Min
Typ
Max
Unit
Power supply voltage (1.8 V)
1.62
1.80
1.98
V
Power supply voltage (3.3 V)
2.7
3.3
3.6
V
Maximum clock frequency
80
—
—
MHz
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7 RF Characteristics
7 RF Characteristics
This section contains tables with RF characteristics of the Espressif product.
The RF data is measured at the antenna port, where RF cable is connected, including the front-end loss. The
external antennas used for the tests on the modules with external antenna connectors have an impedance of
50 Ω.
Devices should operate in the center frequency range allocated by regional regulatory authorities. The target
center frequency range and the target transmit power are configurable by software. See ESP RF Test Tool and
Test Guide for instructions.
Unless otherwise stated, the RF tests are conducted with a 3.3 V (±5%) supply at 25 ºC ambient temperature.
7.1 2.4 GHz Wi-Fi Radio
Table 7-1. 2.4 GHz Wi-Fi RF Characteristics
Name
Description
Center frequency range of operating channel
2412 ~ 2484 MHz
Wi-Fi wireless standard
IEEE 802.11b/g/n/ax
7.1.1 2.4 GHz Wi-Fi RF Transmitter (TX) Characteristics
Table 7-2. 2.4 GHz TX Power with Spectral Mask and EVM Meeting 802.11 Standards
Min
Typ
Max
(dBm)
(dBm)
(dBm)
802.11b, 1 Mbps, DSSS
—
19.5
—
802.11b, 11 Mbps, CCK
—
19.5
—
802.11g, 6 Mbps, OFDM
—
18.5
—
802.11g, 54 Mbps, OFDM
—
16.5
—
802.11n, HT20, MCS0
—
18.5
—
802.11n, HT20, MCS7
—
16.5
—
802.11n, HT40, MCS0
—
17.5
—
802.11n, HT40, MCS7
—
15.5
—
802.11ax, HE20, MCS0
—
18.5
—
802.11ax, HE20, MCS9
—
14.5
—
Rate
Table 7-3. 2.4 GHz TX EVM Test1
Rate
Min
Typ
Limit
(dB)
(dB)
(dB)
802.11b, 1 Mbps, DSSS
—
–25.0
–10.0
802.11b, 11 Mbps, CCK
—
–25.0
–10.0
Cont’d on next page
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7 RF Characteristics
Table 7-3 – cont’d from previous page
Rate
Min
Typ
Limit
(dB)
(dB)
(dB)
802.11g, 6 Mbps, OFDM
—
–25.0
–5.0
802.11g, 54 Mbps, OFDM
—
–30.0
–25.0
802.11n, HT20, MCS0
—
–25.0
–5.0
802.11n, HT20, MCS7
—
–31.5
–27.0
802.11n, HT40, MCS0
—
–25.0
–5.0
802.11n, HT40, MCS7
—
–31.5
–27.0
802.11ax, HE20, MCS0
—
–25.0
–5.0
802.11ax, HE20, MCS9
—
–34.5
–32.0
1 EVM is measured at the corresponding typical TX power provided in
Table 7-2 2.4 GHz TX Power with Spectral Mask and EVM Meeting
802.11 Standards above.
7.1.2 2.4 GHz Wi-Fi RF Receiver (RX) Characteristics
For RX tests, the PER (packet error rate) limit is 8% for 802.11b, and 10% for 802.11g/n/ax.
Table 7-4. 2.4 GHz RX Sensitivity
Rate
Min
Typ
Max
(dBm)
(dBm)
(dBm)
802.11b, 1 Mbps, DSSS
—
–100.0
—
802.11b, 2 Mbps, DSSS
—
–97.0
—
802.11b, 5.5 Mbps, CCK
—
–94.0
—
802.11b, 11 Mbps, CCK
—
–90.0
—
802.11g, 6 Mbps, OFDM
—
–95.0
—
802.11g, 9 Mbps, OFDM
—
–93.0
—
802.11g, 12 Mbps, OFDM
—
–92.0
—
802.11g, 18 Mbps, OFDM
—
–90.0
—
802.11g, 24 Mbps, OFDM
—
–87.0
—
802.11g, 36 Mbps, OFDM
—
–84.0
—
802.11g, 48 Mbps, OFDM
—
–80.0
—
802.11g, 54 Mbps, OFDM
—
–78.0
—
802.11n, HT20, MCS0
—
–94.5
—
802.11n, HT20, MCS1
—
–93.0
—
802.11n, HT20, MCS2
—
–90.0
—
802.11n, HT20, MCS3
—
–87.0
—
802.11n, HT20, MCS4
—
–83.5
—
802.11n, HT20, MCS5
—
–79.0
—
802.11n, HT20, MCS6
—
–77.0
—
802.11n, HT20, MCS7
—
–76.0
—
802.11n, HT40, MCS0
—
–92.0
—
802.11n, HT40, MCS1
—
–90.0
—
Cont’d on next page
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7 RF Characteristics
Table 7-4 – cont’d from previous page
Rate
Min
Typ
Max
(dBm)
(dBm)
(dBm)
802.11n, HT40, MCS2
—
–87.0
—
802.11n, HT40, MCS3
—
–83.0
—
802.11n, HT40, MCS4
—
–81.0
—
802.11n, HT40, MCS5
—
–76.0
—
802.11n, HT40, MCS6
—
–74.0
—
802.11n, HT40, MCS7
—
–73.0
—
802.11ax, HE20, MCS0
—
–94.5
—
802.11ax, HE20, MCS1
—
–91.5
—
802.11ax, HE20, MCS2
—
–89.0
—
802.11ax, HE20, MCS3
—
–86.0
—
802.11ax, HE20, MCS4
—
–83.0
—
802.11ax, HE20, MCS5
—
–79.0
—
802.11ax, HE20, MCS6
—
–77.5
—
802.11ax, HE20, MCS7
—
–75.5
—
802.11ax, HE20, MCS8
—
–71.5
—
802.11ax, HE20, MCS9
—
–69.5
—
Table 7-5. 2.4 GHz Maximum RX Level
Min
Typ
Max
(dBm)
(dBm)
(dBm)
802.11b, 1 Mbps, DSSS
—
5
—
802.11b, 11 Mbps, CCK
—
5
—
802.11g, 6 Mbps, OFDM
—
5
—
802.11g, 54 Mbps, OFDM
—
0
—
802.11n, HT20, MCS0
—
5
—
802.11n, HT20, MCS7
—
0
—
802.11n, HT40, MCS0
—
5
—
802.11n, HT40, MCS7
—
0
—
802.11ax, HE20, MCS0
—
5
—
802.11ax, HE20, MCS9
—
0
—
Rate
Table 7-6. 2.4 GHz RX Adjacent Channel Rejection
Rate
Min
Typ
Max
(dB)
(dB)
(dB)
802.11b, 1 Mbps, DSSS
—
41
—
802.11b, 11 Mbps, CCK
—
40
—
802.11g, 6 Mbps, OFDM
—
37
—
802.11g, 54 Mbps, OFDM
—
17
—
Cont’d on next page
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7 RF Characteristics
Table 7-6 – cont’d from previous page
Rate
Min
Typ
Max
(dB)
(dB)
(dB)
802.11n, HT20, MCS0
—
34
—
802.11n, HT20, MCS7
—
16
—
802.11n, HT40, MCS0
—
24
—
802.11n, HT40, MCS7
—
13
—
802.11ax, HE20, MCS0
—
38
—
802.11ax, HE20, MCS9
—
12
—
7.2 5 GHz Wi-Fi Radio
Table 7-7. 5 GHz Wi-Fi RF Characteristics
Name
Description
Center frequency range of operating channel
5180 ~ 5885 MHz
Wi-Fi wireless standard
IEEE 802.11a/n/ac/ax
7.2.1 5 GHz Wi-Fi RF Transmitter (TX) Characteristics
Table 7-8. 5 GHz TX Power with Spectral Mask and EVM Meeting 802.11 Standards
Min
Typ
Max
(dBm)
(dBm)
(dBm)
802.11a, 6 Mbps, OFDM
—
18.5
—
802.11a, 54 Mbps, OFDM
—
16.5
—
802.11n, HT20, MCS0
—
18.5
—
802.11n, HT20, MCS7
—
15.5
—
802.11n, HT40, MCS0
—
17.5
—
802.11n, HT40, MCS7
—
14.5
—
802.11ac, VHT20, MCS0
—
18.5
—
802.11ac, VHT20, MCS7
—
15.5
—
802.11ax, HE20, MCS0
—
18.5
—
802.11ax, HE20, MCS7
—
15.5
—
Rate
Table 7-9. 5 GHz TX EVM Test1
Rate
Min
Typ
Limit
(dB)
(dB)
(dB)
802.11a, 6 Mbps, OFDM
—
–25.0
–5.0
802.11a, 54 Mbps, OFDM
—
–29.0
–25.0
802.11n, HT20, MCS0
—
–25.0
–5.0
802.11n, HT20, MCS7
—
–31.0
–27.0
Cont’d on next page
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7 RF Characteristics
Table 7-9 – cont’d from previous page
Rate
Min
Typ
Limit
(dB)
(dB)
(dB)
802.11n, HT40, MCS0
—
–25.0
–5.0
802.11n, HT40, MCS7
—
–31.0
–27.0
802.11ac, VHT20, MCS0
—
–25.0
–5.0
802.11ac, VHT20, MCS7
—
–31.0
–27.0
802.11ax, HE20, MCS0
—
–25.0
–5.0
802.11ax, HE20, MCS7
—
–31.5
–27.0
1 EVM is measured at the corresponding typical TX power provided
in Table 7-8 5 GHz TX Power with Spectral Mask and EVM Meeting
802.11 Standards above.
7.2.2
5 GHz Wi-Fi RF Receiver (RX) Characteristics
For RX tests, the PER (packet error rate) limit is 10% for 802.11a/n/ac/ax.
Table 7-10. 5 GHz RX Sensitivity
Min
Typ
Max
(dBm)
(dBm)
(dBm)
802.11a, 6 Mbps, OFDM
—
–94.5
—
802.11a, 9 Mbps, OFDM
—
–93.0
—
802.11a, 12 Mbps, OFDM
—
–91.5
—
802.11a, 18 Mbps, OFDM
—
–89.5
—
802.11a, 24 Mbps, OFDM
—
–86.5
—
802.11a, 36 Mbps, OFDM
—
–83.5
—
802.11a, 48 Mbps, OFDM
—
–78.5
—
802.11a, 54 Mbps, OFDM
—
–76.5
—
802.11n, HT20, MCS0
—
–94.0
—
802.11n, HT20, MCS1
—
–92.5
—
802.11n, HT20, MCS2
—
–89.5
—
802.11n, HT20, MCS3
—
–86.5
—
802.11n, HT20, MCS4
—
–82.5
—
802.11n, HT20, MCS5
—
–78.5
—
802.11n, HT20, MCS6
—
–77.0
—
802.11n, HT20, MCS7
—
–75.5
—
802.11n, HT40, MCS0
—
–91.5
—
802.11n, HT40, MCS1
—
–89.5
—
802.11n, HT40, MCS2
—
–86.5
—
802.11n, HT40, MCS3
—
–83.5
—
802.11n, HT40, MCS4
—
–80.5
—
802.11n, HT40, MCS5
—
–75.5
—
802.11n, HT40, MCS6
—
–73.5
—
802.11n, HT40, MCS7
—
–72.5
—
Rate
Cont’d on next page
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
7 RF Characteristics
Table 7-10 – cont’d from previous page
Min
Typ
Max
(dBm)
(dBm)
(dBm)
802.11ac, VHT20, MCS0
—
–94.5
—
802.11ac, VHT20, MCS1
—
–92.5
—
802.11ac, VHT20, MCS2
—
–89.5
—
802.11ac, VHT20, MCS3
—
–86.5
—
802.11ac, VHT20, MCS4
—
–83.0
—
802.11ac, VHT20, MCS5
—
–78.5
—
802.11ac, VHT20, MCS6
—
–77.0
—
802.11ac, VHT20, MCS7
—
–75.5
—
802.11ax, HE20, MCS0
—
–94.0
—
802.11ax, HE20, MCS1
—
–91.0
—
802.11ax, HE20, MCS2
—
–88.0
—
802.11ax, HE20, MCS3
—
–85.5
—
802.11ax, HE20, MCS4
—
–82.0
—
802.11ax, HE20, MCS5
—
–78.5
—
802.11ax, HE20, MCS6
—
–77.0
—
802.11ax, HE20, MCS7
—
–74.5
—
Rate
Table 7-11. 5 GHz Maximum RX Level
Min
Typ
Max
(dBm)
(dBm)
(dBm)
802.11a, 6 Mbps, OFDM
—
5
—
802.11a, 54 Mbps, OFDM
—
0
—
802.11n, HT20, MCS0
—
5
—
802.11n, HT20, MCS7
—
0
—
802.11n, HT40, MCS0
—
5
—
802.11n, HT40, MCS7
—
0
—
802.11ac, VHT20, MCS0
—
5
—
802.11ac, VHT20, MCS7
—
0
—
802.11ax, HE20, MCS0
—
5
—
802.11ax, HE20, MCS7
—
0
—
Rate
Table 7-12. 5 GHz RX Adjacent Channel Rejection
Rate
Min
Typ
Max
(dB)
(dB)
(dB)
802.11a, 6 Mbps, OFDM
—
29
—
802.11a, 54 Mbps, OFDM
—
9
—
802.11n, HT20, MCS0
—
26
—
802.11n, HT20, MCS7
—
8
—
Cont’d on next page
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
7 RF Characteristics
Table 7-12 – cont’d from previous page
Rate
Min
Typ
Max
(dB)
(dB)
(dB)
802.11n, HT40, MCS0
—
29
—
802.11n, HT40, MCS7
—
11
—
802.11ac, VHT20, MCS0
—
25
—
802.11ac, VHT20, MCS7
—
6
—
802.11ax, HE20, MCS0
—
25
—
802.11ax, HE20, MCS7
—
6
—
7.3 Bluetooth 5 (LE) Radio
Table 7-13. Bluetooth LE RF Characteristics
Name
Description
Center frequency range of operating channel
2402 ~ 2480 MHz
RF transmit power range
–15~20 dBm
7.3.1 Bluetooth LE RF Transmitter (TX) Characteristics
Table 7-14. Bluetooth LE - Transmitter Characteristics - 1 Mbps
Parameter
Description
Carrier frequency offset and drift
Modulation characteristics
Min
Max
Unit
Max. |fn |n=0, 1, 2, 3, ...k
—
7.0
—
kHz
Max. |f0 − fn |n=2, 3, 4, ...k
—
0.6
—
kHz
Max. |fn − fn−5 |n=6, 7, 8, ...k
—
0.6
—
kHz
|f1 − f0 |
—
0.3
—
kHz
∆ F 1avg
—
250.0
—
kHz
—
255.0
—
kHz
∆ F 2avg /∆ F 1avg
—
0.98
—
—
± 2 MHz offset
—
–33
—
dBm
± 3 MHz offset
—
–40
—
dBm
> ± 3 MHz offset
—
–45
—
dBm
Min. ∆ F 2max (for at least
99.9% of all ∆ F 2max )
In-band emissions
Typ
Table 7-15. Bluetooth LE - Transmitter Characteristics - 2 Mbps
Parameter
Carrier frequency offset and drift
Description
Min
Max
Unit
Max. |fn |n=0, 1, 2, 3, ...k
—
7.0
—
kHz
Max. |f0 − fn |n=2, 3, 4, ...k
—
0.6
—
kHz
Max. |fn − fn−5 |n=6, 7, 8, ...k
—
0.7
—
kHz
|f1 − f0 |
—
0.3
—
kHz
∆ F 1avg
—
495.1
—
kHz
Modulation characteristics
Espressif Systems
Typ
Cont’d on next page
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7 RF Characteristics
Table 7-15 – cont’d from previous page
Parameter
Description
Min
Min. ∆ F 2max (for at least
Max
Unit
—
515.0
—
kHz
∆ F 2avg /∆ F 1avg
—
0.99
—
—
± 4 MHz offset
—
–43
—
dBm
± 5 MHz offset
—
–45
—
dBm
> ± 5 MHz offset
—
–45
—
dBm
99.9% of all ∆ F 2max )
In-band emissions
Typ
Table 7-16. Bluetooth LE - Transmitter Characteristics - 125 Kbps
Parameter
Description
Carrier frequency offset and drift
Modulation characteristics
Min
Max
Unit
Max. |fn |n=0, 1, 2, 3, ...k
—
7.0
—
kHz
Max. |f0 − fn |n=1, 2, 3, ...k
—
0.3
—
kHz
|f0 − f3 |
—
0.3
—
kHz
Max. |fn − fn−3 |n=7, 8, 9, ...k
—
0.4
—
kHz
∆ F 1avg
—
251.2
—
kHz
—
256.7
—
kHz
Min. ∆ F 1max (for at least
99.9% of all ∆ F 1max )
In-band emissions
Typ
± 2 MHz offset
—
–31
—
dBm
± 3 MHz offset
—
–40
—
dBm
> ± 3 MHz offset
—
–43
—
dBm
Table 7-17. Bluetooth LE - Transmitter Characteristics - 500 Kbps
Parameter
Description
Carrier frequency offset and drift
Modulation characteristics
Min
Max
Unit
Max. |fn |n=0, 1, 2, 3, ...k
—
7.0
—
kHz
Max. |f0 − fn |n=1, 2, 3, ...k
—
0.5
—
kHz
|f0 − f3 |
—
0.2
—
kHz
Max. |fn − fn−3 |n=7, 8, 9, ...k
—
0.5
—
kHz
∆ F 2avg
—
246.3
—
kHz
—
253.3
—
kHz
± 2 MHz offset
—
–31
—
dBm
± 3 MHz offset
—
–40
—
dBm
> ± 3 MHz offset
—
–43
—
dBm
Max
Unit
Min. ∆ F 2max (for at least
99.9% of all ∆ F 2max )
In-band emissions
Typ
7.3.2 Bluetooth LE RF Receiver (RX) Characteristics
Table 7-18. Bluetooth LE - Receiver Characteristics - 1 Mbps
Parameter
Description
Min
Typ
Sensitivity @30.8% PER
—
—
–98.5
—
dBm
Maximum received signal @30.8% PER
—
—
5
—
dBm
Cont’d on next page
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
7 RF Characteristics
Table 7-18 – cont’d from previous page
Parameter
Max
Unit
9
—
dB
—
–4
—
dB
F = F0 – 1 MHz
—
–3
—
dB
F = F0 + 2 MHz
—
–31
—
dB
F = F0 – 2 MHz
—
–34
—
dB
F = F0 + 3 MHz
—
–33
—
dB
F = F0 – 3 MHz
—
–43
—
dB
F ≥ F0 + 4 MHz
—
–37
—
dB
F ≤ F0 – 4 MHz
—
–50
—
dB
—
—
–28
—
dB
Adjacent channel to F = Fimage + 1 MHz
—
–27
—
dB
image frequency
F = Fimage – 1 MHz
—
–30
—
dB
30 MHz ~ 2000 MHz
—
–13
—
dBm
2003 MHz ~ 2399 MHz
—
–25
—
dBm
2484 MHz ~ 2997 MHz
—
–20
—
dBm
3000 MHz ~ 12.75 GHz
—
–20
—
dBm
—
—
–41
—
dBm
Max
Unit
Co-channel
Adjacent channel
C/I and receiver
selectivity performance
Image frequency
Out-of-band blocking performance
Intermodulation
Description
Min
F = F0 MHz
—
F = F0 + 1 MHz
Typ
Table 7-19. Bluetooth LE - Receiver Characteristics - 2 Mbps
Parameter
Description
Sensitivity @30.8% PER
—
—
–96.0
—
dBm
Maximum received signal @30.8% PER
—
—
5
—
dBm
F = F0 MHz
—
8
—
dB
F = F0 + 2 MHz
—
–8
—
dB
F = F0 – 2 MHz
—
–10
—
dB
F = F0 + 4 MHz
—
–27
—
dB
F = F0 – 4 MHz
—
–42
—
dB
F = F0 + 6 MHz
—
–39
—
dB
F = F0 – 6 MHz
—
–50
—
dB
F ≥ F0 + 8 MHz
—
–48
—
dB
F ≤ F0 – 8 MHz
—
–54
—
dB
—
—
–27
—
dB
Adjacent channel to F = Fimage + 2 MHz
—
–26
—
dB
image frequency
F = Fimage – 2 MHz
—
–28
—
dB
30 MHz ~ 2000 MHz
—
–13
—
dBm
2003 MHz ~ 2399 MHz
—
–25
—
dBm
2484 MHz ~ 2997 MHz
—
–20
—
dBm
3000 MHz ~ 12.75 GHz
—
–20
—
dBm
—
—
–39
—
dBm
Co-channel
C/I and receiver
Adjacent channel
selectivity performance
Image frequency
Out-of-band blocking performance
Intermodulation
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Min
Typ
ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
7 RF Characteristics
Table 7-20. Bluetooth LE - Receiver Characteristics - 125 Kbps
Parameter
Description
Max
Unit
Sensitivity @30.8% PER
—
—
–106.5
—
dBm
Maximum received signal @30.8% PER
—
—
5
—
dBm
F = F0 MHz
—
3
—
dB
F = F0 + 1 MHz
—
–6
—
dB
F = F0 – 1 MHz
—
–7
—
dB
F = F0 + 2 MHz
—
–34
—
dB
F = F0 – 2 MHz
—
–39
—
dB
F = F0 + 3 MHz
—
–30
—
dB
F = F0 – 3 MHz
—
–47
—
dB
F ≥ F0 + 4 MHz
—
–46
—
dB
F ≤ F0 – 4 MHz
—
–54
—
dB
—
—
–28
—
dB
Adjacent channel to F = Fimage + 1 MHz
—
–34
—
dB
image frequency
—
–31
—
dB
Max
Unit
Co-channel
Adjacent channel
C/I and receiver
selectivity performance
Image frequency
Min
F = Fimage – 1 MHz
Typ
Table 7-21. Bluetooth LE - Receiver Characteristics - 500 Kbps
Parameter
Description
Sensitivity @30.8% PER
—
—
–103.0
—
dBm
Maximum received signal @30.8% PER
—
—
5
—
dBm
F = F0 MHz
—
3
—
dB
F = F0 + 1 MHz
—
–6
—
dB
F = F0 – 1 MHz
—
–7
—
dB
F = F0 + 2 MHz
—
–33
—
dB
F = F0 – 2 MHz
—
–38
—
dB
F = F0 + 3 MHz
—
–38
—
dB
F = F0 – 3 MHz
—
–47
—
dB
F ≥ F0 + 4 MHz
—
–41
—
dB
F ≤ F0 – 4 MHz
—
–52
—
dB
—
—
–23
—
dB
Adjacent channel to F = Fimage + 1 MHz
—
–29
—
dB
image frequency
—
–29
—
dB
Co-channel
Adjacent channel
C/I and receiver
selectivity performance
Image frequency
7.4
Min
F = Fimage – 1 MHz
Typ
802.15.4 Radio
Table 7-22. 802.15.4 RF Characteristics
Name
Description
Center frequency range of operating channel
2405 ~ 2480 MHz
1 Zigbee in the 2.4 GHz range supports 16 channels at 5 MHz spacing from
channel 11 to channel 26.
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7 RF Characteristics
7.4.1 802.15.4 RF Transmitter (TX) Characteristics
Table 7-23. 802.15.4 Transmitter Characteristics - 250 Kbps
Parameter
Min
RF transmit power range
–15.0
—
20.0
dBm
—
4.0%
—
—
EVM
7.4.2
Typ
Max
Unit
802.15.4 RF Receiver (RX) Characteristics
Table 7-24. 802.15.4 Receiver Characteristics - 250 Kbps
Parameter
Description
Sensitivity @1% PER
—
—
Maximum received signal @1% PER
—
Adjacent channel
Relative jamming level
Alternate channel
Espressif Systems
Max
Unit
–103.5
—
dBm
—
5
—
dBm
F = F0 + 5 MHz
—
28
—
dB
F = F0 – 5 MHz
—
32
—
dB
F = F0 + 10 MHz
—
48
—
dB
F = F0 – 10 MHz
—
53
—
dB
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Min
Typ
ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
8 Module Schematics
This is the reference design of the module.
GND
VDD33
C1
GND XOUT
GND
GND
1
C20
48MHz
1uF
VDD33
C26
1uF
R2
499
7
/HOLD
NC: No component.
1uF
VDD33
GND
C3
U1
C15
GND
ANT_5G
GND
VDDA5
VDDA4
VDDA3
GND
ANT_2G
VDDA2
VDDA1
VDDPST3
GPIO28
GPIO27
Dual Band Diplexer
0.1uF
49
48
47
46
45
44
43
42
41
40
39
38
37
ANT_5G
GND
L3
C24
GND
RF_ANT_5G
TBD
C25
TBD
TBD
ANT_2G
GND
L2
GND
GND
RF_ANT_2G
TBD
C23
1
H_PORT
GND
CM
3
L_PORT
DI
/WP
FLASH
5
2
3
SPID
SPIQ
SPIWP
SPICS1_IO15
SPICS0
SPIQ
SPIWP
SPIHD
SPICLK
SPID
IO23
IO24
IO25
IO26
IO27
IO28
R3
R4
R5
R6
R7
TBD
GND
VDD33
C11
C10
C8
2.6pF
3.0pF
0.1uF
GND
C29
10uF
GND
C12
VDD33
0.1uF
GND
C31
NC
GND
For chips with in-package SPI flash (e.g., ESP32-C5HF4),
the SPICS0, SPIQ, SPIWP, VDD_SPI, SPIHD, SPICLK and SPID
pins are not connected(NC); U2, C3, C5, R3~R7 are not required.
GND
Figure 8-1. ESP32-C5-WROOM-1 Schematics
COM_ANT_D
L5
GND
5
GND
TBD
GND
2.0nH(0.1nH)
GND
6
COM_ANT
TBD
1
2
C28
TBD
GND
The values of C23, L2, C22, C24, L3, C25, C27, L5 and C28
vary with the actual PCB board.
Add a stub to the ground pad.
0
0
0
0
0
GND
Diplexer
ESP32-C5_QFN48
L7
7
C27
U3
GND
GND
ANT1
2
C22
TBD
RF 2.4G&5G: Single-ended 50ohm.
8
10nF
NC
MTDI
MTMS
XTAL_32K_N
XTAL_32K_P
VDDPST1
CHIP_PU
VDDA8
XTAL_P
XTAL_N
VDDA7
GND
VDDA6
C14
1uF
DO
GND
GND
SPICS1
SPICS0
SPIQ
SPIWP
VDD_SPI
SPIHD
SPICLK
SPID
GPIO23
GPIO24
GPIO25
GPIO26
GND
8
VDD
CLK
GND
SPIHD
6
/CS
4
ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
SPICLK
MTCK
MTDO
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
U0TXD
U0RXD
GPIO13
GPIO14
VDDPST2
C4
VDD_SPI
U2
GND
0
R1
0
0.1uF
1
10uF
GND
12
11
10
9
8
7
6
5
4
3
2
1
R8
13
14
15
16
17
18
19
20
21
22
23
24
C5
GND
C30
GND
VDD_SPI
SPICS0
1.0pF
C19
IO4
IO5
IO6
IO7
IO8
IO9
IO10
TX0
RX0
VDD33 IO13
IO14
0.1uF
C17
0.6pF
GND
EN
IO0
IO1
IO2
IO3
GND
C16
VDD33
GND
10uF
10K(NC)
VDD33
GND
SPICS1_IO15
IO27
IO4
IO5
IO28
C21
R10
The value of R1 varies with the
actual PCB board. R1 could be a
resistor or inductor, the initial
value is suggested to be 24 nH.
IO23
VDD33
GND
The values of C1 and C2 vary with the
selection of the crystal.
GND
ESP32-C5-WROOM-1(Pin-out)
D1
ESD
TBD
2
TBD
IO26
IO25
TX0
RX0
IO24
C2
XTAL_P
XTAL_N
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
For modules with embedded PSRAM, SPICS1 is connected
to the embedded PSRAM and is not available for other uses.
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EPAD
GND
IO26
IO25
TX0
RX0
IO24
NC
IO23
NC
NC/IO15
IO27
IO4
IO5
IO28
GND
3V3
EN
IO2
IO3
IO0
IO1
IO6
IO7
IO8
IO9
IO10
IO13
IO14
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
10
11
12
13
14
EN
IO2
IO3
IO0
IO1
IO6
IO7
IO8
IO9
IO10
IO13
IO14
XIN
ESP32-C5-WROOM-1
NC
VDD33 GND
Y1
3
GND
4
GND
4
Espressif Systems
8 Module Schematics
GND
COM_ANT2
1
C20
1uF
GND XOUT
The values of C1 and C2 vary with the
selection of the crystal.
The value of R1 varies with the
actual PCB board. R1 could be a
resistor or inductor, the initial
value is suggested to be 24 nH.
VDD33
GND
GND
SPICS1_IO15
IO27
IO4
IO5
IO28
XTAL_P
XTAL_N
IO23
C26
1uF
C30
10uF
GND
0
GND
R1
GND
1uF
VDD33
GND
12
11
10
9
8
7
6
5
4
3
2
1
0
R2
499
VDD_SPI
ANT_5G
GND
VDDA5
VDDA4
VDDA3
GND
ANT_2G
VDDA2
VDDA1
VDDPST3
GPIO28
GPIO27
48
47
46
45
44
43
42
41
40
39
38
37
ANT_5G
C3
U1
GND
L3
C24
TBD
ANT_2G
Dual Band Diplexer
GND
L2
TBD
GND
GND
RF_ANT_2G
TBD
C23
1
H_PORT
2
GND
3
L_PORT
C22
U3
TBD
TBD
1
SPICLK
6
SPIHD
7
/CS
CLK
/HOLD
DI
DO
4
SPICS0
VDD
U2
GND
8
0.1uF
/WP
FLASH
5
SPID
2
SPIQ
3
SPIWP
SPICS1_IO15
SPICS0
SPIQ
SPIWP
SPIHD
SPICLK
SPID
IO23
IO24
IO25
IO26
IO27
IO28
R3
R4
R5
R6
R7
ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
GND
NC
GND
6COM_ANT_D
5
GND
L5
TBD COM_ANT
C27
C28
TBD
TBD
Add a stub to the ground pad.
L7
0
0
0
0
0
VDD33
2.0nH(0.1nH)
C11
C10
C8
2.6pF
3.0pF
0.1uF
GND
GND
GND
C29
10uF
GND
C12
VDD33
0.1uF
GND
For chips with in-package SPI flash (e.g., ESP32-C5HF4),
the SPICS0, SPIQ, SPIWP, VDD_SPI, SPIHD, SPICLK and SPID
pins are not connected(NC); U2, C3, C5, R3~R7 are not required.
GND
Figure 8-2. ESP32-C5-WROOM-1U Schematics
R12
0(NC)
R11
0
D2
ESD(NC)
COM_ANT2
COM_ANT1
ANT1
CONN
Diplexer
GND
GND
C31
NC: No component.
GND
7
GND
GND
ESP32-C5_QFN48
C5
GND
R10
GND
CM
1uF
10K(NC)
RF 2.4G&5G: Single-ended 50ohm.
8
0.1uF
GND
RF_ANT_5G
TBD
C25
The values of C23, L2, C22, C24, L3, C25, C27, L5 and C28
vary with the actual PCB board.
SPICS1
SPICS0
SPIQ
SPIWP
VDD_SPI
SPIHD
SPICLK
SPID
GPIO23
GPIO24
GPIO25
GPIO26
GND
0.1uF
VDD_SPI
GND
GND
C15
NC
MTCK
MTDO
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
U0TXD
U0RXD
GPIO13
GPIO14
VDDPST2
10nF
NC
R8
13
14
15
16
17
18
19
20
21
22
23
24
C4
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IO4
IO5
IO6
IO7
IO8
IO9
IO10
TX0
RX0
VDD33 IO13
IO14
C14
49
4
VDD33
GND
0.3pF
C19
For modules with embedded PSRAM, SPICS1 is connected
to the embedded PSRAM and is not available for other uses.
10uF
C17
0.8pF
GND
EN
IO0
IO1
IO2
IO3
C21
C16
VDD33
GND
ESP32-C5-WROOM-1U
GND
TBD
48MHz
VDD33
ESP32-C5-WROOM-1U(Pin-out)
D1
ESD
C2
2
TBD
IO26
IO25
TX0
RX0
IO24
3
4
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C1
MTDI
MTMS
XTAL_32K_N
XTAL_32K_P
VDDPST1
CHIP_PU
VDDA8
XTAL_P
XTAL_N
VDDA7
GND
VDDA6
EPAD
GND
IO26
IO25
TX0
RX0
IO24
NC
IO23
NC
NC/IO15
IO27
IO4
IO5
IO28
GND
3V3
EN
IO2
IO3
IO0
IO1
IO6
IO7
IO8
IO9
IO10
IO13
IO14
VDD33
GND
GND
32
31
30
GND
ANT2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
EN
IO2
IO3
IO0
IO1
IO6
IO7
IO8
IO9
IO10
IO13
IO14
GND
Y1
XIN
GND
25
26
27
28
29
30
31
32
33
34
35
36
GND
VDD33 GND
8 Module Schematics
Espressif Systems
GND
GND
GND
GND
9 Peripheral Schematics
9
Peripheral Schematics
This is the typical application circuit of the module connected with peripheral components (for example,
power supply, antenna, reset button, JTAG interface, and UART interface).
C5
12pF(NC)
1
GND
R5
R3
0(NC)
IO0
R4
0(NC)
IO1
2
NC
X1
32.768KHz(NC)
GND
C6
X1: ESR= Max. 70 KΩ
12pF(NC)
NC: No component.
GND
VDD33
R1
TBD
SW1
R2
C4
U1
C1
C2
22uF
0.1uF
EN
0
0.1uF
GND
GND
C3
TBD
GND
GND
VDD33
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
EN
IO2
IO3
IO0
IO1
IO6
IO7
IO8
IO9
IO10
IO13
IO14
ESP32-C5-WROOM-1
GND
3V3
EN
IO2
IO3
IO0
IO1
IO6
IO7
IO8
IO9
IO10
IO13
IO14
EPAD
GND
IO26
IO25
TX0
RX0
IO24
NC
IO23
NC
NC/IO15
IO27
IO4
IO5
IO28
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD33
IO26
IO25
DEBUG_TX0
DEBUG_RX0
IO24
JP1
1
2
3
4
IO23
1
2
3
4
UART
GND
NC/IO15
IO27
IO4
IO5
IO28
JP3
1
2
1
2
USB_DUSB_D+
USB
R6
R7
C8
C7
TBD
TBD
GND
TBD
TBD
JP2
IO26
IO27
IO28
1
2
3
1
2
3
BOOT
Boot Configurations.
GND
Figure 9-1. ESP32-C5-WROOM-1 Schematics
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9 Peripheral Schematics
C5
RF 2.4G&5G: Single-ended 50ohm.
12pF(NC)
1
GND
R5
R3
0(NC)
IO0
R4
0(NC)
IO1
2
GND
C6
ANT2
12pF(NC)
GND
NC: No component.
R1
TBD
SW1
R2
C1
C2
22uF
0.1uF
EN
0
0.1uF
GND
GND
C3
TBD
GND
GND
EN
IO2
IO3
IO0
IO1
IO6
IO7
IO8
IO9
IO10
IO13
IO14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
JP3
1
2
USB_DUSB_D+
USB
R6
R7
C8
C7
TBD
TBD
GND
EPAD
GND
IO26
IO25
TX0
RX0
IO24
NC
IO23
NC
NC/IO15
IO27
IO4
IO5
IO28
GND
3V3
EN
IO2
IO3
IO0
IO1
IO6
IO7
IO8
IO9
IO10
IO13
IO14
U1
1
2
GND
GND
32
31
30
VDD33
C10
TBD
GND
GND
ANT2
GND
VDD33
RF_ANT
TBD
C9
TBD
X1: ESR= Max. 70 KΩ
GND
C4
L1
NC
X1
32.768KHz(NC)
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD33
IO26
IO25
DEBUG_TX0
DEBUG_RX0
IO24
JP1
1
2
3
4
IO23
1
2
3
4
UART
GND
NC/IO15
IO27
IO4
IO5
IO28
ESP32-C5-WROOM-1U
TBD
TBD
JP2
IO26
IO27
IO28
1
2
3
1
2
3
BOOT
Boot Configurations.
GND
Figure 9-2. ESP32-C5-WROOM-1U Schematics
• If an external antenna ANT2 is used, it is recommended to reserve an RF circuit as shown in the figure
above. By default, ESP32-C5-WROOM-1U uses ANT1, and ANT2 is disabled. To use ANT2, please
contact us.
• Please control the voltage levels of strapping pins. For more details, please refer to Chapter 4 Boot
Configurations.
• Soldering the EPAD to the ground of the base board is not a must, however, it can optimize thermal
performance. If you choose to solder it, please apply the correct amount of soldering paste. Too much
soldering paste may increase the gap between the module and the baseboard. As a result, the adhesion
between other pins and the baseboard may be poor.
• To ensure that the power supply to the ESP32-C5 chip is stable during power-up, it is advised to add an
RC delay circuit at the EN pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and
C = 1 µF. However, specific parameters should be adjusted based on the power-up timing of the module
and the power-up and reset sequence timing of the chip. For ESP32-C5’s power-up and reset sequence
timing diagram, please refer to Section 4.5 Chip Power-up and Reset.
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10 Physical Dimensions
10 Physical Dimensions
10.1 Module Dimensions
Unit: mm
3.3±0.15
6.5
18±0.2
0.8
Antenna Area
1.27
Antenna Area
0.4
28 x 0.9
5
10.922
0.5
0.4
1.3
9.8298
3
Ø0.
4.7
28 x Ø0.55
19.7
28 x 0.9
4.7
1.3
1.27
16.51
27.5±0.2
15.8
28 x 0.85
1.1
28 x 0.45
Top View
Bottom View
Side View
Figure 10-1. ESP32-C5-WROOM-1 Dimensions
Unit: mm
5
1.27
3
2.38
2.38
18±0.2
3.3±0.15
10.46
3
1.27
0.8
4.7
1.3
U
HR
T
2
0.4
4.7
31 x 0.85
1.1
31 x 0.45
3
10.922
3
0.5
9.8298
0.4
1.3
31 x 0.9
15.9
19.6
15.8
1.27
.
Ø1
31 x Ø0.55
1.27
31 x 0.9
16.51
21.2±0.2
11.1
Top View
Bottom View
Side View
Figure 10-2. ESP32-C5-WROOM-1U Dimensions
Note:
For information about tape, reel, and product marking, please refer to ESP32-C5 Module Packaging Information.
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10 Physical Dimensions
10.2
Dimensions of External Antenna Connector
ESP32-C5-WROOM-1U uses the first generation external antenna connector as shown in Figure 10-3
Dimensions of External Antenna Connector. This connector is compatible with the following
connectors:
• U.FL Series connector from Hirose
• MHF I connector from I-PEX
• AMC connector from Amphenol
Unit: mm
Figure 10-3. Dimensions of External Antenna Connector
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10 Physical Dimensions
The external antenna used for ESP32-C5-WROOM-1U during certification testing is SY-WIFI-ESP-Dual Band
Ant.
The module does not include an external antenna upon shipment. If needed, select a suitable external
antenna based on the product’s usage environment and performance requirements.
It is recommended to select an antenna that meets the following requirements:
• 2.4 GHz & 5 GHz band
• 50 Ω impedance
• The maximum gain does not exceed 3.86 dBi (2.4 GHz) or 3.65 dBi (5 GHz), the gain of the antenna
used for certification
• The connector matches the specifications shown in Figure 10-3 Dimensions of External Antenna
Connector
Note:
• If you use an external antenna of a different type or gain, additional testing, such as EMC, may be required beyond
the existing antenna test reports for Espressif modules. Specific requirements depend on the certification type.
• If RF function is enabled, make sure an antenna is connected. Operation without an antenna may result in
unstable behavior or potential damage to the RF circuit.
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
11 PCB Layout Recommendations
11
PCB Layout Recommendations
11.1
PCB Land Pattern
This section provides the following resources for your reference:
• Figures for recommended PCB land patterns with all the dimensions needed for PCB design. See Figure
11-1 ESP32-C5-WROOM-1 PCB Land Pattern and Figure 11-2 ESP32-C5-WROOM-1U PCB Land Pattern.
• Source files of recommended PCB land patterns to measure dimensions not covered in Figure 11-1. You
can view the source files for ESP32-C5-WROOM-1 and ESP32-C5-WROOM-1U with Autodesk Viewer.
• 3D models of ESP32-C5-WROOM-1 and ESP32-C5-WROOM-1U. Please make sure that you download
the 3D model file in .STEP format (beware that some browsers might add .txt).
Unit: mm
Via for thermal pad
Copper
28
1.3
0.4
4.7
10.922
1.27
27.5
1.3
0.4
4.7
28 x 0.9
1
7.99
Antenna Area
28 x 1.5
16.51
6.5
18
9.8298
15
3
14
0.5
17.5
Figure 11-1. ESP32-C5-WROOM-1 PCB Land Pattern
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11 PCB Layout Recommendations
Unit: mm
Via for thermal pad
Copper
0.5
18
32 31 30 28
1.3
0.4
10.922
29
21.2
4.7
1.27
1.3
0.4
4.7
31 x 0.9
1
16.51
5
1.27
31 x 1.5
1.69
Recommend 50 Ω impedance
control for ANT2 pad if used
9.8298
15
3
14
0.5
17.5
Figure 11-2. ESP32-C5-WROOM-1U PCB Land Pattern
11.2
Module Placement for PCB Design
If module-on-board design is adopted, attention should be paid while positioning the module on the base
board. The interference of the base board on the module’s antenna performance should be minimized.
For details about module placement for PCB design, please refer to ESP32-C5 Hardware Design Guidelines >
Section Positioning a Module on a Base Board.
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
12 Product Handling
12 Product Handling
12.1 Storage Conditions
The products sealed in moisture barrier bags (MBB) should be stored in a non-condensing atmospheric
environment of < 40 °C and 90%RH. The module is rated at the moisture sensitivity level (MSL) of 3.
After unpacking, the module must be soldered within 168 hours with the factory conditions 25±5 °C and
60%RH. If the above conditions are not met, the module needs to be baked.
12.2 Electrostatic Discharge (ESD)
• Human body model (HBM): ±2000 V
• Charged-device model (CDM): ±500 V
12.3 Reflow Profile
Solder the module in a single reflow.
Peak temperature: 235 – 250 °C
Peak time: 30 – 70 s
Soldering time: ＞ 30 s
Solder: Sn-Ag-Cu (SAC305) lead-free solder
Temperature (°C)
250
230
217
200
180
150
100
50
Ramp-up
Preheating
Soldering
Cooling
25
25 – 150 °C
60 – 90 s
1 – 3 °C/s
150 – 200 °C
60 – 120 s
＞ 217 °C
60 – 90 s
＜ 180 °C
–5 ~ –1 °C/s
0
50
Time (s)
100
150
200
250
Figure 12-1. Reflow Profile
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12 Product Handling
12.4
Ultrasonic Vibration
Avoid exposing Espressif modules to vibration from ultrasonic equipment, such as ultrasonic welders or
ultrasonic cleaners. This vibration may induce resonance in the in-module crystal and lead to its malfunction or
even failure. As a consequence, the module may stop working or its performance may deteriorate.
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
Datasheet Versioning
Datasheet Versioning
Datasheet
Version
v0.1 ~ v0.5
(excluding v0.5)
Status
Watermark
Definition
This datasheet is under development for products
Draft
Confidential
in the design stage. Specifications may change
without prior notice.
This datasheet is actively updated for products in
v0.5 ~ v1.0
Preliminary
(excluding v1.0)
release
the verification stage. Specifications may change
Preliminary
before mass production, and the changes will be
documentation in the datasheet’s Revision History.
This datasheet is publicly released for products in
v1.0 and higher
Official release
mass production. Specifications are finalized, and
—
major changes will be communicated via Product
Change Notifications (PCN).
Not
Any version
—
Any version
—
Recommended
This datasheet is updated less frequently for
for New Design
(NRND)1
products not recommended for new designs.
End of Life
(EOL)2
This datasheet is no longer mtained for products
that have reached end of life.
1 Watermark will be added to the datasheet title page only when all the product variants covered by this
datasheet are not recommended for new designs.
2 Watermark will be added to the datasheet title page only when all the product variants covered by this
datasheet have reached end of life.
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
Related Documentation and Resources
Related Documentation and Resources
Related Documentation
• ESP32-C5 Series Datasheet- Specifications of the ESP32-C5 hardware.
• ESP32-C5 Technical Reference Manual – Detailed information on how to use the ESP32-C5 memory and peripherals.
• ESP32-C5 Hardware Design Guidelines – Guidelines on how to integrate the ESP32-C5 into your hardware product.
• ESP32-C5 Series SoC Errata – Descriptions of known errors in ESP32-C5 series of SoCs.
• Certificates
https://espressif.com/en/support/documents/certificates
• ESP32-C5 Product/Process Change Notifications (PCN)
https://espressif.com/en/support/documents/pcns?keys=ESP32-C5
• ESP32-C5 Advisories – Information on security, bugs, compatibility, component reliability.
https://espressif.com/en/support/documents/advisories?keys=ESP32-C5
• Documentation Updates and Update Notification Subscription
https://espressif.com/en/support/download/documents
Developer Zone
• ESP-IDF Programming Guide for ESP32-C5 – Extensive documentation for the ESP-IDF development framework.
• ESP-IDF and other development frameworks on GitHub.
https://github.com/espressif
• ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions,
share knowledge, explore ideas, and help solve problems with fellow engineers.
https://esp32.com/
• ESP-FAQ – A summary document of frequently asked questions released by Espressif.
https://espressif.com/projects/esp-faq/en/latest/index.html
• The ESP Journal – Best Practices, Articles, and Notes from Espressif folks.
https://blog.espressif.com/
• See the tabs SDKs and Demos, Apps, Tools, AT Firmware.
https://espressif.com/en/support/download/sdks-demos
Products
• ESP32-C5 Series SoCs – Browse through all ESP32-C5 SoCs.
https://espressif.com/en/products/socs?id=ESP32-C5
• ESP32-C5 Series Modules – Browse through all ESP32-C5-based modules.
https://espressif.com/en/products/modules?id=ESP32-C5
• ESP32-C5 Series DevKits – Browse through all ESP32-C5-based devkits.
https://espressif.com/en/products/devkits?id=ESP32-C5
• ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters.
https://products.espressif.com/#/product-selector?language=en
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Related Documentation and Resources
Contact Us
• See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples
(Online stores), Become Our Supplier, Comments & Suggestions.
https://espressif.com/en/contact-us/sales-questions
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ESP32-C5-WROOM-1 & WROOM-1U Datasheet v1.1
Revision History
Revision History
Date
Version
2026-03-04
v1.1
Release Notes
According to PCN20251201, added notes about ESP32-C5HF4 pins in Figure
8-1 ESP32-C5-WROOM-1 Schematics and Figure 8-2 ESP32-C5-WROOM-1U
Schematics
2026-01-05
v1.0
Official release; cleared all preliminary annotations
• In Chapter 1.2 Series Comparison:
– Updated ”Ordering Code” to ”Part Number”
– Added information for ESP32-C5-WROOM-1-N32R8 and ESP32-C5-
2025-11-25
v0.8
WROOM-1U-N32R8
• In Chapter 4 Boot Configurations, removed content related to crystal frequency selection
In Chapter 1.2 Series Comparison:
2025-09-11
v0.7
• Added Figure 1-1 ESP32-C5 Module Variant Nomenclature
• Updated the ordering code and added the embedded chip for both
ESP32-C5-WROOM-1 and ESP32-C5-WROOM-1U
• In Chapter 2 Block Diagram, added a note about pin mapping between
the chip and the in-package flash
• In Chapter 10.2 Dimensions of External Antenna Connector, added the
2025-08-07
v0.6
external antenna information for certification
• Added Sections 4.5 Chip Power-up and Reset, 6.5 Memory Specifications and Datasheet Versioning
2025-05-21
v0.5
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Disclaimer and Copyright Notice
Information in this document, including URL references, is subject to change without notice.
ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES TO ITS AUTHENTICITY AND
ACCURACY.
NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR
PURPOSE, NOR DOES ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No
licenses express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein.
The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are
hereby acknowledged.
Copyright © 2026 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.
www.espressif.com
