ESP32-C3

ESP32-C3 Series Datasheet Ultra-Low-Power SoC with RISC-V Single-Core CPU 2.4 GHz Wi-Fi (802.11 b/g/n) and Bluetooth® 5 (LE) Optional 4 MB flash in the chip’s package QFN32 (5×5 mm) Package Including: ESP32-C3 ESP32-C3FN4 – Not Recommended for New Designs (NRND) ESP32-C3FH4 ESP32-C3FH4AZ Version 1.5 Espressif Systems Copyright © 2023 www.espressif.com Product Overview ESP32-C3 is an low-power and highly-integrated MCU-based solution that supports 2.4 GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). The functional block diagram of the SoC is shown below. Espressif ESP32-C3 Wi-Fi + Bluetooth® Low Energy SoC CPU and Memory JTAG ROM RF Synthesizer SRAM 2.4 GHz Transmitter Cache 2.4 GHz Balun + Switch 2.4 GHz Receiver RISC-V 32-bit Microprocessor RF Wireless Digital Circuits External Main Clock Fast RC Oscillator Bluetooth LE Link Controller Phase Lock Loop Bluetooth LE Baseband Peripherals GDMA RMT SPI0/1 SPI2 I2C I2S UART TWAI® World Controller Debug Assistant Generalpurpose Timers Wi-Fi Baseband Wi-Fi MAC Security GPIO eFuse Controller DIG ADC Temperature Sensor LED PWM USB Serial/ JTAG System Timer Main System Watchdog Timers SHA RSA RNG HMAC Digital Signature Secure Boot Flash Encryption RTC Watchdog Timer Super Watchdog AES RTC RTC Memory PMU Brownout Detector Power consumption Normal Low power consumption components capable of working in Deep-sleep mode ESP32-C3 Functional Block Diagram For more information on power consumption, see Section 3.7 Power Management. Espressif Systems 2 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 Features Wi-Fi • IEEE 802.11 b/g/n-compliant • Supports 20 MHz, 40 MHz bandwidth in 2.4 GHz band • 1T1R mode with data rate up to 150 Mbps • Wi-Fi Multimedia (WMM) • TX/RX A-MPDU, TX/RX A-MSDU • Immediate Block ACK • Fragmentation and defragmentation • Transmit opportunity (TXOP) • Automatic Beacon monitoring (hardware TSF) • 4 × virtual Wi-Fi interfaces • Simultaneous support for Infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode Note that when ESP32-C3 scans in Station mode, the SoftAP channel will change along with the Station channel • Antenna diversity • 802.11mc FTM Bluetooth® • Bluetooth LE: Bluetooth 5, Bluetooth mesh • High power mode (20 dBm) • Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps • Advertising extensions • Multiple advertisement sets • Channel selection algorithm #2 • Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna CPU and Memory • 32-bit RISC-V single-core processor, up to 160 MHz • CoreMark® score: – 1 core at 160 MHz: 407.22 CoreMark; 2.55 CoreMark/MHz • 384 KB ROM • 400 KB SRAM (16 KB for cache) Espressif Systems 3 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 • 8 KB SRAM in RTC • In-package flash (see details in Chapter 1 ESP32-C3 Series Comparison) • SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to multiple off-package flash • Access to flash accelerated by cache • Supports flash in-Circuit Programming (ICP) Advanced Peripheral Interfaces • 22 or 16 programmable GPIOs • Digital interfaces: – 3 × SPI – 2 × UART – 1 × I2C – 1 × I2S – Remote control peripheral, with 2 transmit channels and 2 receive channels – LED PWM controller, with up to 6 channels – Full-speed USB Serial/JTAG controller – General DMA controller (GDMA), with 3 transmit channels and 3 receive channels – 1 × TWAI® controller compatible with ISO 11898-1 (CAN Specification 2.0) • Analog interfaces: – 2 × 12-bit SAR ADCs, up to 6 channels – 1 × temperature sensor • Timers: – 2 × 54-bit general-purpose timers – 3 × digital watchdog timers – 1 × analog watchdog timer – 1 × 52-bit system timer Power Management • Fine-resolution power control through a selection of clock frequency, duty cycle, Wi-Fi operating modes, and individual power control of internal components • Four power modes designed for typical scenarios: Active, Modem-sleep, Light-sleep, Deep-sleep • Power consumption in Deep-sleep mode is 5 µA • RTC memory remains powered on in Deep-sleep mode Espressif Systems 4 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 Security • Secure boot - permission control on accessing internal and external memory • Flash encryption - memory encryption and decryption • 4096-bit OTP, up to 1792 bits for users • Cryptographic hardware acceleration: – AES-128/256 (FIPS PUB 197) – SHA Accelerator (FIPS PUB 180-4) – RSA Accelerator – Random Number Generator (RNG) – HMAC – Digital signature RF Module • Antenna switches, RF balun, power amplifier, low-noise receive amplifier • Up to +21 dBm of power for an 802.11b transmission • Up to +20 dBm of power for an 802.11n transmission • Up to -105 dBm of sensitivity for Bluetooth LE receiver (125 Kbps) Applications With low power consumption, ESP32-C3 is an ideal choice for IoT devices in the following areas: • Smart Home • POS machines • Industrial Automation • Service robot • Health Care • Audio Devices • Consumer Electronics • Generic Low-power IoT Sensor Hubs • Smart Agriculture • Generic Low-power IoT Data Loggers Espressif Systems 5 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 Contents Note: Check the link or the QR code to make sure that you use the latest version of this document: https://www.espressif.com/documentation/esp32-c3_datasheet_en.pdf Contents Product Overview 2 Features 3 Applications 5 1 ESP32-C3 Series Comparison 11 1.1 Nomenclature 11 1.2 Comparison 11 2 Pins 12 2.1 Pin Layout 12 2.2 Pin Overview 14 2.3 IO Pins 17 2.3.1 IO MUX and GPIO Functions 17 2.3.2 Analog Functions 19 2.3.3 Restrictions for GPIOs 20 2.4 Analog Pins 21 2.5 Power Supply 22 2.5.1 Power Pins 22 2.5.2 Power Scheme 22 2.5.3 Chip Power-up and Reset 23 2.6 Strapping Pins 24 2.6.1 Chip Boot Mode Control 25 2.6.2 ROM Messages Printing Control 25 2.7 Pin Mapping Between Chip and Flash 27 3 Functional Description 28 3.1 CPU and Memory 28 3.1.1 CPU 28 3.1.2 Internal Memory 28 3.1.3 Off-package Flash 28 3.1.4 Address Mapping Structure 29 3.1.5 Cache 29 System Clocks 30 3.2.1 CPU Clock 30 3.2.2 RTC Clock 30 Analog Peripherals 30 3.2 3.3 Espressif Systems 6 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 Contents 3.4 3.3.1 Analog-to-Digital Converter (ADC) 30 3.3.2 Temperature Sensor 31 Digital Peripherals 31 3.4.1 General Purpose Input / Output Interface (GPIO) 31 3.4.2 Serial Peripheral Interface (SPI) 31 3.4.3 Universal Asynchronous Receiver Transmitter (UART) 32 3.4.4 I2C Interface 32 3.4.5 I2S Interface 33 3.4.6 Remote Control Peripheral 33 3.4.7 LED PWM Controller 33 3.4.8 General DMA Controller 34 3.4.9 USB Serial/JTAG Controller 34 ® 3.5 3.6 3.4.10 TWAI Controller 34 Radio and Wi-Fi 35 3.5.1 2.4 GHz Receiver 35 3.5.2 2.4 GHz Transmitter 35 3.5.3 Clock Generator 35 3.5.4 Wi-Fi Radio and Baseband 36 3.5.5 Wi-Fi MAC 36 3.5.6 Networking Features 36 Bluetooth LE 36 3.6.1 Bluetooth LE Radio and PHY 37 3.6.2 Bluetooth LE Link Layer Controller 37 3.7 Power Management 37 3.8 Timers 39 3.8.1 General Purpose Timers 39 3.8.2 System Timer 39 3.8.3 Watchdog Timers 40 3.9 Cryptographic Hardware Accelerators 40 3.10 Physical Security Features 41 3.11 Peripheral Pin Configurations 41 4 Electrical Characteristics 43 4.1 Absolute Maximum Ratings 43 4.2 Recommended Power Supply Characteristics 43 4.3 VDD_SPI Output Characteristics 44 4.4 DC Characteristics (3.3 V, 25 °C) 44 4.5 ADC Characteristics 45 4.6 Current Consumption 45 4.6.1 RF Current Consumption in Active Mode 45 4.6.2 Current Consumption in Other Modes 46 4.7 Reliability 46 4.8 Wi-Fi Radio 47 4.8.1 Wi-Fi RF Transmitter (TX) Specifications 47 4.8.2 Wi-Fi RF Receiver (RX) Specifications 48 4.9 Bluetooth LE Radio Espressif Systems 49 7 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 Contents 4.9.1 Bluetooth LE RF Transmitter (TX) Specifications 49 4.9.2 Bluetooth LE RF Receiver (RX) Specifications 51 5 Packaging 54 6 Related Documentation and Resources 55 Appendix A – ESP32-C3 Consolidated Pin Overview 56 Revision History 57 Espressif Systems 8 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 List of Tables List of Tables 1-1 ESP32-C3 Series Comparison 11 2-1 Pin Overview 15 2-2 Power-Up Glitches on Pins 16 2-3 IO MUX Pin Functions 17 2-4 RTC and Analog Functions 19 2-5 Analog Pins 21 2-6 Power Pins 22 2-7 Voltage Regulators 22 2-8 Description of Timing Parameters for Power-up and Reset 23 2-9 Default Configuration of Strapping Pins 24 2-10 Description of Timing Parameters for the Strapping Pins 24 2-11 Chip Boot Mode Control 25 2-12 ROM Messages Printing Control 26 2-13 Pin Mapping Between Chip and In-package Flash 27 3-1 Components and Power Domains 39 3-2 Peripheral Pin Configurations 41 4-1 Absolute Maximum Ratings 43 4-2 Recommended Power Characteristics 43 4-3 VDD_SPI Internal and Output Characteristics 44 4-4 DC Characteristics (3.3 V, 25 °C) 44 4-5 ADC Characteristics 45 4-6 ADC Calibration Results 45 4-7 Wi-Fi Current Consumption Depending on RF Modes 45 4-8 Current Consumption in Modem-sleep Mode 46 4-9 Current Consumption in Low-Power Modes 46 4-10 Reliability Qualifications 46 4-11 Wi-Fi Frequency 47 4-12 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 47 4-13 TX EVM Test 47 4-14 RX Sensitivity 48 4-15 Maximum RX Level 48 4-16 RX Adjacent Channel Rejection 49 4-17 Bluetooth LE Frequency 49 4-18 Transmitter Characteristics - Bluetooth LE 1 Mbps 49 4-19 Transmitter Characteristics - Bluetooth LE 2 Mbps 50 4-20 Transmitter Characteristics - Bluetooth LE 125 Kbps 50 4-21 Transmitter Characteristics - Bluetooth LE 500 Kbps 50 4-22 Receiver Characteristics - Bluetooth LE 1 Mbps 51 4-23 Receiver Characteristics - Bluetooth LE 2 Mbps 51 4-24 Receiver Characteristics - Bluetooth LE 125 Kbps 52 4-25 Receiver Characteristics - Bluetooth LE 500 Kbps 52 Espressif Systems 9 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 List of Figures List of Figures 1-1 ESP32-C3 Series Nomenclature 11 2-1 ESP32-C3 Pin Layout (Top View) 12 2-2 ESP32-C3FH4AZ Pin Layout (Top View) 13 2-3 ESP32-C3 Power Scheme 23 2-4 Visualization of Timing Parameters for Power-up and Reset 23 2-5 Visualization of Timing Parameters for the Strapping Pins 25 3-1 Address Mapping Structure 29 3-2 Components and Power Domains 38 5-1 QFN32 (5×5 mm) Package 54 Espressif Systems 10 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 1 ESP32-C3 Series Comparison 1 ESP32-C3 Series Comparison 1.1 Nomenclature ESP32-C3 H F x AZ Other Identification Code Flash Flash temperature H: High temperature N: Normal temperature Flash Chip series Figure 1-1. ESP32-C3 Series Nomenclature 1.2 Comparison Table 1-1. ESP32-C3 Series Comparison Ordering Code1 In-Package Flash Ambient Temp.2(°C) — –40 ∼ 105 ESP32-C3FN4 (NRND) 4 MB ESP32-C3FH4 ESP32-C33 ESP32-C3FH4AZ 4 GPIO No. Chip Revision5 QFN32 (5*5) 22 v0.4 –40 ∼ 85 QFN32 (5*5) 22 v0.4 4 MB –40 ∼ 105 QFN32 (5*5) 22 v0.4 4 MB –40 ∼ 105 QFN32 (5*5) 16 v0.4 Package (mm) 1 For details on chip marking and packing, see Section 5 Packaging. 2 Ambient temperature specifies the recommended temperature range of the environment immediately outside an Espressif chip. 3 ESP32-C3 requires an SPI flash off the chip’s package. For details about SPI modes, see Section 2.7 Pin Mapping Between Chip and Flash. 4 For ESP32-C3FH4AZ, SPI0/SPI1 pins for flash connection are not bonded. 5 For how to identify chip revisions, please refer to ESP32-C3 Series SoC Errata. Espressif Systems 11 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins 2 Pins 25 GPIO18 26 GPIO19 27 U0RXD 28 U0TXD 29 XTAL_N 30 XTAL_P 31 VDDA 32 VDDA 2.1 Pin Layout LNA_IN 1 24 SPIQ VDD3P3 2 23 SPID VDD3P3 3 22 SPICLK XTAL_32K_P 4 21 SPICS0 XTAL_32K_N 5 20 SPIWP GPIO2 6 CHIP_EN 7 GPIO3 8 ESP32-C3 19 SPIHD 18 VDD_SPI 17 VDD3P3_CPU GPIO10 16 GPIO9 15 GPIO8 14 MTDO 13 MTCK 12 VDD3P3_RTC 11 MTDI 10 MTMS 9 33 GND Figure 2-1. ESP32-C3 Pin Layout (Top View) Espressif Systems 12 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 25 GPIO18 26 GPIO19 27 U0RXD 28 U0TXD 29 XTAL_N 30 XTAL_P 31 VDDA 32 VDDA 2 Pins LNA_IN 1 24 NC VDD3P3 2 23 NC VDD3P3 3 22 NC XTAL_32K_P 4 21 NC XTAL_32K_N 5 20 NC GPIO2 6 CHIP_EN 7 GPIO3 8 ESP32-C3FH4AZ 19 NC 18 VDD_SPI 17 VDD3P3_CPU GPIO10 16 GPIO9 15 GPIO8 14 MTDO 13 MTCK 12 VDD3P3_RTC 11 MTDI 10 MTMS 9 33 GND Figure 2-2. ESP32-C3FH4AZ Pin Layout (Top View) Espressif Systems 13 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins 2.2 Pin Overview The ESP32-C3 chip integrates multiple peripherals that require communication with the outside world. To keep the chip package size reasonably small, the number of available pins has to be limited. So the only way to route all the incoming and outgoing signals is through pin multiplexing. Pin muxing is controlled via software programmable registers (see ESP32-C3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix). All in all, the ESP32-C3 chip has the following types of pins: • IO pins with the following predefined sets of functions to choose from: – Each IO pin has predefined IO MUX and GPIO functions – see Table 2-3 IO MUX and GPIO Functions – Some IO pins have predefined analog functions – see Table 2-4 Analog Functions Predefined functions means that each IO pin has a set of direct connections to certain on-chip components. During run-time, the user can configure which component from a predefined set to connect to a certain pin at a certain time via memory mapped registers (see the TRM). • Analog pins that have exclusively-dedicated analog functions – see Table 2-5 Analog Pins • Power pins supply power to the chip components and non-power pins – see Table 2-6 Power Pins Notes for Table 2-1 Pin Overview (see below): 1. For more information, see respective sections below. Alternatively, see Appendix A – ESP32-C3 Consolidated Pin Overview. 2. Bold marks the pin function set in which a pin has its default function in the default boot mode. See Section 2.6.1 Chip Boot Mode Control. 3. In column Pin Providing Power, regarding pins powered by VDD_SPI: • Power actually comes from the internal power rail supplying power to VDD_SPI. For details, see Section 2.5.2 Power Scheme. 4. In column Pin Providing Power, regarding pins powered by VDD3P3_CPU / VDD_SPI: • Pin Providing Power (either VDD3P3_CPU or VDD_SPI) can be configured via a register, see ESP32-C3 Technical Reference Manual > Chapter IO MUX and GPIO pins. 5. Except for GPIO18 and GPIO19 whose default drive strength is 40 mA, the default drive strength for all the other pins is 20 mA. 6. Column Pin Settings shows predefined settings at reset and after reset with the following abbreviations: • IE – input enabled • WPU – internal weak pull-up resistor enabled • WPD – internal weak pull-down resistor enabled • USB_PU – USB pull-up resistor enabled – By default, the USB function is enabled for USB pins (i.e., GPIO18 and GPIO19), and the pin pull-up is decided by the USB pull-up resistor. The USB pull-up resistor is controlled by USB_SERIAL_JTAG_DP/DM_PULLUP and the pull-up value is controlled by Espressif Systems 14 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins USB_SERIAL_JTAG_PULLUP_VALUE. For details, see ESP32-C3 Technical Reference Manual > Chapter USB Serial/JTAG Controller) – When the USB function is disabled, USB pins are used as regular GPIOs and the pin’s internal weak pull-up and pull-down resistors are disabled by default (configurable by IO_MUX_FUN_ WPU/WPD) 7. Depends on the value of EFUSE_DIS_PAD_JTAG • 0 - default value. Input enabled, and internal weak pull-up resistor enabled (IE & WPU) • 1 - input enabled (IE) 8. Output enabled 9. By default VDD_SPI is the power supply pin for in-package and off-package flash. It can be reconfigured as a GPIO pin, if the chip is connected to an off-package flash, and this flash is powered by an external power supply. For details about reconfiguration, please refer to ESP32-C3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix. 10. For ESP32-C3FH4AZ, pins within the frame (namely pin 19 ∼ pin 24) are not bonded, and are labelled as ”not connected”. Table 2-1. Pin Overview Pin Pin Pin Pin Settings 6 Pin Providing 1 Power 3-5 No. Name Type At Reset After Reset 1 LNA_IN Analog 2 VDD3P3 Power 3 VDD3P3 Power 4 XTAL_32K_P IO VDD3P3_RTC 5 XTAL_32K_N IO VDD3P3_RTC 6 GPIO2 IO VDD3P3_RTC IE IE 7 CHIP_EN 8 GPIO3 IO VDD3P3_RTC IE 9 MTMS IO VDD3P3_RTC 10 MTDI IO 11 VDD3P3_RTC 12 MTCK 13 Pin Function Sets 1,2 IO MUX Analog IO MUX Analog IO MUX Analog IO MUX Analog IE IO MUX Analog IE IO MUX Analog VDD3P3_RTC IE IO MUX Analog IO VDD3P3_CPU IE 7 IO MUX MTDO IO VDD3P3_CPU IE IO MUX 14 GPIO8 IO VDD3P3_CPU IE IE IO MUX 15 GPIO9 IO VDD3P3_CPU IE, WPU IE, WPU IO MUX 16 GPIO10 IO VDD3P3_CPU IE IO MUX 17 VDD3P3_CPU Power 18 VDD_SPI 9 10 Power 19 SPIHD IO VDD_SPI / VDD3P3_CPU WPU IE, WPU IO MUX 20 SPIWP IO VDD_SPI / VDD3P3_CPU WPU IE, WPU IO MUX 21 SPICS0 IO VDD_SPI / VDD3P3_CPU WPU IE, WPU IO MUX 22 SPICLK IO VDD_SPI / VDD3P3_CPU WPU IE, WPU IO MUX 23 SPID IO VDD_SPI / VDD3P3_CPU WPU IE, WPU IO MUX 24 SPIQ IO VDD_SPI / VDD3P3_CPU WPU IE, WPU IO MUX 25 GPIO18 IO VDD3P3_CPU Analog Power VDD3P3_CPU IO MUX IO MUX Analog Cont’d on next page Espressif Systems 15 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins Table 2-1 – cont’d from previous page Pin Pin Pin Type Pin Settings 6 Pin Providing 1 No. Name 26 GPIO19 IO 27 U0RXD 28 U0TXD 29 XTAL_N Analog 30 XTAL_P Analog 31 VDDA Power 32 VDDA Power 33 GND Power Power 3-5 At Reset Pin Function Sets 1,2 After Reset IO MUX Analog VDD3P3_CPU USB_PU IO MUX Analog IO VDD3P3_CPU IE, WPU IO MUX IO VDD3P3_CPU WPU 8 IO MUX Some pins have glitches during power-up. See details in Table 2-2. Table 2-2. Power-Up Glitches on Pins Pin Glitch1 MTCK Low-level glitch 5 MTDO Low-level glitch 5 GPIO10 Low-level glitch 5 U0RXD Low-level glitch 5 GPIO18 High-level glitch 50000 1 Typical Time Period(ns) Low-level glitch: the pin is at a low level output status during the time period; High-level glitch: the pin is at a high level output status during the time period; Pull-down glitch: the pin is at an internal weak pulled-down status during the time period; Pull-up glitch: the pin is at an internal weak pulled-up status during the time period. Please refer to Table 4-4 for detailed parameters about low/high-level and pull-down/up. Espressif Systems 16 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins 2.3 IO Pins 2.3.1 IO MUX and GPIO Functions The pins of ESP32-C3 can be assigned any function (F0-F2) from their respective sets of IO MUX functions as listed in Table 2-3 IO MUX and GPIO Functions. Each set of the IO MUX functions has a general purpose input/output (GPIO0, GPIO1, etc.) function. If a pin is assigned a GPIO function, this pin’s signal is routed via the GPIO matrix, which incorporates internal signal routing circuitry for mapping signals programmatically. It gives the pin access to almost any IO MUX function. However, the flexibility of programmatic mapping comes at a cost as it might affect speed and latency of routed signals. Notes for Table 2-3 IO MUX and GPIO Functions: 1. Bold marks the default pin functions in the default boot mode. See Section 2.6.1 Chip Boot Mode Control. 2. Regarding highlighted cells, see Section 2.3.3 Restrictions for GPIOs. 3. Each IO MUX function (Fn, n = 0 ~ 2) is associated with a type. The description of type is as follows: • I – input. O – output. T – high impedance. • I1 – input; if the pin is assigned a function other than Fn, the input signal of Fn is always 1. • I0 – input; if the pin is assigned a function other than Fn, the input signal of Fn is always 0. 4. Function names: GPIO… General-purpose input/output with signals routed via the GPIO matrix. For more details on the GPIO matrix, see ESP32-C3 Technical Reference Manual U…RXD > Chapter IO MUX and GPIO Matrix. } U…TXD UART0/1 receive/transmit signals. 5. Groups of functions (see the markings in the table): a. JTAG interface for debugging. b. UART interface for debugging. c. SPI0/1 interface for connection to in-package or off-package flash via SPI bus. It supports 1-, 2-, 4-line SPI modes. See also Section 2.7 Pin Mapping Between Chip and Flash. d. SPI2 main interface for fast SPI connection. It supports 1-, 2-, 4-line SPI modes. Table 2-3. IO MUX Pin Functions Pin No. IO MUX / GPIO Name IO MUX Function 0 Type 1 Type 4 GPIO0 GPIO0 I/O/T GPIO0 I/O/T 5 GPIO1 GPIO1 I/O/T GPIO1 I/O/T 2 Type Cont’d on next page Espressif Systems 17 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins Table 2-3 – cont’d from previous page Pin No. Espressif Systems IO MUX / GPIO Name IO MUX Function 0 Type 1 Type 2 Type 5d I/O/T GPIO2 I/O/T I/O/T GPIO3 I/O/T MTMS I1 GPIO4 GPIO5 MTDI I1 12 GPIO6 MTCK 13 GPIO7 14 6 GPIO2 GPIO2 FSPIQ I1/O/T 8 GPIO3 GPIO3 9 GPIO4 I/O/T FSPIHD I1/O/T 10 GPIO5 I/O/T FSPIWP I1/O/T I1 GPIO6 I/O/T FSPICLK I1/O/T MTDO O/T GPIO7 I/O/T FSPID I1/O/T GPIO8 GPIO8 I/O/T GPIO8 I/O/T 15 GPIO9 GPIO9 I/O/T GPIO9 I/O/T 16 GPIO10 GPIO10 I/O/T GPIO10 I/O/T FSPICS0 I1/O/T 18 GPIO11 GPIO11 I/O/T GPIO11 I/O/T 19 GPIO12 SPIHD I1/O/T GPIO12 I/O/T 20 GPIO13 SPIWP I1/O/T GPIO13 I/O/T 21 GPIO14 SPICS0 O/T GPIO14 I/O/T 22 GPIO15 SPICLK O/T GPIO15 I/O/T 23 GPIO16 SPID I1/O/T GPIO16 I/O/T 24 GPIO17 SPIQ I1/O/T GPIO17 I/O/T 25 GPIO18 GPIO18 I/O/T GPIO18 I/O/T 26 GPIO19 GPIO19 I/O/T GPIO19 I/O/T 27 GPIO20 U0RXD I1 GPIO20 I/O/T 28 GPIO21 U0TXD O GPIO21 I/O/T 5a 5c 5b 18 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins 2.3.2 Analog Functions Notes for Table 2-4 Analog Functions: 1. Bold marks the default pin functions in the default boot mode. See Section 2.6.1 Chip Boot Mode Control. 2. Regarding highlighted cells, see Section 2.3.3 Restrictions for GPIOs. 3. Function names: XTAL_32K_P XTAL_32K_N ADC1_CH… ADC2_CH… USB_DUSB_D+ } } 32 kHz external clock input/output connected to ESP32-C3’s oscillator. P/N means differential clock positive/negative. Analog to digital conversion channel for ADC1 or ADC2. } USB Serial/JTAG function. USB signal is a differential signal transmitted over a pair of D+ and D- wires. Table 2-4. RTC and Analog Functions Espressif Systems Pin Analog No. IO Name 0 Analog Function 1 4 GPIO0 XTAL_32K_P ADC1_CH0 5 GPIO1 XTAL_32K_N ADC1_CH1 6 GPIO2 ADC1_CH2 8 GPIO3 ADC1_CH3 9 GPIO4 ADC1_CH4 10 GPIO5 ADC2_CH0 25 GPIO18 USB_D- 26 GPIO19 USB_D+ 19 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins 2.3.3 Restrictions for GPIOs All IO pins of the ESP32-C3 have GPIO pin functions. However, the IO pins are multiplexed and have other important pin functions. This should be taken into account while certain pins are chosen for general purpose input output. In Table 2-3 IO MUX and GPIO Functions and Table 2-4 Analog Functions some pin functions are highlighted . The non-highlighted GPIO pins are recommended for use first. If more pins are needed, the highlighted GPIOs should be chosen carefully to avoid conflicts with important pin functions. The highlighted IO pins have the following important pin functions: • GPIO – allocated for communication with in-package flash and NOT recommended for other uses. For details, see Section 2.7 Pin Mapping Between Chip and Flash. • GPIO – have one of the following important functions: – Strapping pins – need to be at certain logic levels at startup. See Section 2.6 Strapping Pins. – USB_D+/- – by default, connected to the USB Serial/JTAG Controller. To function as GPIOs, these pins need to be reconfigured by referring to ESP32-C3 Technical Reference Manual > Chapter IO MUX and GPIO Matrix. – JTAG interface – often used for debugging. See Table 2-3 IO MUX and GPIO Functions, note 5a. To free these pins up, the pin functions USB_D+/- of the ESP32-C3 Technical Reference Manual USB Serial/JTAG Controller can be used instead. – UART interface – often used for debugging. See Table 2-3 IO MUX and GPIO Functions, note 5b. – ADC2 – no restrictions, unless there is an on-going Wi-Fi connection. ADC2_CH… analog functions (see Table 2-4 Analog Functions) cannot be used with Wi-Fi simultaneously. See also Appendix A – ESP32-C3 Consolidated Pin Overview. Espressif Systems 20 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins 2.4 Analog Pins Table 2-5. Analog Pins Pin Pin Pin Pin No. Name Type Function 1 LNA_IN I/O Low Noise Amplifier (RF LNA) input / output signals 7 CHIP_EN I High: on, the chip is started up. Low: off, the chip is shut down. Note: Do not leave the CHIP_EN pin floating. 29 XTAL_N — External clock input/output connected to ESP32-C3’s oscillator. 30 XTAL_P — P/N means differential clock positive/negative. Espressif Systems 21 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins 2.5 Power Supply 2.5.1 Power Pins The chip is powered via the power pins described in Table 2-6 Power Pins. Table 2-6. Power Pins Power Supply 1,2 Pin Pin No. Name Direction Power Domain / Other 2 VDD3P3 Input Analog power domain 3 VDD3P3 Input Analog power domain 11 VDD3P3_RTC Input RTC and part of Digital power domains RTC IO 17 VDD3P3_CPU Input Digital power domain Digital IO 18 VDD_SPI 3 Input In-package flash (backup power line) Output Off-package flash 31 VDDA Input Analog power domain 32 VDDA Input Analog power domain 33 GND — External ground connection IO Pins 4 SPI IO 1 See in conjunction with Section 2.5.2 Power Scheme. 2 For recommended and maximum voltage and current, see Section 4.1 Absolute Maximum Ratings and Section 4.2 Recommended Power Supply Characteristics. 3 To configure VDD_SPI as input or output, see ESP32-C3 Technical Reference Manual > Chapter Low-power Management. 4 Digital IO pins are those powered by VDD3P3_CPU, and RTC IO pins are those powered by VDD3P3_RTC and so on, as shown in Figure 2-3 ESP32-C3 Power Scheme. See also Table 2-1 Pin Overview > Column Pin Providing Power. 2.5.2 Power Scheme The power scheme is shown in Figure 2-3 ESP32-C3 Power Scheme. The components on the chip are powered via voltage regulators. Table 2-7. Voltage Regulators Voltage Regulator Espressif Systems Output Power Supply Digital 1.1 V Digital power domain Low-power 1.1 V RTC power domain 22 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins Figure 2-3. ESP32-C3 Power Scheme 2.5.3 Chip Power-up and Reset Once the power is supplied to the chip, its power rails need a short time to stabilize. After that, CHIP_EN – the pin used for power-up and reset – is pulled high to activate the chip. For information on CHIP_EN as well as power-up and reset timing, see Figure 2-4 and Table 2-8. tST BL tRST 2.8 V VDDA, VDD3P3, VDD3P3_RTC, VDD3P3_CPU VIL_nRST CHIP_EN Figure 2-4. Visualization of Timing Parameters for Power-up and Reset Table 2-8. Description of Timing Parameters for Power-up and Reset Parameter Description Min (µs) Time reserved for the power rails of VDDA, VDD3P3, VDD3P3_RTC, tST BL and VDD3P3_CPU to stabilize before the CHIP_EN pin is pulled high 50 to activate the chip tRST Espressif Systems Time reserved for CHIP_EN to stay below VIL_nRST to reset the chip (see Table 4-4) 23 Submit Documentation Feedback 50 ESP32-C3 Series Datasheet v1.5 2 Pins 2.6 Strapping Pins At each startup or reset, a chip requires some initial configuration parameters, such as in which boot mode to load the chip, etc. These parameters are passed over via the strapping pins. After reset, the strapping pins operate as regular IO pins. The parameters controlled by the given strapping pins at chip reset are as follows: • Chip boot mode – GPIO2, GPIO8, and GPIO9 • ROM messages printing – GPIO8 GPIO9 connected to the chip’s internal weak pull-up resistor at chip reset. This resistor determines the default bit value of GPIO9. Also, this resistor determines the bit value if GPIO9 is connected to an external high-impedance circuit. Table 2-9. Default Configuration of Strapping Pins Strapping Pin Default Configuration Bit Value GPIO2 Floating – GPIO8 Floating – GPIO9 Pull-up 1 To change the bit values, the strapping pins should be connected to external pull-down/pull-up resistances. If the ESP32-C3 is used as a device by a host MCU, the strapping pin voltage levels can also be controlled by the host MCU. All strapping pins have latches. At system reset, the latches sample the bit values of their respective strapping pins and store them until the chip is powered down or shut down. The states of latches cannot be changed in any other way. It makes the strapping pin values available during the entire chip operation, and the pins are freed up to be used as regular IO pins after reset. Regarding the timing requirements for the strapping pins, there are such parameters as setup time and hold time. For more information, see Table 2-10 and Figure 2-5. Table 2-10. Description of Timing Parameters for the Strapping Pins Parameter tSU Description Min (ms) Setup time is the time reserved for the power rails to stabilize before the CHIP_EN pin is pulled high to activate the chip. 0 Hold time is the time reserved for the chip to read the strapping pin tH values after CHIP_EN is already high and before these pins start 3 operating as regular IO pins. Espressif Systems 24 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins tSU tH VIL_nRST CHIP_EN VIH Strapping pin Figure 2-5. Visualization of Timing Parameters for the Strapping Pins 2.6.1 Chip Boot Mode Control GPIO2, GPIO8, and GPIO9 control the boot mode after the reset is released. See Table 2-11 Chip Boot Mode Control. Table 2-11. Chip Boot Mode Control Boot Mode Default configuration GPIO2 a GPIO8 GPIO9 – (Floating) – (Floating) 1 (Pull-up) 1 Any value 1 1 1 0 SPI Boot (default) Joint Download Boot a b GPIO2 actually does not determine SPI Boot and Joint Download Boot mode, but it is recommended to pull this pin up due to glitches. b Joint Download Boot mode supports the following download methods: • USB-Serial-JTAG Download Boot • UART Download Boot In SPI Boot mode, the ROM bootloader loads and executes the program from SPI flash to boot the system. In Joint Download Boot mode, users can download binary files into flash using UART0 or USB interface. It is also possible to download binary files into SRAM and execute it from SRAM. 2.6.2 ROM Messages Printing Control During boot process the messages by the ROM code can be printed to: • USB Serial/JTAG controller. For this, set EFUSE_USB_PRINT_CHANNEL and EFUSE_DIS_USB_SERIAL_JTAG to 0. • UART. For this, set EFUSE_DIS_USB_SERIAL_JTAG to 1. In this case, EFUSE_UART_PRINT_CONTROL and GPIO8 control ROM messages printing as shown in Table 2-12 ROM Messages Printing Control. Espressif Systems 25 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins Table 2-12. ROM Messages Printing Control eFuse1 GPIO8 ROM Messages Printing 0 Ignored Always enabled 1 2 3 1 Espressif Systems 0 Enabled 1 Disabled 0 Disabled 1 Enabled Ignored Always disabled eFuse: EFUSE_UART_PRINT_CONTROL 26 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 2 Pins 2.7 Pin Mapping Between Chip and Flash Table 2-13 lists the pin mapping between the chip and flash for all SPI modes. For chip variants with in-package flash (see Table 1-1 Comparison), the pins allocated for communication with in-package flash can be identified depending on the SPI mode used. For off-package flash, these are the recommended pin mappings. For more information on SPI controllers, see also Section 3.4.2 Serial Peripheral Interface (SPI). Notice: It is not recommended to use the pins connected to flash for any other purposes. Table 2-13. Pin Mapping Between Chip and In-package Flash Pin Pin Single SPI Dual SPI Quad SPI / QPI No. Name Flash Flash Flash 22 SPICLK CLK CLK CLK CS# CS# CS# 21 SPICS0 23 SPID DI DI DI 24 SPIQ DO DO DO 20 SPIWP WP# WP# WP# 19 SPIHD HOLD# HOLD# HOLD# 1 Espressif Systems 1 CS0 is for in-package flash 27 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description 3 Functional Description This chapter describes the functions of ESP32-C3. 3.1 CPU and Memory 3.1.1 CPU ESP32-C3 has a low-power 32-bit RISC-V single-core microprocessor with the following features: • four-stage pipeline that supports a clock frequency of up to 160 MHz • RV32IMC ISA • 32-bit multiplier and 32-bit divider • up to 32 vectored interrupts at seven priority levels • up to 8 hardware breakpoints/watchpoints • up to 16 PMP regions • JTAG for debugging For more information, please refer to Chapter ESP-RISC-V CPU in ESP32-C3 Technical Reference Manual. 3.1.2 Internal Memory ESP32-C3’s internal memory includes: • 384 KB of ROM: for booting and core functions. • 400 KB of on-chip SRAM: for data and instructions, running at a configurable frequency of up to 160 MHz. Of the 400 KB SRAM, 16 KB is configured for cache. • RTC FAST memory: 8 KB of SRAM that can be accessed by the main CPU. It can retain data in Deep-sleep mode. • 4 Kbit of eFuse: 1792 bits are reserved for your data, such as encryption key and device ID. • In-package flash : See details in Chapter 1 ESP32-C3 Series Comparison. For more information, please refer to Chapter System and Memory in ESP32-C3 Technical Reference Manual. 3.1.3 Off-package Flash ESP32-C3 supports SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to multiple off-package flash, i.e. flash outside the chip’s pacakge. CPU’s instruction memory space and read-only data memory space can map into the off-package flash of ESP32-C3, whose size can be 16 MB at most. ESP32-C3 supports hardware encryption/decryption based on XTS-AES to protect developers’ programs and data in flash. Through high-speed caches, ESP32-C3 can support at a time up to: • 8 MB of instruction memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and 32-bit reads are supported. Espressif Systems 28 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description • 8 MB of data memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and 32-bit reads are supported. Note: After ESP32-C3 is initialized, software can customize the mapping of off-package flash into the CPU address space. For more information, please refer to Chapter System and Memory in ESP32-C3 Technical Reference Manual. 3.1.4 Address Mapping Structure Figure 3-1. Address Mapping Structure Note: The memory space with gray background is not available for use. 3.1.5 Cache ESP32-C3 has an eight-way set associative cache. This cache is read-only and has the following features: • size: 16 KB Espressif Systems 29 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description • block size: 32 bytes • pre-load function • lock function • critical word first and early restart 3.2 System Clocks For more information, please refer to Chapter Reset and Clock in ESP32-C3 Technical Reference Manual. 3.2.1 CPU Clock The CPU clock has three possible sources: • external main crystal clock • fast RC oscillator (typically about 17.5 MHz, and adjustable) • PLL clock The application can select the clock source from the three clocks above. The selected clock source drives the CPU clock directly, or after division, depending on the application. Once the CPU is reset, the default clock source would be the external main crystal clock divided by 2. Note: ESP32-C3 is unable to operate without an external main crystal clock. 3.2.2 RTC Clock The RTC slow clock is used for RTC counter, RTC watchdog and low-power controller. It has three possible sources: • external low-speed (32 kHz) crystal clock • internal slow RC oscillator (typically about 136 kHz, and adjustable) • internal fast RC oscillator divided clock (derived from the fast RC oscillator divided by 256) The RTC fast clock is used for RTC peripherals and sensor controllers. It has two possible sources: • external main crystal clock divided by 2 • internal fast RC oscillator divide-by-N clock (typically about 17.5 MHz, and adjustable) 3.3 Analog Peripherals For more information, please refer to Chapter On-Chip Sensors and Analog Signal Processing in ESP32-C3 Technical Reference Manual. 3.3.1 Analog-to-Digital Converter (ADC) ESP32-C3 integrates two 12-bit SAR ADCs. • ADC1 supports measurements on 5 channels, and is factory-calibrated. Espressif Systems 30 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description • ADC2 supports measurements on 1 channel, and is not factory-calibrated. Note: ADC2 of some chip revisions is not operable. For details, please refer to ESP32-C3 Series SoC Errata. For ADC characteristics, please refer to Table 4.5. For GPIOs assigned to ADC, please refer to Table 3-2. 3.3.2 Temperature Sensor The temperature sensor generates a voltage that varies with temperature. The voltage is internally converted via an ADC into a digital value. The temperature sensor has a range of –40 °C to 125 °C. It is designed primarily to sense the temperature changes inside the chip. The temperature value depends on factors like microcontroller clock frequency or I/O load. Generally, the chip’s internal temperature is higher than the operating ambient temperature. 3.4 Digital Peripherals 3.4.1 General Purpose Input / Output Interface (GPIO) ESP32-C3 has 22 or 16 GPIO pins which can be assigned various functions by configuring corresponding registers. Besides digital signals, some GPIOs can be also used for analog functions, such as ADC. All GPIOs have selectable internal pull-up or pull-down, or can be set to high impedance. When these GPIOs are configured as an input, the input value can be read by software through the register. Input GPIOs can also be set to generate edge-triggered or level-triggered CPU interrupts. All digital IO pins are bi-directional, non-inverting and tristate, including input and output buffers with tristate control. These pins can be multiplexed with other functions, such as the UART, SPI, etc. For low-power operations, the GPIOs can be set to holding state. The IO MUX and the GPIO matrix are used to route signals from peripherals to GPIO pins. Together they provide highly configurable I/O. Using GPIO Matrix, peripheral input signals can be configured from any IO pins while peripheral output signals can be configured to any IO pins. For more information, please refer to Chapter IO MUX and GPIO Matrix (GPIO, IO_MUX) in ESP32-C3 Technical Reference Manual. 3.4.2 Serial Peripheral Interface (SPI) ESP32-C3 has the following SPI interfaces: • SPI0 used by ESP32-C3’s GDMA controller and cache to access in-package or off-package flash • SPI1 used by the CPU to access in-package or off-package flash • SPI2 is a general purpose SPI controller with access to a DMA channel allocated by the GDMA controller Features of SPI0 and SPI1 • Supports Single SPI, Dual SPI, and Quad SPI, QPI modes • Configurable clock frequency with a maximum of 120 MHz in Single Transfer Rate (STR) mode Espressif Systems 31 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description • Data transmission is in bytes Features of SPI2 • Supports operation as a master or slave • Connects to a DMA channel allocated by the GDMA controller • Supports Single SPI, Dual SPI, and Quad SPI, QPI • Configurable clock polarity (CPOL) and phase (CPHA) • Configurable clock frequency • Data transmission is in bytes • Configurable read and write data bit order: most-significant bit (MSB) first, or least-significant bit (LSB) first • As a master – Supports 2-line full-duplex communication with clock frequency up to 80 MHz – Supports 1-, 2-, 4-line half-duplex communication with clock frequency up to 80 MHz – Provides six SPI_CS pins for connection with six independent SPI slaves – Configurable CS setup time and hold time • As a slave – Supports 2-line full-duplex communication with clock frequency up to 60 MHz – Supports 1-, 2-, 4-line half-duplex communication with clock frequency up to 60 MHz For GPIOs assigned to SPI, please refer to Table 3-2. For more information, please refer to Chapter SPI Controller (SPI) in ESP32-C3 Technical Reference Manual. 3.4.3 Universal Asynchronous Receiver Transmitter (UART) ESP32-C3 has two UART interfaces, i.e. UART0 and UART1, which support IrDA and asynchronous communication (RS232 and RS485) at a speed of up to 5 Mbps. The UART controller provides hardware flow control (CTS and RTS signals) and software flow control (XON and XOFF). Both UART interfaces connect to GDMA via UHCI0, and can be accessed by the GDMA controller or directly by the CPU. For GPIOs assigned to UART, please refer to Table 3-2. For more information, please refer to Chapter UART Controller (UART) in ESP32-C3 Technical Reference Manual. 3.4.4 I2C Interface ESP32-C3 has an I2C bus interface which is used for I2C master mode or slave mode, depending on your configuration. The I2C interface supports: • standard mode (100 Kbit/s) • fast mode (400 Kbit/s) Espressif Systems 32 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description • up to 800 Kbit/s (constrained by SCL and SDA pull-up strength) • 7-bit and 10-bit addressing mode • double addressing mode • 7-bit broadcast address You can configure instruction registers to control the I2C interface for more flexibility. For GPIOs assigned to I2C, please refer to Table 3-2. For more information, please refer to Chapter I2C Controller (I2C) in ESP32-C3 Technical Reference Manual. 3.4.5 I2S Interface ESP32-C3 includes a standard I2S interface. This interface can operate as a master or a slave in full-duplex mode or half-duplex mode, and can be configured for 8-bit, 16-bit, 24-bit, or 32-bit serial communication. BCK clock frequency, from 10 kHz up to 40 MHz, is supported. The I2S interface connects to the GDMA controller. The interface supports TDM PCM, TDM MSB alignment, TDM standard, and PDM standard. For GPIOs assigned to I2S, please refer to Table 3-2. For more information, please refer to Chapter I2S Controller (I2S) in ESP32-C3 Technical Reference Manual. 3.4.6 Remote Control Peripheral The Remote Control Peripheral (RMT) supports two channels of infrared remote transmission and two channels of infrared remote reception. By controlling pulse waveform through software, it supports various infrared and other single wire protocols. All four channels share a 192 × 32-bit memory block to store transmit or receive waveform. For GPIOs assigned to the Remote Control Peripheral, please refer to Table 3-2. For more information, please refer to Chapter Remote Control Peripheral (RMT) in ESP32-C3 Technical Reference Manual. 3.4.7 LED PWM Controller The LED PWM controller can generate independent digital waveform on six channels. The LED PWM controller: • can generate digital waveform with configurable periods and duty cycle. The accuracy of duty cycle can be up to 18 bits. • has multiple clock sources, including APB clock and external main crystal clock. • can operate when the CPU is in Light-sleep mode. • supports gradual increase or decrease of duty cycle, which is useful for the LED RGB color-gradient generator. For GPIOs assigned to LED PWM, please refer to Table 3-2. Espressif Systems 33 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description For more information, please refer to Chapter LED PWM Controller (LEDC) in ESP32-C3 Technical Reference Manual. 3.4.8 General DMA Controller ESP32-C3 has a general DMA controller (GDMA) with six independent channels, i.e. three transmit channels and three receive channels. These six channels are shared by peripherals with DMA feature. The GDMA controller implements a fixed-priority scheme among these channels, whose priority can be configured. The GDMA controller controls data transfer using linked lists. It allows peripheral-to-memory and memory-to-memory data transfer at a high speed. All channels can access internal RAM. Peripherals on ESP32-C3 with DMA feature are SPI2, UHCI0, I2S, AES, SHA, and ADC. For more information, please refer to Chapter GDMA Controller (GDMA) in ESP32-C3 Technical Reference Manual. 3.4.9 USB Serial/JTAG Controller ESP32-C3 integrates a USB Serial/JTAG controller. This controller has the following features: • CDC-ACM virtual serial port and JTAG adapter functionality • USB 2.0 full speed compliant, capable of up to 12 Mbit/s transfer speed (Note that this controller does not support the faster 480 Mbit/s high-speed transfer mode) • programming in-package/off-package flash • CPU debugging with compact JTAG instructions • a full-speed USB PHY integrated in the chip For GPIOs assigned to USB Serial/JTAG, please refer to Table 3-2. For more information, please refer to Chapter USB Serial/JTAG Controller (USB_SERIAL_JTAG) in ESP32-C3 Technical Reference Manual. 3.4.10 TWAI® Controller ESP32-C3 has a TWAI® controller with the following features: • compatible with ISO 11898-1 protocol (CAN Specification 2.0) • standard frame format (11-bit ID) and extended frame format (29-bit ID) • bit rates from 1 Kbit/s to 1 Mbit/s • multiple modes of operation: Normal, Listen Only, and Self-Test (no acknowledgment required) • 64-byte receive FIFO • acceptance filter (single and dual filter modes) • error detection and handling: error counters, configurable error interrupt threshold, error code capture, arbitration lost capture For GPIOs assigned to TWAI, please refer to Table 3-2. Espressif Systems 34 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description For more information, please refer to Chapter Two-wire Automotive Interface (TWAI) in ESP32-C3 Technical Reference Manual. 3.5 Radio and Wi-Fi ESP32-C3 radio consists of the following blocks: • 2.4 GHz receiver • 2.4 GHz transmitter • bias and regulators • balun and transmit-receive switch • clock generator 3.5.1 2.4 GHz Receiver The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them to the digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions, ESP32-C3 integrates RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits, and baseband filters. 3.5.2 2.4 GHz Transmitter The 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives the antenna with a high-powered CMOS power amplifier. The use of digital calibration further improves the linearity of the power amplifier. Additional calibrations are integrated to cancel any radio imperfections, such as: • carrier leakage • I/Q amplitude/phase matching • baseband nonlinearities • RF nonlinearities • antenna matching These built-in calibration routines reduce the cost, time, and specialized equipment required for product testing. 3.5.3 Clock Generator The clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. All components of the clock generator are integrated into the chip, including inductors, varactors, filters, regulators and dividers. The clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise are optimized on chip with patented calibration algorithms which ensure the best performance of the receiver and the transmitter. Espressif Systems 35 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description 3.5.4 Wi-Fi Radio and Baseband ESP32-C3 Wi-Fi radio and baseband support the following features: • 802.11b/g/n • 802.11n MCS0-7 that supports 20 MHz and 40 MHz bandwidth • 802.11n MCS32 • 802.11n 0.4 µs guard interval • data rate up to 150 Mbps • RX STBC (single spatial stream) • adjustable transmitting power • antenna diversity ESP32-C3 supports antenna diversity with an external RF switch. This switch is controlled by one or more GPIOs, and used to select the best antenna to minimize the effects of channel imperfections. 3.5.5 Wi-Fi MAC ESP32-C3 implements the full 802.11 b/g/n Wi-Fi MAC protocol. It supports the Basic Service Set (BSS) STA and SoftAP operations under the Distributed Control Function (DCF). Power management is handled automatically with minimal host interaction to minimize the active duty period. ESP32-C3 Wi-Fi MAC applies the following low-level protocol functions automatically: • 4 × virtual Wi-Fi interfaces • infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode • RTS protection, CTS protection, Immediate Block ACK • fragmentation and defragmentation • TX/RX A-MPDU, TX/RX A-MSDU • transmit opportunity (TXOP) • Wi-Fi multimedia (WMM) • GCMP, CCMP, TKIP, WAPI, WEP, BIP, WPA2-PSK/WPA2-Enterprise, and WPA3-PSK/WPA3-Enterprise • automatic beacon monitoring (hardware TSF) • 802.11mc FTM 3.5.6 Networking Features Espressif provides libraries for TCP/IP networking, ESP-WIFI-MESH networking, and other networking protocols over Wi-Fi. TLS 1.0, 1.1 and 1.2 is also supported. 3.6 Bluetooth LE ESP32-C3 includes a Bluetooth Low Energy subsystem that integrates a hardware link layer controller, an RF/modem block and a feature-rich software protocol stack. It supports the core features of Bluetooth 5 and Espressif Systems 36 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description Bluetooth mesh. 3.6.1 Bluetooth LE Radio and PHY Bluetooth Low Energy radio and PHY in ESP32-C3 support: • 1 Mbps PHY • 2 Mbps PHY for higher data rates • coded PHY for longer range (125 Kbps and 500 Kbps) • HW Listen before talk (LBT) 3.6.2 Bluetooth LE Link Layer Controller Bluetooth Low Energy Link Layer Controller in ESP32-C3 supports: • LE advertising extensions, to enhance broadcasting capacity and broadcast more intelligent data • multiple advertisement sets • simultaneous advertising and scanning • multiple connections in simultaneous central and peripheral roles • adaptive frequency hopping and channel assessment • LE channel selection algorithm #2 • connection parameter update • high duty cycle non-connectable advertising • LE privacy 1.2 • LE data packet length extension • link layer extended scanner filter policies • low duty cycle directed advertising • link layer encryption • LE Ping 3.7 Power Management The ESP32-C3 has an advanced Power Management Unit (PMU). It can be flexibly configured to power up different power domains of the chip to achieve the best balance between chip performance, power consumption, and wakeup latency. Configuring the PMU is a complex procedure. To simplify power management for typical scenarios, there are the following predefined power modes that power up different combinations of power domains: • Active mode – The CPU, RF circuits, and all peripherals are on. The chip can process data, receive, transmit, and listen. • Modem-sleep mode – The CPU is on, but the clock frequency can be reduced. The wireless connections can be configured to remain active as RF circuits are periodically switched on when required. Espressif Systems 37 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description • Light-sleep mode – The CPU stops running, and can be optionally powered on. The chip can be woken up via all wake up mechanisms: MAC, RTC timer, or external interrupts. Wireless connections can remain active. Some groups of digital peripherals can be optionally shut down. • Deep-sleep mode – Only RTC is powered on. Wireless connection data is stored in RTC memory. For power consumption in different power modes, see Section 4.6 Current Consumption. Figure 3-2 Components and Power Domains and the following Table 3-1 show the distribution of chip components between power domains and power subdomains . Espressif’s ESP32-C3 Wi-Fi + Bluetooth® Low Energy SoC Digital Power Domain CPU RISC-V 32-bit Microprocessor World Controller ROM JTAG GPIO I2S UART RNG LED PWM Flash Encryption DIG ADC RMT Temperature Sensor Generalpurpose Timers SPI0/1 Cache Debug Assistant TWAI® I2C SRAM USB Serial/ JTAG System Timer Main System Watchdog Timers Optional Digital Peripherals Wireless Digital Circuits Bluetooth LE Link Controller Wi-Fi MAC SHA RSA HMAC Digital Signature Bluetooth LE Baseband Wi-Fi Baseband AES SPI2 Secure Boot GDMA Analog Power Domain RTC Power Domain PMU eFuse Controller Brownout Detector RTC Memory Super Watchdog RTC Timer RTC Watchdog Timer RF Circuits 2.4 GHz Receiver 2.4 GHz Transmitter RF Synthesizer 2.4 GHz Balun + Switch PLL RC_FAST_CLK XTAL_CLK Phase Lock Loop Fast RC Oscillator External Main Clock Power distribution Power domain Power subdomain Figure 3-2. Components and Power Domains Espressif Systems 38 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description Table 3-1. Components and Power Domains Power RTC Digital Analog Domain Power CPU Mode Active Modem-sleep ON ON ON ON Optional Wireless Digital Digital Periph Circuits ON ON ON ON ON 1 1 FOSC_ XTAL_ CLK CLK PLL RF Circuits ON ON ON ON ON 1 ON ON ON ON OFF2 1 ON Light-sleep ON ON OFF ON OFF ON OFF OFF OFF OFF2 Deep-sleep ON OFF OFF OFF OFF ON OFF OFF OFF OFF 1 Configurable, see the TRM. 2 If Wireless Digital Circuits are on, RF circuits are periodically switched on when required by internal operation to keep active wireless connections running. For more information, please refer to Chapter Low-Power Management (RTC_CNTL) in ESP32-C3 Technical Reference Manual. 3.8 Timers 3.8.1 General Purpose Timers ESP32-C3 is has with two 54-bit general-purpose timers, which are based on 16-bit prescalers and 54-bit auto-reload-capable up/down-timers. The timers’ features are summarized as follows: • a 16-bit clock prescaler, from 1 to 65536 • a 54-bit time-base counter programmable to be incrementing or decrementing • able to read real-time value of the time-base counter • halting and resuming the time-base counter • programmable alarm generation • level interrupt generation For more information, please refer to Chapter Timer Group (TIMG) in ESP32-C3 Technical Reference Manual. 3.8.2 System Timer ESP32-C3 integrates a 52-bit system timer, which has two 52-bit counters and three comparators. The system timer has the following features: • counters with a fixed clock frequency of 16 MHz • three types of independent interrupts generated according to alarm value • two alarm modes: target mode and period mode • 52-bit target alarm value and 26-bit periodic alarm value • automatic reload of counter value Espressif Systems 39 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description • counters can be stalled if the CPU is stalled or in OCD mode For more information, please refer to Chapter System Timer (SYSTIMER) in ESP32-C3 Technical Reference Manual. 3.8.3 Watchdog Timers For more information, please refer to Chapter Watchdog Timers (WDT) in ESP32-C3 Technical Reference Manual. Digital Watchdog Timers ESP32-C3 contains three digital watchdog timers: one in each of the two timer groups (called Main System Watchdog Timers, or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT). During the flash boot process, RWDT and the MWDT in timer group 0 (TIMG0) are enabled automatically in order to detect and recover from booting errors. Digital watchdog timers have the following features: • four stages, each with a programmable timeout value. Each stage can be configured, enabled and disabled separately • interrupt, CPU reset, or core reset for MWDT upon expiry of each stage; interrupt, CPU reset, core reset, or system reset for RWDT upon expiry of each stage • 32-bit expiry counter • write protection, to prevent RWDT and MWDT configuration from being altered inadvertently • flash boot protection If the boot process from an SPI flash does not complete within a predetermined period of time, the watchdog will reboot the entire main system. Analog Watchdog Timer ESP32-C3 also has one analog watchdog timer: RTC super watchdog timer (SWD). It is an ultra-low-power circuit in analog domain that helps to prevent the system from operating in a sub-optimal state and resets the system if required. SWD has the following features: • Ultra-low power • Interrupt to indicate that the SWD timeout period is close to expiring • Various dedicated methods for software to feed SWD, which enables SWD to monitor the working state of the whole operating system 3.9 Cryptographic Hardware Accelerators ESP32-C3 is equipped with hardware accelerators of general algorithms, such as AES-128/AES-256 (FIPS PUB 197), ECB/CBC/OFB/CFB/CTR (NIST SP 800-38A), SHA1/SHA224/SHA256 (FIPS PUB 180-4), and RSA3072. The chip also supports independent arithmetic, such as large-number modular multiplication and large-number Espressif Systems 40 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description multiplication. The maximum operation length for RSA and large-number modular multiplication is 3072 bits. The maximum operand length for large-number multiplication is 1536 bits. 3.10 Physical Security Features • Transparent off-package flash encryption (AES-XTS algorithm) with software inaccessible key prevents unauthorized readout of your application code or data. • Secure boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature) can be booted. • HMAC module can use a software inaccessible MAC key to generate MAC signatures for identity verification and other purposes. • Digital Signature module can use a software inaccessible secure key to generate RSA signatures for identity verification. • World Controller provides two running environments for software. All hardware and software resources are sorted to two groups, and placed in either secure or general world. The secure world cannot be accessed by hardware in the general world, thus establishing a security boundary. 3.11 Peripheral Pin Configurations Table 3-2. Peripheral Pin Configurations Interface Signal Pin Function ADC ADC1_CH0 XTAL_32K_P Two 12-bit SAR ADCs ADC1_CH1 XTAL_32K_N ADC1_CH2 GPIO2 ADC1_CH3 GPIO3 ADC1_CH4 MTMS ADC2_CH0 MTDI MTDI MTDI MTCK MTCK MTMS MTMS MTDO MTDO U0RXD_in Any GPIO pins JTAG UART JTAG for software debugging U0CTS_in Two UART channels with hardware flow control and GDMA U0DSR_in U0TXD_out U0RTS_out U0DTR_out U1RXD_in U1CTS_in U1DSR_in U1TXD_out U1RTS_out U1DTR_out Espressif Systems 41 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 3 Functional Description Interface Signal Pin Function I2C I2CEXT0_SCL_in Any GPIO pins One I2C channel in slave or master mode I2CEXT0_SDA_in I2CEXT1_SCL_in I2CEXT1_SDA_in I2CEXT0_SCL_out I2CEXT0_SDA_out I2CEXT1_SCL_out I2CEXT1_SDA_out LED PWM ledc_ls_sig_out0~5 Any GPIO pins Six independent PWM channels I2S I2S0O_BCK_in Any GPIO pins Stereo input and output from/to the audiocodec Any GPIO pins Two channels for an IR transceiver of various I2S_MCLK_in I2SO_WS_in I2SI_SD_in I2SI_BCK_in I2SI_WS_in I2SO_BCK_out I2S_MCLK_out I2SO_WS_out I2SO_SD_out I2SI_BCK_out I2SI_WS_out I2SO_SD1_out Remote Control RMT_SIG_IN0~1 Peripheral RMT_SIG_OUT0~1 SPI0/1 SPICLK_out_mux SPICLK Support Standard SPI, Dual SPI, Quad SPI, and SPICS0_out SPICS0 QPI that allow connection to off-package flash SPICS1_out Any GPIO pins SPID_in/_out SPID SPIQ_in/_out SPIQ SPIWP_in/_out SPIWP SPIHD_in/_out SPIHD FSPICLK_in/_out_mux Any GPIO pins SPI2 waveforms SPI, Quad SPI, and QPI FSPICS0_in/_out • Connection to off-package flash, RAM, and FSPICS1~5_out other SPI devices FSPID_in/_out USB Serial/JTAG TWAI • Master mode and slave mode of SPI, Dual FSPIQ_in/_out • Four modes of SPI transfer format FSPIWP_in/_out • Configurable SPI frequency FSPIHD_in/_out • 64-byte FIFO or GDMA buffer USB_D+ GPIO19 USB-to-serial converter, and USB-to-JTAG USB_D- GPIO18 converter twai_rx Any GPIO pins Compatible with ISO 11898-1 protocol twai_tx twai_bus_off_on twai_clkout Espressif Systems 42 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 4 Electrical Characteristics 4 Electrical Characteristics 4.1 Absolute Maximum Ratings Stresses above those listed in Table 4-1 Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and normal operation of the device at these or any other conditions beyond those indicated in Section 4.2 Recommended Power Supply Characteristics is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 4-1. Absolute Maximum Ratings Parameter Description Input power pins Ioutput 2 TST ORE 1 Min Allowed input voltage Max Unit –0.3 3.6 — 1000 mA –40 150 °C Cumulative IO output current Storage temperature V 1 For more information on input power pins, see Section 2.5.1 Power Pins. 2 The product proved to be fully functional after all its IO pins were pulled high while being connected to ground for 24 consecutive hours at ambient temperature of 25 °C. 4.2 Recommended Power Supply Characteristics For recommended ambient temperature, see Section 1 ESP32-C3 Series Comparison. Table 4-2. Recommended Power Characteristics Parameter 1 Description VDDA, VDD3P3, VDD3P3_RTC Min Typ Max Unit Recommended input voltage 3.0 3.3 3.6 V Recommended input voltage 3.0 3.3 3.6 V VDD_SPI (as input) — 3.0 3.3 3.6 V IV DD Cumulative input current 0.5 — — A VDD3P3_CPU 2, 3 1 See in conjunction with Section 2.5 Power Supply. 2 If VDD3P3_CPU is used to power VDD_SPI (see Section 2.5.2 Power Scheme), the voltage drop on RSP I should be accounted for. See also Section 4.3 VDD_SPI Output Characteristics. 3 If writing to eFuses, the voltage on VDD3P3_CPU should not exceed 3.3 V as the circuits responsible for burning eFuses are sensitive to higher voltages. Espressif Systems 43 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 4 Electrical Characteristics 4.3 VDD_SPI Output Characteristics Table 4-3. VDD_SPI Internal and Output Characteristics Parameter Description 1 Typ VDD_SPI powered by VDD3P3_CPU via RSP I RSP I Unit 7.5 for 3.3 V flash_CPU 2 1 See in conjunction with Section 2.5.2 Power Scheme. 2 VDD3P3_CPU must be more than VDD_flash_min + I_flash_max * RSP I ; Ω where • VDD_flash_min – minimum operating voltage of flash_CPU • I_flash_max – maximum operating current of flash_CPU 4.4 DC Characteristics (3.3 V, 25 °C) Table 4-4. DC Characteristics (3.3 V, 25 °C) Parameter Description CIN Pin capacitance VIH High-level input voltage VIL Low-level input voltage IIH IIL VOH VOL 2 2 Min Typ — Max Unit 2 — pF — VDD1+ 0.3 V –0.3 — 0.25 × VDD1 V High-level input current — — 50 nA Low-level input current — — 50 nA — — V 0.75 × VDD1 High-level output voltage 0.8 × VDD Low-level output voltage 1 1 — — 0.1 × VDD V — 40 — mA — 28 — mA 1 IOH IOL High-level source current (VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3) Low-level sink current (VDD1= 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3) RP U Internal weak pull-up resistor — 45 — kΩ RP D Internal weak pull-down resistor — 45 — kΩ — VDD1+ 0.3 V — 0.25 × VDD1 V VIH_nRST VIL_nRST Chip reset release voltage CHIP_EN voltage is within the specified range) 0.75 × VDD1 Chip reset voltage (CHIP_EN voltage is within the specified range) 1 VDD – voltage from a power pin of a respective power domain. 2 VOH and VOL are measured using high-impedance load. Espressif Systems 44 Submit Documentation Feedback –0.3 ESP32-C3 Series Datasheet v1.5 4 Electrical Characteristics 4.5 ADC Characteristics Table 4-5. ADC Characteristics Symbol Parameter Min ADC connected to an external DNL (Differential nonlinearity) 1 100 nF capacitor; DC signal input; Ambient temperature at 25 °C; INL (Integral nonlinearity) Wi-Fi off Sampling rate — Max Unit –7 7 LSB –12 12 LSB — 100 kSPS 2 1 To get better DNL results, you can sample multiple times and apply a filter, or calculate the average value. 2 kSPS means kilo samples-per-second. The calibrated ADC results after hardware calibration and software calibration are shown in Table 4-6. For higher accuracy, you may implement your own calibration methods. Table 4-6. ADC Calibration Results Parameter Description Total error Min Max Unit ATTEN0, effective measurement range of 0 ~ 750 –10 10 mV ATTEN1, effective measurement range of 0 ~ 1050 –10 10 mV ATTEN2, effective measurement range of 0 ~ 1300 –10 10 mV ATTEN3, effective measurement range of 0 ~ 2500 –35 35 mV 4.6 Current Consumption 4.6.1 RF Current Consumption in Active Mode The current consumption measurements are taken with a 3.3 V supply at 25 °C of ambient temperature at the RF port. All transmitters’ measurements are based on a 100% duty cycle. Table 4-7. Wi-Fi Current Consumption Depending on RF Modes Work Mode 1 Description TX Active (RF working) RX Espressif Systems Peak (mA) 802.11b, 1 Mbps, @21 dBm 335 802.11g, 54 Mbps, @19 dBm 285 802.11n, HT20, MCS7, @18.5 dBm 276 802.11n, HT40, MCS7, @18.5 dBm 278 802.11b/g/n, HT20 84 802.11n, HT40 87 45 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 4 Electrical Characteristics 4.6.2 Current Consumption in Other Modes Table 4-8. Current Consumption in Modem-sleep Mode CPU Frequency Mode (MHz) 160 Modem-sleep2,3 80 Typ Description All Peripherals Clocks All Peripherals Clocks Disabled (mA) Enabled (mA)1 CPU is running 23 28 CPU is idle 16 21 CPU is running 17 22 CPU is idle 13 18 1 In practice, the current consumption might be different depending on which peripherals are enabled. 2 In Modem-sleep mode, Wi-Fi is clock gated. 3 In Modem-sleep mode, the consumption might be higher when accessing flash. For a flash rated at 80 Mbit/s, in SPI 2-line mode the consumption is 10 mA. Table 4-9. Current Consumption in Low-Power Modes Mode Description Typ (µA) Light-sleep VDD_SPI and Wi-Fi are powered down, and all GPIOs are high-impedance Deep-sleep RTC timer + RTC memory 5 Power off CHIP_EN is set to low level, the chip is powered off 1 130 4.7 Reliability Table 4-10. Reliability Qualifications Test Item HTOL (High Temperature Operating Life) ESD (Electro-Static Discharge Sensitivity) Latch up Test Conditions Test Standard 125 °C, 1000 hours JESD22-A108 HBM (Human Body Mode)1± 2000 V JS-001 2 CDM (Charge Device Mode) ± 1000 V JS-002 Current trigger ± 200 mA JESD78 Voltage trigger 1.5 × VDDmax Bake 24 hours @125 °C Preconditioning Moisture soak (level 3: 192 hours @30 °C, 60% RH) IR reflow solder: 260 + 0 °C, 20 seconds, three times TCT (Temperature Cycling Test) J-STD-020, JESD47, JESD22-A113 –65 °C / 150 °C, 500 cycles JESD22-A104 130 °C, 85% RH, 96 hours JESD22-A118 150 °C, 1000 hours JESD22-A103 uHAST (Highly Accelerated Stress Test, unbiased) HTSL (High Temperature Storage Life) Cont’d on next page Espressif Systems 46 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 4 Electrical Characteristics Table 4-10 – cont’d from previous page Test Item LTSL (Low Temperature Storage Life) Test Conditions Test Standard –40 °C, 1000 hours JESD22-A119 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. 2 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 4.8 Wi-Fi Radio Table 4-11. Wi-Fi Frequency Parameter Center frequency of operating channel Min Typ Max (MHz) (MHz) (MHz) 2412 — 2484 4.8.1 Wi-Fi RF Transmitter (TX) Specifications Table 4-12. TX Power with Spectral Mask and EVM Meeting 802.11 Standards Min Typ Max (dBm) (dBm) (dBm) 802.11b, 1 Mbps — 21.0 — 802.11b, 11 Mbps — 21.0 — 802.11g, 6 Mbps — 21.0 — 802.11g, 54 Mbps — 19.0 — 802.11n, HT20, MCS0 — 20.0 — 802.11n, HT20, MCS7 — 18.5 — 802.11n, HT40, MCS0 — 20.0 — 802.11n, HT40, MCS7 — 18.5 — Rate Table 4-13. TX EVM Test Rate Typ SL1 (dB) (dB) (dB) 802.11b, 1 Mbps, @21 dBm — –24.5 –10 802.11b, 11 Mbps, @21 dBm — –25.0 –10 802.11g, 6 Mbps, @21 dBm — –23.0 –5 802.11g, 54 Mbps, @19 dBm — –27.5 –25 802.11n, HT20, MCS0, @20 dBm — –22.5 –5 802.11n, HT20, MCS7, @18.5 dBm — –29.0 –27 802.11n, HT40, MCS0, @20 dBm — –22.5 –5 802.11n, HT40, MCS7, @18.5 dBm — –28.0 –27 1 Espressif Systems Min SL stands for standard limit value. 47 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 4 Electrical Characteristics 4.8.2 Wi-Fi RF Receiver (RX) Specifications Table 4-14. RX Sensitivity Min Typ Max (dBm) (dBm) (dBm) 802.11b, 1 Mbps — –98.4 — 802.11b, 2 Mbps — –96.0 — 802.11b, 5.5 Mbps — –93.0 — 802.11b, 11 Mbps — –88.6 — 802.11g, 6 Mbps — –93.8 — 802.11g, 9 Mbps — –92.2 — 802.11g, 12 Mbps — –91.0 — 802.11g, 18 Mbps — –88.4 — 802.11g, 24 Mbps — –85.8 — 802.11g, 36 Mbps — –82.0 — 802.11g, 48 Mbps — –78.0 — 802.11g, 54 Mbps — –76.6 — 802.11n, HT20, MCS0 — –93.6 — 802.11n, HT20, MCS1 — –90.8 — 802.11n, HT20, MCS2 — –88.4 — 802.11n, HT20, MCS3 — –85.0 — 802.11n, HT20, MCS4 — –81.8 — 802.11n, HT20, MCS5 — –77.8 — 802.11n, HT20, MCS6 — –76.0 — 802.11n, HT20, MCS7 — –74.8 — 802.11n, HT40, MCS0 — –90.0 — 802.11n, HT40, MCS1 — –88.0 — 802.11n, HT40, MCS2 — –85.2 — 802.11n, HT40, MCS3 — –82.0 — 802.11n, HT40, MCS4 — –78.8 — 802.11n, HT40, MCS5 — –74.6 — 802.11n, HT40, MCS6 — –73.0 — 802.11n, HT40, MCS7 — –71.4 — Rate Table 4-15. Maximum RX Level Min Typ Max (dBm) (dBm) (dBm) 802.11b, 1 Mbps — 5 — 802.11b, 11 Mbps — 5 — 802.11g, 6 Mbps — 5 — 802.11g, 54 Mbps — 0 — 802.11n, HT20, MCS0 — 5 — Rate Cont’d on next page Espressif Systems 48 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 4 Electrical Characteristics Table 4-15 – cont’d from previous page Min Typ Max (dBm) (dBm) (dBm) 802.11n, HT20, MCS7 — 0 — 802.11n, HT40, MCS0 — 5 — 802.11n, HT40, MCS7 — 0 — Rate Table 4-16. RX Adjacent Channel Rejection Rate Min Typ Max (dB) (dB) (dB) 802.11b, 1 Mbps — 35 — 802.11b, 11 Mbps — 35 — 802.11g, 6 Mbps — 31 — 802.11g, 54 Mbps — 20 — 802.11n, HT20, MCS0 — 31 — 802.11n, HT20, MCS7 — 16 — 802.11n, HT40, MCS0 — 25 — 802.11n, HT40, MCS7 — 11 — 4.9 Bluetooth LE Radio Table 4-17. Bluetooth LE Frequency Parameter Min Typ Max (MHz) (MHz) (MHz) 2402 — 2480 Center frequency of operating channel 4.9.1 Bluetooth LE RF Transmitter (TX) Specifications Table 4-18. Transmitter Characteristics - Bluetooth LE 1 Mbps Parameter RF transmit power Carrier frequency offset and drift Modulation characteristics Description Min Typ Max Unit –24.00 0 20.00 Gain control step — 3.00 — dB Max |fn |n=0, 1, 2, ..k — 17.00 — kHz Max |f0 − fn | — 1.75 — kHz Max |fn − fn−5 | — 1.46 — kHz |f1 − f0 | — 0.80 — kHz ∆ f 1avg — 250.00 — kHz — 190.00 — kHz — 0.83 — — RF power control range Min ∆ f 2max (for at least 99.9% of all ∆ f 2max ) ∆ f 2avg /∆ f 1avg dBm Cont’d on next page Espressif Systems 49 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 4 Electrical Characteristics Table 4-18 – cont’d from previous page Parameter Description In-band spurious emissions Min Typ Max Unit ± 2 MHz offset — –37.62 — dBm ± 3 MHz offset — –41.95 — dBm > ± 3 MHz offset — –44.48 — dBm Table 4-19. Transmitter Characteristics - Bluetooth LE 2 Mbps Parameter Description Min Carrier frequency offset and drift Modulation characteristics In-band spurious emissions Max Unit –24.00 0 20.00 Gain control step — 3.00 — dB Max |fn |n=0, 1, 2, ..k — 20.80 — kHz Max |f0 − fn | — 1.30 — kHz Max |fn − fn−5 | — 1.33 — kHz |f1 − f0 | — 0.70 — kHz ∆ f 1avg — 498.00 — kHz — 430.00 — kHz ∆ f 2avg /∆ f 1avg — 0.93 — — ± 4 MHz offset — –43.55 — dBm ± 5 MHz offset — –45.26 — dBm > ± 5 MHz offset — –45.26 — dBm RF power control range RF transmit power Typ Min ∆ f 2max (for at least 99.9% of all ∆ f 2max ) dBm Table 4-20. Transmitter Characteristics - Bluetooth LE 125 Kbps Parameter Description Min Carrier frequency offset and drift Modulation characteristics Unit 0 20.00 Gain control step — 3.00 — dB Max |fn |n=0, 1, 2, ..k — 17.50 — kHz Max |f0 − fn | — 0.45 — kHz |fn − fn−3 | — 0.70 — kHz |f0 − f3 | — 0.30 — kHz ∆ f 1avg — 250.00 — kHz — 235.00 — kHz ± 2 MHz offset — –37.90 — dBm ± 3 MHz offset — –41.00 — dBm > ± 3 MHz offset — –42.50 — dBm Min ∆ f 1max (for at least 99.9% of all∆ f 2max ) In-band spurious emissions Max –24.00 RF power control range RF transmit power Typ dBm Table 4-21. Transmitter Characteristics - Bluetooth LE 500 Kbps Parameter RF transmit power Description Min RF power control range Typ Max –24.00 0 20.00 — 3.00 — Gain control step Unit dBm dB Cont’d on next page Espressif Systems 50 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 4 Electrical Characteristics Table 4-21 – cont’d from previous page Parameter Description Carrier frequency offset and drift Modulation characteristics Min Max Unit Max |fn |n=0, 1, 2, ..k — 17.00 — kHz Max |f0 − fn | — 0.88 — kHz |fn − fn−3 | — 1.00 — kHz |f0 − f3 | — 0.20 — kHz ∆ f 2avg — 208.00 — kHz — 190.00 — kHz ± 2 MHz offset — –37.90 — dBm ± 3 MHz offset — –41.30 — dBm > ± 3 MHz offset — –42.80 — dBm Min ∆ f 2max (for at least 99.9% of all ∆ f 2max ) In-band spurious emissions Typ 4.9.2 Bluetooth LE RF Receiver (RX) Specifications Table 4-22. Receiver Characteristics - Bluetooth LE 1 Mbps Parameter Description Sensitivity @30.8% PER — — –97 — dBm Maximum received signal @30.8% PER — — 5 — dBm Co-channel C/I — — 8 — dB F = F0 + 1 MHz — –3 — dB F = F0 – 1 MHz — –4 — dB F = F0 + 2 MHz — –29 — dB F = F0 – 2 MHz — –31 — dB F = F0 + 3 MHz — –33 — dB F = F0 – 3 MHz — –27 — dB F ≥ F0 + 4 MHz — –29 — dB F ≤ F0 – 4 MHz — –38 — dB — — –29 — dB F = Fimage + 1 MHz — –41 — dB F = Fimage – 1 MHz — –33 — dB 30 MHz ~ 2000 MHz — –5 — dBm 2003 MHz ~ 2399 MHz — –18 — dBm 2484 MHz ~ 2997 MHz — –15 — dBm 3000 MHz ~ 12.75 GHz — –5 — dBm — — –30 — dBm Adjacent channel selectivity C/I Image frequency Adjacent channel to image frequency Out-of-band blocking performance Intermodulation Min Typ Max Unit Table 4-23. Receiver Characteristics - Bluetooth LE 2 Mbps Parameter Description Min Sensitivity @30.8% PER — — Maximum received signal @30.8% PER — Co-channel C/I — Typ Max Unit –93 — dBm — 3 — dBm — 10 — dB Cont’d on next page Espressif Systems 51 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 4 Electrical Characteristics Table 4-23 – cont’d from previous page Parameter Description Adjacent channel selectivity C/I Image frequency Adjacent channel to image frequency Out-of-band blocking performance Intermodulation Min Typ Max Unit F = F0 + 2 MHz — –7 — dB F = F0 – 2 MHz — –7 — dB F = F0 + 4 MHz — –28 — dB F = F0 – 4 MHz — –26 — dB F = F0 + 6 MHz — –26 — dB F = F0 – 6 MHz — –27 — dB F ≥ F0 + 8 MHz — –29 — dB F ≤ F0 – 8 MHz — –28 — dB — — –28 — dB F = Fimage + 2 MHz — –26 — dB F = Fimage – 2 MHz — –7 — dB 30 MHz ~ 2000 MHz — –5 — dBm 2003 MHz ~ 2399 MHz — –19 — dBm 2484 MHz ~ 2997 MHz — –16 — dBm 3000 MHz ~ 12.75 GHz — –5 — dBm — — –29 — dBm Table 4-24. Receiver Characteristics - Bluetooth LE 125 Kbps Parameter Description Sensitivity @30.8% PER — — –105 — dBm Maximum received signal @30.8% PER — — 5 — dBm Co-channel C/I — — 3 — dB F = F0 + 1 MHz — –6 — dB F = F0 – 1 MHz — –6 — dB F = F0 + 2 MHz — –33 — dB F = F0 – 2 MHz — –43 — dB F = F0 + 3 MHz — –37 — dB F = F0 – 3 MHz — –47 — dB F ≥ F0 + 4 MHz — –40 — dB F ≤ F0 – 4 MHz — –50 — dB — — –40 — dB F = Fimage + 1 MHz — –50 — dB F = Fimage – 1 MHz — –37 — dB Adjacent channel selectivity C/I Image frequency Adjacent channel to image frequency Min Typ Max Unit Table 4-25. Receiver Characteristics - Bluetooth LE 500 Kbps Parameter Description Min Typ Max Unit Sensitivity @30.8% PER — — –100 — dBm Maximum received signal @30.8% PER — — 5 — dBm Co-channel C/I — — 3 — dB F = F0 + 1 MHz — –2 — dB Cont’d on next page Espressif Systems Adjacent channel selectivity C/I 52 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 4 Electrical Characteristics Table 4-25 – cont’d from previous page Parameter Image frequency Adjacent channel to image frequency Espressif Systems Description Min Typ Max Unit F = F0 – 1 MHz — –3 — dB F = F0 + 2 MHz — –32 — dB F = F0 – 2 MHz — –33 — dB F = F0 + 3 MHz — –23 — dB F = F0 – 3 MHz — –40 — dB F ≥ F0 + 4 MHz — –34 — dB F ≤ F0 – 4 MHz — –44 — dB — — –34 — dB F = Fimage + 1 MHz — –46 — dB F = Fimage – 1 MHz — –23 — dB 53 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 5 Packaging 5 Packaging • For information about tape, reel, and chip marking, please refer to Espressif Chip Packaging Information. • The pins of the chip are numbered in anti-clockwise order starting from Pin 1 in the top view. For pin numbers and pin names, see also Figure 2-1 ESP32-C3 Pin Layout (Top View). • The source file of recommended PCB land pattern is provided for your reference. You can view it with Autodesk Viewer. • For reference PCB layout, please refer to ESP32-C3 Hardware Design Guidelines. Figure 5-1. QFN32 (5×5 mm) Package Espressif Systems 54 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 6 Related Documentation and Resources 6 Related Documentation and Resources Related Documentation • ESP32-C3 Technical Reference Manual – Detailed information on how to use the ESP32-C3 memory and peripherals. • ESP32-C3 Hardware Design Guidelines – Guidelines on how to integrate the ESP32-C3 into your hardware product. • ESP32-C3 Series SoC Errata – Descriptions of known errors in ESP32-C3 series of SoCs. • Certificates https://espressif.com/en/support/documents/certificates • ESP32-C3 Product/Process Change Notifications (PCN) https://espressif.com/en/support/documents/pcns?keys=ESP32-C3 • ESP32-C3 Advisories – Information on security, bugs, compatibility, component reliability. https://espressif.com/en/support/documents/advisories?keys=ESP32-C3 • Documentation Updates and Update Notification Subscription https://espressif.com/en/support/download/documents Developer Zone • ESP-IDF Programming Guide for ESP32-C3 – Extensive documentation for the ESP-IDF development framework. • ESP-IDF and other development frameworks on GitHub. https://github.com/espressif • ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions, share knowledge, explore ideas, and help solve problems with fellow engineers. https://esp32.com/ • The ESP Journal – Best Practices, Articles, and Notes from Espressif folks. https://blog.espressif.com/ • See the tabs SDKs and Demos, Apps, Tools, AT Firmware. https://espressif.com/en/support/download/sdks-demos Products • ESP32-C3 Series SoCs – Browse through all ESP32-C3 SoCs. https://espressif.com/en/products/socs?id=ESP32-C3 • ESP32-C3 Series Modules – Browse through all ESP32-C3-based modules. https://espressif.com/en/products/modules?id=ESP32-C3 • ESP32-C3 Series DevKits – Browse through all ESP32-C3-based devkits. https://espressif.com/en/products/devkits?id=ESP32-C3 • ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters. https://products.espressif.com/#/product-selector?language=en Contact Us • See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples (Online stores), Become Our Supplier, Comments & Suggestions. https://espressif.com/en/contact-us/sales-questions Espressif Systems 55 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 56 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 * Pin Name LNA_IN VDD3P3 VDD3P3 XTAL_32K_P XTAL_32K_N GPIO2 CHIP_EN GPIO3 MTMS MTDI VDD3P3_RTC MTCK MTDO GPIO8 GPIO9 GPIO10 VDD3P3_CPU VDD_SPI SPIHD SPIWP SPICS0 SPICLK SPID SPIQ GPIO18 GPIO19 U0RXD U0TXD XTAL_N XTAL_P VDDA VDDA GND Pin Type Analog Power Power IO IO IO Analog IO IO IO Power IO IO IO IO IO Power Power IO IO IO IO IO IO IO IO IO IO Analog Analog Power Power Power Pin Providing Power VDD3P3_RTC VDD3P3_RTC VDD3P3_RTC VDD3P3_RTC VDD3P3_RTC VDD3P3_RTC VDD3P3_CPU VDD3P3_CPU VDD3P3_CPU VDD3P3_CPU VDD3P3_CPU VDD3P3_CPU VDD_SPI / VDD3P3_CPU VDD_SPI / VDD3P3_CPU VDD_SPI / VDD3P3_CPU VDD_SPI / VDD3P3_CPU VDD_SPI / VDD3P3_CPU VDD_SPI / VDD3P3_CPU VDD3P3_CPU VDD3P3_CPU VDD3P3_CPU VDD3P3_CPU Pin Settings At Reset After Reset 0 Analog Function 1 XTAL_32K_P XTAL_32K_N IE IE ADC1_CH0 ADC1_CH1 ADC1_CH2 IE IE IE IE ADC1_CH3 ADC1_CH4 ADC2_CH0 IE IE, WPU WPU WPU WPU WPU WPU WPU IE IE IE IE, WPU IE IE, WPU IE, WPU IE, WPU IE, WPU IE, WPU IE, WPU USB_DUSB_D+ IE, WPU WPU For details, see Section 2 Pins. Regarding highlighted cells, see Section 2.3.3 Restrictions for GPIOs. IO MUX Function 1 Type 2 0 Type Type GPIO0 GPIO1 GPIO2 I/O/T I/O/T I/O/T GPIO0 GPIO1 GPIO2 I/O/T I/O/T I/O/T FSPIQ I1/O/T GPIO3 MTMS MTDI I/O/T I1 I1 GPIO3 GPIO4 GPIO5 I/O/T I/O/T I/O/T FSPIHD FSPIWP I1/O/T I1/O/T MTCK MTDO GPIO8 GPIO9 GPIO10 I1 O/T I/O/T I/O/T I/O/T GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 I/O/T I/O/T I/O/T I/O/T I/O/T FSPICLK FSPID I1/O/T I1/O/T FSPICS0 I1/O/T GPIO11 SPIHD SPIWP SPICS0 SPICLK SPID SPIQ GPIO18 GPIO19 U0RXD U0TXD I/O/T I1/O/T I1/O/T O/T O/T I1/O/T I1/O/T I/O/T I/O/T I1 O GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T I/O/T Appendix A – ESP32-C3 Consolidated Pin Overview Espressif Systems Appendix A – ESP32-C3 Consolidated Pin Overview Revision History Revision History Date Version Release notes • Marked ESP32-C3FN4 as (NRND) • Improved the content in the following sections: – Section Product Overview – Section 2 Pins – Section 3.7 Power Management – Section 3.4.2 Serial Peripheral Interface (SPI) 2023-08-11 v1.5 – Section 4.1 Absolute Maximum Ratings – Section 4.2 Recommended Power Supply Characteristics – Section 4.3 VDD_SPI Output Characteristics – Section 4.5 ADC Characteristics • Added Appendix A • Updated the maximum value of ”RF power control range” to 20 dBm in Section 4.9 Bluetooth LE Radio • Other minor updates • Deleted feature ”Antenna diversity” from Section 3.6.1 Bluetooth LE Radio 2022-12-15 v1.4 and PHY • Deleted feature ”Supports external power amplifier” • Updated the glitch type of GPIO18 to high-level glitch in Table Pin Overview • Updated notes for Table Pin Overview • Added links to the Technical Reference Manual and Peripheral Pin Configurations in Chapter 3 Functional Description • Added a note about ADC2 error in Section 3.3.1 Analog-to-Digital Converter (ADC) 2022-11-15 v1.3 • Updated Section 3.8.3 Watchdog Timers • Added Table ADC Characteristics • Updated Section 4.6.2 Current Consumption in Other Modes • Updated RF transmit power in Section 4.9 Bluetooth LE Radio • Updated the typo in Section 5 Packaging • Updated Chapter 6 Related Documentation and Resources • Added a new chip variant ESP32-C3FH4AZ; 2022-04-13 v1.2 • Updated Figure ESP32-C3 Functional Block Diagram; • Added the wake up source for Deep-sleep mode in Section 3.7 Power Management. Cont’d on next page Espressif Systems 57 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 Revision History Cont’d from previous page Date Version Release notes • Updated Figure ESP32-C3 Functional Block Diagram to show power modes; • Added CoreMark score in Features; 2021-10-26 v1.1 • Updated Table Pin Description to show default pin functions; • Updated Figure ESP32-C3 Power Scheme and related descriptions; • Added Table SPI Signals; • Added note 3 to Table Recommended Power Supply Characteristics; • Other updates to wording. • Updated power modes; • Updated Section 2.6 Strapping Pins; • Updated some clock names and their frequencies in Section 3.2 System Clocks; • Added clarification about ADC1 and ADC2 in Section 3.3.1 Analog-to-Digital 2021-05-28 v1.0 Converter (ADC); • Updated the default configuration of U0RXD and U0TXD after reset in Table IO MUX; • Updated sampling rate in Table ADC Characteristics; • Updated Table Reliability; • Added the link to recommended PCB land pattern in Chapter 5 Packaging. 2021-04-23 v0.8 Updated Wi-Fi Radio and Bluetooth LE Radio data. • Updated information about USB Serial/JTAG Controller; • Added GPIO2 to Section 2.6 Strapping Pins; • Updated Figure Address Mapping Structure; • Added Table IO MUX and Table Pin Overview in Section 3.4.1 General Pur- 2021-04-07 v0.7 pose Input / Output Interface (GPIO); • Updated information about SPI2 in Section 3.4.2 Serial Peripheral Interface (SPI); • Updated fixed-priority channel scheme in Section 3.4.8 General DMA Controller; • Updated Table Reliability. • Clarified that of the 400 KB SRAM, 16 KB is configured as cache; 2021-01-18 v0.6 • Updated maximum value to standard limit value in Table Wi-Fi RF Transmitter (TX) Specifications in Section 4.8.1 Wi-Fi RF Transmitter (TX) Specifications. Cont’d on next page Espressif Systems 58 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 Revision History Cont’d from previous page Date Version Release notes • Updated information about Wi-Fi; • Added connection between in-package flash ports and chip pins to table notes in Section Pin Definitions; • Updated Figure ESP32-C3 Power Scheme, added Figure Visualization of Timing Parameters for Power-up and Reset and Table Description of Timing Parameters for Power-up and Reset in Section 2.5.2 Power Scheme; 2021-01-13 v0.5 • Added Figure Visualization of Timing Parameters for the Strapping Pins and Table Description of Timing Parameters for the Strapping Pins in Section 2.6 Strapping Pins; • Updated Table Peripheral Pin Configurations in Section 3.11 Peripheral Pin Configurations; • Added Chapter 4 Electrical Characteristics; • Added Chapter 5 Packaging. 2020-11-27 v0.4 Espressif Systems Preliminary version. 59 Submit Documentation Feedback ESP32-C3 Series Datasheet v1.5 Disclaimer and Copyright Notice Information in this document, including URL references, is subject to change without notice. ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES TO ITS AUTHENTICITY AND ACCURACY. NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG. www.espressif.com All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are hereby acknowledged. Copyright © 2023 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.