YTM32B1LE05H0MFMR

ics ro n YTM32B1LE0x Data Sheet Yu n tu M icr oe le ct Support: YTM32B1LE05H0MLHT, YTM32B1LE05H0MLFT, YTM32B1LE05H0MLET, YTM32B1LE05H0MFMR, YTM32B1LE05H0MFMIR, YTM32B1LE04H0MLFT, YTM32B1LE04H0MLET, YTM32B1LE04H0MFMR Document Number: YTM32B1LE0x DS Rev.2.1, 2025/9/1 YUNTU reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Yuntu Microelectronics • • Yu n • tu M • Data Sheet ics ro n ct AEC-Q100 qualified ASIL-B compliant RoHS compliant ARM Cortex-M0+ – Configurable Nested Vectored Interrupt Controller (NVIC) – Single-cycle access to I/O: Up to 50 percent faster than standard I/O, improves reaction time to external events allowing bit manipulation and software protocol emulation – Two-stage pipeline: Reduced number of cycles per instruction (CPI), enabling faster branch instruction and ISR entry, and reducing power consumption – Excellent code density in comparison to 8-bit and 16-bit MCUs: Reduced flash size, system cost and power consumption – 100 percent compatible with ARM Cortex-M0 and a subset ARM Cortex-M3/M4: Reuse existing compilers and debug tools – Simplified architecture: 56 instructions and 17 registers enable easy programming and efficient packaging of 8/16/32-bit data in memory – Linear 4 GB address space removes the need for paging/banking, reducing software complexity – ARM third-party ecosystem support: Software and tools to help minimize development time/cost – Support systick with a 8-bit divider and enablement 4 DMA channels with up to 41 peripheral hardware trigger sources DIVSQRT module with 32-bit integer divide and square root arithmetic operations Memory – Up to 128 KB Program Flash (PFlash) with ECC – Up to 16 KB SRAM with ECC – Single power supply (2.97 ~ 5.5 V) with full functional flash program/erase/read operations Clocks – Fast IRC (FIRC), up to 48 MHz – Fast crystal oscillator (FXOSC), range 4~40 MHz – Slow IRC (SIRC), up to 2 MHz – Slow crystal oscillator (SXOSC), run at 32.768 KHz – Low power oscillator (LPO), run at 750 Hz icr oe • • • • • Power Management – Low-power ARM Cortex-M0+ with excellent energy efficiency – Support four power modes: Active, Sleep, Deepsleep and Standby – Support clock gating for unused modules – Support specific peripherals remain working in low power modes • Mixed-signal Analog – One Analog-to-Digital Converter (ADC) with 12-bit 1Msps sample rate, it has 16 channels and supports temperature sensor – One Analog Comparator (ACMP) with 8-bit DAC • Communications – Up to three Universal Asynchronous Receiver Transmitter (UART) with optional 13-bit break, full duplex Non-return to Zero (NRZ) and LIN extension support – Up to three Serial Port Interface (SPI) with full-duplex or single-wire bidirectional and master or slave mode – Up to two Inter-integrated Circuit (I2C) – One FlexCAN support CAN2.0A/B and FD • Reliability, Safety and Security – Clock Monitor Unit (CMU) – Internal Watchdog (WDG) with independent clock source – Cyclic Redundancy Check (CRC) with 32/16/4-bit polynomial generator • Timers – Up to three Enhanced Timers (eTMR) – Periodic Timer (pTMR) for RTOS task scheduler time base for timer modules – Low Power Timer (lpTMR) – 16-bit Real Time Clock (RTC) • Human-Machine Interface – Up to 58 GPIO pins with interrupt functionality – Non-Maskable Interrupt (NMI) • I/O and package – Support LQFP 64/48/32 – Support QFN 32 • Operating Characteristics – Voltage range: 2.97V ~ 5.5V – Ambient temperature range: -40◦ C ~ 125◦ C le 1 Features YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 1 Yuntu Microelectronics Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ct le icr oe M tu Yu n Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 7 7 7 7 7 7 8 8 8 9 9 9 9 10 11 11 11 11 11 12 12 12 ics Features . . . . . . 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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Core Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 ARM Cortex-M0+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Nested Vector Interrupt Controller (NVIC) . . . . . . . . . 4.1.3 Debug Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 System Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 System Clock Unit (SCU). . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Power Control Unit (PCU). . . . . . . . . . . . . . . . . . . . . . 4.2.3 Reset Control Unit (RCU) . . . . . . . . . . . . . . . . . . . . . . 4.2.4 IP Controller (IPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 Direct Memory Access (DMA). . . . . . . . . . . . . . . . . . . 4.2.6 Trigger Multiplex Unit (TMU) . . . . . . . . . . . . . . . . . . . 4.2.7 Chip Integration Module (CIM) . . . . . . . . . . . . . . . . . . 4.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Embedded Flash Module (EFM) . . . . . . . . . . . . . . . . . . 4.3.2 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . 4.4.2 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . 4.5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 Periodic Timer (pTMR) . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 Low Power Timer (lpTMR) . . . . . . . . . . . . . . . . . . . . . 4.5.3 Enhanced Timer (eTMR) . . . . . . . . . . . . . . . . . . . . . . . 4.5.4 Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Security, Integrity and Safety . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . 4.6.2 Watchdog (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.3 ECC Management Unit (EMU). . . . . . . . . . . . . . . . . . . 4.7 Operation Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1 Divide and Square Root (DIVSQRT). . . . . . . . . . . . . . . 4.8 Communication Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.1 Flexible Controller Area Network (FlexCAN) . . . . . . . . 4.8.2 Universal Asynchronous Receiver/Transmitter (UART). 4.8.3 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . 4.8.4 Inter-Integrated Circuit (I2C). . . . . . . . . . . . . . . . . . . . 4.9 Human Machine Interface . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.1 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . 4.9.2 Port Controller (PCTRL) . . . . . . . . . . . . . . . . . . . . . . . 5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Part Number Information . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Thermal Operating Characteristics . . . . . . . . . . . . . . . 6.1.2 Moisture Handling Ratings . . . . . . . . . . . . . . . . . . . . . 6.1.3 ESD Handling Ratings. . . . . . . . . . . . . . . . . . . . . . . . . 6.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . 6.2.2 Voltage and Current Operating Requirements . . . . . . . ro n 1 2 3 4 i Yuntu Microelectronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 15 16 16 16 16 16 17 18 20 20 20 20 20 20 21 21 22 23 24 24 25 26 26 29 29 29 30 30 30 31 31 32 32 34 37 Yu n tu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ro n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . le 6.2.3 DC Electrical Specifications at 3.3V . . . . . . . . 6.2.4 DC Electrical Specifications at 5.0V . . . . . . . . 6.2.5 Power and Ground Pins . . . . . . . . . . . . . . . . 6.2.6 POR, LVR and LVD Operating Requirements . 6.2.7 Power Mode Transition Operating Behaviors . 6.2.8 Power Consumption . . . . . . . . . . . . . . . . . . . 6.2.9 Power Sequence . . . . . . . . . . . . . . . . . . . . . . 6.2.9.1 Power Up Sequence . . . . . . . . . . . . . . . . 6.2.9.2 MCU Power Supply Ramp Rate . . . . . . . 6.2.9.3 Power Up Requirements . . . . . . . . . . . . 6.2.10 EMC Performance. . . . . . . . . . . . . . . . . . . . 6.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Power Supply Fluctuation Requirements . . . . 6.3.2 Device Clock Specifications. . . . . . . . . . . . . . 6.3.3 I/O Electrical Characteristics . . . . . . . . . . . . . 6.3.3.1 AC Electrical Characteristics . . . . . . . . . 6.4 Peripheral Operating Requirements and Behaviors 6.4.1 FXOSC(4~40MHz) Characteristics . . . . . . . . . 6.4.2 FIRC(48MHz) Characteristics . . . . . . . . . . . . 6.4.3 SXOSC(32.768KHz) Characteristics . . . . . . . . 6.4.4 SIRC(2MHz) Characteristics . . . . . . . . . . . . . 6.4.5 LPO(750Hz) Characteristics. . . . . . . . . . . . . . 6.4.6 ADC Characteristics . . . . . . . . . . . . . . . . . . . 6.4.7 ACMP Characteristics . . . . . . . . . . . . . . . . . . 6.4.8 SPI Characteristics1 . . . . . . . . . . . . . . . . . . . 6.4.9 NVM Specifications . . . . . . . . . . . . . . . . . . . 6.4.9.1 Flash Command Timing Specifications . . 6.4.9.2 Reliability Specifications . . . . . . . . . . . . 6.4.10 Debug Module Electrical . . . . . . . . . . . . . . . 6.4.10.1 SWD Electrical Specifications. . . . . . . . 6.4.10.2 SWD Input Clock Timing. . . . . . . . . . . 6.4.10.3 SWD Output Data Timing . . . . . . . . . . 6.5 Thermal Attributes. . . . . . . . . . . . . . . . . . . . . . . . 7 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 IO Signal Description . . . . . . . . . . . . . . . . . . . . . . 7.2 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 ii Yuntu Microelectronics 2 Overview ics YTM32B1LE0x series provide the highly scalable portfolio of ARM® Cortex® -M0+ MCUs in the automotive industry. With 2.97 ~ 5.5 V supply and focus on exceptional EMC/ESD robustness, YTM32B1LE0x series devices are well suited to a wide range of applications in electrical harsh environments, and is optimized for cost-sensitive applications offering low pin count option. The YTM32B1LE0x series offers a broad range of memory, peripherals and package options. They share common peripherals and pin counts allowing developers to migrate easily within an MCU family or among the MCU families to take advantage of more memory or feature integration. This scalability allows developers to standardize on the YTM32B1LE0x series for their end product platforms, maximizing hardware and software reuse and reducing time-to-market. YTM32B1LE0x System NVIC SCU RCU IPC Flash FIRC 48MHz SRAM TMU DMA icr oe IOPORT Clocks le Serial wire debug interface PCU Memories ct ARM Cortex-M0+ Core Function Safety Analog ro n 3 Block Diagram Timers Communication Human Machine Interfaces Interfaces SIRC 2MHz LPO 750Hz FXOSC 4~40MHz SXOSC 32.768KHz Operations eTMR0(8CH) ADC x1 CRC x1 ACMP x1 M CMU eTMR1(8CH) eTMR2(2CH) lpTMR x1 pTMR x1 EMU RTC x1 GPIO x58 SPI x3 PCTRL DIVSQRT x1 I2C x2 FlexCAN x1 Yu n tu WDG UART x3 Figure 1: YTM32B1LE0x Block Diagram 4 Features The following sections describe the high-level module features for YTM32B1LE0x device. 4.1 Core Modules 4.1.1 ARM Cortex-M0+ • Up to 48 MHz core frequency from 2.97 V to 5.5 V • Supports up to 32 interrupt request sources Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 1 Yuntu Microelectronics • 2 stage pipeline microarchitecture for reduced power consumption and improved architectural performance (cycles per instruction) • Binary compatible instruction set architecture with the Cortex-M0 core • Thumb instruction set combines high code density with 32-bit performance • Serial wire debug (SWD) reduces the number of pins required for debugging • Single cycle 32 bits by 32 bits multiplier • Up to 32 interrupt sources • Supports four priority levels for interrupts with two bits in each IPRn registers • Includes a single non-maskable interrupt ro n 4.1.3 Debug Controller ics 4.1.2 Nested Vector Interrupt Controller (NVIC) • 2-pin serial wire debug (SWD) provides external debugger interface ct 4.2 System Modules 4.2.1 System Clock Unit (SCU) Yu n tu M icr oe le • Fast internal RC oscillator (FIRC) – Up to 48 MHz – Default system boot clock source – Support trim for temperature and process • Slow internal RC oscillator (SIRC) – Run at 2 MHz – Can be selected as system clock source – Always on unless it is forced to be disable in standby mode – Support trim for temperature and process • Fast crystal oscillator (FXOSC) – Support 4~40 MHz crystal – Can be selected as system clock source – Support bypass mode • Slow crystal oscillator (SXOSC) – 32.768 KHz real time oscillator – Can’t be selected as system clock – Provides accurate clock to watchdog(WDG) and real time clock(RTC) • SCU provides glitch free switcher to select system clock source • SCU provides system clock dividers to generate core clock, fast bus clock and slow bus clock • SCU contains 2 CMU blocks – CMU monitors FXOSC and FIRC clock – CMU reference clock is SIRC – CMU can detect frequency out of range, loss of checked clock and loss of reference clock 4.2.2 Power Control Unit (PCU) • Combination of power management blocks including POR, Bandgap, LVD, Brownout, full power regulator and low power regulator • Responsible for sequencing the system enter and exit the Standby mode • Low Voltage Reset(LVR) for all system relevant power domains Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 2 Yuntu Microelectronics 4.2.3 Reset Control Unit (RCU) • • • • Manage the system power up, pin reset, functional reset and fault reset flow Record the reset sources of most recent resets Configurable filter for reset pin Reset pin filter can work in Active, Sleep, Deepsleep and Standby mode 4.2.4 IP Controller (IPC) ro n ics • Peripheral Bus clock enable • IPC clock source selection as follow – FIRC 48 MHz – FXOSC 4~40 MHz – SIRC 2 MHz – SXOSC 32.768 KHz – LPO 750 Hz • IPC clock divide values from 1 to 16 ct 4.2.5 Direct Memory Access (DMA) M icr oe le • All address range data transfer from source to destination • Support separate source/destination data size configuration – Word(32-bit), half word(16-bit), byte(8-bit) transfer size • Support separate source/destination address offset configuration – Address increase/decrease/not change selectable • Up to 4 DMA channels – Fix priority and round-robin arbitration – Support channel to channel link • Software/Hardware trigger • Up to 41 peripheral hardware triggers • Internal data fifo for data transfer • Support update DMA transfer information from system memory after transfer complete tu 4.2.6 Trigger Multiplex Unit (TMU) • Allow software to select the trigger sources for peripherals as trigger sources Yu n 4.2.7 Chip Integration Module (CIM) • • • • • • System function configuration ADC/ACMP trigger synchronize selection Software trigger generate eTMR external clock and fault selection eTMR channel input/output selection Chip and die information 4.3 Memories 4.3.1 Embedded Flash Module (EFM) • 128 KB Program Flash(PFlash) with ECC which supports single error correction (SEC) and double error detection (DED) Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 3 Yuntu Microelectronics • • • • 24 MHz single cycle reads of bytes, aligned halfword (16-bit) and aligned word (32-bit) Automated generation of ECC parity while programming and erasing Optional interrupt on command completion Program and erase operations do not require any special power sources other than the normal VDD supply 4.3.2 On-chip SRAM 4.4 Analog 4.4.1 Analog-to-Digital Converter (ADC) • • ro n Yu n • tu M • • icr oe le • Support 12-bit, 10-bit, 8-bit and 6-bit single-ended configurable resolution Up to 1.0µs for 12-bit resolution conversion time Support DMA and conversion result FIFO with watermark Support up to 17 input channels – 16 channels to measure external analog signals from pad – 1 channel to measure internal temperature sensor Support multiple conversion modes – Single mode: convert one or more channels once a time – Continuous mode: convert one or more channels until stopped by software – Discontinuous mode: convert one channel once a time Support software/hardware trigger for ADC start conversion Support two low power modes – Wait mode: prevent ADC overrun when FIFO is full – Auto off mode: automatic control ADC power off Support watchdog for conversion result monitoring Support interrupt generate – Ready for conversion – End of sampling – End of conversion – End of sequence conversion – Overrun event – Watchdog event Support work and wake up when the whole chip under low power mode ct • • • • ics • 16 KB SRAM with ECC supports single error correction (SEC) and double error detection (DED) 4.4.2 Analog Comparator (ACMP) • • • • • • Up to 8 channels Operational over the entire supply range Inputs may range from rail to rail Programmable hysteresis control Selectable inversion on comparator output Function mode: – Common mode – Sample mode – Window mode – Continuous mode ∗ One-shot mode Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 4 Yuntu Microelectronics ro n ics ∗ Loop mode • Up to 8 channels can be used to execute automatic comparisons • Digitally filtered, filter can be bypassed • Two software selectable performance levels – Shorter propagation delay at the expense of higher power – Low power with longer propagation delay • Functional in low power mode • Support independent DAC input channel to the comparator – Optional DAC reference source: internal or external reference source – 8-bit DAC resolution • Support several interrupts – For common/sample/window mode ∗ Generate interrupt on rising-edge, falling-edge or both edges of the comparator output – For continuous mode ∗ Generate interrupt when the comparison results don’t match expectations • Interrupt can generate without any clock • A comparison event can be selected to trigger DMA transfer ct 4.5 Timer Timers can generate interrupts Four channels of 32-bit timers, each timer has independent timeout periods Ability to stop in debug mode Support chain mode to connect multiple timers to a longer timer icr oe • • • • le 4.5.1 Periodic Timer (pTMR) 4.5.2 Low Power Timer (lpTMR) Yu n tu M • 16-bit time counter or pulse counter with compare – Optional interrupt can generate asynchronous wake-up from any low power mode – Hardware trigger output – Counter supports free-running mode or reset on compare • Configurable clock source for prescaler and glitch filter • Configurable input source for pulse counter – Rising-edge – Falling-edge • Support triggering DMA transfer 4.5.3 Enhanced Timer (eTMR) • There are three eTMRs with below configurations – eTMR0: 8 channels – eTMR1: 8 channels – eTMR2: 2 channels • Bus clock and external clock can be the source clock of each eTMR • Each eTMR contains a 7-bits clock prescaler • Each eTMR contains a 16-bit counter • Each channel can be configured as three modes – Input Capture mode ∗ Support rising edges, falling edges or dual edges Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 5 Yuntu Microelectronics • ics icr oe • • le ct • • • • • • ro n • ∗ Support input filter with a prescaler that can be selected for channels, eTMR0: channel 0-3, eTMR1: channel 0-3, eTMR2: channel 0-1 – Output Compare mode ∗ The output signal can be configured to set, clear or toggle on match point – PWM mode ∗ Independent mode for each channel ∗ Complementary mode for each pair channels: Pair channels: channel 0-1, channel 2-3, channel 4-5, channel 6-7 ∗ Supports independent deadtime insertion for odd and even channel ∗ Fault control mechanism: eTMR0 and eTMR1 support 4 fault inputs for global fault control Each eTMR can be configured to generate triggers – Output triggers on match point – Output pulse-out with adjustable pulse width PWM outputs can be controlled by software Polarity control is available for every channel of each eTMR Mask control is available for every channel of each eTMR Synchronized loading of write buffered registers is available in each eTMR Capture test mode is available in each eTMR eTMR1 can be configured as quadrature decoder, which supports relative position counting or external event counting – Support phase A and phase B input filters – Contains a independent 16-bits counter with a clock prescaler – Support 4 up-down counting modes Support GTB (Global Time Base) for all eTMRs Support several interrupts – Channel interrupt (input capture interrupt and output compare interrupt) – Counter overflow interrupt – Fault interrupt Support DMA tu 32-bit seconds counter with prescaler of 1 Hz Support compensation with RTC clock Lock support of register access for control and alarm register Selectable of 1 Hz to 128 Hz square wave output Support two clock sources Yu n • • • • • M 4.5.4 Real Time Clock (RTC) 4.6 Security, Integrity and Safety 4.6.1 Cyclic Redundancy Check (CRC) • Hardware CRC generator circuit uses – CRC-32 polynomial: X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1 – CRC-16 polynomial: X 16 + X 12 + X 5 + 1 – CRC-4 polynomial: X 4 + X + 1 • Programmable initial seed value • Accept with 8-bit or 16-bit or 32-bit input data size • Option to transpose input data or output data (the CRC result) bitwise • Option for inversion of final CRC result Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 6 Yuntu Microelectronics • 32-bit CPU register programming interface 4.6.2 Watchdog (WDG) • Support regular or window servicing mode • Support reset request or interrupt for first timeout • Support fixed key for dog feeding 4.6.3 ECC Management Unit (EMU) ct ro n ics • Error injection – Error injection provides a method for diagnostic coverage of SRAM. – Error injection uses two-stage enable mechanism. – Error injection provides support for inducing single-bit or multi-bit inversions on read data when accessing SRAM • Error reports – Error report provides information and optionally interrupt notification on SRAM error events associated with ECC (Error Correction Code) and parity – Error report provides count registers which count all correctable error so far le 4.7 Operation Unit 4.7.1 Divide and Square Root (DIVSQRT) M icr oe • Support 32-bit integer divide and square root arithmetic operations – Divide arithmetic support unsigned and signed 32-bit integer – Support selectable action to divide-zero – Square arithmetic support unsigned 32-bit integer • Input data and result are memory-mapped with easy programming model – Support data write to start calculation and data read get result – Support control and status register for calculation 4.8 Communication Interfaces tu 4.8.1 Flexible Controller Area Network (FlexCAN) Yu n • Full implementation of the CAN FD protocol and CAN Specification 2.0 Part B – Standard data frames – Extended data frames – Zero to sixty-four bytes data length – Programmable bit rate – Content-related addressing • Compliant with the ISO 11898-1 standard • Silicon-proven implementation passing ISO 16845-1:2016 CAN conformance tests • Flexible mailboxes configurable to store 0 to 8, 16, 32 or 64 bytes data length • Each mailbox configurable as receive or transmit, all supporting standard and extended messages • Individual Rx Mask registers per mailbox • Full-featured Rx FIFO with storage capacity for up to six frames and automatic internal pointer handling with DMA support • Transmission abort capability • Flexible message buffers, totaling 32 message buffers of 8 bytes data length each, configurable as Rx or Tx Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 7 Yuntu Microelectronics ics ro n ct le • • • • Programmable clock source to the CAN Protocol Engine, either peripheral clock or oscillator clock RAM not used by reception or transmission structures can be used as general purpose RAM space Listen-Only mode capability Programmable Loop-Back mode supporting self-test operation Programmable transmission priority scheme: lowest ID, lowest buffer number or highest priority Time stamp based on 16-bit free-running timer Global network time, synchronized by a specific message Maskable interrupts Independence from the transmission medium (an external transceiver is assumed) Short latency time due to an arbitration scheme for high-priority messages Low-power modes, with programmable wake-up on bus activity Transceiver Delay Compensation feature when transmitting CAN FD messages at faster data rates Remote request frames may be managed automatically or by software CAN bit time settings and configuration bits can only be written in Freeze mode Tx mailbox status (lowest priority buffer or empty buffer) Identifier Acceptance Filter Hit Indicator (IDHIT) register for received frames SYNCH bit available in Error in Status 1 register to indicate that the FlexCAN is synchronous with CAN bus CRC status for transmitted message Rx FIFO Global Mask register Selectable priority between mailboxes and Rx FIFO during matching process Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 128 extended, 256 standard or 512 partial (8-bit) IDs, with up to 32 ID Filter Table elements icr oe • • • • • • • • • • • • • • • • • 4.8.2 Universal Asynchronous Receiver/Transmitter (UART) tu M Support LIN mode Transmit/Receive FIFO Support Transmit/Receive via DMA Baud rate setting 1-bit or 2-bit STOP size 7-bit, 8-bit, 9-bit or 10-bit frame size Transmit/Receive polarity setting Receive data match Line idle, address match wake-up Support transmit/receive line switch, single line mode Hardware flow control support Yu n • • • • • • • • • • • 4.8.3 Serial Peripheral Interface (SPI) • • • • • • Support clock polarity and phase configuration Configurable frame size Transmit/Receive FIFO Support single line mode Support Master and slave mode Support Transmit/Receive via DMA 4.8.4 Inter-Integrated Circuit (I2C) • Support standard, fast and ultra fast mode • Support 7-bit/10-bit address mode with master and slave Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 8 Yuntu Microelectronics • • • • • • • Support SMBUS mode Support multi-master arbitration and synchronization Support Master and slave clock stretching Transmit/Receive FIFO (Master only) Analog and digital filter on both SCL and SDA pins Support Transmit/Receive via DMA I2C1 do not support slave mode 4.9 Human Machine Interface ro n Port Data Input register visible in all digital pin multiplexing modes Port Data Output register with corresponding set/clear/toggle registers Port Data Direction register Port Input Disable register Pin interrupts – Interrupt flag and enable registers for each pin, functional in all digital pin multiplexing modes – Support for interrupt, DMA request or Peripheral Trigger configured per pin – Support for edge sensitive (rising, falling, both) or level sensitive (low, high) configured per pin – Asynchronous wake-up in low power modes – Each pin can be configured for 1 of interrupt, DMA request or trigger output icr oe 4.9.2 Port Controller (PCTRL) le ct • • • • • ics 4.9.1 General Purpose Input/Output (GPIO) M • Individual pull control fields with pull-up, pulldown and pull-disable support • Individual drive strength field supporting high and low drive strength • Individual mux control field supporting analog or pin disabled, GPIO and up to 6 chip-specific digital functions • Individual passive filter field supporting enabling and disabling passive filter for specific input 5 Ordering Information Yu n tu The following chips are available for ordering. Product Table 1: Ordering Information Memory Package IO and ADC channel Communication Part number Flash(KB) SRAM(KB) Pin count Package GPIOs (Normal) ADC channels FlexCAN YTM32B1LE05H0MLHT 128KB 16KB 64 LQFP 58 16 1 YTM32B1LE05H0MLFT 128KB 16KB 48 LQFP 43 13 1 YTM32B1LE05H0MLET 128KB 16KB 32 LQFP 28 12 1 YTM32B1LE05H0MFMR 128KB 16KB 32 QFN 28 9 1 YTM32B1LE05H0MFMIR 128KB 16KB 32 QFN 28 9 1 YTM32B1LE04H0MLFT 64KB 8KB 48 LQFP 43 13 1 YTM32B1LE04H0MLET 64KB 8KB 32 LQFP 28 12 1 YTM32B1LE04H0MFMR 64KB 8KB 32 QFN 28 9 1 Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 9 Yuntu Microelectronics 5.1 Part Number Information YTM 32 B 1 LE 0 5 H0 M LH I T Product Status MCU Type Product Line Generation Level Major Revision Memory Size ics Reserved Ambient Temperature Package ro n Optional Mode Packing The part numbers field description is shown as below. ct Figure 2: Part Numbers Field Values YTM: Qualified YTM Product Status PTM: Prototype 32 MCU Type 32: 32-bit B: General D: Dashboard P: Powertrain B Product Line V: Vision N: Network Z: High voltage, integrity 1 Generation 1st generation product Hx: High end Lx Level Mx: Middle end Lx: Low end 0 Major Revision 1st revision 1 2 3 H 2M 4M 6M 5 Memory Size M 64K 128K 256K L 8K 16K 32K H0 Reserved Reserved C: -40◦ C ~85◦ C V: -40◦ C ~105◦ C M Ambient Temperature M: -40◦ C ~125◦ C W: -40◦ C ~150◦ C Pin Counts LQFP QFN BGA 32 LE FM 48 LF - Yu n tu M icr oe Field Description le Table 2: Part Number Field Description Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 4 8M 512K 64K 5 1M 128K - 10 Yuntu Microelectronics Table 2: Part Number Field Description LH Package I Optional Mode T1 Packing Values 64 LH 100 LL 144 LQ 176 LU 257 289 I: ISELED T: Trays/Tubes R: Tape and Reel - MH MM MQ - - ics Field Description ro n 1. The chip mark will not contain packing information 6 Electrical Characteristics ct 6.1 Ratings Parameter Value icr oe Symbol le 6.1.1 Thermal Operating Characteristics Min. Typ. Max. Unit TA M−Grade Part Ambient temperature under bias -40 – 125 ◦C TJ M−Grade Part Junction temperature under bias -40 – 135 ◦C M 6.1.2 Moisture Handling Ratings Symbol Min. Max. Unit Notes Moisture sensitivity level 3 3 – 1 tu MSL Description Yu n 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices 6.1.3 ESD Handling Ratings Symbol VHBM Description Min. Max. Unit Notes -4000 4000 V 1 All pins except the corner pins -500 500 V 2 Corner pins only -750 750 V Latch-up current at ambient temperature of 125 °C -100 100 mA Electrostatic discharge voltage, human body model Electrostatic discharge voltage, charged-device model VCDM ILAT Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 3 11 Yuntu Microelectronics Table 5 continued from previous page Symbol Description Latch-up current at ambient temperature of 25 °C Min. Max. Unit -200 200 mA Notes 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components ics 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 6.2 DC Characteristics Symbol ro n 6.2.1 Absolute Maximum Ratings Description Supply voltage IVDD Maximum current into VDD VIO Digital/Analog IO Input voltage IO Instantaneous maximum current of single pin -0.3 5.81 V – 70 mA -0.3 VDD + 0.3 V -25 25 mA VDD - 0.3 VDD + 0.3 V le Analog supply voltage Unit Notes icr oe VDDA Max. ct VDD Min. 1. 60 seconds lifetime - No restrictions i.e. the part is not held in reset and can switch. 10 hours lifetime - The part is held in reset by an external circuit i.e. the part cannot switch. M NOTE: tu • The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. • The device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Yu n 6.2.2 Voltage and Current Operating Requirements Symbol Description Min. Max. Unit Notes VDD Supply voltage 2.97 5.5 V VDDA Analog supply voltage 2.97 VDD V VREFH Reference voltage 2.97 VDDA V -0.1 0.1 V VDD − VDDA VDD to VDDA differential voltage IICIO Continuous DC input current (positive / negative) that can be injected into an I/O pin -1 1 mA IICcont Contiguous pin DC injection current — regional limit, includes sum of positive rejection currents of 16 contiguous pins – 15 mA Tramp MCU supply ramp rate Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 5 V/100ms 100 V/ms – 12 Yuntu Microelectronics 1. All pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VSS – 0.3V or greater than VDD + 0.3V, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VSS –0.3V–VIN )/ |IICIO |. The positive injection current limiting resistor is calculated as R = [VIN –(VDD + 0.3V)]/ |IICIO |. The actual resistor values should be an order of magnitude higher to tolerate transient voltages. 6.2.3 DC Electrical Specifications at 3.3V Value Parameter Unit Min. Typ. Max. VDD I/O supply voltage 2.97 3.3 4.0 Vih Input buffer high voltage 0.7 * VDD – VDD + 0.3 Vil Input buffer low voltage VSS - 0.3 – 0.3 * VDD Vhys Input buffer hysteresis 0.1 * VDD – 0.3 * VDD V Ioh Normal drive I/O current source capability measured when pad = (VDD - 0.8V) 5 10 – mA Iol Normal drive I/O current sink capability measured when pad = 0.8V 5 Ioh High drive I/O current source capability measured when pad = (VDD - 0.8V) Iol High drive I/O current sink capability measured when pad = 0.8V ro n ct mA 12 20 – mA Hi-Z (Off state) leakage current (per pin) @25◦ C – 50 500 nA Hi-Z (Off state) leakage current (per pin) @125◦ C – – 500 nA VDD - 0.8 – VDD V Normal drive pad (2.97V ≤ VDD ≤ 4.0V, IOL = -2.8mA) VSS – 0.8 V Output low current total for all ports – – 50 mA icr oe M 10 le – Output high voltage Normal drive pad (2.97V ≤ VDD ≤ 4.0V, IOH = -2.8mA) tu IOLT V 20 Output low voltage Yu n VOL V mA Ileak VOH V – 12 Notes ics Symbol Input leakage current (per pin) for full temperature range IIN Normal pins – 0.002 0.5 µA High Drive pins – 0.005 0.5 µA RPU Internal pull-up resistors 20 – 100 kΩ RPD Internal pull-down resistors 20 – 105 kΩ 6.2.4 DC Electrical Specifications at 5.0V Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 13 Yuntu Microelectronics Symbol Value Parameter Unit Min. Typ. Max. I/O supply voltage 4 5 5.5 V Vih Input buffer high voltage 0.7 * VDD – VDD + 0.3 V Vil Input buffer low voltage VSS - 0.3 – 0.3 * VDD V Vhys Input buffer hysteresis 0.1 * VDD – 0.3 * VDD V Ioh Normal drive I/O current source capability measured when pad = (VDD - 0.8V) 10 20 – mA Iol Normal drive I/O current sink capability measured when pad = 0.8V 10 20 – Ioh High drive I/O current source capability measured when pad = (VDD - 0.8V) 20 30 Iol High drive I/O current sink capability measured when pad = 0.8V 20 30 Hi-Z (Off state) leakage current (per pin) @25◦ C – ro n – mA ct mA 500 nA VDD - 0.8 – VDD V Normal drive pad (4V ≤ VDD ≤ 5.5V, IOL = -2.8mA) VSS – 0.8 V Output low current total for all ports – – 50 mA – icr oe Output high voltage 380 le – Normal drive pad (4V ≤ VDD ≤ 5.5V, IOH = -2.8mA) Output low voltage M IOLT – nA Hi-Z (Off state) leakage current (per pin) @125◦ C VOL mA 500 Ileak VOH ics VDD Notes Input leakage current (per pin) for full temperature range Normal pins – 0.002 0.5 µA High drive pins – 0.005 0.5 µA RPU Internal pull-up resistors 20 – 70 kΩ RPD Internal pull-down resistors 15 – 70 kΩ Yu n tu IIN Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 14 Yuntu Microelectronics 6.2.5 Power and Ground Pins VSS Package C DEC1 C DEC0 C DEC0 VDDA 48 LQFP VSS Package VDDA / VREFH 32 LQFP icr oe CREF C DEC0 C DEC1 VDD le ct VSS C DEC1 VDD ics VSS VDD C DEC1 C DEC1 64 LQFP ro n CREF C DEC1 VREFH VDD C DEC0 VDDA C DEC0 C DEC1 VDD VREFL Package VSS Package C DEC1 C DEC0 C DEC1 tu VDD 32 QFN C Yu n VDD 0CED M VSS VSS Figure 3: Pinout Decoupling Symbol Description Min. Typ. Max. Unit CREF 1,2,3 ADC reference high decoupling capacitance 50 100 200 nF CDEC0 2,3,4 Recommended decoupling capacitance for VDD 1 2.2 10 µF CDEC1 2,3,4 Recommended bypass decoupling capacitance for VDD 50 100 200 nF 1. For improved performance, it is recommended to use 2.2 µF, 0.1 µF and 1nF capacitors in parallel. Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 15 Yuntu Microelectronics 2. All decoupling capacitors should be placed as close as possible to the corresponding supply and ground pins. 3. All decoupling capacitors must be low ESR ceramic capacitors(for example X7R type). 4. The requirement and value of CDEC will be decided by the device application requirement. 6.2.6 POR, LVR and LVD Operating Requirements Description Min. Typ. Max. Unit VPOR Rising and falling VDD POR detect voltage 2.3 2.5 2.7 V VLVD Falling low-voltage threshold(LVDCFG=4) 2.5 2.6 2.7 V Falling low-voltage threshold(LVDCFG=10) 3.8 4.2 4.5 V LVD hysteresis(LVD5VHYS=01b) -2 – 2 % LVD hysteresis(LVD5VHYS=10b) -4.2 – 4.2 % LVD hysteresis(LVD5VHYS=11b) -8.4 – 8.4 % ro n VLVD_HYST Notes ics Symbol SLEEP -> ACTIVE FIRC DEEPSLEEP -> ACTIVE STANDBY -> ACTIVE TPOR Core, bus frequency Min. Typ. Max. 48MHz, 24MHz – 1µs – le System clock icr oe Description ct 6.2.7 Power Mode Transition Operating Behaviors FIRC 48MHz, 24MHz – 5µs – FIRC 48MHz, 24MHz – 40µs – FIRC(reset value) 48MHz, 24MHz – 250µs – M 6.2.8 Power Consumption Symbol Clock configuration ACTIVE IDD_ACTIVE FIRC tu Mode IDD_SLEEP Yu n SLEEP DEEPSLEEP IDD_DEEPSLEEP STANDBY IDD_STANDBY – FIRC FIRC Description Running while(1) loop in flash, all peripheral clock enabled. core @48MHz, bus @24MHz VDD =5V Temperature Min Typ Max Units ≤ 25 °C – 9.0 14.5 mA 125 °C – 9.0 14.5 mA ≤ 25 °C – 3.9 5.0 mA 125 °C – 4.0 5.0 mA Deepsleep mode current, VDD =5V SIRC=1, SXOSC=0 ≤ 25 °C – 100 150 µA 125 °C – 130 250 µA Standby mode current, VDD =5V SIRC=0, SXOSC=0 ≤ 25 °C – 4.0 20 µA 125 °C – 50 100 µA Sleep mode current, VDD =5V 6.2.9 Power Sequence 6.2.9.1 Power Up Sequence Hardwares must follow sequence below to ensure that the chip is powered up properly. Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 16 Yuntu Microelectronics 1. VDD must be powered up first. 2. VDDA must be powered up later than or at the same time as VDD. 3. VREFH must be powered up later than or at the same time as VDDA. T1 ics T1 > 0 T2 > 0 T2 ro n VREFH le 6.2.9.2 MCU Power Supply Ramp Rate ct Figure 4: Power Sequence Yu n tu M icr oe During the power-up sequence of MCU, it is critical that the power supply maintains a ramp-rate within the specified range, starting from VDD_OFF at 0.1V and rising to the MCU’s operational voltage level (VDD ). Failure to comply with this specification may result in unintended behavior, operational stagnation or even damage to the MCU. Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 17 Yuntu Microelectronics Tramp(Max.) Tramp(Min.) VDD CORRECT safe range VDD_OFF residual and/or low voltage - out of range NOT CORRECT ro n VDD_OFF VDD le VDD_OFF NOT CORRECT ct non strictly rising ramp - out of range ics VDD icr oe VDD step ramp - out of range NOT CORRECT VDD_OFF M Figure 5: Power Supply Ramp Rate tu 6.2.9.3 Power Up Requirements Yu n It is necessary to ensure that VDD meets the following timing during the power-up process of YTM32B1LE0x. Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 18 Yuntu Microelectronics A B A B V4 ics V3 V1 T2 T3 T4 ct T1 ro n V2 A : There is no guarantee of proper functionality when the MCU is in uncertain status. icr oe le B : The MCU operates normally. Figure 6: Power Up Requirements Name V1 Restart threshold voltage V2 Minimum MCU operating voltage 5.5 T1 Power up time T2 Power down time Data Sheet 2.5 Upper voltage limit of Maximum operating voltage for normal MCU operation MCU operating normally and interaction with peripherals Name T4 The MCU starts working when the power supply reaches V2. 2.97 Symbol T3 0.2 Lower voltage limit of Minimum operating voltage for normal MCU operation MCU operating normally and interaction with peripherals. Yu n V4 Unit (V) When restarting the MCU, VDD should keep below V1 for a period of T3. tu V3 Description M Symbol Description Rising time of MCU VDD from 0V to V3 10 µs < T1 < 50ms Drop time of MCU VDD from V3 to V1 10 µs < T2 < 500ms during the MCU restart/power down process Restart threshold voltage Minimum duration of MCU VDD below V1, retain time when restarting MCU Restart power up time Requirement Rising time of MCU VDD normal operation from V1 to V3 YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 T3 > 100 µs 10 µs < T4 < 50ms 19 Yuntu Microelectronics NOTE: The power-up process needs to be restarted if a VDD voltage drop occurs during the T1~T4 power-up process before the VDD voltage reaches the V2 voltage. Restarting the power-up of MCU needs to ensure that the voltage of VDD continues to drop below V1 and remains there for T3 time. 6.2.10 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components, and MCU software operation play a significant role in the EMC performance. ics 6.3 AC Characteristics 6.3.1 Power Supply Fluctuation Requirements ct ro n 1. The power supply fluctuation must be maintained within ± 10% of the power supply voltage, and the fluctuation frequency should not exceed 100 KHz. 2. The maximum power supply fluctuation should not exceed ± 20% of the power supply voltage, and in this case, the fluctuation frequency should be less than 30 KHz. 3. Power supply fluctuations exceeding the above requirements may cause chip abnormalities and require a power-up process according to the requirements outlined in Power Up Requirements. Description Min. Max. Unit fcore System and core clock – 48 MHz fbus Bus clock – 24 MHz icr oe Symbol le 6.3.2 Device Clock Specifications Notes M 6.3.3 I/O Electrical Characteristics 6.3.3.1 AC Electrical Characteristics Yu n tu Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and the rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal Low High 80% Midpoint1 50% 20% Fall Time VIL The midpoint is VIL ( VIH Rise Time VIL) 2 Figure 7: Input Signal Measurement Reference All digital I/O switching characteristics, unless otherwise specified, assume that the output pins have the following characteristics. • CL = 30pF loads Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 20 Yuntu Microelectronics • Normal drive strength 6.4 Peripheral Operating Requirements and Behaviors 6.4.1 FXOSC(4~40MHz) Characteristics The following diagram is Fast Crystal OSC circuit. MCU C1 ct C2 ics EXTAL ro n XTAL Min. Typ. Max. Unit 2.97 – 5.5 V – 2.0 – mA 4 – 40 MHz 0.7*VDD – VDD V Input high voltage – EXTAL pin in external clock mode, VDD =3.3V 0.7*VDD – VDD V Input low voltage – EXTAL pin in external clock mode, VDD =5V VSS – 0.3*VDD V Input low voltage – EXTAL pin in external clock mode, VDD =3.3V VSS – 0.3*VDD V FXOSC startup time (40MHz oscillator) – 0.5 3.5 ms Duty of FXOSC (40MHz oscillator) 40 50 60 % C1 Load capacitance – – – pF C2 Load capacitance – – – pF RF FXOSC internal feedback resistor 400 500 700 kΩ VPP Peak-to-peak amplitude of oscillation (40MHz oscillator) 1.2 2.25 VDD V VDD IDDOSC Description Supply voltage FXOSC oscillator icr oe Symbol le Figure 8: FXOSC Diagram Oscillator frequency VIH Input high voltage – EXTAL pin in external clock mode, VDD =5V Yu n VIL tu M FOSC TFXOSCSU DFXOSC Notes 1 1. Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as: gm_crit=4 * (ESR + RS ) * (2πF)2 * (C0 + CL )2 where: • gmXOSC is the transcondutance of the internal oscillator circuit Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 21 Yuntu Microelectronics ESR is the equivalent series resistance of the external crystal RS is the series resistance connected between XTAL pin and external crystal for current limitation F is the external crystal oscillation frequency C0 is the shunt capacitance of the external crystal CL is the external crystal total load capacitance. CL = CS + [ C1 * C2 / (C1 + C2 ) ] CS is stray or parasitic capacitance on the pin due to any PCB traces C1 , C2 external load capacitances on EXTAL and XTAL pins. le ct ro n ics • • • • • • • icr oe The internal circuitry of the chip utilizes an ld current source as the load for the amplifier circuit, with an NMOS transistor serving as the amplifying transistor. When the gain (Gm) of the amplifying transistor is greater than the intrinsic gain (Gmcrit) of the external crystal oscillator, theoretically, the crystal oscillator will start to oscillate. Generally, it is required that Gm>5*Gmcrit. Rfb provides the DC bias point for the input terminal of the amplifying transistor. Figure 9: Block Diagram of Crystal Oscillator Circuit M Table 18: Startup Time - Gain Selection for Gmxosc of 40MHz Crystal Oscillator Circuits (Simulation) Yu n tu Gain Setting 0 1 2 3 4 5 6 7 Gm (at startup) Min. Typ. Max. 0 1.4 2.2 3.6 2.8 4.5 7.2 4.2 6.8 10.8 4.9 7.9 12.6 6.2 10.2 16.2 7.6 12.5 19.9 9.1 14.7 23.5 Unit mS mS mS mS mS mS mS mS 6.4.2 FIRC(48MHz) Characteristics Symbol Description Min. Typ. Max. Unit FFIRC Fast internal reference frequency – 48 – MHz Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 Notes 22 Yuntu Microelectronics Table 19 continued from previous page Description Min. Typ. Max. Unit ACCFIRC FIRC frequency accuracy, factory trimmed, 25 °C -1.0 – 1.0 % FIRC frequence accuracy, factory trimmed, -40◦ C – 125◦ C -1.5 – 1.5 % IFIRC FIRC operating current – 250 – µA TStartup Startup time – – 20 µs 6.4.3 SXOSC(32.768KHz) Characteristics Slow crystal oscillator frequency IDDOSC SXOSC oscillator Tstartup SXOSC startup time (32.768KHz oscillator) DSXOSC Duty of SXOSC (32.768KHz oscillator) Typ. Max. Unit 30 32.768 35 KHz – 4 – µA – – 1 s ct FSXOSC Min. ro n Description 40 50 60 % – – – pF le Symbol Notes ics Symbol – – – pF 6 8 11 MΩ 0.94 1.2 VDD V Load capacitance C2 Load capacitance RF SXOSC internal feedback resistor VPP Peak-to-peak amplitude of oscillation (32.768KHz oscillator) icr oe C1 Notes 1 1. Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as: gm_crit=4 * (ESR + RS ) * (2πF)2 * (C0 + CL )2 tu gmXOSC is the transcondutance of the internal oscillator circuit. gmXOSC > 10 µS ESR is the equivalent series resistance of the external crystal RS is the series resistance connected between XTAL pin and external crystal for current limitation F is the external crystal oscillation frequency C0 is the shunt capacitance of the external crystal CL is the external crystal total load capacitance. CL = CS + [ C1 * C2 / (C1 + C2 ) ] CS is stray or parasitic capacitance on the pin due to any PCB traces C1 , C2 external load capacitances on EXTAL and XTAL pins Yu n • • • • • • • • M where: Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 23 ics Yuntu Microelectronics ro n The internal circuitry of the chip utilizes an ld current source as the load for the amplifier circuit, with an NMOS transistor serving as the amplifying transistor. When the gain (Gm) of the amplifying transistor is greater than the intrinsic gain (Gmcrit) of the external crystal oscillator, theoretically, the crystal oscillator will start to oscillate. Generally, it is required that Gm>5*Gmcrit. Rfb provides the DC bias point for the input terminal of the amplifying transistor. Description Min. Typ. Max. Unit FSIRC Slow internal reference frequency – 2 – MHz ACCSIRC SIRC frequency accuracy, factory trimmed, 25 °C -3.0 – 3.0 % SIRC frequency accuracy, factory trimmed, 0 °C – 85 °C -4.0 – 4.0 % SIRC frequence accuracy, factory trimmed, −40 °C – 125 °C -5.0 – 5.0 % SIRC operating current – 23 – µA – 10 50 µs M icr oe Symbol le 6.4.4 SIRC(2MHz) Characteristics ct Figure 10: Block Diagram of Crystal Oscillator Circuit tu ISIRC Startup time Yu n TStartup Notes 6.4.5 LPO(750Hz) Characteristics Symbol Description Min. Typ. Max. Unit FLPO Low power oscillator frequency 300 750 2000 Hz Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 Notes 24 Yuntu Microelectronics 6.4.6 ADC Characteristics INTERNAL CIRCUIT SCHEME EXTERNAL CIRCUIT VDD R SMP R IN CP CS ics CEXT VA Description VDDA Analog supply voltage IVDDA Analog supply current ∆VDDA Test condition Min. Typ. Max. Unit Notes 5.0 5.5 V – 2 – mA VDD - VDDA 0 – 100 mV VREFH Reference voltage 2.97 – VDDA V IREFH Reference current – – 800 µA VIN Input voltage 0 – VREFH V RSMP Sampling switch impedance – – 1.5 kΩ CEXT External capacitance 50 – – nF CP Pin capacitance – 6 – pF CS Sampling capacitance – 6 7 pF tu icr oe le 2.97 M Symbol ct Figure 11: ADC Circuit ro n Note: RIN is the internal resistance of signal source. Test condition1 Min. Typ. Max. Unit Notes Description TSTARTUP Analog startup time 5 – – µs TSAMPLE Sampling time 200 – 2000 ns 500 – 2000 ns Yu n Symbol Tsample_TS Tempsensor sampling time – 1. These parameters of this table can be configured by register, please refer to Reference Manual for details. Symbol Description Test condition DNL Differential nonlinear 12-bit resolution – ±1.0 – LSB INL Integer nonlinear 12-bit resolution – ±2.0 – LSB Data Sheet Min. Typ. Max. Unit Notes YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 25 Yuntu Microelectronics Table 25 continued from previous page Symbol Description ACCTS Temperature sensor accuracy Min. Typ. Max. Unit Notes -10 Slope of temperature ADC sampling and voltage curve frequncy @ 500kHz K1 FADC Test condition ◦C 616.9 ADC conversion clock 2 16 2. ADC conversion clock = ADC function clock / [(ipc_divider +1 ) * (adc_clock_div +1)] VACMP 1 Analog supply voltage IACMP Analog supply current VINOFFSET Analog input offset voltage VIN Analog input voltage VHYST0 Analog comparator hysteresis 0 VHYST1 MHz 2 ro n Description Test condition Min. Typ. Max. Unit Notes 2.97 5.0 ct Symbol /V ics 1. T = C - K*V, see Reference Manual for details. 6.4.7 ACMP Characteristics ◦C 10 5.5 V 20 40 µA -10 – 10 mV VSS – VDD V 12 20 45 mV Analog comparator hysteresis 1 24 40 85 mV VHYST2 Analog comparator hysteresis 2 36 60 130 mV DACDNL Differential nonlinear – ±1 – LSB M icr oe le – 1. ACMP connects to VDD. tu 6.4.8 SPI Characteristics1 Yu n Num. Symbol ffunc 1 2 fop Description Conditions Min. Max. Unit Functional frequency Slave – 24 MHz Frequency of operation Master – 24 MHz Master Loopback4 – 24 MHz Slave – 12 MHz Master – 12 MHz – 12 MHz Slave 83.3 – ns Master 83.3 – ns 83.3 – ns Slave – – ns Master (PCSSCK+1) * tdelay 3 - 22 – ns Master Loopback4 (PCSSCK+1) * tdelay 3 - 22 – ns – ns Master 2 tSCK SCK period Master 3 4 Data Sheet tPCSSCK tSCKPCS 5 6 PCS to SCK delay After SCK delay Loopback4 Loopback4 Slave – YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 26 Yuntu Microelectronics Table 27 continued from previous page Conditions Min. Max. Unit 3 – ns 3 (SCKPCS+1) * tdelay - 22 – ns Slave tSCK /2 - 1 tSCK /2 + 1 ns Master tSCK /2 - 1 tSCK /2 + 1 ns Master Master 5 tWSCK 7 Clock (SCK) high or low time Master 6 tsetup Data setup time (inputs) tholdin Data hold time (inputs) tSCK /2 - 1 tSCK /2 + 1 ns 7 – ns Master 27 – ns 5 – ns Slave 0 – ns Master 0 – ns – ns tvalid Data valid (after SCK edge) Loopback4 Loopback4 Slave – 33 ns – 9 ns – 9 ns 0 – ns 0 – ns 0 – ns – 2 ns – 2 ns Master Master Loopback4 9 tholdout Data hold time (outputs) Slave Master tRI/FI Rise/Fall time input ct Master 10 Loopback4 Slave Master Master tRO/FO Rise/Fall time output Loopback4 – 2 ns Slave – 5 ns Master – 5 ns Master Loopback4 – 5 ns icr oe 11 2 le Master 8 Loopback4 Slave Master 7 (SCKPCS+1) * tdelay - 22 Loopback4 ics Description ro n Num. Symbol 1. The trace length for the SCK pad should be kept as short as possible when used in Master loopback mode, and it does not support off-board communication. M 2. ffunc = SPI functional clock, which is generated from IPC. 3. tdelay = (1/fop ) * 2TXCFG[PRESCALE] . 4. Master Loopback mode - In this mode SCK clock is delayed for sampling the input data which is enabled by setting SPI_CTRL[SPDEN] bit as 1. tu 5. Set the PCSSCK configuration bit as 0, for a minimum of 1 delay cycle of SPI delay clock, where PCSSCK ranges from 0 to 255. 6. Set the SCKPCS configuration bit as 0, for a minimum of 1 delay cycle of SPI delay clock, where SCKPCS ranges from 0 to 255. Yu n 7. While selecting odd dividers, ensure Duty Cycle is meeting this parameter. Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 27 Yuntu Microelectronics PCS1 (OUTPUT) 3 2 SCK (CPOL=0) (OUTPUT) 10 11 10 11 4 5 5 SCK (CPOL=1) (OUTPUT) MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 LSB IN 8 MOSI (OUTPUT) MSB OUT2 9 BIT 6 . . . 1 LSB OUT ro n 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. ics 6 ct Figure 12: SPI Master Mode Timing (CHPA=0) PCS1 2 10 3 5 SCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 5 10 4 11 7 MSB IN2 BIT 6 . . . 1 LSB IN 9 8 PORT DATA MASTER MSB OUT2 M MOSI (OUTPUT) 11 icr oe SCK (CPOL=0) (OUTPUT) le (OUTPUT) BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Yu n tu Figure 13: SPI Master Mode Timing (CHPA=1) Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 28 Yuntu Microelectronics ro n ics PCS Figure 14: SPI Slave Mode Timing (CHPA=0) ct PCS 2 5 10 4 11 icr oe 5 11 le 10 3 9 8 BIT 6 . . . 1 6 MOSI 7 BIT 6 . . . 1 LSB IN M MSB IN tu Figure 15: SPI Slave Mode Timing (CHPA=1) Yu n 6.4.9 NVM Specifications 6.4.9.1 Flash Command Timing Specifications Symbol Description Min. Typ. Max. Unit Tpgm Program execution time 46 50 53.5 µs Terase Erase execution time 4.0 4.5 5.0 ms Tchip_erase Chip erase execution time 30 35 40 ms Notes 6.4.9.2 Reliability Specifications Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 29 Yuntu Microelectronics Symbol Description Min. Max. Unit tnvmretp Data retention 20 – years tnvmcycp Cycling endurance 100,000 – cycles Notes 6.4.10 Debug Module Electrical Table 30: SWD Full Voltage Range Electricals Symbol Description SWD_CLK frequency T2 SWD_CLK cycle period T3 SWD_CLK pulse width T4 SWD_CLK rise and fall time T5 SWD_CLK input data setup time to SWD_CLK rise edge T6 SWD_CLK input data hold time after SWD_CLK rise edge T7 SWD_CLK high to SWD_DIO output data valid T8 SWD_CLK high to SWD_DIO output data Hi-Z Min. Typ. Max. Unit – – 20 MHz ro n T1 ics 6.4.10.1 SWD Electrical Specifications – – ns 20 – – ns – – 3 ns 8 – – ns 1.5 – – ns – – 35 ns 5 – – ns icr oe le ct 50 6.4.10.2 SWD Input Clock Timing T2 T3 T4 T4 Figure 16: SWD Clock Timing Yu n tu M T3 SWD_CLK Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 30 Yuntu Microelectronics 6.4.10.3 SWD Output Data Timing SWD_CLK T5 SWD_DIO T6 Input data valid SWD_DIO Output data valid ro n T8 ics T7 SWD_DIO le 6.5 Thermal Attributes ct Figure 17: SWD Data Timing icr oe Table 31: Thermal Characteristics Package Family Unit RJC RJB LQFP32L 89 18 35 ◦ C/W LQFP48L 78 16 32 ◦ C/W LQFP64L 65 13 30 ◦ C/W QFN32L 41 14 16 ◦ C/W tu QFN Thermal Resistance RJA M LQFP Package Type Yu n NOTE: Based on environmental simulation per JEDEC standards, the PCB is a JEDEC-compliant 2S2P board. Data in this table is for reference only. Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 31 Yuntu Microelectronics 7 Pinouts 7.1 IO Signal Description The pinouts signal description is as follows: Table 32: Pinmux Table ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 1 1 - PTD_1 - PTD_1 eTMR0_CH3 SPI1_SIN - I2C1_SCL - TMU_OUT2 2 2 2 - PTD_0 - PTD_0 eTMR0_CH2 SPI1_SCK - I2C1_SDA - TMU_OUT1 3 - - - PTE_11 - PTE_11 SPI2_PCS0 lpTMR0_ALT1 - - - TMU_OUT5 4 - - - PTE_10 - PTE_10 CLKOUT SPI2_PCS1 - - - TMU_OUT4 5 3 - 1 PTE_5 - PTE_5 TCLK_IN2 - eTMR1_CH1 CAN0_TX - - 6 4 - 2 PTE_4 - PTE_4 CLKOUT - eTMR1_CH0 CAN0_RX - - 7 5 3 3 VDD VDD - - - - - - - 8 6 4 - VDDA VDDA - - - - - - - 9 - - - VREFH VREFH - - - - - - - - - 5 - VREFL VREFL - - - - - - - 10 7 6 4 VSS VSS - - - - 11 8 7 5 PTB_7 EXTAL PTB_7 I2C0_SCL 12 9 8 6 PTB_6 XTAL PTB_6 I2C0_SDA 13 - - - PTE_3 - 14 10 - 7 15 11 - 8 16 12 - - PTE_9 17 13 - 9 PTE_8 ACMP0_IN3 PTE_8 eTMR0_CH6 18 14 9 10 PTB_5 19 15 10 11 PTB_4 20 16 11 12 21 17 12 22 - 23 - 24 ro n ct - - UART2_TX - - TMU_OUT2 - UART2_RX - - TMU_OUT1 icr oe le - - SPI1_SIN - - TMU_IN6 ACMP0_OUT PTD_16 EXTAL32K PTD_16 eTMR0_CH1 - SPI0_SIN ACMP0_ACTIVE - - PTD_15 XTAL32K PTD_15 eTMR0_CH0 - SPI0_SCK - - - SPI1_SCK - - - - - - - - - SPI0_PCS1 SPI0_PCS0 CLKOUT TMU_IN0 - PTB_4 eTMR0_CH4 SPI0_SOUT - - TMU_IN1 - PTC_3 ADC0_SE11 PTC_3 eTMR0_CH3 ACMP0_IN4 CAN0_TX UART0_TX - - - 13 PTC_2 ADC0_SE10 PTC_2 eTMR0_CH2 ACMP0_IN5 CAN0_RX UART0_RX - - - - - PTD_7 ACMP0_IN6 PTD_7 UART2_TX eTMR0_CH3 - - - - - - PTD_6 ACMP0_IN7 PTD_6 UART2_RX eTMR0_CH2 - - - - 18 - 14 PTD_5 lpTMR0_ALT2 - - TMU_IN7 - 25 19 13 - PTC_1 ADC0_SE9 PTC_1 eTMR0_CH1 SPI2_SOUT SPI2_SIN - eTMR1_CH7 - 26 - 14 - PTC_0 ADC0_SE8 PTC_0 eTMR0_CH0 SPI2_SIN SPI2_PCS1 - eTMR1_CH6 - 27 - - - PTC_17 ADC0_SE15 PTC_17 eTMR1_FLT3 - SPI2_PCS2 - - - 28 20 - - PTC_16 ADC0_SE14 PTC_16 eTMR1_FLT2 - SPI2_SCK - - - 29 21 - - PTC_15 ADC0_SE13 PTC_15 eTMR1_CH3 SPI2_SCK SPI2_SOUT - TMU_IN8 - 30 22 - - PTC_14 ADC0_SE12 PTC_14 eTMR1_CH2 - SPI2_PCS0 - TMU_IN9 - 31 23 15 15 PTB_3 ADC0_SE7 PTB_3 eTMR1_CH1 SPI0_SIN eTMR1_QD_PHA - TMU_IN2 - 32 24 16 16 PTB_2 ADC0_SE6 PTB_2 eTMR1_CH0 SPI0_SCK eTMR1_QD_PHB - TMU_IN3 - 33 25 17 17 PTB_1 ADC0_SE5 PTB_1 UART0_TX SPI0_SOUT TCLK_IN0 CAN0_TX - - 34 26 18 18 PTB_0 ADC0_SE4 PTB_0 UART0_RX SPI0_PCS0 lpTMR0_ALT3 CAN0_RX - - 35 27 - - PTC_9 eTMR1_FLT1 - - - - - PTE_9 eTMR0_CH7 PTB_5 eTMR0_CH5 M Yu n Data Sheet - PTE_3 eTMR0_FLT0 ics 1 tu 64 48 32 32 NAME LQFP LQFP LQFP QFN - - - PTD_5 - PTC_9 UART1_TX YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 32 Yuntu Microelectronics 64 48 32 32 NAME LQFP LQFP LQFP QFN ALT0 ALT2 PTC_8 UART1_RX ALT3 ALT4 ALT5 ALT6 ALT7 eTMR1_FLT0 - - - - 36 28 - - PTC_8 37 29 19 19 PTA_7 ADC0_SE3 PTA_7 eTMR0_FLT2 - RTC_CLKIN - - - 38 - 20 - PTA_6 ADC0_SE2 PTA_6 eTMR0_FLT1 SPI1_PCS1 - - - - 39 - - - PTE_7 - SPI1_PCS2 - - - - 40 30 - 20 VSS VSS 41 31 - 21 VDD VDD 42 32 - - PTB_13 - PTB_13 eTMR0_CH1 43 - - - PTB_12 - 44 - - - PTD_4 45 33 21 22 46 34 22 47 35 48 PTE_7 eTMR0_CH7 - - - - - - - - - - - - - - - - - - - PTB_12 eTMR0_CH0 - - - - - - PTD_4 eTMR0_FLT3 - - - PTD_3 - PTD_3 - SPI1_PCS0 I2C1_SCL - PTD_2 - PTD_2 - SPI1_SOUT 23 23 PTA_3 - PTA_3 eTMR2_CH0 ics - ALT1 36 24 24 PTA_2 - PTA_2 eTMR2_CH1 49 37 25 25 PTA_1 50 38 26 26 PTA_0 51 39 27 - PTC_7 - PTC_7 UART1_TX - 52 40 28 - PTC_6 - PTC_6 UART1_RX - 53 - - - PTE_6 - PTE_6 54 - - - PTE_2 - PTE_2 SPI0_SOUT lpTMR0_ALT3 55 41 - - PTA_13 - 56 42 - - PTA_12 - 57 43 - 27 PTA_11 - 58 44 - 28 PTA_10 - 59 - - - PTE_1 - 60 - - - PTE_0 - 61 45 29 29 PTC_5 62 46 30 30 63 47 31 31 64 48 32 - eTMR2_CH0 TMU_IN4 NMI_b I2C1_SDA eTMR2_CH1 TMU_IN5 - I2C0_SCL SPI2_SCK - UART0_TX - I2C0_SDA SPI2_SIN - UART0_RX - ADC0_SE1 PTA_1 eTMR1_CH1 ACMP0_IN1 - SPI2_SOUT eTMR1_QD_PHA - TMU_OUT0 ADC0_SE0 PTA_0 eTMR1_CH0 ACMP0_IN0 - SPI2_PCS0 - - TMU_OUT3 SPI2_PCS1 CAN0_TX eTMR1_QD_PHA - - CAN0_RX eTMR1_QD_PHB - - - - - - - - - ct le icr oe - PTA_13 eTMR1_CH7 - - UART2_TX - - PTA_12 eTMR1_CH6 - - UART2_RX - - PTA_11 eTMR1_CH5 - I2C1_SCL ACMP0_ACTIVE - - PTA_10 eTMR1_CH4 - I2C1_SDA - - - SPI0_SIN - I2C1_SCL SPI1_PCS0 eTMR1_FLT1 - PTE_0 SPI0_SCK TCLK_IN1 I2C1_SDA SPI1_SOUT eTMR1_FLT2 - eTMR1_CH1 - - - PTC_4 ACMP0_IN2 PTC_4 eTMR1_CH0 RTC_CLKOUT - - PTA_5 M PTE_1 - tu - PTA_4 - PTC_5 eTMR2_CH0 RTC_CLKOUT eTMR1_QD_PHB SWD_CLK PTA_5 - TCLK_IN1 - - - RESET_b PTA_4 - - ACMP0_OUT - - SWD_IO Yu n 32 SPI0_PCS2 ro n - Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 33 Yuntu Microelectronics 7.2 Packages PTD1 1 PTA1 PTA0 PTC7 PTC6 PTE6 PTE2 PTA13 PTA12 PTA11 PTA10 PTE1 PTE0 PTC5 PTC4 PTA5 PTA4 The information of package pinouts is as follows: 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 PTA2 2 47 PTA3 3 46 PTD2 4 45 PTE5 5 44 PTE4 6 43 VDD 7 8 9 64-pin LQFP VSS 10 PTB7 11 PTB6 12 PTE3 13 PTD16 14 PTD15 15 PTB12 PTB13 41 VDD 40 VSS 39 PTE7 38 PTA6 PTC8 35 PTC9 34 PTB0 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PTB1 PTB3 PTC14 PTC15 PTC16 PTC0 PTC17 PTC1 PTD5 PTD6 PTD7 PTC2 PTC3 PTB4 PTB5 PTE8 PTB2 PTA7 36 le 37 icr oe PTE9 PTD4 42 ct VDDA VREFH PTD3 ro n PTE10 ics PTD0 PTE11 Yu n tu M Figure 18: 64-pin LQFP Package Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 34 PTD1 1 48 47 46 45 44 43 42 41 40 39 38 37 36 PTA2 PTD0 2 35 PTA3 PTE5 3 34 PTD2 PTE4 4 33 PTD3 VDD 5 32 PTB13 VDDA 6 31 VDD VSS 7 30 VSS PTB7 8 29 PTA7 48-pin LQFP 28 PTC8 10 27 PTC9 PTD15 11 26 PTB0 PTB6 ro n 9 PTD16 PTB2 PTB1 ct PTB3 PTC14 PTC15 PTC16 PTC1 PTD5 PTC3 PTC2 PTB5 PTE8 PTB4 25 12 13 14 15 16 17 18 19 20 21 22 23 24 PTE9 ics PTA1 PTA0 PTC7 PTC6 PTA13 PTA12 PTA11 PTC5 PTA10 PTC4 PTA5 PTA4 Yuntu Microelectronics PTA5 PTC4 PTC5 PTC6 PTC7 PTA0 PTA1 31 30 29 28 27 26 25 1 PTA4 PTD1 32 icr oe le Figure 19: 48-pin LQFP Package PTA3 22 PTD2 21 PTD3 20 PTA6 6 19 PTA7 7 18 PTB0 17 10 11 12 13 14 15 16 PTB1 9 PTB4 23 3 PTB5 2 VDD PTB2 PTB3 8 PTC0 PTB7 PTC1 VSSA/VSS 32-pin LQFP PTC2 5 PTC3 4 VREFL M VDDA/VREFH tu Yu n PTA2 PTD0 PTB6 Data Sheet 24 Figure 20: 32-pin LQFP Package YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 35 PTA5 PTC4 PTC5 PTA10 PTA11 PTA0 PTA1 30 29 28 27 26 25 24 PTA2 PTE4 2 23 PTA3 VDD 3 22 PTD3 21 VDD 32-pin QFN 20 VSS 19 PTA7 PTB1 9 ro n PTB2 8 PTD15 PTB3 PTB0 PTC2 18 17 10 11 12 13 14 15 16 PTD5 7 PTC3 6 PTB4 PTB6 PTD16 PTB5 4 5 PTE8 VSS PTB7 ics PTA4 1 31 PTE5 32 Yuntu Microelectronics Figure 21: 32-pin QFN Package Yu n tu M icr oe le ct Note: The chip mark will not contain packing information(T/R) Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 36 Yuntu Microelectronics 7.3 Dimensions ct ro n ics Package dimensions are as follows: icr oe le PIN 1 Yu n tu M Figure 22: 64pin LQFP Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 37 ro n ics Yuntu Microelectronics icr oe le ct PIN 1 Yu n tu M Figure 23: 48pin LQFP Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 38 ro n ics Yuntu Microelectronics icr oe le ct PIN 1 Yu n tu M Figure 24: 32pin LQFP Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 39 Yuntu Microelectronics ro n ics PIN 1 Special Design Note: The items marked with "• " (A/D/E/A1) are key characteristics. The above projects must comply with the management and control requirements of automotive electronic projects. icr oe le ct ** Yu n tu M Figure 25: 32pin QFN Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 40 Revision History Revision History The following table provides a revision history for this document. 1.2 2023/4/28 1.3 2023/5/23 1.4 2023/6/15 1.5 2023/7/21 1.6 2023/8/14 1.7 2023/10/8 1.8 2024/9/20 ics 2022/12/19 ro n 1.1 Initial version Changed maximum value from 150 to 135 in the second row of ‘Thermal Operating Characteristics’ table. Changed VLAT to ILAT in ‘ESD Handling Ratings’ table. Updated FIRC frequency accuracy information and changed the min value to -1.5, max value to 1.5 in ‘FIRC(48MHz) Characteristics’ table. Added the whole chapter of ‘Features’ Updated the value of VHBM in ‘ESD Handling Ratings’ Added the note of 5.8 in ‘Absolute Maximum Ratings’ Updated the contents of ‘Voltage and Current Operating Requirements’ Updated the value of Ileak and IIN of ‘DC Electrical Specifications at 3.3V’ Updated the value of Ileak and IIN of ‘DC Electrical Specifications at 5.0V’ Updated the typical value in ‘Power Consumption’ Corrected the value of Max to Typ in ‘Device Clock Specifications’ Updated the contents of ‘FXOSC(4-40MHz) Characteristics’ Updated the contents of ‘SXOSC(32.768KHz) Characteristics’ Updated the contents of ‘ACMP Characteristics’ Added the new section of ‘Thermal Attributes’ Updated the table in the figure of 32pin QFN Updated the table of ‘Ordering Information’ Added the pinmux table of YTM32B1LE04x in ‘IO Signal Description’ Added the coplanarity specifications of product in the section of ‘Dimensions’ Added the location information of PIN 1 in the section of ‘Dimensions’ Updated the content in the table of ‘Ordering Information’ Added the new section of ‘Power Up Requirements’ Updated the content in the section of ‘IO Signal Description’ Updated the ordering information and part numbers in ‘Ordering information’ Updated the figure and table in ‘Power and Ground Pins’ Updated the power up time in ‘Power Up Requirements’ Updated the figure and first table in ‘ADC Characteristics’ In section Ordering Information, table ‘Ordering Information’, removed cost versions. In subsection Power Consumption, updated the description of ‘SIRC’ core and ‘FXOSC’ core. Added the information about ASIL-B in the chapter of ‘Features’ Updated all package dimensions in the section of ‘Dimensions’ Updated supply voltage 2.7V to 2.97V in the whole Data Sheet Added Min and Max value in subsection of ‘Moisture Handling Ratings’ Added Min and Max value in subsection of ‘ESD Handling Ratings’ Added Min and Max value in subsection of ‘Absolute Maximum Ratings’ Added Min and Max value in subsection of ‘Voltage and Current Operating Requirements’ Added Min and Max value in subsection of ‘DC Electrical Specifications at 3.3V’ Added Min and Max value in subsection of ‘DC Electrical Specifications at 5.0V’ Added Min and Max value in subsection of ‘Power and Ground Pins’ Added Min and Max value in subsection of ‘POR,LVR and LVD Operating Requirements’ Added Min and Max value in subsection of ‘Power Consumption’ Added the whole subsection of ‘Power Supply Fluctuation Requirements’ Added Min and Max value in subsection of ‘FXOSC(4-40MHz) Characteristics’ Added Min and Max value in subsection of ‘FIRC(48MHz) Characteristics’ Added Min and Max value in subsection of ‘SXOSC(32.768KHz) Characteristics’ Added Min and Max value in subsection of ‘SIRC(2MHz) Characteristics’ Added Min and Max value in subsection of ‘LPO(750Hz) Characteristics’ Added Min and Max value in subsection of ‘ADC Characteristics’ Added Min and Max value in subsection of ‘ACMP Characteristics’ Updated Max value of VVDDA and VREFH in subsection of ‘Voltage and Current Operating Requirements’ Updated the description in subsection of ‘Power Supply Fluctuation Requirements’ Updated format of table about gain selection in subsection of ‘FXOSC(4-40MHz) Characteristics’ Removed the subsubsection of ‘Flash High Voltage Current Behaviors’ Added the value of Tramp in subsection of ‘Voltage and Current Operating Requirements’ Added the whole subsubsection of ‘MCU Power Supply Ramp Rate’ Corrected Min value of VIN in subsection of ‘ACMP Characteristics’ Added the whole subsection of ‘SPI Characteristics’ Added the value of RJC , RJB and note in the section of ‘Thermal Attributes’ Corrected the name of PIN9 to ”PTE8” of QFN32 package in section of ’Packages’ ct 2022/10/17 le 1.0 Substantive Change(s) icr oe Date 2024/12/5 Yu n 1.9 tu M Rev.No. 2.0 2025/2/27 2.1 2025/9/1 Data Sheet YTM32B1LE0x Data Sheet, REV. 2.1, September 2025 41 Copyright and Contact Copyright and Contact Information in this document is provided solely to enable system and software implementers to use Yuntu Microelectronics products. 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