SD NAND Product
TM3FxxxUXX
1 Description
SD NAND Flash is an embedded storage solution for low-power application.The SD NAND consists of the
NAND flash and the high-performance controller with the LGA 8 package. 3.3V supply voltage (VCC) is required
for the NAND area.The SD NAND Flash is based on an advance 8-pin interface (clock, command, Data*4, power
and ground). The SD NAND Flash is fully compliant with SD2.0/SD3.0 interface and operation is similar to SD
card.
2 Features
Advance
Advanced dynamic ECC engine to improve reliability
Copyrights Protection Mechanism--Complying with highest security of SDMI standard
Low power consumption, with the standby energy saving management mode automatically
High-speed Flash Controller inside
Interface
Support clock frequencies 50MHz/208Mhz
Complies to SD specifications version 2.x/3.x with 1-I/O and 4-I/O
Supports SPI Mode
Support UHS-I (SDR50, SDR104, DDR50)
Power Supply and Consumption
Voltage range: 2.7V ~ 3.6V
Standby: 100uA (Typical)
Operating current: 40mA(Typical)
Temperature
Operation: -25OC to 85OC
Storage: -65OC to 150OC
Reliability
P/E cycles with ECC: 100K
MTBF: 1,000,000hours
Note:The 1Gb-4Gb capacity only supports a clock of 50MHz and is an SD2.0 interface.
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3 Block Architecture
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4 Pin Description
4.1 Device Top View
4.2 Pin Definition
Pin #
1
2
3
4
5
6
7
8
Note:
Name
DAT2
DAT3
CLK
GND
CMD
DAT0
DAT1
VCC
SD Mode
Type
Description
I/O/PP
Data Line (bit 2)
I/O/PP
Data Line (bit 3)
I
Clock
S
Supply Voltage Ground
PP
Command/Response
I/O/PP
Data Line (bit 0)
I/O/PP
Data Line (bit 1)
S
Supply Voltage
Name
RSV
CS
CLK
GND
DI
DO
RSV
VCC
SPI Mode
Type
Description
—
Reserved
I
Chip Select (neg true)
I
Clock
S
Supply Voltage Ground
I
Data In
O/PP
Data Out
—
Reserved
S
Supply Voltage
S: power supply; l: input; O: output using push-pull drivers; PP: I/O using push-pull drivers.
The extended DAT lines(DAT1-DAT3) are input on power up. They start to operate as DAT lines after
SET_BUS_WIDTH command. The host shall keep its own DAT1-DAT3 lines in input mode, as well, while
they are not used. It is defined so, in order to keep compatibility to MultiMediaCards.
After power up this line is input with 50KOhm pull-up (can be used for card detection or SPI mode
selection). The pull-up should be disconnected by the user, during regular data transfer, with
SET_CLR_CARD_DETECT(ACMD42)command.
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5 SD Bus Mode Protocol
The SD bus has six communication lines and three supply lines:
CMD: Command is bi-directional signal.
DAT0-3: Data lines are bi-directional signals.
CLK: Host clock signal
VCC: Power supply.
GND: Ground
The following figure shows the bus topology with one host in SD Bus mode.
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6 SPI Bus Mode Protocol
The SPI mode consists of a secondary communication protocol that is offered by Flash-based SD Memory
Cards. This mode is a subset of the SD Memory Card protocol, designed to communicate with a SPI channel,
commonly found in Motorola's (and lately a few other vendors') micro controllers. The interface is selected during
the first reset command after power up (CMD0) and cannot be changed once the part is powered on.
The SPI standard defines the physical link only, and not the complete data transfer protocol. The SD Memory
Card SPI implementation uses a subset of the SD Memory Card protocol and command set.
The advantage of the SPI mode is the capability of using an off-the-shelf host, hence reducing the design-in
effort to minimum. The disadvantage is the loss of performance of the SPI mode versus SD mode (e.g. Single data
line and hardware CS signal per card).
The commands and functions in SD mode defined after the Version 2.00 are not supported in SPI mode. The
card may respond to the commands and functions even if the card is in SPI mode but host should not use them in
SPI mode.
CS: Chip select signal from host to card.
CLK: Clock signal from host to card.
DataIn: Data signal from host to card.
DataOut: Card to host data signal.
.
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7 Card Initialize
To initialize the SD NAND, follow the following procedure is recommended example.
1).Supply Voltage for initialization
Host System can apply the Operating Voltage from initialization to the card. Apply more than 74 cycles of
Dummy-clock to the SD card.
2).Select operation mode (SD mode or SPI mode)
In case of SPI mode operation, host should drive 1 pin (CD/DAT3) of SD Card I/F to “Low” level. Then,
issue CMD0. In case of SD mode operation, host should drive or detect 1 pin of SD Card I/F (Pull up register of 1
pin is pull up to “High” normally) Card maintain selected operation mode except re-issue of CMD0 or power on
below is SD mode initialization procedure.
3).Send the ACMD41 with Arg = 0 and identify the operating voltage range of the Card.
4).Apply the indicated operating voltage to the card.
Reissue ACMD41 with apply voltage storing and repeat ACMD41 until the busy bit is cleared. (Bit 31 Busy =
1) If response time out occurred, host can recognize not SD Card.
5).Issue the CMD2 and get the Card ID (CID).
6).Issue the CMD3 and get the RCA. (RCA value is randomly changed by access, not equal zero)
7).Issue the CMD7 and move to the transfer state.
If necessary, Host may issue the ACMD42 and disabled the pull up resistor for Card detect.
8).Issue the ACMD13 and poll the Card status as SD Memory Card.Check SD_CARD_TYPE value. If
significant 8 bits are “all zero”, that means SD Card. If it is not, stop initialization.
9).Issue CMD7 and move to standby state. Issue CMD9 and get CSD. Issue CMD10 and get CID.
10).Back to the Transfer state with CMD7.
11).Issue ACMD6 and choose the appropriate bus-width.
Then the Host can access the Data between the SD card as a storage device.
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SPI Mode Initialization Flow
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Normal SD initial flow
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8 Function Description
The sector size of the SD NAND Flash is 512-byte which is the same as that in an IDE magnetic disk
drive. To write or read a sectors, the host computer software simply issues a Read or Write command to the SD
NAND Flash.
8.1 ECC
TITAN SD NAND Flash provides the internal ECC which can protect user data without other controlling
sequence. ECC could use the spare area in NAND FLASH memory and the occupied size is determined by the
+ECC protected abilities. The ECC default setting is enabled after device power up.
8.2 Bad Block Manage
The device occasionally contains bad blocks. Please read one word of first page of first spare in each
block. TITAN makes sure that every invalid block has data at this word. If the data of the word is “0”, define the
block as a bad block.
8.3 Automatic Sleep Mode
TITAN SD NAND Flash provides automatic entrance and exit from sleep mode. If no further commands
are received within 5msec, chip would enter sleep mode. The host does not have to take any action for this to occur.
TITANSD NAND Flash provide ultra-low power consumption during sleep mode (around 100uA) and suitable for
IoT application.
8.4 Wear Leveling
Wear-leveling is an intrinsic part of the Erase Pooling functionality of SD using NAND memory. The
Wear Level command is supported as a NOP operation to maintain backward compatibility with existing software
utilities.
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9 Registers
Six registers are defined within the card interface: OCR, CID, CSD, RCA, DSR and SCR. These can be
accessed only by corresponding commands. The OCR, CID, CSD and SCR registers carry the card/content specific
information, while the RCA and DSR registers are configuration registers storing actual configuration parameters
Register
OCR
CID
CSD
RCA
DSR
SCR
SD Status
Width
32
128
128
16
16
64
512
Comment
Operation Conditions Register
Card IDentification
Card-Specific Data
Relative Card Address
Driver Stage Register
SD CARD Configuration Register
Status Bits and Card Features
9.1 OCR Register
The 32-bit operation conditions register stores the VDD voltage profile. Additionally, this register
includes status information bits. One status bit is set if the power up procedure has been finished. This register
includes another status bit indicating the capacity status after set power up status bit.
Bit Position
0-3
4
5
6
7
8
9
10
11
12
13
14
15
OCR Fields Definition
Bit Position
16
17
18
19
20
21
22
23
24(1)
25-29
30
31
Reserved
Reserved
Reserved
Reserved
Reserved for low voltage range
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2.7 ~ 2.8
OCR Fields Definition
2.8 ~ 2.9
2.9 ~ 3.0
3.0 ~ 3.1
3.1 ~ 3.2
3.2 ~ 3.3
3.3 ~ 3.4
3.4 ~ 3.5
3.5 ~ 3.6
Switching to 1.8V Accepted (S18A)
Reserved
Card Capacity Status (CCS)(2)
Card power up status bit (busy)(3)
(1) Only UHS-I card supports this bit.
(2) This bit is valid only when the card power up status bit is set.
(3) This bit is set to LOW if the card has not finished the power up routine.
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9.2 CID Register
The CID register is 16 bytes long and contains a unique identification number as shown in below table.
Name
Width
CID Slice
Manufacture ID (MID)
8
[127:120]
OEM/Application ID (OID)
16
[119:104]
Product Name (PNM)
Product Revision (PRV)
Serial Number (PSN)
Reserved
40
8
32
4
[103: 64]
[63:56]
[55:24]
[23:20]
Manufacture Data Code (MDT)
12
[19:8]
CRC7 checksum (CRC)
Not used, always 1
7
1
[7:1]
[0:0]
Comment
The manufacturer IDs are controlled
and assigned by the SD Card
Association.
Identifies the card OEM and/or the
card contents. The OID is assigned
by the 3C.*
5 ASCII characters long
Two binary coded decimal digits
32 Bits unsigned integer
Manufacture date–yym (offset from
2000)
Calculated
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9.3 CSD Register
The Card-Specific Data register provides information regarding access to the device contents. The CSD
defines the data format, error correction type, maximum data access time, whether the DSR register can be used,
etc. The programmable part of the register (entries marked by W or E, see below) can be changed by CMD27. The
types of the entries in the table below are coded as follows: R = readable, W(1) = writable once, W = multiple
writable.
Field
CSD_STRUCTURE
TAAC
NSAC
TRAN_SPEED
CCC
READ_BL_LEN
READ_BL_PARTIAL
WRITE_BLK_MISALIGN
READ_BLK_MISALIGN
DSR_IMP
C_SIZE
VDD_R_CURR_MIN
VDD_R_CURR_MAX
VDD_W_CURR_MIN
VDD_W_CURR_MAX
C_SIZE_MULT
ERASE_BLK_EN
SECTOR_SIZE
WP_GRP_SIZE
WP_GRP_ENABLE
R2W_FACTOR
WRITE_BL_LEN
WRITE_BL_PARTIAL
FILE_FORMAT_GRP
COPY
PERM_WRITE_PROTECT
TMP_WRITE_PROTECT
FILE_FORMAT
CRC
-
Width
2
6
8
8
8
12
4
1
1
1
1
2
12
3
3
3
3
3
1
7
7
1
2
3
4
1
5
1
1
1
1
2
2
7
1
Value
00b
00 0000b
xxh
xxh
32h or 5Ah
01x110110101b
xh
1b
xb
xb
xb
00b
xxxh
xxxb
xxxb
xxxb
xxxb
xxxb
xb
xxxxxxxb
xxxxxxxb
xb
00b
xxxb
xxxxb
xb
00000b
xb
xb
xb
xb
xxb
00b
xxxxxxxb
1b
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W(1)
R/W(1)
R/W(1)
R/W
R/W(1)
R/W
R/W
-
CSD-slice
[127:126]
[125:120]
[119:112]
[111:104]
[103:96]
[95:84]
[83:80]
[79:79]
[78:78]
[77:77]
[76:76]
[75:74]
[73:62]
[61:59]
[58:56]
[55:53]
[52:50]
[49:47]
[46:46]
[45:39]
[38:32]
[31:31]
[30:29]
[28:26]
[25:22]
[21:21]
[20:16]
[15:15]
[14:14]
[13:13]
[12:12]
[11:10]
[9:8]
[7:1]
[0:0]
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9.4 RCA Register
The writable 16-bit relative card address register carries the device address that is published by the
device during the identification. This address is used for the addressed host-device communication after the
identification procedure. The default value of the RCA register is 0x0000. The value 0x0000 is reserved to set all
cards into the Stand-by State with CMD7
9.5 DSR Register
The 16-bit driver stage register is described in detail in Chapter 6.5. It can be optionally used to improve
the bus performance for extended operating conditions (depending on parameters like bus length, transfer rate or
number of devices). The CSD register carries the information about the DSR register usage. The default value of
the DSR register is 0x404.
9.6 SCR Register
In addition to the CSD register, there is another configuration register named SD CARD Configuration
Register (SCR). SCR provides information on the SD Memory Device's special features that were configured into
the given device. The size of SCR register is 64 bits. This register shall be set in the factory by the SD Memory
Device manufacturer. The following table describes the SCR register content
Field
SCR_STRUCTURE
SD_SPEC
DATA_STAT_AFTER_ERASE
SD_SECURITY
SD_BUS_WIDTHS
SD_SPEC3
CMD_SUPPORT
-
Width
4
4
1
3
4
1
13
14
32
Type
R
R
R
R
R
R
R
R
CSD-slice
[63:60]
[59:56]
[55:55]
[54:52]
[51:48]
[47]
[46:34]
[33:32]
[31:0]
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10 Electronic characteristic
10.1 Absolute Maximum Ratings
Parameter
Storage Temperature
Ambient Operation Temperature
Applied Input/Output Voltage
10.2 DC Characteristics
Parameters
Supply Voltage (VCC)
Input Leakage Current
Output Leakage Current
Operation Current (Read 50MHz)(32Gb)
Operation Current (Write 50MHz)(32Gb)
Standby Current
Value
-65OC ~ 150OC
-40OC ~ 85OC
0V ~ VCC*1.1
Min
2.7
-----------
TM3FxxxUXX
Typical
3.3
----30
30
100
Max
3.6
5
5
-------
UNIT
V
uA
uA
mA
mA
uA
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11 Reference Design
Note：
RDAT and RCMD(10K~100kΩ) are pull-up resistors protecting the CMD and the DAT lines against bus floating when
SD NAND is in a high-impedance mode.
The host shall pull-up all DAT0-3 lines by RDAT, even if the host uses the SD NAND as 1-bit mode only in SD
mode. It is recommended to have 2.2uF capacitance on VCC.
RCLK reference 0~120 Ω.
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12 Part Information
TM 3F xxx U X X
TITAN
I:-40℃~85℃
K:-40℃~105℃
J:-40℃~125℃
A：A version
3F:SD NAND Flash
01G:1Gb
02G:2Gb
04G:4Gb
16G:16Gb
32G:32Gb
64G:64Gb
256:256Gb
512:512Gb
U：3.3V
Product Description:
Part Number
Capacity
Sequential Read
Sequential Write
Package
TM3F01GUAI
1Gb(128MB)
15MB/S
5MB/S
LGA8-6*8
TM3F02GUAI
2Gb(256MB)
15MB/S
5MB/S
LGA8-6*8
TM3F04GUAI
4Gb(512MB)
17MB/S
10MB/S
LGA8-6*8
TM3F16GUAI
16Gb(2GB)
22MB/S
8MB/S
LGA8-6.6*8
TM3F32GUAI
32Gb(4GB)
70MB/S
15MB/S
LGA8-6.6*8
Note: Different testing environments can lead to differences in read and write speeds.
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13 Package
LGA8-6*8
Top View
Side View
Bottom View
Dimensions
Item
D
E
A
A1
b
L
e
Unit
mm
mm
mm
mm
mm
mm
mm
8.10
6.10
0.80
0.05
0.85
1.05
Spec
(8.00)
(6.00)
(0.75)
(0.02)
(0.80)
(1.00)
7.90
5.90
0.70
0.00
0.75
0.95
1.27BSC
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LGA8-6.6*8
1
8
4
5
8
1
5
Top View
4
Side View
Bottom View
Dimensions
D
E
D1
E1
A
A1
A2
b
L
e
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
8.10
6.70
6.10
3.90
0.80
0.27
0.05
0.85
1.05
(8.00)
(6.60)
(6.00)
(3.80)
(0.75)
(0.25)
(0.02)
(0.80)
(1.00)
7.90
6.50
5.90
3.70
0.70
0.23
0.00
0.75
0.95
1.27BSC
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LGA-9*10
1
8
4
5
8
1
4
5
Top View
Side View
Bottom View
Dimensions
Item
D
E
D1
E1
A
A1
A2
b
L
e
h
Unit
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
10.10
9.10
6.10
3.90
0.80
0.27
0.05
0.85
1.05
(10.00)
(9.00)
(6.00)
(3.80)
(0.75)
(0.25)
(0.02)
(0.80)
(1.00)
9.90
8.90
5.90
3.70
0.70
0.23
0.00
0.75
0.95
Spec
1.27BSC 1.0REF
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LGA-9*12.5
1
8
4
5
Top View
Side View
Bottom View
Dimensions
Item
D
E
D1
E1
A
A1
aaa
bbb
eee
fff
SE
SE1
SD
e
Unit
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
9.10
12.60
0.10
0.10
0.15
0.05 5.67BS 3.425B 0.635B 1.27BS 0.85 0.75
C
SC
SC
C
Spec
(9.00) (12.50)
8.90
12.40
3.91
11.45
0.80
0.27
(3.81)
(11.35)
(0.75)
(0.25)
3.71
11.25
0.70
0.23
L
b
mm mm
0.90 0.80
0.80 0.70
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