TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Features
Description
Supply Voltage: 1.8 V to 5.5 V
The family of the amplifier are single/dual/quad
chopper-stabilized zero-drift operational amplifiers
optimized for single or dual supply operation from 1.8
V to 5.5 V and ±0.9 V to ±2.75 V. TP555X features
very low input offset voltage and low noise with no 1/f
noise corner down to 0.1 Hz. The TP555X is
designed to have ultra-low offset voltage and offset
temperature drift, wide gain bandwidth and rail-to-rail
input/output swing while minimizing power
consumption.
Low Offset Voltage: 5 μV (max)
Zero Drift: 0.05 µV/°C (max)
No 1/f Noise Corner Down to 0.1Hz
− Input Noise Voltage: 15 nV/√Hz at 1 kHz
− 0.1 Hz to 10 Hz Voltage Noise: 350 nVPP
Slew Rate: 2.5 V/μs
Bandwidth: 3.5 MHz
Low Supply Current: 550 μA per Amplifier
This TP555X family can provide very low offset
voltage (max 5 μV) and near-zero drift over time and
temperature with excellent CMRR and PSRR.
Low Input Bias Current: 50 pA Typical
Rail-to-Rail Output Voltage Range
High gain, CMRR, PSRR: 130 dB
The TP5551 (single version) is available in SOT23-5,
and SOP8 packages. The TP5552 (dual version) is
offered in MOSP8, SOP8 package. The TP5554
(quad version) is available in TSSOP14, SOP14
package. All versions are specified for operation from
−40°C to 125°C.
7 kV HBM ESD Rating
−40°C to 125°C Operation Range
Applications
Medical Instrumentation
Temperature Measurements
Precision current sensing
Precision Low Drift, Low Frequency ADC Drivers
Process Control Systems
Precision Voltage Reference Buffers
Typical Application Circuit
TP5551
+
www.3peak.com
1 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Table of Contents
Features .............................................................................................................................................................. 1
Applications ....................................................................................................................................................... 1
Description ......................................................................................................................................................... 1
Typical Application Circuit ................................................................................................................................ 1
Revision History ................................................................................................................................................ 3
Pin Configuration and Functions ..................................................................................................................... 4
Specifications .................................................................................................................................................... 5
Absolute Maximum Ratings (1) ...................................................................................................................... 5
ESD, Electrostatic Discharge Protection ...................................................................................................... 5
Electrical Characteristics .............................................................................................................................. 6
Typical Performance Characteristics ............................................................................................................ 8
Detailed Description ........................................................................................................................................ 10
Overview..................................................................................................................................................... 10
Functional Block Diagram .......................................................................................................................... 10
Application and Implementation ..................................................................................................................... 11
Typical Application ....................................................................................................................................... 11
Application Information ................................................................................................................................ 11
Tape and Reel Information .............................................................................................................................. 15
Package Outline Dimensions ......................................................................................................................... 16
SOT23-5 ..................................................................................................................................................... 16
SOP8 .......................................................................................................................................................... 17
MSOP8 ....................................................................................................................................................... 18
TSSOP14 ................................................................................................................................................... 19
SOP14 ........................................................................................................................................................ 20
Order Information ............................................................................................................................................ 21
IMPORTANT NOTICE AND DISCLAIMER ....................................................................................................... 22
www.3peak.com
2 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Revision History
Date
Revision
Notes
2018-08-30
Rev.B.0
Updated Full Temperature Specification
2020-05-25
Rev.B.1
Updated Specification of PSRR:
25°C: min 95 → min 110;
−40°C to 125°C: min 85 → min 105
2022-02-17
Rev.B.2
Updated Format of Document
2022-03-19
Rev.B.3
Updated Tape and Reel Information
2023-07-08
Rev.B.4
The following updates are all about the new datasheet formats or typo, the
actual product remains unchanged.
Updated to new format of package dimensions and tape and reel information.
www.3peak.com
3 / 22
Rev.B.4
TP5551
TP5551/TP5552/TP5554
SOT23-5/SC70-5
(-T and -C Suffixes)
Pin Configuration and Functions
OUT
1
V-
2
+IN
3
Ultra-Low Noise, 3.5 MHz
5
V+
Zero Drift,
RRIO Op-amps
A
4
TP5551
TP5551U
SOT23-5/SC70-5
(-T and -C Suffixes)
SOT23-5/SC70-5
(-T and -C Suffixes)
1
V-
2
+IN
3
5
V+
A
4
-IN
+IN
1
V-
2
-IN
3
5
V+
4
OUT
A
OUT
-IN
TP5551U
SOT23-5/SC70-5
TP5552
(-T and -C Suffixes) 8-Pin SOIC/MSOP
TP5551
8-Pin SOIC
(-S Suffix)
1
+IN
﹣In
1
V-
2
8
7
-IN
2 NC
3
A
NC
5
Out A
﹢Vs
﹣In A
﹢In
3
6
Out
﹢In A
﹣Vs
4
5
NC
﹣Vs
(-S and -V Suffixes)
V+
1
8
2
4
3
TP5554
14-Pin SOIC/TSSOP
(-S and -T Suffixes)
A
OUT
B
4
﹢Vs
Out A
1
14
Out D
2
13
﹣In D
7
Out B
﹣In A
6
﹣In B
﹢In A
3
12
﹢In D
5
﹢In B
﹢Vs
4
11
﹣Vs
﹢In B
5
10
﹢In C
A
B
www.3peak.com
4 / 22
D
C
﹣In B
6
9
﹣In C
Out B
7
8
Out C
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Specifications
Absolute Maximum Ratings (1)
Parameter
Min
Max
Unit
7
V
+ 0.3
V
Supply Voltage
(V−)
Input Voltage
(V+)
− 0.3
Input Current: +IN, −IN (2)
Output Current: OUT
Output Short-Circuit Duration
(3)
±20
mA
±60
mA
Indefinite
Current ar Supply Pins
±50
mA
150
°C
TJ
Maximum Junction Temperature
TA
Operating Temperature Range
−40
125
°C
Storage Temperature Range
−65
150
°C
260
°C
TSTG
TL
Lead Temperature (Soldering 10 sec)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure
to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
(2) The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 500mV beyond
the power supply, the input current should be limited to less than 10 mA.
(3) A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power
supply voltage and how many amplifiers are shorted. Thermal resistance varies with the amount of PC board metal
connected to the package. The specified values are for short traces connected to the leads.
ESD, Electrostatic Discharge Protection
Symbol
HBM
CDM
Parameter
Human Body Model ESD
Charged Device Model ESD
Condition
Minimum Level
Unit
ANSI/ESDA/JEDEC JS-001
(1)
7
kV
ANSI/ESDA/JEDEC JS-002
(2)
2
kV
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
www.3peak.com
5 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Electrical Characteristics
All test conditions: VDD = 5 V, RL = 10 K, VCM = VDD/2, TA = +27°C, unless otherwise noted.
Symbol
VDD
Parameter
Conditions
Max
Unit
5.5
V
1400
μA
TP5551, TA = −40°C to 85°C
1600
μA
TP5551, TA = −40°C to 125°C
1750
μA
950
μA
TP5552/4, TA = −40°C to 85°C
1150
μA
TP5552/4, TA = −40°C to 125°C
1300
μA
±5
μV
±10
μV
0.05
μV/°C
Supply Voltage Range
Min
1.8
TP5551
IQ
VOS
Quiescent current per amplifier
Typ
1200
TP5552/4
550
input Offset Voltage
±1
TA = −40°C to 125°C
dVos/dT
PSRR
VN (p-p)
VN
CIN
IB
IOS
VCM
CMRR
vs temperature
130
dB
input voltage noise, f = 0.01 Hz to
1 Hz
0.1
μVpp
input voltage noise, f = 0.1 Hz to
10 Hz
0.35
μVpp
Input voltage noise density, f = 1
kHz
15
nV/√Hz
Input capacitor Differential
3
pF
Input capacitor Common-Mode
2
pF
Input Current
±50
pA
Over temperature
±200
pA
vs power supply
110
Vs = +1.8 V to +5.5 V,
TA = −40°C to 125°C
105
±100
(V−)
Common-mode voltage range
Common-mode rejection ratio
Output Voltage Swing from rail
ISC
Short-circuit current
SR
Vs = +1.8 V to +5.5 V
Input offset current
VO
GBW
0.008
pA
(V+)
−
0.1
0.1
+
V
VS = 5 V, VCM = 0.5 V to 4.5 V
110
130
dB
VS = 5 V, VCM = 0 V to 5 V
100
120
dB
VS = 5 V, VCM = 0 V to 5 V,
TA = −40°C to 125°C
90
RL = 10 kΩ
dB
10
RL = 10 kΩ, TA = −40°C to 125°C
25
mV
30
mV
±50
mA
Unity Gain Bandwidth
CL = 100 pF
3.5
MHz
Slew rate
G = +1, CL = 100 pF
2.5
V/μs
www.3peak.com
6 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Electrical Characteristics (Continued)
All test conditions: VDD = 5 V, RL = 10 K, VCM = VDD/2, TA = +27°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tor
Overload recovery time
G = −10
35
μs
ts
Settling time to 0.01%
CL = 100 pF
20
μs
120
dB
AVO
θJA
Open-Loop Voltage Gain
Thermal Resistance
Junction to Ambient
www.3peak.com
(V−) + 100 mV < VO < (V+) − 100 mV,
RL = 100 kΩ
100
(V−) +100 mV < VO < (V+) – 100 mV,
RL = 100 kΩ, TA = −40°C to 125°C
90
dB
SOT23-5
200
MSOP8
210
SOP8
158
SOP14
83
TSSOP14
100
7 / 22
°C/W
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Typical Performance Characteristics
Offset Voltage Distribution
Supply Current Distribution
35
Population Of Amplifiers
50
40
35
30
25
20
15
30
25
20
15
10
10
5
5
Supply Curent(μA)
2.5
2
2.25
1.5
1.75
1.25
0
1
-1
-1.5
-1.25
-2
-2.5
500 510 520 530 540 550 560 570 580 590 600
-1.75
0
0
-2.25
Population Of Amplifiers
45
Offset Voltage(μV)
Figure 1. Supply Current Distribution
Figure
2. Noise
Offset
Voltage
Distribution
Voltage
Spectral
Density
vs Frequency
Quiesent Current vs Temperature
100
1000
Volage noise (nV/√Hz)
900
800
I Q(μV)
700
600
500
400
300
10
200
1
100
-50
-25
0
25
50
75
100
125
0.01
150
0.1
1
10
100
1k
10k
Frequency (Hz)
Temperature(°C)
Figure 4. Voltage Noise Spectral Density vs
Figure 3. Quiescent Current vs Temperature
Frequency
CMRR vs FREQUENCY
OPEN-LOOP GAIN vs FREQUENCY
120
100
100
140
90
120
80
100
60
60
50
40
40
10
-20
10
100
1k
10k
100k
1M
0
0
10M
1
Frequency(Hz)
10
100
1k
10k
100k
1M
Frequency(Hz)
Figure 5. Open-Loop Gain vs Frequency
www.3peak.com
60
20
20
0
80
40
30
20
CMRR(dB)
70
Phase(deg)
Aol(dB)
80
Figure 6. CMRR vs Frequency
8 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Typical Performance Characteristics (Continued)
Positive Over-Voltage Recovery
2V/div
G=+1
RL=10KΩ
Input
Output
1V/div
Output Voltage (50mV/div)
Small-Scale Step Response
Time (50μs/div)
Time (5μs/div)
Figure 7. Small-Scale Step Response
Figure 8. Positive Over-Voltage Recovery
Negative Over-Voltage Recovery
1V/div
Input
1V/div
1V/div
1V/div
Negative Over-Voltage Recovery
Output
Output
Time (50μs/div)
Time (50μs/div)
Figure 9 Negative Over-Voltage Recovery
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Input
Figure 10 Large-Scale Step Response
9 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Detailed Description
Overview
The TP5551/2/4 op amps are zero drift, rail-to-rail operation amplifiers that can be run from a single-supply
voltage. They use an auto-calibration technique with a time-continuous 3.5 MHz op amp in the signal path while
consuming only 550 μA of supply current per channel. This amplifier is zero-corrected with an 150 kHz clock.
Upon power-up, the amplifier requires approximately 100 μs to achieve specified VOS accuracy. This design has
no aliasing or flicker noise.
Functional Block Diagram
Figure 11 Functional Block Diagram
www.3peak.com
10 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Application and Implementation
NOTE
Information in the following applications sections is not part of the 3PEAK’s component specification and
3PEAK does not warrant its accuracy or completeness. 3PEAK’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design implementation
to confirm system functionality.
Typical Application
TP5551
+
Figure 12. Single Supply, High Gain Amplifier, AV = 10,000 V/V
TP5551
+
Figure 13 Thermistor Measurement
Application Information
Rail-To-Rail Input And Output
The TP5551/2/4 feature rail-to-rail input and output with a supply voltage from 1.8 V to 5.5 V. This allows the
amplifier inputs to have a wide common mode range (50 mV beyond supply rails) while maintaining high CMRR
(120 dB) and maximizes the signal to noise ratio of the amplifier by having the V OH and VOL levels be at the V+
and V- rails, respectively.
Input Protection
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11 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
The TP5551/2/4 have internal ESD protection diodes that are connect between the inputs and supply rail. When
either input exceeds one of the supply rails by more than 300 mV, the ESD diodes become forward biased and
large amounts of current begin to flow through them. Without current limiting, this excessive fault current causes
permanent damage to the device. Thus an external series resistor must be used to ensure the input currents
never exceed 10 mA.
V+
500Ω
IN+
Current-limiting resistor
required if input voltage
exceeds supply rails by
>0.5V.
500Ω
+2.5V
IN-
Ioverload
10mA max
TP5551
VIN
V-
Vout
5kΩ
INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN
-2.5V
Low Input Referred Noise
Flicker noise, as known as 1/f noise, is inherent in semiconductor devices and increases as frequency
decreases. So at lower frequencies, flicker noise dominates, causing higher degrees of error for sub-Hertz
frequencies or dc precision application.
The TP5551/2/4 amplifiers are chopper stabilized amplifiers, the flicker noise is reduced greatly because of this
technique. This reduction in 1/f noise allows the TP5551/2/4 to have much lower noise at dc and low frequency
compared to standard low noise amplifier.
Residual voltage ripple
The chopping technique can be used in amplifier design due to the internal notch filter. Although the chopping
related voltage ripple is suppressed, higher noise spectrum exists at the chopping frequency and its harmonics
due to residual ripple.
So if the frequency of input signal is nearby the chopping frequency, the signal maybe interfered by the residue
ripple. To further suppress the noise at the chopping frequency, it is recommended that a post filter be placed
at the output of the amplifier.
Broad Band and External Resistor Noise Considerations
The total broadband noise output from any amplifier is primarily a function of three types of noise: input voltage
noise from the amplifier, input current noise from the amplifier, and thermal (Johnson) noise from the external
resistors used around the amplifier. These noise sources are not correlated with each other and their combined
noise can be summed in a root sum squared manner. The full equation is given as:
en total = [en2 + 4kTRs + (in Rs )2 ]1/2
(1)
Where:
en = the input voltage noise density of the amplifier.
In = the input current noise of the amplifier.
www.3peak.com
12 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
RS = source resistance connected to the noninverting terminal.
K = Boltzmann‘s constant (1.38 x 10−23J/K).
T = ambient temperature in Kelvin (K).
The total equivalent rms noise over a specific bandwidth is expressed as:
en ,rms = en total BW
(2)
The input voltage noise density (en) of the TP555x is 55 nV/√Hz, and the input current noise can be neglected.
When the source resistance is 190 kΩ, the voltage noise contribution from the source resistor and the amplifier
are equal. With source resistance greater than 190 kΩ, the overall noise of the system is dominated by the
Johnson noise of the resistor itself.
High Source Impedance Application
The TP5551/2/4 uses switches at the chopper amplifier input, the input signal is chopped at 125 kHz to reduce
input offset voltage down to 10 µV. The dynamic behavior of these switches induces a charge injection current
to the input terminals of the amplifier. The charge injection current has a DC path to ground through the
resistances seen at the input terminals of the amplifier. Higher input impedance causes an apparent shift in the
input bias current of the amplifier.
Because the chopper amplifier has charge injection currents at each terminal, the input offset current will be
larger than standard amplifiers. The IOS of TP5551/2/4 are 150 pA under the typical condition. So the input
impedance should be balanced across each input. The input impedance of the amplifier should be matched
between the IN+ and IN− terminals to minimize the total input offset current. Input offset currents show up as
an additional output offset voltage, as shown in the following equation:
vos ,total = vos − R f I os
(3)
For a gain configure using 1MΩ feedback resistor, a 150pA total input offset current will have an additional
output offset voltage of 0.15 mV. By keeping the input impedance low and balanced across the amplifier inputs,
the input offset current effect will be suppressed efficiently.
Ri
Rf
Vref
+2.5V
TP5551
Rs
Vout
VIN
-2.5V
Rb
Vref
Figure 14 Circuit Implication for reducing Input offset current effect
PCB Surface Leakage
In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need
to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. It is
recommended to use multi-layer PCB layout and route the OPA’s −IN and +IN signal under the PCB surface.
The effective way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown below for
www.3peak.com
13 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Inverting
Gain application.
1. For Non-Inverting Gain and Unity-Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface.
b) Connect the guard ring to the inverting input pin (VIN−). This biases the guard ring to the Common Mode
input voltage.
2. For Inverting Gain and Trans-impedance Gain Amplifiers (convert current to voltage, such as photo detectors):
a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same
reference voltage as the op-amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN−) to the input with a wire that does not touch the PCB surface.
Guard Ring
VIN+
VIN-
+VS
Figure 15 Layout of Guard Ring
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14 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Tape and Reel Information
Package
D1
(mm)
W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P0
(mm)
W0
(mm)
Pin1
Quadrant
TP5551-SR
SOP8
330.0
17.6
6.5
5.4
2.0
8.0
12.0
Q1
TP5551-TR
SOT23-5
179.0
12.0
3.3
3.25
1.4
4.0
8.0
Q3
TP5552-SR
SOP8
330.0
17.6
6.5
5.4
2.0
8.0
12.0
Q1
TP5552-VR
MSOP8
330.0
17.6
5.2
3.3
1.5
8.0
12.0
Q1
TP5554-SR
SOP14
330.0
21.6
6.5
9.1
2.1
8.0
16.0
Q1
TP5554-TR
TSSOP14
330.0
17.6
6.8
5.5
1.6
8.0
12.0
Q1
Order Number
www.3peak.com
15 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
Package Outline Dimensions
SOT23-5
www.3peak.com
16 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
SOP8
www.3peak.com
17 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
MSOP8
www.3peak.com
18 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
TSSOP14
www.3peak.com
19 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz
Zero Drift, RRIO Op-amps
SOP14
www.3peak.com
20 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz, Zero Drift, RRIO Op-amps
Order Information
Order Number
Operating Temperature
Range
Package
Marking
Information
MSL
Transport Media,
Quantity
Eco Plan
TP5551-TR
−40 to 125°C
SOT23-5
E51T
MSL3
Tape and Reel, 3000
Green
TP5551-SR
−40 to 125°C
SOP8
TP5551
MSL3
Tape and Reel, 4000
Green
TP5552-SR
−40 to 125°C
SOP8
TP5552
MSL3
Tape and Reel, 4000
Green
TP5552-VR
−40 to 125°C
MSOP8
TP5552
MSL3
Tape and Reel, 3000
Green
TP5554-SR
−40 to 125°C
SOP14
TP5554
MSL3
Tape and Reel, 2500
Green
TP5554-TR
−40 to 125°C
TSSOP14
TP5554
MSL3
Tape and Reel, 3000
Green
Green: 3PEAK defines "Green" to mean RoHS compatible and free of halogen substances.
www.3peakic.com.cn
21 / 22
Rev.B.4
TP5551/TP5552/TP5554
Ultra-Low Noise, 3.5 MHz, Zero Drift, RRIO Op-amps
IMPORTANT NOTICE AND DISCLAIMER
Copyright© 3PEAK 2012-2023. All rights reserved.
Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks, and domain names contained in this document /material are the property
of 3PEAK. You may NOT reproduce, modify, publish, transmit or distribute any Trademark without the prior written consent of 3PEAK.
Performance Information. Performance tests or performance range contained in this document/material are either results of design simulation or actual tests
conducted under designated testing environment. Any variation in testing environment or simulation environment, including but not limited to testing method,
testing process or testing temperature, may affect actual performance of the product.
Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design
recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no
warranties of any kind, express or implied, including without limitation, implied warranties as to merchantability, fitness for a particular purpose or noninfringement of any third-party’s intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to be used in
any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation, aerospace, or any situations where failure
could result in bodily harm, loss of life, or significant property damage. 3PEAK disclaims all liability for any such unauthorized use.
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