TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Features
Description
• Quad, 16-/12-Bit Pin Compatible DACs
• – TPC116S4: 16 Bits
– TPC112S4: 12 Bits
• Low Power Consumption (800 μA typ)
• Differential Nonlinearity: ±1 LSB (Max)
• Glitch Energy: 2 nV-s
• Power-on Reset to Zero
• Supply Range: 2.7 V to 5.5 V
• Buffered Rail-to-Rail Output Operation
• Safe Power-on Reset (POR) to Zero DAC Output
• Fast 30-MHz, 3-Wire SPI/QSPI/MICROWIRE-
The TPC116S4/TPC112S4 are pin-compatible 16-bit and
12-bit digital-to-analog converters. The products are fourchannel, low-power, and buffered voltage-out DACs, which
are guaranteed monotonic by design. The devices use
a precision external reference applied through the highresistance input for rail-to-rail operation and low system
power consumption.
The TPC116S4/TPC112S4 accept a wide range of 2.7-V
to 5.5-V supply voltage. The parts incorporate a power-on
reset circuit to ensure that the DAC output powers up to 0
V and remains there until a valid write takes place.
The on-chip precision output amplifiers of the TPC116S4/
TPC112S4 allow rail-to-rail output swing to be achieved.
For remote sensing applications, the inverting input of
the output amplifier is available to users. The TPC116S4/
TPC112S4 use a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible
with standard SPI®, QSPI™, MICROWIRE™, and DSP
interface standards.
Compatible Serial Interface
•
•
•
•
Schmitt-Trigger Inputs for Direct Optocoupler Interface
SYNC Interrupt Facility
High-Performance Drop-in Compatible with TLV5614
Available in TSSOP16 Package
The TPC116S4/TPC112S4 are available in the small-sized
TSSOP16 package. All packages are specified over the
−40°C to +125°C extended industrial temperature range.
Applications
•
•
•
•
•
Gain and Offset Adjustment
Process Control and Servo Loops
Programmable Voltage and Current Sources
Programmable Attenuators
Automatic Test Equipment
Typical Application Circuit
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Table of Contents
Features................................................................................................................................................................1
Applications......................................................................................................................................................... 1
Description........................................................................................................................................................... 1
Typical Application Circuit..................................................................................................................................1
Revision History...................................................................................................................................................3
Pin Configuration and Functions....................................................................................................................... 4
Specifications.......................................................................................................................................................6
Absolute Maximum Ratings (1)........................................................................................................................6
ESD, Electrostatic Discharge Protection........................................................................................................ 6
Thermal Information........................................................................................................................................6
Electrical Characteristics................................................................................................................................ 7
Timing Characteristics.................................................................................................................................... 8
Typical Performance Characteristics............................................................................................................ 10
Detailed Description.......................................................................................................................................... 13
Overview.......................................................................................................................................................13
Functional Block Diagram.............................................................................................................................13
Application and Implementation...................................................................................................................... 14
Application Information ................................................................................................................................ 14
Typical Application........................................................................................................................................15
Tape and Reel Information................................................................................................................................ 16
Package Outline Dimensions........................................................................................................................... 17
TSSOP16......................................................................................................................................................17
Order Information.............................................................................................................................................. 18
IMPORTANT NOTICE AND DISCLAIMER......................................................................................................... 19
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Revision History
Date
Revision
2022-12-05
Rev.A.4
Updated the Functional Block Diagram.
2024-12-03
Rev.A.5
Updated to a new datasheet format.
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Notes
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Pin Configuration and Functions
TPC11xS4
TSSOP16
Top View
NC
1
16
VDD
NC
2
15
REFIN
LDAC
3
14
OUTA
DIN
4
13
OUTB
SCLK
5
12
OUTC
NC
6
11
OUTD
SYNC
7
10
NC
GND
8
9
GND
Table 1. Pin Functions
Pin No.
Name
I/O
1
NC
NC
Not connect.
2
NC
NC
Not connect.
Load DAC.
DI
•
•
The DAC outputs are only updated when the LDAC is low.
DI
•
•
•
•
•
•
•
Schmitt-Trigger logic input.
3
4
5
LOAD
DIN
SCLK
6
NC
DI
NC
Description
When the LOAD signal is high, no DAC output updates occur when the input
digital data is read into the serial interface.
Serial data input.
Data is clocked into the 16-/24-bit input shift register on each falling edge of the
serial clock input.
Serial clock input.
Data can be transferred at rates up to 30 MHz.
Schmitt-Trigger logic input.
Not connect.
•
•
•
Level-triggered control input (active LOW).
This is the frame synchronization signal for the input data.
7
SYNC
DI
8
GND
P
Ground reference point for all circuitry on the part.
9
GND
P
Ground reference point for all circuitry on the part.
10
NC
NC
Not connect.
11
OUTD
AO
DACD output.
12
OUTC
AO
DACC output.
13
OUTB
AO
DACB output.
14
OUTA
AO
DACA output.
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When SYNC goes low, it enables the input shift register, and the data is
transferred in on the falling edges of the following clocks.
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Pin No.
Name
I/O
15
REFIN
AI
Reference voltage input.
16
VDD
P
Power supply input.
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Description
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Specifications
Absolute Maximum Ratings (1)
Parameter
Supply Voltage, VDD – GND
Min
Input Voltage
Input Current: +IN, −IN (3)
Output Short-Circuit Duration
Max
Unit
7
V
GND –
0.3
VDD +
0.3
V
−20
20
mA
(2)
(4)
Indefinite
TJ
Maximum Junction Temperature
TA
Operating Temperature Range
TSTG
Storage Temperature Range
TL
Lead Temperature (Soldering 10 sec)
150
°C
−40
125
°C
−65
150
°C
260
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure
to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
(2) The supplies must be established simultaneously, with, or before, the application of any input signals.
(3) The inputs are protected by ESD protection diodes to the negative power supply. If the input extends more than 500 mV
beyond the negative power supply, the input current should be limited to less than 10 mA.
(4) A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power
supply voltage and how many amplifiers are shorted. The thermal resistance varies with the amount of PC board metal
connected to the package. The specified values are for short traces connected to the leads.
ESD, Electrostatic Discharge Protection
Symbol
HBM
Parameter
Condition
Human Body Model ESD
CDM
Charged Device Model ESD
Minimum Level
Unit
ANSI/ESDA/JEDEC JS-001
(1)
8
kV
ANSI/ESDA/JEDEC JS-002
(2)
2
kV
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Thermal Information
Package Type
TSSOP16
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θJA
θJC
Unit
180
35
°C/W
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Electrical Characteristics
All test conditions: VDD = 5 V, VREF = 5 V, CL = 100 pF, RL = 10 kΩ, TA = −40℃ to +105°C, unless otherwise noted. Typical
values are at TA = +25℃.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static Accuracy (1)
N
Resolution
INL
Integral Nonlinearity
DNL
Differential Nonlinearity
TPC112S4
12
TPC116S4
16
TPC112S4 (12-bit) (2)
−2
±0.25
2
−16
±8
16
TPC112S4 (12-bit) (2)
−1
±0.05
1
TPC116S4 (16-bit) (2)
−1
±0.5
1
6.5
30
mV
0
30
mV
TPC116S4 (16-bit)
(2)
Zero Offset Error
OE
Full-Scale Offset Error
−30
Offset-Error Drift
GE
Bits
±1
Gain Error
−0.3
Gain Temperature Coefficient
±0.13
LSB
LSB
μV/°C
0.3
%FS
ppmFS/°
±2
C
Reference Input
VREF
Reference-Input Voltage Range
RREF
Reference-Input Impedance
0.5
VDD
333
V
kΩ
DAC Output
Output Voltage Range
0
DC Output Impedance
CL
RL
Capacitive Load (3)
Resistive Load
VREF
0.1
V
Ω
Series resistance = 0 Ω
0.1
nF
Series resistance = 1 kΩ
15
μF
(3)
5
kΩ
Short-Circuit Current
VDD = 5.5 V
35
mA
Power-up Time
From power-down mode
25
μs
Digital Inputs (SCLK, DIN, SYNC)
VDD = 5 V
2
V
1.5
V
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Leakage Current
CIN
Input Capacitance
1
pF
VHYS
Hysteresis Voltage
0.15
V
1
V/μs
VDD = 3.3 V
VDD = 5 V
0.6
V
VDD = 3.3 V
0.4
V
±10
μA
VIN = 0 V or VDD
±5
Dynamic Performance (3)
SR
Voltage-Output Slew Rate
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Positive and negative
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Symbol
BW
Parameter
Conditions
Min
Typ
Max
Unit
Voltage-Output Settling Time
1/4 scale to 3/4 scale, to ≤ 0.5
LSB, 12 bits
14
μs
Reference −3-dB Bandwidth
Hex code = 800 (TPC112S4),
Hex code = 8000 (TPC116S4)
100
kHz
Digital Feedthrough
Code = 0, all digital inputs from 0
V to VDD, SCLK < 50 MHz
0.5
nV·s
DAC Glitch Impulse
Major code transition
2
nV·s
Output Noise
10 kHz
90
nV/√Hz
Integrated Output Noise
0.1 Hz to 10 Hz
25
μVP-P
Power Requirements
VDD
Supply Voltage
2.7
5.5
V
0.8
1.5
mA
0.5
1
mA
500
μA
VDD = 5 V, no load; all digital
IDD
inputs at 0 V or VDD, supply
current only; excludes reference
input current, midscale
Supply Current
VDD = 3.3 V, no load; all digital
IDD
inputs at 0 V or VDD, supply
current only; excludes reference
input current, midscale
Supply Current
Power-down Supply Current
No load, all digital inputs at 0 V or
VDD
(1) Linearity is tested within 20 mV of GND and VDD.
(2) Gain and offset are tested within 100 mV of GND and VDD.
(3) All timing specifications are measured with VIL = VGND, VIH = VDD.
Timing Characteristics
Figure 1. 16-Bit Serial-Interface Timing Diagram (TPC112S4)
Figure 2. 24-Bit Serial-Interface Timing Diagram (TPC116S4)
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Figure 3. LDAC Timing Diagram
Table 2. Timing Characteristics (Figures 1, 2 and 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
30
MHz
fSCLK
Serial Clock Frequency
0
tCH
SCLK Pulse-Width High
8
ns
tCL
SCLK Pulse-Width Low
8
ns
tCSS0
SYNC Fall to SCLK Fall Setup
Time
8
ns
tCSH0
SYNC Fall to SCLK Fall Hold
Time
0
ns
tCSH1
SYNC Rise to SCLK Fall Hold
Time
0
ns
tCSA
SYNC Rise to SCLK Fall
tCSF
SCLK Fall to SYNC Fall
tDS
12
ns
100
ns
DIN to SCLK Fall Setup Time
5
ns
tDH
DIN to SCLK Fall Hold Time
4.5
ns
tCSPW
SYNC Pulse-Width High
20
ns
tCLPW
SYNC Pulse-Width Low
20
ns
tCSC
SYNC Rise to SYNC Fall
20
ns
tL1
SCLK Falling Edge to LDAC
Falling Edge for Asynchronous
LDAC Update
50
ns
tL2
LDAC Pulse Width LOW Time
50
ns
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Typical Performance Characteristics
All test conditions: VS = 5 V, TA = +25℃, unless otherwise noted.
Figure 4. INL and DNL vs. Digital Input Code (+25℃
TPC116S4)
Figure 5. INL and DNL vs. Digital Input Code (−40°C
TPC116S4)
Figure 6. INL and DNL vs. Digital Input Code (+105°C
TPC116S4)
Figure 7. Power-Supply Current vs. Temperature
(TPC116S4)
Figure 8. Power-Supply Current vs. Temperature
(TPC116S4)
Figure 9. Zero-Scale Error vs. Temperature (TPC116S4)
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10 / 20
BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Figure 10. Zero-Scale Error vs. Temperature (TPC116S4)
Figure 11. Full-Scale Error vs. Temperature (TPC116S4)
Figure 12. Full-Scale Error vs. Temperature (TPC116S4)
Figure 13. Source and Sink Current Capability
(TPC116S4)
Figure 14. Source and Sink Current Capability
(TPC116S4)
Figure 15. Supply Current vs. Logic Input Voltage
(TPC116S4)
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Figure 16. Supply Current vs. Logic Input Voltage
(TPC116S4)
Figure 17. Supply Current vs. Supply Voltage
(TPC116S4)
Figure 18. Full-Scale Settling Time (2.7-V Falling Edge)
Figure 19. Full-Scale Settling Time (5-V Falling Edge)
Figure 20. Full-Scale Settling Time (5-V Rising Edge)
Figure 21. Full-Scale Settling Time (2.7-V Rising Edge)
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Detailed Description
Overview
The TPC116S4 and TPC112S4 are pin-compatible and software-compatible 12-bit and 16-bit DACs. The TPC116S4 and
TPC112S4 are 4-channel, low-power, high-reference input resistance, and buffered voltage-output DACs. The TPC116S4
and TPC112S4 minimize the digital noise feedthrough from their inputs to outputs by powering down the SCLK and DIN
input buffers after the completion of each data frame. The data frames are 16 bits for the TPC112S4 and 24 bits for the
TPC116S4. During power up, the TPC116S4 and TPC112S4 reset the DAC output to zero, providing additional safety for
applications that drive valves or other transducers which need to be off during power up. The TPC116S4 and TPC112S4
contain a segmented resistor string-type DAC, a serial-in/parallel-out shift register, a DAC register, a power-on-reset (POR)
circuit, and control logic. On the falling edge of the clock (SCLK) pulse, the serial input (DIN) data is shifted into the device,
MSB first.
Functional Block Diagram
Figure 22. Functional Block Diagram
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Application and Implementation
Note
Information in the following application sections is not part of the 3PEAK’s component specification and 3PEAK does not
warrant its accuracy or completeness. 3PEAK’s customers are responsible for determining suitability of components for
their purposes. Customers should validate and test their design implementation to confirm system functionality.
Application Information
DAC Reference (REF)
The external reference input features a typical input impedance of 333 kΩ and accepts an input voltage from +2 V to VDD.
Connect an external voltage supply between REF and GND to apply an external reference.
Serial Interface
The 3-wire serial interface of the TPC116S4/TPC112S4 is compatible with MICROWIRE, SPI, QSPI, and DSP. The interface
provides three inputs: SCLK, SYNC, and DIN. The chip-select input (SYNC) frames the serial data loading at DIN. Following
a chip-select input high-to-low transition, the data is shifted synchronously and latched into the input register on each falling
edge of the serial-clock input (SCLK). Each serial word is 16 bits for the TPC112S4 and 24 bits for the TPC116S4. The first
3 bits are the control bits followed by 1 power-down bit as well as 12 data bits (MSB first) for the TPC112S4 and 22 data bits
(MSB first) for the TPC116S4 as shown in Table 3 and Table 4. The serial input register transfers its contents to the input
registers after loading 16/24 bits of data and updates the DAC output immediately after the data is received on the 16-/24-bit
falling edge of the clock. To initiate a new data transfer, SYNC is driven high and kept for a minimum of 20 ns before the
next write sequence. The SCLK can be either high or low between SYNC write pulses. Figure 1 and Figure 2 show the timing
diagrams for the complete 3-wire serial interface transmission. The DAC code of the TPC116S4 is unipolar binary with VOUT =
(code / 65,536) × VREF, while that of the TPC112S4 is unipolar binary with VOUT = (code / 4096) × VREF.
Table 3. Operating Mode Truth Table (TPC112S4)
16-Bit Word
A2
A1
A0
PD
DAC Data Bit
D15
D14
D13
D12
D11～D0
1
0
0
0
X
Update DAC A Data
1
0
1
0
X
Update DAC B Data
1
1
0
0
X
Update DAC C Data
1
1
1
0
X
Update DAC D Data 100 k to
GND
X
X
X
1
X
Table 4. Operating Mode Truth Table (TPC116S4)
Function
Power down
24-Bit Word
A2
A1
A0
PD
DAC
Data Bit
D23
D22
D21
D20
D19
D18
D17
D16
D15～
D0
X
X
X
X
1
0
0
0
X
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Function
Update DAC A Data
BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
X
X
X
X
1
0
1
0
X
Update DAC B Data
X
X
X
X
1
1
0
0
X
Update DAC C Data
X
X
X
X
1
1
1
0
X
Update DAC D Data
X
X
X
X
X
X
X
1
X
Power down
Typical Application
Figure 23 shows the typical application schematic.
Figure 23. Typical Application Circuit
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Tape and Reel Information
Package
D1
(mm)
W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P0
(mm)
W0
(mm)
Pin1
Quadrant
TPC112S4-TR
TSSOP16
330
17.6
6.8
5.4
1.3
8
12
Q1
TPC116S4-TR
TSSOP16
330
17.6
6.8
5.4
1.3
8
12
Q1
Order Number
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Package Outline Dimensions
TSSOP16
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
Order Information
Operating Temperature
Range
Package
Marking Information
MSL
Transport Media, Quantity
Eco Plan
TPC112S4-TR
−40 to 125°C
TSSOP16
112S4
1
Tape and Reel, 3000
Green
TPC116S4-TR
−40 to 125°C
TSSOP16
116S4
1
Tape and Reel, 3000
Green
Order Number
Green: 3PEAK defines "Green" to mean RoHS compatible and free of halogen substances.
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
IMPORTANT NOTICE AND DISCLAIMER
Copyright© 3PEAK 2012-2024. All rights reserved.
Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks, and domain names contained in
this document /material are the property of 3PEAK. You may NOT reproduce, modify, publish, transmit or distribute any
Trademark without the prior written consent of 3PEAK.
Performance Information. Performance tests or performance range contained in this document/material are either results
of design simulation or actual tests conducted under designated testing environment. Any variation in testing environment or
simulation environment, including but not limited to testing method, testing process or testing temperature, may affect actual
performance of the product.
Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference
designs), application or other design recommendations, networking tools, security information and other resources "As Is".
3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including
without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any thirdparty’s intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to
be used in any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation,
aerospace, or any situations where failure could result in bodily harm, loss of life, or significant property damage. 3PEAK
disclaims all liability for any such unauthorized use.
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BA20241210A5
TPC116S4/TPC112S4
Quad 16-/12-Bit, Low-Power, High-Performance DACs
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