Data sheet
BMX055
Small, versatile 9-axis sensor module
Bosch Sensortec
BMX055: Data sheet
Document revision
1.1
Document release date
November 7 , 2014
Document number
BST-BMX055-DS000-02
Technical reference code(s)
0 273 141 179
Notes
Data and descriptions within this document are subject to
change without notice.
Product photos and pictures are for illustration purposes only and
may differ from the real product’s appearance.
th
BMX055
Data sheet
Page 2
BMX055
Basic Description
Key features
3 sensors in one device
Small package
Common voltage supplies
Digital interface
Smart operation and integration
Consumer electronics suite
Accelerometer features
Programmable functionality
On-chip FIFO
On-chip interrupt controller
On-chip temperature sensor
Ultra-low power IC
Gyroscope features
Programmable functionality
On-chip FIFO
On-chip interrupt controller
Low power IC
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
an advanced triaxial 16bit gyroscope, a
versatile, leading edge triaxial 12bit accelerometer
and a full performance geomagnetic sensor
LGA package 20 pins
footprint 3.0 x 4.5 mm², height 0.95mm
VDD voltage range: 2.4V to 3.6V
SPI (4-wire, 3-wire), I²C, 4 interrupt pins
VDDIO voltage range: 1.2V to 3.6V
All sensors can be operated individually
9-axis FusionLib software compatible
MSL1, RoHS and RoHS2 compliant, halogen-free
Operating temperature: -40°C ... +85°C
Acceleration ranges ±2g/±4g/±8g/±16g
Low-pass filter bandwidths 1kHz - =31.25 Hz:
tactive = tut + tw,up1 - 0.9 ms (or tactive = tut + tw,up2 - 0.9 ms)
else:
tactive = 4 tut + tw,up1 - 0.9 ms (or tactive = 4 tut + tw,up2 - 0.9 ms)
During the wake-up phase all analog modules are held powered-up, while during the sleep
phase most analog modules are powered down. Consequently, a wake-up time of more than
tw,up1 (tw,up2) ms is needed to settle the analog modules so that reliable acceleration data are
generated.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
5.2
Page 27
IMU data accelerometer
5.2.1
Acceleration data
The width of acceleration data is 12 bits given in two´s complement representation. The 12 bits
for each axis are split into an MSB upper part (one byte containing bits 11 to 4) and an LSB
lower part (one byte containing bits 3 to 0 of acceleration and a (ACC 0x02, 0x04, 0x06)
new_data flag). Reading the acceleration data registers shall always start with the LSB part. In
order to ensure the integrity of the acceleration data, the content of an MSB register is locked by
reading the corresponding LSB register (shadowing procedure). When shadowing is enabled,
the MSB must always be read in order to remove the data lock. The shadowing procedure can
be disabled (enabled) by writing ´1´ (´0´) to the bit shadow_dis. With shadowing disabled, the
content of both MSB and LSB registers is updated by a new value immediately. Unused bits of
the LSB registers may have any value and should be ignored. The (ACC 0x02, 0x04, 0x06)
new_data flag of each LSB register is set if the data registers have been updated. The flag is
reset if either the corresponding MSB or LSB part is read.
Two different streams of acceleration data are available, unfiltered and filtered. The unfiltered
data is sampled with 2kHz. The sampling rate of the filtered data depends on the selected filter
bandwidth and is always twice the selected bandwidth (BW = ODR/2). Which kind of data is
stored in the acceleration data registers depends on bit (ACC 0x13) data_high_bw. If (ACC
0x13) data_high_bw is ´0´ (´1´), then filtered (unfiltered) data is stored in the registers. Both
data streams are offset-compensated.
The bandwidth of filtered acceleration data is determined by setting the (ACC 0x10) bw bit as
followed:
Table 7: Bandwidth configuration
bw
Bandwidth
00xxx
01000
01001
01010
01011
01100
01101
01110
01111
1xxxx
*)
7.81Hz
15.63Hz
31.25Hz
62.5Hz
125Hz
250Hz
500Hz
1000Hz
*)
Update Time
tut
64ms
32ms
16ms
8ms
4ms
2ms
1ms
0.5ms
-
*) Note: Settings 00xxx result in a bandwidth of 7.81 Hz; settings 1xxxx result in a bandwidth of
1000 Hz. It is recommended to actively set an application specific and an appropriate bandwidth
and to use the range from ´01000b´ to ´01111b´ only in order to be compatible with future
products.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 28
The accelerometer supports four different acceleration measurement ranges. A measurement
range is selected by setting the (ACC 0x0F) range bits as follows:
Table 8: Range selection
Range
0011
0101
1000
1100
others
Acceleration
measurement
range
±2g
±4g
±8g
±16g
reserved
Resolution
0.98mg/LSB
1.95mg/LSB
3.91mg/LSB
7.81mg/LSB
-
5.2.2
Temperature Sensor
The width of temperature data is 8 bits given in two´s complement representation. Temperature
values are available in the (ACC 0x08) temp register.
The slope of the temperature sensor is 0.5K/LSB, its center temperature is 23°C [(ACC 0x08)
temp = 0x00].
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
5.3
Page 29
Self-test accelerometer
This feature permits to check the sensor functionality by applying electrostatic forces to the
sensor core instead of external accelerations. By actually deflecting the seismic mass, the
entire signal path of the sensor can be tested. Activating the self-test results in a static offset of
the acceleration data; any external acceleration or gravitational force applied to the sensor
during active self-test will be observed in the output as a superposition of both acceleration and
self-test signal.
Before the self-test is enabled the g-range should be set to 8 g. The self-test is activated
individually for each axis by writing the proper value to the (ACC 0x32) self_test_axis bits (´01b´
for x-axis, ´10b´ for y-axis, ´11b´ for z-axis, ´00b´ to deactivate self-test). It is possible to control
the direction of the deflection through bit (ACC 0x32) self_test_sign. The excitation occurs in
negative (positive) direction if (ACC 0x32) self_test_sign = ´0b´ (´1b´). The amplitude of the
deflection has to be set high by writing (ACC 0x32) self_test_amp=´1b´. After the self-test is
enabled, the user should wait 50ms before interpreting the acceleration data.
In order to ensure a proper interpretation of the self-test signal it is recommended to perform the
self-test for both (positive and negative) directions and then to calculate the difference of the
resulting acceleration values. Table 9 shows the minimum differences for each axis. The
actually measured signal differences can be significantly larger.
Table 9: Self-test difference values
x-axis signal
y-axis signal
z-axis signal
800 mg
800 mg
400 mg
resulting minimum
difference signal
It is recommended to perform a reset of the device after a self-test has been performed. If the
reset cannot be performed, the following sequence must be kept to prevent unwanted interrupt
generation: disable interrupts, change parameters of interrupts, wait for at least 50ms, enable
desired interrupts.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
5.4
Page 30
Offset compensation accelerometer
Offsets in measured signals can have several causes but they are always unwanted and
disturbing in many cases. Therefore, the accelerometer offers an advanced set of four digital
offset compensation methods which are closely matched to each other. These are slow, fast,
and manual compensation as well as inline calibration.
The compensation is performed with filtered data, and is then applied to both, unfiltered and
filtered data. If necessary the result of this computation is saturated to prevent any overflow
errors (the smallest or biggest possible value is set, depending on the sign). However, the
registers used to read and write compensation values have a width of 8 bits.
An overview of the offset compensation principle is given in Figure 5:
I2C/SPI/NVM mapping
12 bit acceleration data range
+-16g
+-8g
+-4g
8g
Sign
4g
4g
Sign
2g
2g
2g
Sign
1g
1g
1g
1g
500mg
500mg
500mg
500mg
500mg
250mg
250mg
250mg
250mg
250mg
125mg
125mg
125mg
125mg
62.5mg
62.5mg
62.5mg
62.5mg
31.2mg
31.2mg
31.2mg
31.2mg
31.2mg
15.6mg
15.6mg
15.6mg
15.6mg
15.6mg
7.8mg
7.8mg
7.8mg
7.8mg
3.9mg
3.9mg
MSB
125mg
Read/
Write
62.5mg
LSB
Sign
Sign
+-2g
MSB
MSB
-
1.9mg
LSB
MSB
LSB
MSB
LSB
LSB
7.8mg
3.9mg
1.9mg
0.97mg
Figure 5: Principle of offset compensation
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 31
The public offset compensation registers (ACC 0x38) offset_x, (ACC 0x39) offset_y, (ACC
0x3A) offset_z are images of the corresponding registers in the NVM. With each image update
(see section 5.5 Non-volatile memory accelerometer for details) the contents of the NVM
registers are written to the public registers. The public registers can be over-written by the user
at any time. After changing the contents of the public registers by either an image update or
manually, all 8bit values are extended to 12bit values for internal computation. In the opposite
direction, if an internally computed value changes it is converted to an 8bit value and stored in
the public register.
Depending on the selected g-range the conversion from 12bit to 8bit values can result in a loss
of accuracy of one to several LSB. This is shown in Figure 5.
In case an internally computed compensation value is too small or too large to fit into the
corresponding register, it is saturated in order to prevent an overflow error.
By writing ´1´ to the (ACC 0x36) offset_reset bit, all offset compensation registers are reset to
zero.
5.4.1
Fast compensation
st
Slow compensation is based on a 1 order high-pass filter, which continuously drives the
average value of the output data stream of each axis to zero. The bandwidth of the high-pass
filter is configured with bit (ACC 0x37) cut_off according to Table 10.
Table 10: Compensation period settings
(ACC 0x37)
cut_off
0b
1b
high-pass filter
bandwidth
1
10 Hz
The slow compensation can be enabled (disabled) for each axis independently by setting the
bits (ACC 0x36) hp_x_en, hp_y_en, hp_z_en to ´1´ (´0´), respectively.
Slow compensation should not be used in combination with low-power mode. In low-power
mode the conditions (availability of necessary data) for proper function of slow compensation
are not fulfilled.
5.4.2
Fast compensation
Fast compensation is a one-shot process by which the compensation value is set in such a way
that when added to the raw acceleration, the resulting acceleration value of each axis
approaches the target value. This is best suited for “end-of-line trimming” with the customer’s
device positioned in a well-defined orientation. For fast compensation the g-range has to be
switched to 2g.
The algorithm in detail: An average of 16 consecutive acceleration values is computed and the
difference between target value and computed value is written to (ACC 0x38, 0x39, 0x3A)
offset_filt_x/y/z. The public registers (ACC 0x38, 0x39, 0x3A) offset_filt_x/y/z are updated with
the contents of the internal registers (using saturation if necessary) and can be read by the
user.
Fast compensation is triggered for each axis individually by setting the (ACC 0x36) cal_trigger
bits as shown in Table 11:
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 32
Table 11: Fast compensation axis selection
(ACC 0x36)
cal_trigger
00b
01b
10b
11b
Selected Axis
none
x
y
z
Register (ACC 0x36) cal_trigger is a write-only register. Once triggered, the status of the fast
correction process is reflected in the status bit (ACC 0x36) cal_rdy. Bit (ACC 0x36) cal_rdy is ‘0’
while the correction is in progress. Otherwise it is ‘1’. Bit (ACC 0x36) cal_rdy is ´0´ when (ACC
0x36) cal_trigger is not ´00´.
For the fast offset compensation, the compensation target can be chosen by setting the bits
(ACC 0x37) offset_target_x, (ACC 0x37) offset_target_y, and (ACC 0x37) offset_target_z
according to Table 12:
Table 12: Offset target settings
(ACC 0x37)
offset_target_x/y/z
00b
01b
10b
11b
Target value
0g
+1g
-1g
0g
Fast compensation should not be used in combination with any of the low-power modes. In lowpower mode the conditions (availability of necessary data) for proper function of fast
compensation are not fulfilled.
5.4.3
Manual compensation
The contents of the public compensation registers (ACC 0x38, 0x39, 0x3A) offset_filt_x/y/z can
be set manually via the digital interface. It is recommended to write into these registers directly
after a new data interrupt has occurred in order not to disturb running offset computations.
Writing to the offset compensation registers is not allowed while the fast compensation
procedure is running.
5.4.4
Inline calibration
For certain applications, it is often desirable to calibrate the offset once and to store the
compensation values permanently. This can be achieved by using one of the aforementioned
offset compensation methods to determine the proper compensation values and then storing
these values permanently in the NVM. See section 5.5 Non-volatile memory accelerometer for
details of the storing procedure.
Each time the device is reset, the compensation values are loaded from the non-volatile
memory into the image registers and used for offset compensation. until they are possibly
overwritten using one of the other compensation methods.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
5.5
Page 33
Non-volatile memory accelerometer
The entire memory of the accelerometer consists of three different kinds of registers: hardwired, volatile, and non-volatile. Part of it can be both read and written by the user. Access to
non-volatile memory is only possible through (volatile) image registers.
Altogether, there are eight registers (octets) with NVM backup which are accessible by the user.
The addresses of the image registers range from (ACC 0x38) to (ACC 0x3C). While the
addresses up to (ACC 0x3A) are used for offset compensation (see 5.4 Offset Compensation),
addresses (ACC 0x3B) and (ACC 0x3C) are general purpose registers not linked to any
sensor-specific functionality.
The content of the NVM is loaded to the image registers after a reset (either POR or softreset)
or after a user request which is performed by writing ´1´ to the write-only bit (ACC 0x33)
nvm_load. As long as the image update is in progress, bit (ACC 0x33) nvm_rdy is ´0´,
otherwise it is ´1´.
The image registers can be read and written like any other register.
Writing to the NVM is a three-step procedure:
1. Write the new contents to the image registers.
2. Write ´1´ to bit (ACC 0x33) nvm_prog_mode in order to unlock the NVM.
3. Write ´1´ to bit (ACC 0x33) nvm_prog_trig and keep ´1´ in bit (ACC 0x33)
nvm_prog_mode in order to trigger the write process.
Writing to the NVM always renews the entire NVM contents. It is possible to check the write
status by reading bit (ACC 0x33) nvm_rdy. While (ACC 0x33) nvm_rdy = ´0´, the write process
is still in progress; if (ACC 0x33) nvm_rdy = ´1´, then writing is completed. As long as the write
process is ongoing, no change of power mode and image registers is allowed. Also, the NVM
write cycle must not be initiated while image registers are updated, in low-power mode, and in
suspend mode.
Please note that the number of permitted NVM write-cycles is limited as specified in table 2.
The number of remaining write-cycles can be obtained by reading bits (ACC 0x33)
nvm_remain.
5.6
Interrupt controller accelerometer
The accelerometer is equipped with eight programmable interrupt engines. Each interrupt can
be independently enabled and configured. If the trigger condition of an enabled interrupt is
fulfilled, the corresponding status bit is set to ´1´ and the selected interrupt pin is activated. The
accelerometer provides two interrupt pins, INT1 and INT2; interrupts can be freely mapped to
any of these pins. The state of a specific interrupt pin is derived from a logic ´or´ combination of
all interrupts mapped to it.
The interrupt status registers are updated when a new data word is written into the acceleration
data registers. If an interrupt is disabled, all active status bits associated with it are immediately
reset.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 34
5.6.1
General features
An interrupt is cleared depending on the selected interrupt mode, which is common to all
interrupts. There are three different interrupt modes: non-latched, latched, and temporary. The
mode is selected by the (ACC 0x21) latch_int bits according to Table 13.
Table 13: Interrupt mode selection
(ACC 0x21) latch_int
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Interrupt mode
non-latched
temporary, 250ms
temporary, 500ms
temporary, 1s
temporary, 2s
temporary, 4s
temporary, 8s
latched
non-latched
temporary, 250µs
temporary, 500µs
temporary, 1ms
temporary, 12.5ms
temporary, 25ms
temporary, 50ms
latched
An interrupt is generated if its activation condition is met. It cannot be cleared as long as the
activation condition is fulfilled. In the non-latched mode the interrupt status bit and the selected
pin (the contribution to the ´or´ condition for INT1 and/or INT2) are cleared as soon as the
activation condition is no more valid. Exceptions to this behavior are the new data, orientation,
and flat interrupts, which are automatically reset after a fixed time.
In latched mode an asserted interrupt status and the selected pin are cleared by writing ´1´ to
bit (ACC 0x21) reset_int. If the activation condition still holds when it is cleared, the interrupt
status is asserted again with the next change of the acceleration registers.
In the temporary mode an asserted interrupt and selected pin are cleared after a defined period
of time. The behavior of the different interrupt modes is shown graphically in Figure 6. The
timings in this mode are subject to the same tolerances as the bandwidths (see table 2).
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 35
internal signal from
interrupt engine
interrupt output
non-latched
latch period
temporary
latched
Figure 6: Interrupt modes
Several interrupt engines can use either unfiltered or filtered acceleration data as their input. For
these interrupts, the source can be selected with the bits in register (ACC 0x1E). These are
(ACC 0x1E) int_src_data, (ACC 0x1E) int_src_tap, (ACC 0x1E) int_src_slo_no_mot, (ACC
0x1E) int_src_slope, (ACC 0x1E) int_src_high, and (ACC 0x1E) int_src_low. Setting the
respective bits to ´0´ (´1´) selects filtered (unfiltered) data as input. The orientation recognition
and flat detection interrupt always use filtered input data.
It is strongly recommended to set interrupt parameters prior to enabling the interrupt. Changing
parameters of an already enabled interrupt may cause unwanted interrupt generation and
generation of a false interrupt history. A safe way to change parameters of an enabled interrupt
is to keep the following sequence: disable the desired interrupt, change parameters, wait for at
least 10ms, and then re-enable the desired interrupt.
5.6.2
Mapping to physical interrupt pins (inttype to INT Pin#)
Registers (ACC 0x19) to (ACC 0x1B) are dedicated to mapping of interrupts to the interrupt pins
“INT1” or “INT2”. Setting (ACC 0x19) int1_”inttype” to ´1´ (´0´) maps (unmaps) “inttype” to pin
“INT1”. Correspondingly setting (ACC 0x1B) int2_”inttype” to ´1´ (´0´) maps (unmaps) “inttype”
to pin “INT2”.
Note: “inttype” to be replaced with the precise notation, given in the memory map in chapter 6.
Example: For flat interrupt (int1_flat): Setting (ACC 0x19) int1_flat to ´1´ maps int1_flat to pin
“INT1”.
5.6.3
Electrical behavior (INT pin# to open-drive or push-pull)
Both interrupt pins can be configured to show the desired electrical behavior. The ´active´ level
of each interrupt pin is determined by the (ACC 0x20) int1_lvl and (ACC 0x20) int2_lvl bits.
If (ACC 0x20) int1_lvl = ´1´ (´0´) / (ACC 0x20) int2_lvl = ´1´ (´0´), then pin “INT1” / pin “INT2” is
active ´1´ (´0´). The characteristic of the output driver of the interrupt pins may be configured
with bits (ACC 0x20) int1_od and (ACC 0x20) int2_od. By setting bits (ACC 0x20) int1_od /
(ACC 0x20) int2_od to ´1´, the output driver shows open-drive characteristic, by setting the
configuration bits to ´0´, the output driver shows push-pull characteristic. When open-drive
characteristic is selected in the design, external pull-up or pull-down resistor should be applied
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 36
according the int_lvl configuration. When open-drive characteristic is selected in the design,
external pull-up or pull-down resistor should be applied according the int_lvl configuration.
5.6.4
New data interrupt
This interrupt serves for synchronous reading of acceleration data. It is generated after storing a
new value of z-axis acceleration data in the data register. The interrupt is cleared automatically
when the next data acquisition cycle starts. The interrupt status is ´0´ for at least 50µs.
The interrupt mode of the new data interrupt is fixed to non-latched.
It is enabled (disabled) by writing ´1´ (´0´) to bit (ACC 0x17) data_en. The interrupt status is
stored in bit (ACC 0x0A) data_int.
Due to the settling time of the filter, the first interrupt after wake-up from suspend or standby
mode will take longer than the update time.
5.6.5
Slope / any-motion detection
Slope / any-motion detection uses the slope between successive acceleration signals to detect
changes in motion. An interrupt is generated when the slope (absolute value of acceleration
difference) exceeds a preset threshold. It is cleared as soon as the slope falls below the
threshold. The principle is made clear in Figure 7.
acceleration
acc(t0)
acc(t0−1/(2*bw))
time
slope(t0)=acc(t0)−acc(t0−1/(2*bw))
slope
slope_th
time
slope_dur
slope_dur
INT
time
Figure 7: Principle of any-motion detection
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 37
The threshold is defined through register (ACC 0x28) slope_th. In terms of scaling 1 LSB of
(ACC 0x28) slope_th corresponds to 3.91 mg in 2g-range (7.81 mg in 4g-range, 15.6 mg in 8grange and 31.3 mg in 16g-range). Therefore the maximum value is 996 mg in 2g-range (1.99g
in 4g-range, 3.98g in 8g-range and 7.97g in 16g-range).
The time difference between the successive acceleration signals depends on the selected
bandwidth and equates to 1/(2*bandwidth) (t=1/(2*bw)). In order to suppress false triggers, the
interrupt is only generated (cleared) if a certain number N of consecutive slope data points is
larger (smaller) than the slope threshold given by (ACC 0x28) slope_th. This number is set by
the (ACC 0x27) slope_dur bits. It is N = (ACC 0x27) slope_dur + 1 for (ACC 0x27).
Example: (ACC 0x27) slope_dur = 00b, …, 11b = 1decimal, …, 4decimal.
5.6.5.1
Enabling (disabling) for each axis
Any-motion detection can be enabled (disabled) for each axis separately by writing ´1´ (´0´) to
bits (ACC 0x16) slope_en_x, (ACC 0x16) slope_en_y, (ACC 0x16) slope_en_z. The criteria for
any-motion detection are fulfilled and the slope interrupt is generated if the slope of any of the
enabled axes exceeds the threshold (ACC 0x28) slope_th for [(ACC 0x27) slope_dur +1]
consecutive times. As soon as the slopes of all enabled axes fall or stay below this threshold for
[(ACC 0x27) slope_dur +1] consecutive times the interrupt is cleared unless interrupt signal is
latched.
5.6.5.2
Axis and sign information of slope / any motion interrupt
The interrupt status is stored in bit (ACC 0x09) slope_int. The any-motion interrupt supplies
additional information about the detected slope. The axis which triggered the interrupt is given
by that one of bits (ACC 0x0B) slope_first_x, (ACC 0x0B) slope_first_y, (ACC 0x0B)
slope_first_z that contains a value of ´1´. The sign of the triggering slope is held in bit (ACC
0x0B) slope_sign until the interrupt is retriggered. If (ACC 0x0B) slope_sign = ´0´ (´1´), the sign
is positive (negative).
5.6.6
Tap sensing
Tap sensing has a functional similarity with a common laptop touch-pad or clicking keys of a
computer mouse. A tap event is detected if a pre-defined slope of the acceleration of at least
one axis is exceeded. Two different tap events are distinguished: A ‘single tap’ is a single event
within a certain time, followed by a certain quiet time. A ‘double tap’ consists of a first such
event followed by a second event within a defined time frame.
Single tap interrupt is enabled (disabled) by writing ´1´ (´0´) to bit (ACC 0x16) s_tap_en. Double
tap interrupt is enabled (disabled) by writing ´1´ (´0´) to bit (ACC 0x16) d_tap_en.
The status of the single tap interrupt is stored in bit (ACC 0x09) s_tap_int, the status of the
double tap interrupt is stored in bit (ACC 0x09) d_tap_int.
The slope threshold for detecting a tap event is set by bits (ACC 0x2B) tap_th. The meaning of
(ACC 0x2B) tap_th depends on the range setting. 1 LSB of (ACC 0x2B) tap_th corresponds to
a slope of 62.5mg in 2g-range, 125mg in 4g-range, 250mg in 8g-range, and 500mg in 16grange.
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In Figure 8 the meaning of the different timing parameters is visualized:
slope
1st tap
2nd tap
tap_th
time
tap_shock
tap_quiet
tap_dur
tap_shock
tap_quiet
single tap detection
12.5 ms
time
double tap detection
12.5 ms
time
Figure 8: Timing of tap detection
The parameters (ACC 0x2A) tap_shock and (ACC 0x2A) tap_quiet apply to both single tap and
double tap detection, while (ACC 0x2A) tap_dur applies to double tap detection only. Within the
duration of (ACC 0x2A) tap_shock any slope exceeding (ACC 0x2B) tap_th after the first event
is ignored. Contrary to this, within the duration of (ACC 0x2A) tap_quiet no slope exceeding
(ACC 0x2B) tap_th must occur, otherwise the first event will be cancelled.
5.6.6.1
Single tap detection
A single tap is detected and the single tap interrupt is generated after the combined durations of
(ACC 0x2A) tap_shock and (ACC 0x2A) tap_quiet, if the corresponding slope conditions are
fulfilled. The interrupt is cleared after a delay of 12.5 ms.
Do not map single-tap to any INT pin if you do not want to use it.
5.6.6.2
Double tap detection
A double tap interrupt is generated if an event fulfilling the conditions for a single tap occurs
within the set duration in (ACC 0x2A) tap_dur after the completion of the first tap event. The
interrupt is automatically cleared after a delay of 12.5 ms.
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5.6.6.3
Selecting the timing of tap detection
For each of parameters (ACC 0x2A) tap_shock and (ACC 0x2A) tap_quiet two values are
selectable. By writing ´0´ (´1´) to bit (ACC 0x2A) tap_shock the duration of (ACC 0x2A)
tap_shock is set to 50 ms (75 ms). By writing ´0´ (´1´) to bit (ACC 0x2A) tap_quiet the duration
of (ACC 0x2A) tap_quiet is set to 30 ms (20 ms).
The length of (ACC 0x2A) tap_dur can be selected by setting the (ACC 0x2A) tap_dur bits
according to Table 14:
Table 14: Selection of tap_dur
(ACC 0x2A) tap_dur
000b
001b
010b
011b
100b
101b
110b
111b
length of tap_dur
50 ms
100 ms
150 ms
200 ms
250 ms
375 ms
500 ms
700 ms
5.6.6.4
Axis and sign information of tap sensing
The sign of the slope of the first tap which triggered the interrupt is stored in bit (ACC 0x0B)
tap_sign (´0´ means positive sign, ´1´ means negative sign). The value of this bit persists after
clearing the interrupt.
The axis which triggered the interrupt is indicated by bits (ACC 0x0B) tap_first_x, (ACC 0x0B)
tap_first_y, and (ACC 0x0B) tap_first_z.
The bit corresponding to the triggering axis contains a ´1´ while the other bits hold a ´0´. These
bits are cleared together with clearing the interrupt status.
5.6.6.5
Tap sensing in low power mode
In low-power mode, a limited number of samples is processed after wake-up to decide whether
an interrupt condition is fulfilled. The number of samples is selected by bits (ACC 0x2B)
tap_samp according to Table 15.
Table 15: Meaning of (ACC 0x2B) tap_samp
(ACC 0x2B) tap_samp
00b
01b
10b
11b
Number of Samples
2
4
8
16
5.6.7
Orientation recognition
The orientation recognition feature informs on an orientation change of the sensor with respect
to the gravitational field vector ‘g’. The measured acceleration vector components with respect
to the gravitational field are defined as shown in Figure 9.
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Figure 9: Definition of vector components
Therefore, the magnitudes of the acceleration vectors are calculated as follows:
acc_x = 1g x sin x cos
acc_y = −1g x sin x sin
acc_z = 1g x cos
acc_y/acc_x = −tan
Depending on the magnitudes of the acceleration vectors the orientation of the device in the
space is determined and stored in the three (ACC 0x0C) orient bits. These bits may not be reset
in the sleep phase of low-power mode. There are three orientation calculation modes with
different thresholds for switching between different orientations: symmetrical, highasymmetrical, and low-asymmetrical. The mode is selected by setting the (ACC 0x2C)
orient_mode bits as given in Table 16.
Table 16: Orientation mode settings
(ACC 0x2C) orient_mode
00b
01b
10b
11b
Orientation Mode
symmetrical
high-asymmetrical
low-asymmetrical
symmetrical
For each orientation mode the (ACC 0x0C) orient bits have a different meaning as shown in
Table 17 to Table 19:
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Table 17: Meaning of the (ACC 0x0C) orient bits in symmetrical mode
(ACC 0x0C) orient
Name
Angle
x00
portrait upright
315° < < 45°
x01
portrait upside down
135° < < 225°
x10
landscape left
45° < < 135°
x11
landscape right
225° < < 315°
Condition
|acc_y| < |acc_x| - ‘hyst’
and acc_x - ‘hyst’’ ≥ 0
|acc_y| < |acc_x| - ‘hyst’
and acc_x + ‘hyst’ < 0
|acc_y| ≥ |acc_x| + ‘hyst’
and acc_y < 0
|acc_y| ≥ |acc_x| + ‘hyst’
and acc_y ≥ 0
Table 18: Meaning of the (ACC 0x0C) orient bits in high-asymmetrical mode
(ACC 0x0C) orient
Name
Angle
x00
portrait upright
297° < < 63°
x01
portrait upside down
117° < < 243°
x10
landscape left
63° < < 117°
x11
landscape right
243° < < 297°
Condition
|acc_y| < 2∙|acc_x| - ‘hyst’
and acc_x - ‘hyst’ ≥ 0
|acc_y| < 2∙|acc_x| - ‘hyst’
and acc_x + ‘hyst’ < 0
|acc_y| ≥ 2∙|acc_x| + ‘hyst’
and acc_y < 0
|acc_y| ≥ 2∙|acc_x| + ‘hyst’
and acc_y ≥ 0
Table 19: Meaning of the (ACC 0x0C) orient bits in low-asymmetrical mode
(ACC 0x0C) orient
Name
Angle
x00
portrait upright
333° < < 27°
x01
portrait upside down
153° < < 207°
x10
landscape left
27° < < 153°
x11
landscape right
207° < < 333°
Condition
|acc_y| < 0.5∙|acc_x| - ‘hyst’
and acc_x - ‘hyst’ ≥ 0
|acc_y| < 0.5∙|acc_x| - ‘hyst’
and acc_x + ‘hyst’ < 0
|acc_y| ≥ 0.5∙|acc_x| +
‘hyst’
and acc_y < 0
|acc_y| ≥ 0.5∙|acc_x| +
‘hyst’
and acc_y ≥ 0
In the preceding tables, the parameter ‘hyst’ stands for a hysteresis, which can be selected by
setting the (ACC 0x2C) orient_hyst bits. 1 LSB of (ACC 0x2C) orient_hyst always corresponds
to 62.5 mg, in any g-range (i.e. increment is independent from g-range setting). It is important to
note that by using a hysteresis ≠ 0 the actual switching angles become different from the angles
given in the tables since there is an overlap between the different orientations.
The most significant bit of the (ACC 0x0C) orient bits (which is displayed as an ´x´ in the above
given tables) contains information about the direction of the z-axis. It is set to ´0´ (´1´) if acc_z ≥
0 (acc_z < 0).
Figure 10 shows the typical switching conditions between the four different orientations for the
symmetrical mode i.e. without hysteresis:
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portrait
portraitupright
upright
landscape left
portrait
portraitupside
upside
down
Page 42
landscape
landscaperight
right
portrait upright
2
1.5
1
0.5
0
0
45
90
135
180
225
270
315
360
-0.5
acc_y/acc_x
-1
acc_x/sin(theta)
-1.5
acc_y/sin(theta)
-2
phi
Figure 10: Typical orientation switching conditions w/o hysteresis
The orientation interrupt is enabled (disabled) by writing ´1´ (´0´) to bit (ACC 0x16) orient_en.
The interrupt is generated if the value of (ACC 0x0C) orient has changed. It is automatically
cleared after one stable period of the (ACC 0x0C) orient value. The interrupt status is stored in
the (ACC 0x09) orient_int bit. The register (ACC 0x0C) orient always reflects the current
orientation of the device, irrespective of which interrupt mode has been selected. Bit (ACC
0x0C) orient reflects the device orientation with respect to the z-axis. The bits (ACC 0x0C)
orient reflect the device orientation in the x-y-plane. The conventions associated with
register (ACC 0x0C) orient are detailed in chapter 6.
5.6.7.1
Orientation blocking
The change of the (ACC 0x0C) orient value and – as a consequence – the generation of the
interrupt can be blocked according to conditions selected by setting the value of the (ACC
0x2C) orient_blocking bits as described by Table 20.
Table 20: Blocking conditions for orientation recognition
(ACC 0x2C) orient_blocking
00b
01b
10b
11b
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Conditions
no blocking
theta blocking
or
acceleration in any axis > 1.5g
theta blocking
or
acceleration slope in any axis > 0.2 g
or
acceleration in any axis > 1.5g
theta blocking
or
acceleration slope in any axis > 0.4 g
or
acceleration in any axis > 1.5g and value of orient is
not stable for at least 100 ms
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The theta blocking is defined by the following inequality:
tan
blocking _ theta
.
8
The parameter blocking_theta of the above given equation stands for the contents of the (ACC
0x2D) orient_theta bits. It is possible to define a blocking angle between 0° and 44.8°. The
internal blocking algorithm saturates the acceleration values before further processing. As a
consequence, the blocking angles are strictly valid only for a device at rest; they can be
different if the device is moved.
Example:
To get a maximum blocking angle of 19° the parameter blocking_theta is determined in the
following way: (8 * tan(19°) )² = 7.588, therefore, blocking_value = 8dec = 001000b has to be
chosen.
In order to avoid unwanted generation of the orientation interrupt in a nearly flat position (z ~ 0,
sign change due to small movements or noise), a hysteresis of 0.2 g is implemented for the zaxis, i. e. a after a sign change the interrupt is only generated after |z| > 0.2 g.
5.6.7.2
Up-Down Interrupt Suppression Flag
Per default an orientation interrupt is triggered when any of the bits in register (ACC 0x0C)
orient changes state. The accelerometer can be configured to trigger orientation interrupts only
when the device position changes in the x-y-plane while orientation changes with respect to the
z-axis are ignored. A change of the orientation of the z-axis, and hence a state change of bit
(ACC 0x0C) orient is ignored (considered) when bit (ACC 0x2D) orient_ud_en is set to ‘0’
(‘1’).
5.6.8
Flat detection
The flat detection feature gives information about the orientation of the devices´ z-axis relative
to the g-vector, i. e. it recognizes whether the device is in a flat position or not.
The flat angle is adjustable by (0x2E) flat_theta from 0° to 44.8°. The flat angle can be set
according to following formula:
1
atan
flat_theta
8
A hysteresis of the flat detection can be enabled by (0x2F) flat_hy bits. In this case the flat
position is set if the angle drops below following threshold:
1
flat _ hy flat _ hy
hyst,ll atan
flat_theta 1
8
1024
16
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The flat position is reset if the angle exceeds the following threshold:
1
flat _ hy flat _ hy
hyst,ul atan flat_theta 1
8
1024
16
The flat interrupt is enabled (disabled) by writing ´1´ (´0´) to bit (ACC 0x16) flat_en. The flat
value is stored in the (ACC 0x0C) flat bit if the interrupt is enabled. This value is ´1´ if the device
is in the flat position, it is ´0´ otherwise. The flat interrupt is generated if the flat value has
changed and the new value is stable for at least the time given by the (ACC 0x2F)
flat_hold_time bits. A flat interrupt may be also generated if the flat interrupt is enabled. The
actual status of the interrupt is stored in the (ACC 0x09) flat_int bit. The flat orientation of the
sensor can always be determined from reading the (ACC 0x0C) flat bit after interrupt
generation. If unlatched interrupt mode is used, the (ACC 0x09) flat_int value and hence the
interrupt is automatically cleared after one sample period. If temporary or latched interrupt mode
is used, the (ACC 0x09) flat_int value is kept fixed until the latch time expires or the interrupt is
reset.
The meaning of the (ACC 0x2F) flat_hold_time bits can be seen from Table 21.
Table 21: Meaning of flat_hold_time
(ACC 0x2F) flat_hold_time
00b
01b
10b
11b
Time
0
512 ms
1024 ms
2048 ms
5.6.9
Low-g interrupt
This interrupt is based on the comparison of acceleration data against a low-g threshold, which
is most useful for free-fall detection.
The interrupt is enabled (disabled) by writing ´1´ (´0´) to the (ACC 0x17) low_en bit. There are
two modes available, ‘single’ mode and ‘sum’ mode. In ‘single’ mode, the acceleration of each
axis is compared with the threshold; in ‘sum’ mode, the sum of absolute values of all
accelerations |acc_x| + |acc_y| + |acc_z| is compared with the threshold. The mode is selected
by the contents of the (ACC 0x24) low_mode bit: ´0´ means ‘single’ mode, ´1´ means ‘sum’
mode.
The low-g threshold is set through the (ACC 0x23) low_th register. 1 LSB of (ACC 0x23) low_th
always corresponds to an acceleration of 7.81 mg (i.e. increment is independent from g-range
setting).
A hysteresis can be selected by setting the (ACC 0x24) low_hy bits. 1 LSB of (ACC 0x24)
low_hy always corresponds to an acceleration difference of 125 mg in any g-range (as well,
increment is independent from g-range setting).
The low-g interrupt is generated if the absolute values of the acceleration of all axes (´and´
relation, in case of single mode) or their sum (in case of sum mode) are lower than the
threshold for at least the time defined by the (ACC 0x22) low_dur register. The interrupt is reset
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if the absolute value of the acceleration of at least one axis (´or´ relation, in case of single
mode) or the sum of absolute values (in case of sum mode) is higher than the threshold plus
the hysteresis for at least one data acquisition. In bit (ACC 0x09) low_int the interrupt status is
stored.
The relation between the content of (ACC 0x22) low_dur and the actual delay of the interrupt
generation is: delay [ms] = [(ACC 0x22) low_dur + 1] • 2 ms. Therefore, possible delay times
range from 2 ms to 512 ms.
5.6.10 High-g interrupt
This interrupt is based on the comparison of acceleration data against a high-g threshold for the
detection of shock or other high-acceleration events.
The high-g interrupt is enabled (disabled) per axis by writing ´1´ (´0´) to bits (ACC 0x17)
high_en_x, (ACC 0x17) high_en_y, and (ACC 0x17) high_en_z, respectively. The high-g
threshold is set through the (ACC 0x26) high_th register. The meaning of an LSB of (ACC
0x26) high_th depends on the selected g-range: it corresponds to 7.81 mg in 2g-range, 15.63
mg in 4g-range, 31.25 mg in 8g-range, and 62.5 mg in 16g-range (i.e. increment depends from
g-range setting).
A hysteresis can be selected by setting the (ACC 0x24) high_hy bits. Analogously to (ACC
0x26) high_th, the meaning of an LSB of (ACC 0x24) high_hy is g-range dependent: It
corresponds to an acceleration difference of 125 mg in 2g-range, 250 mg in 4g-range, 500 mg
in 8g-range, and 1000mg in 16g-range (as well, increment depends from g-range setting).
The high-g interrupt is generated if the absolute value of the acceleration of at least one of the
enabled axes (´or´ relation) is higher than the threshold for at least the time defined by the (ACC
0x25) high_dur register. The interrupt is reset if the absolute value of the acceleration of all
enabled axes (´and´ relation) is lower than the threshold minus the hysteresis for at least the
time defined by the (ACC 0x25) high_dur register. In bit (ACC 0x09) high_int the interrupt status
is stored. The relation between the content of (ACC 0x25) high_dur and the actual delay of the
interrupt generation is delay [ms] = [(ACC 0x22) low_dur + 1] • 2 ms. Therefore, possible delay
times range from 2 ms to 512 ms. The interrupt will be cleared immediately once acceleration is
lower than threshold.
5.6.10.1 Axis and sign information of high-g interrupt
The axis which triggered the interrupt is indicated by bits (ACC 0x0C) high_first_x, (ACC 0x0C)
high_first_y, and (ACC 0x0C) high_first_z. The bit corresponding to the triggering axis contains
a ´1´ while the other bits hold a ´0´. These bits are cleared together with clearing the interrupt
status. The sign of the triggering acceleration is stored in bit (ACC 0x0C) high_sign. If (ACC
0x0C) high_sign = ´0´ (´1´), the sign is positive (negative).
5.6.11 No-motion / slow motion detection
The slow-motion/no-motion interrupt engine can be configured in two modes.
In slow-motion mode an interrupt is triggered when the measured slope of at least one enabled
axis exceeds the programmable slope threshold for a programmable number of samples.
Hence the engine behaves similar to the any-motion interrupt, but with a different set of
parameters. In order to suppress false triggers, the interrupt is only generated (cleared) if a
certain number N of consecutive slope data points is larger (smaller) than the slope threshold
given by (ACC 0x27) slo_no_mot_dur. The number is N = (ACC 0x27)
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slo_no_mot_dur + 1.
In no-motion mode an interrupt is generated if the slope on all selected axes remains smaller
than a programmable threshold for a programmable delay time. Figure 11 shows the timing
diagram for the no-motion interrupt. The scaling of the threshold value is identical to that of the
slow-motion interrupt. However, in no-motion mode register (ACC 0x27) slo_no_mot_dur
defines the delay time before the no-motion interrupt is triggered. Table 22 lists the delay times
adjustable with register (ACC 0x27) slo_no_mot_dur. The timer tick period is 1 second. Hence
using short delay times can result in considerable timing uncertainty.
If bit (ACC 0x18) slo_no_mot_sel is set to ‘1’ (‘0’) the no-motion/slow-motion interrupt engine is
configured in the no-motion (slow-motion) mode. Common to both modes, the engine monitors
the slopes of the axes that have been enabled with bits (ACC 0x18) slo_no_mot_en_x, (ACC
0x18) slo_no_mot_en_y, and (ACC 0x18) slo_no_mot_en_z for the x-axis, y-axis and z-axis,
respectively. The measured slope values are continuously compared against the threshold
value defined in register (ACC 0x29) slo_no_mot_th. The scaling is such that 1 LSB of (ACC
0x29) slo_no_mot_th corresponds to 3.91 mg in 2g-range (7.81 mg in 4g-range, 15.6 mg in 8grange and 31.3 mg in 16g-range). Therefore the maximum value is 996 mg in 2g-range (1.99g
in 4g-range, 3.98g in 8g-range and 7.97g in 16g-range). The time difference between the
successive acceleration samples depends on the selected bandwidth and equates to 1/(2 * bw).
Table 22: No-motion time-out periods
(ACC 0x27)
slo_no_mot_dur
0
1
2
...
14
15
Delay
time
1s
2s
3s
...
15 s
16 s
(ACC 0x27)
slo_no_mot_dur
16
17
18
19
20
21
Delay
time
40 s
48 s
56 s
64 s.
72 s
80 s
(ACC 0x27)
slo_no_mot_dur
32
33
34
...
62
63
Delay
Time
88 s
96 s
104 s
...
328 s
336 s
Note: slo_no_mot_dur values 22 to 31 are not specified
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acceleration
Page 47
acc(t0+Δt)
acc(t0)
slope
axis x, y, or z
slope(t0+Δt)= acc(t0+Δt) - acc(t0)
axis x, y, or z
slo_no_mot_th
-slo_no_mot_th
slo_no_mot_dur
timer
INT
time
Figure 11: Timing of no-motion interrupt
5.7
Softreset accelerometer
A softreset causes all user configuration settings to be overwritten with their default value and
the sensor to enter normal mode.
A softreset is initiated by means of writing value ‘0xB6’ to register (ACC 0x14)softrset.
Subsequently a waiting time of tw,up1 (max.) is required prior to accessing any configuration
register.
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6 Register description accelerometer
6.1
General remarks accelerometer
The entire communication with the device is performed by reading from and writing to registers.
Registers have a width of 8 bits; they are mapped to a common space of 64 addresses from
(ACC 0x00) up to (ACC 0x3F). Within the used range there are several registers which are
either completely or partially marked as ‘reserved’. Any reserved bit is ignored when it is written
and no specific value is guaranteed when read. It is recommended not to use registers at all
which are completely marked as ‘reserved’. Furthermore it is recommended to mask out (logical
and with zero) reserved bits of registers which are partially marked as reserved.
Registers with addresses from (ACC 0x00) up to (ACC 0x0E) are read-only. Any attempt to
write to these registers is ignored. There are bits within some registers that trigger internal
sequences. These bits are configured for write-only access, e. g. (ACC 0x21) reset_int or the
entire (ACC 0x14) softreset register, and read as value ´0´.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
6.2
Page 49
Register map accelerometer
Register Address
0x3F
0x3E
0x3D
0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Access Default
fifo_data_output_register
fifo_mode
fifo_data_select
GP1
GP0
offset_z
offset_y
offset_x
offset_target_y
cal_rdy
offset_target_z
cal_trigger
offset_reset
nvm_remain
offset_target_x
hp_z_en
hp_y_en
nvm_load
self_test_amp
i2c_wdt_en
nvm_rdy
self_test_sign
cut_off
hp_x_en
i2c_wdt_sel
spi3
nvm_prog_trig
nvm_prog_mode
self_test_axis
fifo_water_mark_level_trigger_retain
flat_hold_time
flat_hy
flat_theta
orient_theta
orient_blocking
tap_th
orient_ud_en
orient_hyst
tap_samp
tap_quiet
tap_shock
orient_mode
tap_dur
slo_no_mot_th
slope_th
slo_no_mot_dur
slope_dur
high_th
high_dur
high_hy
low_mode
low_hy
low_th
low_dur
reset_int
int2_od
int2_lvl
latch_int
int1_od
int1_lvl
int_src_data
int_src_tap
int_src_slo_no_mot
int_src_slope
int_src_high
int_src_low
int2_slope
int1_ffull
int1_slope
slo_no_mot_en_z
high_en_z
slope_en_z
int2_high
int1_fwm
int1_high
slo_no_mot_en_y
high_en_y
slope_en_y
int2_low
int1_data
int1_low
slo_no_mot_en_x
high_en_x
slope_en_x
int2_flat
int2_data
int1_flat
int2_orient
int2_fwm
int1_orient
int2_s_tap
int2_ffull
int1_s_tap
int2_d_tap
int2_slo_no_mot
int1_d_tap
int_ffull_en
s_tap_en
data_en
d_tap_en
int1_slo_no_mot
slo_no_mot_sel
low_en
flat_en
int_fwm_en
orient_en
softreset
data_high_bw
suspend
shadow_dis
lowpower_mode
lowpower_en
sleeptimer_mode
deep_suspend
sleep_dur
bw
range
fifo_overrun
flat
tap_sign
data_int
flat_int
fifo_frame_counter
tap_first_z
fifo_wm_int
orient_int
orient
tap_first_y
fifo_full_int
s_tap_int
tap_first_x
high_sign
slope_sign
d_tap_int
slo_no_mot_int
temp
acc_z_msb
high_first_z
slope_first_z
high_first_y
slope_first_y
high_first_x
slope_first_x
slope_int
high_int
low_int
acc_z_lsb
new_data_z
acc_y_msb
acc_y_lsb
new_data_y
acc_x_msb
acc_x_lsb
new_data_x
chip_id
ro
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
wo
w/r
w/r
w/r
w/r
w/r
ro
w/r
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x10
0x00
0x00
0xF0
0x00
0xFF
0x00
0x11
0x08
0x48
0x18
0x0A
0x04
0x14
0x14
0x00
0xC0
0x0F
0x81
0x30
0x09
0x00
0x05
0xFF
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0x0F
0x03
0x00
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
-0xFA
common w/r registers: Application specific settings which are not equal to the default settings,
must be re-set to its designated values after POR, soft-reset and wake up from deep suspend.
user w/r registers: Initial default content = 0x00. Freely programmable by the user.
Remains unchanged after POR, soft-reset and wake up from deep suspend.
Figure 12: Register map accelerometer part
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 50
ACC Register 0x00 (BGW_CHIPID)
The register contains the chip identification code.
Name
Bit
Read/Write
Reset
Value
Content
0x00
7
R
n/a
Bit
Read/Write
Reset
Value
Content
3
R
n/a
chip_id:
6
R
BGW_CHIPID
5
R
4
R
n/a
n/a
n/a
2
R
1
R
0
R
n/a
n/a
n/a
chip_id
chip_id
Fixed value b’1111’1010
ACC Register 0x01 is reserved
ACC Register 0x02 (ACCD_X_LSB)
The register contains the least-significant bits of the X-channel acceleration readout value.
When reading out X-channel acceleration values, data consistency is guaranteed if the
ACCD_X_LSB is read out before the ACCD_X_MSB and shadow_dis=’0’. In this case, after the
ACCD_X_LSB has been read, the value in the ACCD_X_MSB register is locked until the
ACCD_X_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Acceleration data may be read from register ACCD_X_LSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x02
7
R
n/a
Bit
Read/Write
Reset
Value
Content
3
R
acc_x_lsb:
undefined:
new_data_x:
6
R
ACCD_X_LSB
5
R
4
R
n/a
n/a
n/a
2
R
1
R
0
R
n/a
n/a
n/a
n/a
undefined
undefined
undefined
new_data_x
acc_x_lsb
Least significant 4 bits of acceleration read-back value; (two’s-complement
format)
random data; to be ignored.
‚0’: acceleration value has not been updated since it has been read out last
‚1’: acceleration value has been updated since it has been read out last
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 51
ACC Register 0x03 (ACCD_X_MSB)
The register contains the most-significant bits of the X-channel acceleration readout value.
When reading out X-channel acceleration values, data consistency is guaranteed if the
ACCD_X_LSB is read out before the ACCD_X_MSB and shadow_dis=’0’. In this case, after the
ACCD_X_LSB has been read, the value in the ACCD_X_MSB register is locked until the
ACCD_X_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Acceleration data may be read from register ACCD_X_MSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x02
7
R
6
R
ACCD_X_MSB
5
R
4
R
n/a
n/a
n/a
n/a
Bit
Read/Write
Reset
Value
Content
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
acc_x_msb
acc_x_msb
acc_x_msb: Most significant 8 bits of acceleration read-back value (two’s-complement
format)
ACC Register 0x04 (ACCD_Y_LSB)
The register contains the least-significant bits of the Y-channel acceleration readout value.
When reading out Y-channel acceleration values, data consistency is guaranteed if the
ACCD_Y_LSB is read out before the ACCD_Y_MSB and shadow_dis=’0’. In this case, after the
ACCD_Y_LSB has been read, the value in the ACCD_Y_MSB register is locked until the
ACCD_Y_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Acceleration data may be read from register ACCD_Y_LSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x04
7
R
6
R
ACCD_Y_LSB
5
R
4
R
n/a
n/a
n/a
n/a
Bit
Read/Write
Reset
Value
Content
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
undefined
undefined
undefined
new_data_y
acc_y_lsb
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
acc_y_lsb:
undefined:
new_data_y:
Page 52
Least significant 4 bits of acceleration read-back value; (two’s-complement
format)
random data; to be ignored
‚0’: acceleration value has not been updated since it has been read out last
‚1’: acceleration value has been updated since it has been read out last
ACC Register 0x05 (ACCD_Y_MSB)
The register contains the most-significant bits of the Y-channel acceleration readout value.
When reading out Y-channel acceleration values, data consistency is guaranteed if the
ACCD_Y_LSB is read out before the ACCD_Y_MSB and shadow_dis=’0’. In this case, after the
ACCD_Y_LSB has been read, the value in the ACCD_Y_MSB register is locked until the
ACCD_Y_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Acceleration data may be read from register ACCD_Y_MSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x05
7
R
n/a
Bit
Read/Write
Reset
Value
Content
3
R
n/a
6
R
ACCD_Y_MSB
5
R
4
R
n/a
n/a
n/a
acc_y_msb
2
R
n/a
1
R
n/a
0
R
n/a
acc_y_msb
acc_y_msb: Most significant 8 bits of acceleration read-back value (two’s-complement
format)
ACC Register 0x06 (ACCD_Z_LSB)
The register contains the least-significant bits of the Z-channel acceleration readout value.
When reading out Z-channel acceleration values, data consistency is guaranteed if the
ACCD_Z_LSB is read out before the ACCD_Z_MSB and shadow_dis=’0’. In this case, after the
ACCD_Z_LSB has been read, the value in the ACCD_Z_MSB register is locked until the
ACCD_Z_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Acceleration data may be read from register ACCD_Z_LSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x06
7
R
n/a
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
6
R
ACCD_Z_LSB
5
R
4
R
n/a
n/a
n/a
acc_z_lsb
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Bit
Read/Write
Reset
Value
Content
Page 53
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
undefined
undefined
undefined
new_data_z
Acc_z_lsb: Least significant 4 bits of acceleration read-back value; (two’s-complement
format)
undefined:
random data; to be ignored
new_data_z:
‚0’: acceleration value has not been updated since it has been read out last
‚1’: acceleration value has been updated since it has been read out last
ACC Register 0x07 (ACCD_Z_MSB)
The register contains the most-significant bits of the Z-channel acceleration readout value.
When reading out Z-channel acceleration values, data consistency is guaranteed if the
ACCD_Z_LSB is read out before the ACCD_Z_MSB and shadow_dis=’0’. In this case, after the
ACCD_Z_LSB has been read, the value in the ACCD_Z_MSB register is locked until the
ACCD_Z_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Acceleration data may be read from register ACCD_Z_MSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x07
7
R
6
R
ACCD_Z_MSB
5
R
4
R
n/a
n/a
n/a
n/a
Bit
Read/Write
Reset
Value
Content
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
acc_z_msb
acc_z_msb
acc_z_msb: Most significant 8 bits of acceleration read-back value (two’s-complement
format)
ACC Register 0x08 (ACCD_TEMP)
The register contains the current chip temperature represented in two’s complement format. A
readout value of temp=0x00 corresponds to a temperature of 23°C.
Name
0x08
ACCD_TEMP
Bit
7
6
5
4
Read/Write
R
R
R
R
Reset
n/a
n/a
n/a
n/a
Value
Content
temp
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Bit
Read/Write
Reset
Value
Content
temp:
3
R
n/a
Page 54
2
R
n/a
1
R
n/a
0
R
n/a
temp
Temperature value (two s-complement format)
ACC Register 0x09 (INT_STATUS_0)
The register contains interrupt status flags. Each flag is associated with a specific interrupt
function. It is set when the associated interrupt triggers. The setting of latch_int controls if
the interrupt signal and hence the respective interrupt flag will be permanently latched,
temporarily latched or not latched. The interrupt function associated with a specific status flag
must be enabled.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
flat_int:
orient_int:
s_tap_int:
d_tap_int
slo_not_mot_int:
slope_int:
high_int:
low_int:
0x09
7
R
6
R
INT_STATUS_0
5
R
4
R
n/a
n/a
n/a
n/a
flat_int
orient_int
s_tap_int
d_tap_int
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
slo_no_mot_int
slope_int
high_int
low_int
flat interrupt status: ‘0’inactive, ‘1’ active
orientation interrupt status: ‘0’inactive, ‘1’ active
single tap interrupt status: ‘0’inactive, ‘1’ active
double tap interrupt status: ‘0’inactive, ‘1’ active
slow/no-motion interrupt status: ‘0’inactive, ‘1’ active
slope interrupt status: ‘0’inactive, ‘1’ active
high-g interrupt status: ‘0’inactive, ‘1’ active
low-g interrupt status: ‘0’inactive, ‘1’ active
ACC Register 0x0A (INT_STATUS_1)
The register contains interrupt status flags. Each flag is associated with a specific interrupt
function. It is set when the associated interrupt engine triggers. The setting of latch_int
controls if the interrupt signal and hence the respective interrupt flag will be permanently
latched, temporarily latched or not latched. The interrupt function associated with a specific
status flag must be enabled.
Name
Bit
Read/Write
0x0A
7
R
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
6
R
INT_STATUS_1
5
R
4
R
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
data_int:
fifo_wm_int:
fifo_full_int:
reserved:
Page 55
n/a
n/a
n/a
n/a
data_int
fifo_wm_int
fifo_full_int
reserved
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
reserved
data ready interrupt status: ‘0’inactive, ‘1’ active
FIFO watermark interrupt status: ‘0’inactive, ‘1’ active
FIFO full interrupt status: ‘0’inactive, ‘1’ active
reserved, write to ‘0’
ACC Register 0x0B (INT_STATUS_2)
The register contains interrupt status flags. Each flag is associated with a specific interrupt
engine. It is set when the associated interrupt engine triggers. The setting of latch_int
controls if the interrupt signal and hence the respective interrupt flag will be permanently
latched, temporarily latched or not latched. The interrupt function associated with a specific
status flag must be enabled.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
tap_sign:
tap_first_z:
tap_first_y:
tap_first_x:
slope_sign:
slope_first_z:
slope_first_y:
slope_first_x:
0x0B
7
R
6
R
INT_STATUS_2
5
R
4
R
n/a
n/a
n/a
n/a
tap_sign
tap_first_z
tap_first_y
tap_first_x
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
slope_sign
slope_first_z
slope_first_y
slope_first_x
sign of single/double tap triggering signal was ‘0’positive, or ‘1’ negative
single/double tap interrupt: ‘1’ triggered by, or ‘0’not triggered by z-axis
single/double tap interrupt: ‘1’ triggered by, or ‘0’not triggered by y-axis
single/double tap interrupt: ‘1’ triggered by, or ‘0’not triggered by x-axis
slope sign of slope tap triggering signal was ‘0’positive, or ‘1’ negative
slope interrupt: ‘1’ triggered by, or ‘0’not triggered by z-axis
slope interrupt: ‘1’ triggered by, or ‘0’not triggered by y-axis
slope interrupt: ‘1’ triggered by, or ‘0’not triggered by x-axis
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 56
ACC Register 0x0C (INT_STATUS_3)
The register contains interrupt status flags. Each flag is associated with a specific interrupt
engine. It is set when the associated interrupt engine triggers. With the exception of orient
the setting of latch_int controls if the interrupt signal and hence the respective interrupt
flag will be permanently latched, temporarily latched or not latched. The interrupt function
associated with a specific status flag must be enabled.
Name
Bit
Read/Write
Reset
Value
Content
0x0C
7
R
6
R
INT_STATUS_3
5
R
4
R
n/a
n/a
n/a
n/a
Bit
Read/Write
Reset
Value
Content
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
high_sign
high_first_z
high_first_y
high_first_x
flat:
orient:
orient:
high_sign:
high_first_z:
high_first_y:
high_first_x:
flat
orient
device is in ‘1’ flat, or ‘0’ non flat position;
only valid if (ACC 0x16) flat_en = ‘1’ ‘
Orientation value of z-axis: ´0´ upward looking, or ´1´ downward
looking. The flag always reflect the current orientation status, independent of
the setting of latch_int. The flag is not updated as long as an
orientation blocking condition is active.
orientation value of x-y-plane:
‘00’portrait upright;
‘01’portrait upside down;
‘10’landscape left;
‘11’landscape right;
The flags always reflect the current orientation status, independent of the
setting of latch_int. The flag is not updated as long as an orientation
blocking condition is active.
sign of acceleration signal that triggered high-g interrupt was ‘0’positive, ‘1’
negative
high-g interrupt: ‘1’ triggered by, or ‘0’not triggered by z-axis
high-g interrupt: ‘1’ triggered by, or ‘0’not triggered by y-axis
high-g interrupt: ‘1’ triggered by, or ‘0’not triggered by x-axis
ACC Register 0x0D is reserved
ACC Register 0x0E (FIFO_STATUS)
The register contains FIFO status flags.
Name
Bit
Read/Write
Reset
0x0E
7
R
n/a
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
6
R
n/a
FIFO_STATUS
5
R
n/a
4
R
n/a
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Value
Content
Bit
Read/Write
Reset
Value
Content
fifo_overrun
Page 57
fifo_frame_counter
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
fifo_frame_counter
fifo_overrun:
FIFO overrun condition has ‘1’ occurred, or ‘0’not occurred; flag can be
cleared by writing to the FIFO configuration register FIFO_CONFIG_1 only
fifo_frame_counter:
Current fill level of FIFO buffer. An empty FIFO corresponds to
0x00. The frame counter can be cleared by reading out all frames from the
FIFO buffer or writing to the FIFO configuration register FIFO_CONFIG_1.
ACC Register 0x0F (PMU_RANGE)
The register allows the selection of the accelerometer g-range.
Name
Bit
Read/Write
Reset
Value
Content
0x0F
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
0
6
R/W
PMU_RANGE
5
R/W
4
R/W
0
0
0
2
R/W
1
R/W
0
R/W
0
1
1
reserved
0
range:
reserved:
range
Selection of accelerometer g-range:
´0011b´ ±2g range; ´0101b´ ±4g range; ´1000b´ ±8g range;
´1100b´ ±16g range; all other settings reserved (do not use)
write ‘0’
ACC Register 0x10 (PMU_BW)
The register allows the selection of the acceleration data filter bandwidth.
Name
Bit
Read/Write
Reset
Value
Content
0x10
7
R/W
6
R/W
PMU_BW
5
R/W
4
R/W
0
0
0
0
Bit
Read/Write
Reset
3
R/W
1
reserved
bw
0
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
2
R/W
1
1
R/W
1
0
R/W
1
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© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Value
Content
bw:
reserved:
Page 58
bw
Selection of data filter bandwidth:
´00xxxb´ 7.81 Hz,
´01000b´ 7.81 Hz, ´01001b´ 15.63 Hz,
´01010b´ 31.25 Hz, ´01011b´ 62.5 Hz, ´01100b´ 125 Hz,
´01101b´ 250 Hz,
´01110b´ 500 Hz, ´01111b´ 1000 Hz,
´1xxxxb´ 1000 Hz
write ‘0’
ACC Register 0x11 (PMU_LPW)
Selection of the main power modes and the low power sleep period.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
0x11
7
R/W
6
R/W
PMU_LPW
5
R/W
4
R/W
0
0
0
0
suspend
lowpower_en
deep_suspend
sleep_dur
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
sleep_dur
reserved
suspend, low_power_en, deep_suspend:
Main power mode configuration setting {suspend; lowpower_en;
deep_suspend}:
{0; 0; 0}
NORMAL mode;
{0; 0; 1}
DEEP_SUSPEND mode;
{0; 1; 0}
LOW_POWER mode;
{1; 0; 0}
SUSPEND mode;
{all other}
illegal
Please note that only certain power mode transitions are permitted.
sleep_dur: Configures the sleep phase duration in LOW_POWER mode:
´0000b´ to ´0101b´
0.5 ms,
´0110b´ 1 ms,
´0111b´
2 ms,
´1000b´ 4 ms,
´1001b´
6 ms,
´1010b´ 10 ms,
´1011b´
25 ms,
´1100b´ 50 ms,
´1101b´
100 ms,
´1110b´ 500 ms,
´1111b´
1s
Please note, that all application specific settings which are not equal to the default settings
(refer to 6.2 register map), must be re-set to its designated values after DEEP_SUSPEND.
ACC Register 0x12 (PMU_LOW_POWER)
Configuration settings for low power mode.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
0x12
7
R/W
Page 59
6
R/W
PMU_LOW_POWER
5
R/W
4
R/W
0
0
0
0
reserved
lowpower_mode
sleeptimer_mode
reserved
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
reserved
lowpower_mode: select ‘0’ LPM1, or ‘1´ LPM2 configuration for SUSPEND and
LOW_POWER mode. In the LPM1 configuration the power consumption in
LOW_POWER mode and SUSPEND mode is significantly reduced when
compared to LPM2 configuration, but the FIFO is not accessible and writing
to registers must be slowed down. In the LPM2 configuration the power
consumption in LOW_POWER mode is reduced compared to NORMAL
mode, but the FIFO is fully accessible and registers can be written to at full
speed.
sleeptimer_mode: when in LOW_POWER mode ‘0’ use event-driven time-base mode
(compatible with BMA250), or ‘1´ use equidistant sampling time-base
mode. Equidistant sampling of data into the FIFO is maintained in
equidistant time-base mode only.
reserved:
write ‘0’
ACC Register 0x13 (ACCD_HBW)
Acceleration data acquisition and data output format.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
data_high_bw:
shadow_dis:
0x13
7
R/W
ACCD_HBW
5
R/W
4
R/W
0
0
data_high_bw
6
R/W
0 (1 in 8-bit
mode)
shadow_dis
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
0
reserved
reserved
select whether ‘1´ unfiltered, or ‘0’ filtered data may be read from the
acceleration data registers.
‘1´ disable, or ‘0’ the shadowing mechanism for the acceleration data
output registers. When shadowing is enabled, the content of the acceleration
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
reserved:
Page 60
data component in the MSB register is locked, when the component in the
LSB is read, thereby ensuring the integrity of the acceleration data during
read-out. The lock is removed when the MSB is read.
write ‘0’
ACC Register 0x14 (BGW_SOFTRESET)
Controls user triggered reset of the sensor.
Name
Bit
Read/Write
Reset
Value
Content
0x14
7
W
0
Bit
Read/Write
Reset
Value
Content
3
W
0
softreset:
6
W
BGW_SOFTRESET
5
W
4
W
0
0
0
2
W
1
W
0
W
0
0
0
softreset
softreset
0xB6 triggers a reset. Other values are ignored. Following a delay, all
user configuration settings are overwritten with their default state or the
setting stored in the NVM, wherever applicable. This register is functional in
all operation modes. Please note that all application specific settings which
are not equal to the default settings (refer to 6.2 register map), must be
reconfigured to their designated values.
ACC Register 0x15 is reserved
ACC Register 0x16 (INT_EN_0)
Controls which interrupt engines in group 0 are enabled.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
flat_en:
orient_en:
0x16
7
R/W
6
R/W
INT_EN_0
5
R/W
4
R/W
0
0
0
0
flat_en
orient_en
s_tap_en
d_tap_en
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
reserved
slope_en_z
slope_en_y
slope_en_x
flat interrupt: ‘0’disabled, or ‘1’ enabled
orientation interrupt: ‘0’disabled, or ‘1’ enabled
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
s_tap_en:
d_tap_en
reserved:
slope_en_z:
slope_en_y:
slope_en_x:
Page 61
single tap interrupt: ‘0’disabled, or ‘1’ enabled
double tap interrupt: ‘0’disabled, or ‘1’ enabled
write ‘0’
slope interrupt, z-axis component: ‘0’disabled, or ‘1’ enabled
slope interrupt, y-axis component: ‘0’disabled, or ‘1’ enabled
slope interrupt, x-axis component: ‘0’disabled, or ‘1’ enabled
ACC Register 0x17 (INT_EN_1)
Controls which interrupt engines in group 1 are enabled.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
reserved:
int_fwm_en:
int_ffull_en:
data_en
low_en:
high_en_z:
high_en_y:
high_en_x:
0x17
7
R/W
6
R/W
INT_EN_1
5
R/W
4
R/W
0
0
0
0
reserved
int_fwm_en
int_ffull_en
data_en
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
low_en
high_en_z
high_en_y
high_en_x
write ‘0’
FIFO watermark interrupt: ‘0’disabled, or ‘1’ enabled
FIFO full interrupt: ‘0’disabled, or ‘1’ enabled
data ready interrupt: ‘0’disabled, or ‘1’ enabled
low-g interrupt: ‘0’disabled, or ‘1’ enabled
high-g interrupt, z-axis component: ‘0’disabled, or ‘1’ enabled
high-g interrupt, y-axis component: ‘0’disabled, or ‘1’ enabled
high-g interrupt, x-axis component: ‘0’disabled, or ‘1’ enabled
ACC Register 0x18 (INT_EN_2)
Controls which interrupt engines in group 2 are enabled.
Name
Bit
Read/Write
Reset
Value
Content
0x18
7
R/W
6
R/W
INT_EN_2
5
R/W
4
R/W
0
0
0
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
slo_no_mot_sel
slo_no_mot_en_z
slo_no_mot_en_y
slo_no_mot_en_x
reserved
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 62
reserved:
write ‘0’
slo_no_mot_sel: select ‘0’slow-motion, ‘1’ no-motion interrupt function
slo_no_mot_en_z: slow/n-motion interrupt, z-axis component: ‘0’disabled, or ‘1’ enabled
slo_no_mot_en_y: slow/n-motion interrupt, y-axis component: ‘0’disabled, or ‘1’ enabled
slo_no_mot_en_x: slow/n-motion interrupt, x-axis component: ‘0’disabled, or ‘1’ enabled
ACC Register 0x19 (INT_MAP_0)
Controls which interrupt signals are mapped to the INT1 pin.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
6
R/W
INT_MAP_0
5
R/W
4
R/W
0
0
0
0
int1_flat
int1_orient
int1_s_tap
int1_d_tap
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
int1_slo_no_mot
int1_slope
int1_high
int1_low
int1_flat:
int1_orient:
int1_s_tap:
int1_d_tap:
int1_slo_no_mot:
int1_slope:
int1_high:
int1_low:
0x19
7
R/W
map flat interrupt to INT1 pin: ‘0’disabled, or ‘1’ enabled
map orientation interrupt to INT1 pin: ‘0’disabled, or ‘1’ enabled
map single tap interrupt to INT1 pin: ‘0’disabled, or ‘1’ enabled
map double tap interrupt to INT1 pin: ‘0’disabled, or ‘1’ enabled
map slow/no-motion interrupt to INT1 pin: ‘0’disabled, or ‘1’ enabled
map slope interrupt to INT1 pin: ‘0’disabled, or ‘1’ enabled
map high-g to INT1 pin: ‘0’disabled, or ‘1’ enabled
map low-g to INT1 pin: ‘0’disabled, or ‘1’ enabled
ACC Register 0x1A (INT_MAP_1)
Controls which interrupt signals are mapped to the INT1 and INT2 pins.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
0x1A
7
R/W
6
R/W
INT_MAP_1
5
R/W
4
R/W
0
0
0
0
int2_data
int2_fwm
int2_ffull
reserved
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Content
int2_data:
int2_fwm:
int2_ffull:
reserved:
int1_ffull:
int1_fwm:
int1_data:
Page 63
reserved
int1_ffull
int1_fwm
int1_data
map data ready interrupt to INT2 pin: ‘0’disabled, or ‘1’ enabled
map FIFO watermark interrupt to INT2 pin: ‘0’disabled, or ‘1’ enabled
map FIFO full interrupt to INT2 pin: ‘0’disabled, or ‘1’ enabled
write ‘0’
map FIFO full interrupt to INT1 pin: ‘0’disabled, or ‘1’ enabled
map FIFO watermark interrupt to INT1 pin: ‘0’disabled, or ‘1’ enabled
map data ready interrupt to INT1 pin: ‘0’disabled, or ‘1’ enabled
ACC Register 0x1B (INT_MAP_2)
Controls which interrupt signals are mapped to the INT2 pin.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
0x1B
7
R/W
6
R/W
INT_MAP_2
5
R/W
4
R/W
0
0
0
0
int2_flat
int2_orient
int2_s_tap
int2_d_tap
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
int2_slo_no_mot
int2_slope
int2_high
int2_low
int2_flat:
int2_orient:
int2_s_tap:
int2_d_tap:
int2_slo_no_mot:
int2_slope:
int2_high:
int2_low:
map flat interrupt to INT2 pin: ‘0’disabled, or ‘1’ enabled
map orientation interrupt to INT2 pin: ‘0’disabled, or ‘1’ enabled
map single tap interrupt to INT2 pin: ‘0’disabled, or ‘1’ enabled
map double tap interrupt to INT2 pin: ‘0’disabled, or ‘1’ enabled
map slow/no-motion interrupt to INT2 pin: ‘0’disabled, or ‘1’ enabled
map slope interrupt to INT2 pin: ‘0’disabled, or ‘1’ enabled
map high-g to INT2 pin: ‘0’disabled, or ‘1’ enabled
map low-g to INT2 pin: ‘0’disabled, or ‘1’ enabled
ACC Register 0x1C is reserved
ACC Register 0x1D is reserved
ACC Register 0x1E (INT_SRC)
Contains the data source definition for interrupts with selectable data source.
Name
0x1E
INT_SRC
Bit
7
6
5
Read/Write
R/W
R/W
R/W
Reset
0
0
0
Value
Content
reserved
int_src_data
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
4
R/W
0
int_src_tap
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Bit
Read/Write
Reset
Value
Content
Page 64
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
int_src_slo_no_m
ot
int_src_slope
int_src_high
int_src_low
reserved:
write ‘0’
int_src_data:
select ‘0’filtered, or ‘1’ unfiltered data for new data interrupt
int_src_tap:
select ‘0’filtered, or ‘1’ unfiltered data for single-/double tap interrupt
int_src_slo_no_mot: select ‘0’filtered, or ‘1’ unfiltered data for slow/no-motion interrupt
int_src_slope:
select ‘0’filtered, or ‘1’ unfiltered data for slope interrupt
int_src_high:
select ‘0’filtered, or ‘1’ unfiltered data for high-g interrupt
int_src_low:
select ‘0’filtered, or ‘1’ unfiltered data for low-g interrupt
ACC Register 0x1F is reserved
ACC Register 0x20 (INT_OUT_CTRL)
Contains the behavioural configuration (electrical behavior) of the interrupt pins.
Name
Bit
Read/Write
Reset
Value
Content
0x20
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
reserved:
int2_od:
int2_lvl:
int1_od:
int1_lvl:
6
R/W
INT_OUT_CTRL
5
R/W
4
R/W
0
0
0
2
R/W
1
R/W
0
R/W
0
1
0
1
int2_od
int2_lvl
int1_od
int1_lvl
reserved
write ‘0’
select ‘0’push-pull, or ‘1’ open drain behavior for INT2 pin
select ‘0’active low, or ‘1’active high level for INT2 pin
select ‘0’push-pull, or ‘1’ open drain behavior for INT1 pin
select ‘0’active low, or ‘1’active high level for INT1 pin
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 65
ACC Register 0x21 (INT_RST_LATCH)
Contains the interrupt reset bit and the interrupt mode selection.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
reset_int:
reserved:
latch_int:
0x21
7
W
0
6
R/W
INT_RST_LATCH
5
R/W
4
R/W
0
0
0
reset_int
Reserved
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
latch_int
write ‘1’ clear any latched interrupts, or ‘0’ keep latched interrupts
active
write ‘0’
´0000b´ non-latched,
´0001b´ temporary, 250 ms,
´0010b´ temporary, 500 ms, ´0011b´ temporary, 1 s,
´0100b´ temporary, 2 s,
´0101b´ temporary, 4 s,
´0110b´ temporary, 8 s,
´0111b´ latched,
´1000b´ non-latched,
´1001b´ temporary, 250 s,
´1010b´ temporary, 500 s, ´1011b´ temporary, 1 ms,
´1100b´ temporary, 12.5 ms, ´1101b´ temporary, 25 ms,
´1110b´ temporary, 50 ms, ´1111b´ latched
ACC Register 0x22 (INT_0)
Contains the delay time definition for the low-g interrupt.
Name
Bit
Read/Write
Reset
Value
Content
0x22
7
W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
1
low_dur:
6
R/W
INT_0
5
R/W
4
R/W
0
0
0
2
R/W
1
R/W
0
R/W
0
0
1
low_dur
low_dur
low-g interrupt trigger delay according to [low_dur + 1] • 2 ms in a
range from 2 ms to 512 ms; the default corresponds to a delay of 20 ms.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 66
ACC Register 0x23 (INT_1)
Contains the threshold definition for the low-g interrupt.
Name
Bit
Read/Write
Reset
Value
Content
0x23
7
W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
0
low_th:
6
R/W
INT_1
5
R/W
4
R/W
0
1
1
2
R/W
1
R/W
0
R/W
0
0
0
low_th
low_th
low-g interrupt trigger threshold according to low_th • 7.81 mg in a
range from 0 g to 1.992 g; the default value corresponds to an acceleration
of 375 mg
ACC Register 0x24 (INT_2)
Contains the low-g interrupt mode selection, the low-g interrupt hysteresis setting, and the highg interrupt hysteresis setting.
Name
Bit
Read/Write
Reset
Value
Content
0x24
7
R/W
1
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
1
reserved
low_mode
high_hy:
low_mode:
low_hy:
6
R/W
INT_2
5
R/W
4
R/W
0
0
0
high_hy
reserved
low_hy
hysteresis of high-g interrupt according to high_hy · 125 mg (2-g
range), high_hy · 250 mg (4-g range), high_hy · 500 mg (8-g
range), or high_hy · 1000 mg (16-g range)
select low-g interrupt ‘0’ single-axis mode, or ‘1’ axis-summing mode
hysteresis of low-g interrupt according to low_hy · 125 mg independent
of the selected accelerometer g-range
ACC Register 0x25 (INT_3)
Contains the delay time definition for the high-g interrupt.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Name
Bit
Read/Write
Reset
Value
Content
0x25
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
1
high_dur:
Page 67
6
R/W
INT_3
5
R/W
4
R/W
0
0
0
2
R/W
1
R/W
0
R/W
1
1
1
high_dur
high_dur
high-g interrupt trigger delay according to [high_dur + 1] • 2 ms in a
range from 2 ms to 512 ms; the default corresponds to a delay of 32 ms.
ACC Register 0x26 (INT_4)
Contains the threshold definition for the high-g interrupt.
Name
Bit
Read/Write
Reset
Value
Content
0x26
7
R/W
1
Bit
Read/Write
Reset
Value
Content
3
R/W
0
high_th:
6
R/W
INT_4
5
R/W
4
R/W
1
0
0
2
R/W
1
R/W
0
R/W
0
0
0
high_th
high_th
threshold of high-g interrupt according to high_th · 7.81 mg (2-g range),
high_th · 15.63 mg (4-g range), high_th · 31.25 mg (8-g range),
or high_th · 62.5 mg (16-g range)
ACC Register 0x27 (INT_5)
Contains the definition of the number of samples to be evaluated for the slope interrupt (anymotion detection) and the slow/no-motion interrupt trigger delay.
Name
Bit
Read/Write
Reset
Value
Content
0x27
7
R/W
0
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
6
R/W
INT_5
5
R/W
4
R/W
0
0
0
slo_no_mot_dur
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Bit
Read/Write
Reset
Value
Content
Page 68
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
slo_no_mot_dur
slope_dur
slo_no_mot_dur:
Function depends on whether the slow-motion or no-motion
interrupt function has been selected. If the slow-motion interrupt function has
been enabled (slo_no_mot_sel = ‘0’) then [slo_no_mot_dur+1]
consecutive slope data points must be above the slow/no-motion threshold
(slo_no_mot_th) for the slow-/no-motion interrupt to trigger. If the no-motion
interrupt function has been enabled (slo_no_mot_sel = ‘1’) then
slo_no_motion_dur defines the time for which no slope data points
must exceed the slow/no-motion threshold (slo_no_mot_th) for the slow/nomotion interrupt to trigger. The delay time in seconds may be calculated
according with the following equation:
slope_dur:
slo_no_mot_dur=’b00’ [slo_no_mot_dur + 1]
slo_no_mot_dur=’b01’ [slo_no_mot_dur · 4 + 20]
slo_no_mot_dur=’1’ [slo_no_mot_dur · 8 + 88]
slope interrupt triggers if [slope_dur+1] consecutive slope data points
are above the slope interrupt threshold slope_th
ACC Register 0x28 (INT_6)
Contains the threshold definition for the any-motion interrupt.
Name
Bit
Read/Write
Reset
Value
Content
0x28
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
0
slope_th:
6
R/W
INT_6
5
R/W
4
R/W
0
0
1
2
R/W
1
R/W
0
R/W
1
0
0
slope_th
slope_th
Threshold of the any-motion interrupt. It is range-dependent and defined as a
sample-to-sample difference according to
slope_th · 3.91 mg (2-g range) /
slope_th · 7.81 mg (4-g range) /
slope_th · 15.63 mg (8-g range) /
slope_th · 31.25 mg (16-g range)
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 69
ACC Register 0x29 (INT_7)
Contains the threshold definition for the slow/no-motion interrupt.
Name
Bit
Read/Write
Reset
Value
Content
0x29
7
R/W
6
R/W
INT_7
5
R/W
4
R/W
0
0
0
1
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
1
0
0
slo_no_mot_th
slo_no_mot_th
slo_no_mot_th: Threshold of slow/no-motion interrupt. It is range-dependent and defined
as a sample-to-sample difference according to
slo_no_mot_th · 3.91 mg (2-g range),
slo_no_mot_th · 7.81 mg (4-g range),
slo_no_mot_th · 15.63 mg (8-g range),
slo_no_mot_th · 31.25 mg (16-g range)
ACC Register 0x2A (INT_8)
Contains the timing definitions for the single tap and double tap interrupts.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
tap_quiet:
tap_shock:
reserved:
tap_dur:
0x2A
7
R/W
6
R/W
INT_8
5
R/W
4
R/W
0
0
0
0
tap_quiet
tap_shock
reserved
reserved
3
R/W
2
R/W
1
R/W
0
R/W
0
1
0
0
reserved
tap_dur
selects a tap quiet duration of ‘0’ 30 ms, ‘1’ 20 ms
selects a tap shock duration of ‘0’ 50 ms, ‘1’75 ms
write ‘0’
selects the length of the time window for the second shock event for double
tap detection according to ´000b´ 50 ms, ´001b´ 100 ms, ´010b´ 150
ms, ´011b´ 200 ms, ´100b´ 250 ms, ´101b´ 375 ms, ´110b´ 500
ms, ´111b´ 700 ms.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 70
ACC Register 0x2B (INT_9)
Contains the definition of the number of samples processed by the single / double-tap interrupt
engine after wake-up in low-power mode. It also defines the threshold definition for the single
and double tap interrupts.
Name
Bit
Read/Write
Reset
Value
Content
0x2B
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
1
tap_samp:
reserved:
tap_th:
6
R/W
INT_9
5
R/W
4
R/W
0
0
0
reserved
tap_th
2
R/W
1
R/W
0
R/W
0
1
0
tap_samp
tap_th
selects the number of samples that are processed after wake-up in the lowpower mode according to ´00b´ 2 samples, ´01b´ 4 samples, ´10b´ 8
samples, and ´11b´ 16 samples
write ‘0’
threshold of the single/double-tap interrupt corresponding to an acceleration
difference of tap_th · 62.5mg (2g-range), tap_th · 125mg (4grange), tap_th · 250mg (8g-range), and tap_th · 500mg (16grange).
ACC Register 0x2C (INT_A)
Contains the definition of hysteresis, blocking, and mode for the orientation interrupt
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
0x2C
7
R/W
6
R/W
INT_A
5
R/W
4
R/W
0
0
0
1
reserved
orient_hyst
3
R/W
2
R/W
1
R/W
0
R/W
1
0
0
0
orient_blocking
orient_mode
reserved:
write ‘0’
orient_hyst: sets the hysteresis of the orientation interrupt; 1 LSB corresponds to 62.5 mg
irrespective of the selected g-range
orient_blocking:
selects the blocking mode that is used for the generation of the
orientation interrupt. The following blocking modes are available:
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 71
´00b´ no blocking,
´01b´ theta blocking or acceleration in any axis > 1.5g,
´10b´ ,theta blocking or acceleration slope in any axis > 0.2 g or
acceleration in any axis > 1.5g
´11b´ theta blocking or acceleration slope in any axis > 0.4 g or
acceleration in any axis > 1.5g and value of orient is not stable for
at least 100ms
orient_mode: sets the thresholds for switching between the different orientations. The
settings: ´00b´ symmetrical, ´01b´ high-asymmetrical, ´10b´ lowasymmetrical, ´11b´ symmetrical.
ACC Register 0x2D (INT_B)
Contains the definition of the axis orientation, up/down masking, and the theta blocking angle
for the orientation interrupt.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
0x2D
7
R/W
6
R/W
INT_B
5
R/W
4
R/W
n/a
1
0
0
reserved
orient_ud_en
3
R/W
2
R/W
1
R/W
0
R/W
1
0
0
0
orient_theta
orient_theta
orient_ud_en:
change of up/down-bit ´1´ generates an orientation interrupt, ´0´ is
ignored and will not generate an orientation interrupt
orient_theta: defines a blocking angle between 0° and 44.8°
ACC Register 0x2E (INT_C)
Contains the definition of the flat threshold angle for the flat interrupt.
Name
Bit
Read/Write
Reset
Value
Content
0x2E
7
R/W
6
R/W
INT_C
5
R/W
4
R/W
n/a
n/a
0
0
Bit
Read/Write
Reset
Value
Content
reserved:
flat_theta:
3
R/W
2
R/W
1
R/W
0
R/W
1
0
0
0
reserved
flat_theta
flat_theta
write ‘0’
defines threshold for detection of flat position in range from 0° to 44.8°.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 72
ACC Register 0x2F (INT_D)
Contains the definition of the flat interrupt hold time and flat interrupt hysteresis.
Name
Bit
Read/Write
Reset
Value
Content
0x2F
7
R/W
6
R/W
INT_D
5
R/W
4
R/W
0
0
0
1
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
1
reserved
flat_hold_time
reserved
flat_hy
reserved:
write ‘0’
flat_hold_time: delay time for which the flat value must remain stable for the flat interrupt
to be generated: ´00b´ 0 ms, ´01b´ 512 ms, ´10b´ 1024 ms,
´11b´ 2048 ms
flat_hy:
defines flat interrupt hysteresis; flat value must change by more than twice
the value of flat interrupt hysteresis to detect a state change. For details see
chapter 5.6.8.
‘000b’ hysteresis of the flat detection disabled
ACC Register 0x30 (FIFO_CONFIG_0)
Contains the FIFO watermark level.
Name
Bit
Read/Write
Reset
Value
0x30
7
R/W
n/a
Content
Bit
Read/Write
Reset
Value
Content
6
R/W
FIFO_CONFIG_0
5
R/W
4
R/W
n/a
0
0
fifo_water_mark_level_trigger_retain<
5:4>
reserved
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
fifo_water_mark_level_trigger_retain
reserved:
write ‘0’
fifo_water_mark_level_trigger_retain: fifo_water_mark_level_trigger_retain defines
the FIFO watermark level. An interrupt will be generated, when the number
of entries in the FIFO is equal to fifo_water_mark_level_trigger_retain;
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 73
ACC Register 0x31 is reserved
ACC Register 0x32 (PMU_SELF_TEST)
Contains the settings for the sensor self-test configuration and trigger.
Name
Bit
Read/Write
Reset
Value
Content
0x32
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
reserved_0
self_test_sign
reserved:
reserved_0:
self_test_amp;
self_test_sign:
self_test_axis:
6
R/W
PMU_SELF_TEST
5
R/W
4
R/W
0
0
0
reserved
self_test_amp
self_test-axis
write ‘0x0’
write ‘0x0’
select amplitude of the selftest deflection ´1´ high,
default value is low (´0´),
select sign of self-test excitation as ´1´ positive, or ´0´ negative
select axis to be self-tested: ´00b´ self-test disabled, ´01b´ x-axis, ´10b´
y-axis, or ´11b´ z-axis; when a self-test is performed, only the
acceleration data readout value of the selected axis is valid; after the selftest has been enabled a delay of a least 50 ms is necessary for the read-out
value to settle
ACC Register 0x33 (TRIM_NVM_CTRL)
Contains the control settings for the few-time programmable non-volatile memory (NVM).
Name
Bit
Read/Write
Reset
Value
Content
0x33
7
R
n/a
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
6
R
TRIM_NVM_CTRL
5
R
4
R
n/a
n/a
n/a
nvm_remain
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Bit
Read/Write
Reset
Value
Content
Page 74
3
R/W
2
R
1
W
0
R/W
0
n/a
0
0
nvm_load
nvm_rdy
nvm_prog_trig
nvm_prog_mode
nvm_remain:
number of remaining write cycles permitted for NVM; the number is
decremented each time a write to the NVM is triggered
nvm_load:
´1´ trigger, or ‘0’ do not trigger an update of all configuration registers
from NVM; the nvm_rdy flag must be ‘1’ prior to triggering the update
nvm_rdy:
status of NVM controller: ´0´ NVM write / NVM update operation is in
progress, ´1´ NVM is ready to accept a new write or update trigger
nvm_prog_trig:
‘1’ trigger, or ‘0’ do not trigger an NVM write operation; the trigger is
only accepted if the NVM was unlocked before and nvm_remain is
greater than ‘0’; flag nvm_rdy must be ‘1’ prior to triggering the write cycle
nvm_prog_mode: ‘1’ unlock, or ‘0’ lock NVM write operation
ACC Register 0x34 (BGW_SPI3_WDT)
Contains settings for the digital interfaces.
Name
Bit
Read/Write
Reset
Value
Content
0x34
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
reserved:
i2c_wdt_en:
i2c_wdt_sel:
spi3:
6
R/W
BGW_SPI3_WDT
5
R/W
4
R/W
0
0
0
2
R/W
1
R/W
0
R/W
0
0
0
0
reserved
i2c_wdt_en
i2c_wdt_sel
spi3
reserved
write ‘0’
if I²C interface mode is selected then ‘1´ enable, or ‘0’ disables the
watchdog at the SDI pin (= SDA for I²C)
select an I²C watchdog timer period of ‘0’ 1 ms, or ‘1’ 50 ms
select ´0´ 4-wire SPI, or ´1´ 3-wire SPI mode
ACC Register 0x35 is reserved
ACC Register 0x36 (OFC_CTRL)
Contains control signals and configuration settings for the fast and the slow offset
compensation.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
0x36
7
W
0
Page 75
6
W
OFC_CTRL
5
W
4
R
0
0
0
offset_reset
cal_trigger
cal_rdy
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
reserved
hp_z_en
hp_y_en
hp_x_en
offset_reset:
´1´ set all offset compensation registers (0x38 to 0x3A) to zero, or ‘0’
keep their values
offset_trigger: trigger fast compensation for ´01b´ x-axis, ´10b´ y-axis, or ´11b´
z-axis; ´00b´ do not trigger offset compensation; offset compensation
must not be triggered when cal_rdy is ‘0’
cal_rdy:
indicates the state of the fast compensation: ´0´ offset compensation is in
progress, or ´1´ offset compensation is ready to be retriggered
reserved:
write ‘0’
hp_z_en:
‘1´ enable, or ‘0’ disable slow offset compensation for the z-axis
hp_y_en:
‘1´ enable, or ‘0’ disable slow offset compensation for the y-axis
hp_x_en:
‘1´ enable, or ‘0’ disable slow offset compensation for the x-axis
ACC Register 0x37 (OFC_SETTING)
Contains configuration settings for the fast and the slow offset compensation.
Name
Bit
Read/Write
Reset
Value
0x37
7
R/W
0
Content
reserved
Bit
Read/Write
Reset
Value
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
Content
offset_target_y
6
R/W
OFC_SETTING
5
R/W
4
R/W
0
0
0
offset_target_z
offset_target_x
offset_target_y
cut_off
reserved:
write ‘0’
offset_target_z: offset compensation target value for z-axis is ´00b´ 0 g, ´01b´ +1 g,
´10b´ -1 g, or ´11b´ 0 g
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 76
offset_target_y: offset compensation target value for y-axis is ´00b´ 0 g, ´01b´ +1 g,
´10b´ -1 g, or ´11b´ 0 g
offset_target_x: offset compensation target value for x-axis is ´00b´ 0 g, ´01b´ +1 g,
´10b´ -1 g, or ´11b´ 0 g
cut_off:
select ‘0’ 1 Hz, or ‘1’ 10 Hz cut-off frequency for slow offset
compensation high-pass filter
ACC Register 0x38 (OFC_OFFSET_X)
Contains the offset compensation value for x-axis acceleration readout data.
Name
Bit
Read/Write
Reset
Value
Content
0x38
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
0
6
R/W
OFC_OFFSET_X
5
R/W
4
R/W
0
0
0
2
R/W
1
R/W
0
R/W
0
0
0
offset_x
offset_x
offset_ x: offset value, which is added to the internal filtered and unfiltered x-axis
acceleration data; the offset value is represented with two’s complement
notation, with a mapping of +127 +0.992g, 0 0 g, and -128 -1 g; the
scaling is independent of the selected g-range; the content of the
offset_x may be written to the NVM; it is automatically restored from
the NVM after each power-on or softreset; offset_x may be written
directly by the user; it is generated automatically after triggering the fast
offset compensation procedure for the x-axis
Example:
Original readout
value
0g
0g
0g
Value in offset
register
127
0
-128
Compensated readout value
0.992 g
0g
-1 g
ACC Register 0x39 (OFC_OFFSET_Y)
Contains the offset compensation value for y-axis acceleration readout data.
Name
Bit
Read/Write
Reset
Value
0x39
7
R/W
0
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
6
R/W
OFC_OFFSET_Y
5
R/W
4
R/W
0
0
0
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© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Content
Bit
Read/Write
Reset
Value
Content
offset_y:
Page 77
offset_y
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
offset_y
offset value, which is added to the internal filtered and unfiltered y-axis
acceleration data; the offset value is represented with two’s complement
notation, with a mapping of +127 +0.992g, 0 0 g, and -128 -1 g; the
scaling is independent of the selected g-range; the content of the
offset_y may be written to the NVM; it is automatically restored from
the NVM after each power-on or softreset; offset_y may be written
directly by the user; it is generated automatically after triggering the fast
offset compensation procedure for the y-axis
For reference see example at ACC Register 0x38 (OFC_OFFSET_X)
ACC Register 0x3A (OFC_OFFSET_Z)
Contains the offset compensation value for z-axis acceleration readout data.
Name
Bit
Read/Write
Reset
Value
Content
0x3A
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
0
offset_z:
6
R/W
OFC_OFFSET_Z
5
R/W
4
R/W
0
0
0
2
R/W
1
R/W
0
R/W
0
0
0
offset_z
offset_z
offset value, which is added to the internal filtered and unfiltered z-axis
acceleration data; the offset value is represented with two’s complement
notation, with a mapping of +127 +0.992g, 0 0 g, and -128 -1 g; the
scaling is independent of the selected g-range; the content of the
offset_z may be written to the NVM; it is automatically restored from
the NVM after each power-on or softreset; offset_z may be written
directly by the user; it is generated automatically after triggering the fast
offset compensation procedure for the z-axis
For reference see example at ACC Register 0x38 (OFC_OFFSET_X)
ACC Register 0x3B (TRIM_GP0)
Contains general purpose data register with NVM back-up.
Name
Bit
0x3B
7
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
6
TRIM_GP0
5
4
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© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 78
Read/Write
Reset
Value
Content
R/W
R/W
R/W
R/W
0
0
0
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
GP0:
GP0
GP0
general purpose NVM image register not linked to any sensor-specific
functionality; register may be written to NVM and is restored after each
power-up or softreset
ACC Register 0x3C (TRIM_GP1)
Contains general purpose data register with NVM back-up.
Name
Bit
Read/Write
Reset
Value
Content
0x3C
7
R/W
6
R/W
TRIM_GP1
5
R/W
4
R/W
0
0
0
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
GP1:
GP1
GP1
general purpose NVM image register not linked to any sensor-specific
functionality; register may be written to NVM and is restored after each
power-up or softreset
ACC Register 0x3D is reserved
ACC Register 0x3E (FIFO_CONFIG_1)
Contains FIFO configuration settings. The FIFO buffer memory is cleared and the fifo-full flag is
cleared when writing to FIFO_CONFIG_1 register.
Name
Bit
Read/Write
Reset
Value
Content
0x3E
7
R/W
0
fifo_mode
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6
R/W
FIFO_CONFIG_1
5
R/W
4
R/W
0
0
0
Reserved
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Bit
Read/Write
Reset
Value
Content
Page 79
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
Reserved
fifo_data_select
fifo_mode:
selects the FIFO operating mode:
´00b´ BYPASS (buffer depth of 1 frame; old data is discarded),
´01b´ FIFO (data collection stops when buffer is filled with 32 frames),
´10b´ STREAM (sampling continues when buffer is full; old is discarded),
´11b´ reserved, do not use
fifo_data_select:
selects whether ´00b´ X+Y+Z, ´01b´ X only, ´10b´ Y only,
´11b´ Z only acceleration data are stored in the FIFO
ACC Register 0x3F (FIFO_DATA)
FIFO data readout register. The format of the LSB and MSB components corresponds to that of
the acceleration data readout registers. The new data flag is preserved. Read burst access may
be used since the address counter will not increment when the read burst is started at the
address of FIFO_DATA. The entire frame is discarded when a fame is only partially read out.
Name
Bit
Read/Write
Reset
Value
Content
0x3F
7
R
6
R
FIFO_DATA
5
R
4
R
n/a
n/a
n/a
n/a
Bit
Read/Write
Reset
Value
Content
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
fifo_data_output_register
fifo_data_output_register
fifo_data_output_register:
FIFO data readout; data format depends on the setting of
register fifo_data_select:
if X+Y+Z data are selected, the data of frame n is reading out in the order of
X-lsb(n), X-msb(n), Y-lsb(n), Y-msb(n), Z-lsb(n), Z-msb(n);
if X-only is selected, the data of frame n and n+1 are reading out in the order
of X-lsb(n), X-msb(n), X-lsb(n+1), X-msb(n+1); the Y-only and Z-only modes
behave analogously
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BMX055
Data sheet
Page 80
7 Functional description Gyroscope
Note: Default values for registers can be found in chapter 8.
7.1
Power modes gyroscope
The gyroscope has four different power modes. Besides normal mode, which represents the
fully operational state of the device, there are three energy saving modes: deep-suspend mode,
suspend mode, and fast power up
Figure 13: Block diagram of the power modes of gyroscope
After power-up gyro is in normal mode so that all parts of the device are held powered-up and
data acquisition is performed continuously.
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BMX055
Data sheet
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In deep-suspend mode the device reaches the lowest possible power consumption. Only the
interface section is kept alive. No data acquisition is performed and the content of the
configuration registers is lost. Deep suspend mode is entered (left) by writing ‘1’ (‘0’) to the
2
(GYR 0x11) deep_suspend bit. The I C watchdog timer remains functional. The (GYR 0x11)
deep_ suspend bit, the (GYR 0x34) spi3 bit, (GYR 0x34) i2c_wdt_en bit and the (GYR 0x34)
i2c_wdt_sel bit are functional in deep-suspend mode. Equally the interrupt level and driver
configuration registers (GYR 0x20) int1_lvl, (GYR 0x20) int1_od, (GYR 0x20) int2_lvl, and (GYR
0x20) int2_od are accessible. Still it is possible to enter normal mode by writing to the (GYR
0x14) softreset register. Please note, that all application specific settings which are not equal to
the default settings (refer to 8.2 register map gyroscope), must be re-set to its designated
values after leaving deep-suspend mode.
In suspend mode the whole analog part is powered down. No data acquisition is performed.
While in suspend mode the latest rate data and the content of all configuration registers are
kept. The only supported operations are reading and writing registers as well as writing to the
(GYR 0x14) softreset register.
Suspend mode is entered (left) by writing ´1´ (´0´) to the (GYR 0x11) suspend bit. Bit (GYR
0x12) fast_power_up must be set to ‘0’.
Although write access to registers is supported at the full interface clock speed (SCL or SCK), a
waiting period must be inserted between two consecutive write cycles (please refer also to
section 9.2.1).
In external wake-up mode, when the device is in deep suspend mode or suspend mode, it
can be woken-up by external trigger to pin INT3/4. Register settings:
Table 23: Trigger source
ext_trig_sel [1:0]
‘00’
‘01’
‘10’
‘11’
Trigger source
No
INT3 pin
INT4 pin
SDO2 pin (SPI3 mode)
In fast power-up mode the sensing analog part is powered down, while the drive and the
digital part remains largely operational. No data acquisition is performed. Reading and writing
registers as well as writing to the (GYR 0x14) softreset register are supported without any
restrictions. The latest rate data and the content of all configuration registers are kept. Fast
power-up mode is entered (left) by writing ´1´ (´0´) to the (GYR 0x11) suspend bit with bit (GYR
0x12) fast_power_up set to ‘1’.
7.1.1
Advanced power-saving modes
In addition to the power modes described in Figure 13, there are other advanced power modes
that can be used to optimize the power consumption of the BMX055.
The power_save_mode is set by setting power_save_mode=´1´ (GYR 0x12). This power mode
implements a duty cycle and change between normal mode and fast-power-up mode. By
setting the sleep_dur (time in ms in fast-power-up mode) (GYR 0x11 bits ) and
auto_sleep_dur (time in ms in normal mode) (GYR 0x12 bits ) different timings can be
used. Some of these settings allow the sensor to consume less than 3mA. See also diagram
below:
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BMX055
Data sheet
i[mA]
powerup
autosleep
dur
autosleep
dur
Page 82
autosleep
dur
autosleep
dur
autosleep
dur
NORMAL
Fast Power
Up
sleep
dur
sleep
dur
sleep
dur
sleep
dur
OFF
sleep
dur
t
Figure 14: Duty-cycling
The possible configuration for the autosleep_dur and sleep_dur are indicated in the table below:
Table 24: Sleep durations gyroscope
sleep_dur
‘000’
‘001’
‘010’
‘011’
‘100’
‘101’
‘110’
‘111’
Time (ms)
2 ms
4 ms
5 ms
8 ms
10 ms
15 ms
18 ms
20 ms
Table 25: Autosleep durations gyroscope
autosleep_dur
‘000’
‘001’
‘010’
‘011’
‘100’
‘101’
‘110’
‘111’
Time (ms)
Not allowed
4 ms
5 ms
8 ms
10 ms
15 ms
20 ms
40 ms
The only restriction for the use of the power save mode comes from the configuration of the
digital filter bandwidth (GYR 0x10). For each Bandwidth configuration, a minimum
autosleep_dur must be ensured. For example, for Bandwidth=47Hz, the minimum
autosleep_dur is 5ms. This is specified in the table below. For sleep_dur there is no restriction.
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Data sheet
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Table 26: Minimum autosleep duration according to bandwidth
bw
‘0111’
‘0110’
‘0101’
‘0100’
‘0011’
‘0010’
‘0001’
‘0000’
7.2
Bandwidth (Hz)
32 Hz
64 Hz
12 Hz
23 Hz
47 Hz
116 Hz
230 Hz
Unfiltered (523Hz)
min. autosleep_dur (ms)
20 ms
10 ms
20 ms
10 ms
5 ms
4 ms
4 ms
4 ms
BMX055 Data Gyroscope
7.2.1
Rate data
The angular rate data can be read-out through addresses GYR 0x02 through GYR 0x07. The
angular rate data is in 2’s complement form according to Table 27 below. In order to not corrupt
the angular rate data, the LSB should always be read out first. Once the LSB of the x,y, or z
read-out registers have been read, the MSBs are locked until the MSBs are read out.
This default behavior can be switched off by setting the address (GYR 0x13) bit 6 (shadow_dis)
= ‘1’. In this case there is no MSB locking, and the data is updated between each read.
2
The burst-access mechanism provides an efficient way to read out the angular rate data in I C
or SPI mode. During a burst-access, the gyro automatically increments the starting read
address after each byte. Any address in the user space can be used as a starting address.
When the address (GYR 0x3F – fifo_data) is reached, the address counter is stopped. In the
user space address range, the (GYR 0x3F – fifo_data) will be continuously read out until burst
read ends. It is also possible to start directly with address 0x3F. In this case, the fifo_data
(GYR 0x3F) data will be read out continuously. The burst-access allows data to be transferred
over the I2C bus with an up to 50% reduced data density. The angular rate data in all read-out
registers is locked as long as the burst read access is active. Reading the chip angular rate
registers in burst read access mode ensures that the angular rate values in all readout registers
belong to the same sample.
Table 27: Gyroscope register content for 16bit mode
Decimal value
+32767
…
0
…
-32767
Angular rate (in 2000°/s range mode)
+ 2000°/s
…
0°/s
…
- 2000°/s
Per default, the bandwidth of the data being read-out is limited by the internal low-pass filters
according to the filter configuration. Unfiltered (high-bandwidth) data can be read out through
the serial interface when the data_high_bw (GYR 0x13 bit 7) is set to ‘1’.
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Data sheet
7.3
Page 84
Angular rate Read-Out
Bandwidth configuration: The gyro processes the 2kHz data out of the analog front end with a
CIC/Decimation filter, followed by an IIR filter before sending this data to the interrupt handler.
The possible decimation factors are 2, 5, 10 and 20. It is also possible to bypass these filters,
and use the unfiltered 2kHz data. The decimation factor / bandwidth of the filter can be set by
setting the address space GYR 0x10 bits (bw) as shown in the memory map
section.
7.4
Self-test Gyro
A built-in self test (BIST) facility has been implemented which provides a quick way to
determine if the gyroscope is operational within the specified conditions.
The BIST uses three parameters for evaluation of proper device operation:
- Drive voltage regulator
- Sense frontend offset regulator of x-,y- and z-channel
- Quad regulator for x-,y- and z-channel
If any of the three parameters is not within the limits the BIST result will be “Fail”.
To trigger the BIST ´bit0´ bite_trig in address GYR 0x3C must be set `1´. When the test is
performed, bit1 bist_rdy will be ´1´. If the result is failed the bit bist_failed will be set to ´1´,
otherwise stay a ´0´.
bite_trig
0x3C = `1`
bist_rdy = ´1´
bist_failed = ´1´
Result: Failure
bist_failed = ´0´
Result: OK
Figure 15: Flow Diagram
Another possibility to get information about the sensor status is to read out rate_ok GYR 0x3C
bit4. ´1´ indicates proper sensor function, no trigger is needed for this.
7.5
Offset compensation gyroscope
Offsets in measured signals can have several causes but they are always unwanted and
disturbing in many cases. Therefore, the gyro offers an advanced set of four digital offset
compensation methods which are closely matched to each other. These are slow, fast, and
manual compensation as well as inline calibration.
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Data sheet
Page 85
The compensation is performed with filtered data, and is then applied to both, unfiltered and
filtered data. If necessary the result of this computation is saturated to prevent any overflow
errors (the smallest or biggest possible value is set, depending on the sign). However, the
registers used to read and write compensation values have a width of 8 bits.
The public offset compensation registers (GYR 0x36) to (GYR 0x39) are image of the
corresponding registers in the NVM. With each image update (see section 7.6 Non-volatile
memory gyroscope for details) the contents of the NVM registers are written to the public
registers. The public register can be over-written by the user at any time.
In case an internally computed compensation value is too small or too large to fit into the
corresponding register, it is saturated in order to prevent an overflow error.
For every axes an offset up to 125°/s with 12 bits full resolution can be calibrated (resolution
0.06°/s).
The modes will be controlled using SPI/I2C commands.
By writing ´1´ to the (GYR 0x21) offset_reset bit, all dynamic (fast & slow) offset compensation
registers are reset to zero.
7.5.1
Slow compensation
In slow regulation mode, the rate data is monitored permanently. If the rate data is above 0°/s
for a certain period of time, an adjustable rate is subtracted by the offset controller. This
procedure of monitoring the rate data and subtracting of the adjustable rate at a time is
repeated continuously. Thus, the output of the offset converges to 0°/s.
The slow regulation can be enabled through the slow_offset_en_x/y/z (GYR 0x31 ) bits for
each axis. The slow offset cancellation will work for filtered and unfiltered data
(slow_offset_unfilt (GYR 0x1A ); slow_offset_unfilt=1 unfiltered data are selected)
Slow Offset cancellation settings are the adjustable rate (slow offset_th 0x31 ) and the
time period (slow_offset_dur 0x31 )
7.5.2
Fast compensation
A fast offset cancellation controller is implemented in gyro. The fast offset cancellation process
is triggerable via SPI/I2C.
The fast offset cancellation can be enabled through the fast_offset_en_x/y/z (GYR 0x32 )
bits for each axis. The enable bits will not start the fast offset cancellation! The fast offset
cancellation has to be started by setting the fast_offset_en (GYR 0x32 ) bit. Afterwards the
algorithm will start and if the algorithm is finished the fast_offset_en (GYR 0x32 ) will be
reset to 0.
The fast offset cancellation will work for filtered and unfiltered data (fast_offset_unfilt (GYR 0x1B
); fast_offset_unfilt=1 unfiltered data are selected)
The fast offset cancellation parameters are fast_offset_wordlength (GYR 0x32 )
The sample rate for the fast offset cancellation corresponds to the sample rate of the selected
bandwidth. For unfiltered data and bandwidth settings 0-2 the sample rate for the fast offset
cancellation will be 400Hz.
The resolution of the calculated offset values for the fast offset compensation depends on the,
range setting being less accurate for higher range (e.g. range=2000°/s).Therefore we
recommend a range setting of range=125°/s for fast offset compensation.
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Data sheet
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7.5.3
Manual compensation
The contents of the public compensation registers (GYR 0x36 … 0x39) offset_x/y/z can be set
manually via the digital interface. It is recommended to write into these registers directly after a
new data interrupt has occurred in order not to disturb running offset computations.
Writing to the offset compensation registers is not allowed while the fast compensation
procedure is running.
7.5.4
Inline calibration
For certain applications, it is often desirable to calibrate the offset once and to store the
compensation values permanently. This can be achieved by using one of the aforementioned
offset compensation methods to determine the proper compensation values and then storing
these values permanently in the NVM. See section 7.6 Non-volatile memory gyroscope for
details of the storing procedure.
Each time the device is reset, the compensation values are loaded from the non-volatile
memory into the image registers and used for offset compensation until they are possibly
overwritten using one of the other compensation methods.
7.6
Non-volatile memory gyroscope
The entire memory of the gyro consists of three different kinds of registers: hard-wired, volatile,
and non-volatile. Part of it can be both read and written by the user. Access to non-volatile
memory is only possible through (volatile) image registers.
Altogether, there are eight registers (octets) with NVM backup which are accessible by the user.
The addresses of the image registers range from (GYR 0x36) to (GYR 0x3B). While the
addresses up to (GYR 0x39) are used for offset compensation (see 7.5 Offset compensation
gyroscope), addresses (GYR 0x3A) and (GYR 0x3B) are general purpose registers not linked to
any sensor-specific functionality.
The content of the NVM is loaded to the image registers after a reset (either POR or softreset)
or after a user request which is performed by writing ´1´ to the write-only bit (GYR 0x33)
nvm_load. As long as the image update is in progress, bit (GYR 0x33) nvm_rdy is ´0´,
otherwise it is ´1´. In order to read out the correct values (after NVM loading) waiting time is
min. 1ms.
The image registers can be read and written like any other register.
Writing to the NVM is a three-step procedure:
4. Write the new contents to the image registers.
5. Write ´1´ to bit (GYR 0x33) nvm_prog_mode in order to unlock the NVM.
6. Write ´1´ to bit (GYR 0x33) nvm_prog_trig and keep ´1´ in bit (GYR 0x33)
nvm_prog_mode in order to trigger the write process.
Writing to the NVM always renews the entire NVM contents. It is possible to check the write
status by reading bit (GYR 0x33) nvm_rdy. While (GYR 0x33) nvm_rdy = ´0´, the write process
is still in progress; if (GYR 0x33) nvm_rdy = ´1´, then writing is completed. As long as the write
process is ongoing, no change of power mode and image registers is allowed. Also, the NVM
write cycle must not be initiated while image registers are updated, in suspend mode.
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BMX055
Data sheet
Page 87
Please note that the number of permitted NVM write-cycles is limited as specified in Table 3.
The number of remaining write-cycles can be obtained by reading bits (GYR 0x33)
nvm_remain.
7.7
Interrupt controller Gyroscope
The gyro is equipped with 3 programmable interrupt engines. Each interrupt can be
independently enabled and configured. If the trigger condition of an enabled interrupt is fulfilled,
the corresponding status bit is set to ´1´ and the selected interrupt pin is activated. The gyro
provides two interrupt pins, INT3 and INT4; interrupts can be freely mapped to any of these
pins. The state of a specific interrupt pin is derived from a logic ´or´ combination of all interrupts
mapped to it.
The interrupt status registers are updated when a new data word is written into the rate data
registers. If an interrupt is disabled, all active status bits associated with it are immediately
reset.
Gyro Interrupts are fully functional in normal mode, only. Interrupts are limited in their
functionality in other operation modes. Please contact our technical support for further
assistance.
7.7.1
General features
An interrupt is cleared depending on the selected interrupt mode, which is common to all
interrupts. There are three different interrupt modes: non-latched, latched, and temporary. The
mode is selected by the (GYR 0x21) latch_int bits according to Table 28.
Table 28: Interrupt mode selection
(GYR 0x21) latch_int
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Interrupt mode
non-latched
temporary, 250ms
temporary, 500ms
temporary, 1s
temporary, 2s
temporary, 4s
temporary, 8s
latched
non-latched
temporary, 250µs
temporary, 500µs
temporary, 1ms
temporary, 12.5ms
temporary, 25ms
temporary, 50ms
latched
An interrupt is generated if its activation condition is met. It cannot be cleared as long as the
activation condition is fulfilled. In the non-latched mode the interrupt status bit and the selected
pin (the contribution to the ´or´ condition for INT3 and/or INT4) are cleared as soon as the
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Data sheet
Page 88
activation condition is no more valid. Exception to this behavior is the new data interrupt which
is automatically reset after a fixed time.
In latched mode an asserted interrupt status and the selected pin are cleared by writing ´1´ to
bit (GYR 0x21) reset_int. If the activation condition still holds when it is cleared, the interrupt
status is asserted again with the next change of the rate registers.
In the temporary mode an asserted interrupt and selected pin are cleared after a defined period
of time. The behavior of the different interrupt modes is shown graphically in Figure 16. The
timings in this mode are subject to the same tolerances as the bandwidths (see Table 3).
internal signal from
interrupt engine
interrupt output
non-latched
latch period
temporary
latched
Figure 16: Interrupt modes
7.7.2
Mapping to physical interrupt pins (inttype to INT Pin#)
Registers (GYR 0x17) to (GYR 0x19) are dedicated to mapping of interrupts to the interrupt pins
“INT3” or “INT4”. Setting (GYR 0x17) int1_”inttype” to ´1´ (´0´) maps (unmaps) “inttype” to pin
“INT3”. Correspondingly setting (GYR 0x19) int2_”inttype” to ´1´ (´0´) maps (unmaps) “inttype”
to pin “INT4”.
Note: “inttype” has to be replaced with the precise notation, given in the memory map in chapter
8.
7.7.3
Electrical behaviour (INT pin# to open-drive or push-pull)
Both interrupt pins can be configured to show the desired electrical behavior. The ´active´ level
of each interrupt pin is determined by the (GYR 0x16) int1_lvl and (GYR 0x16) int2_lvl bits.
If (GYR 0x16) int1_lvl = ´1´ (´0´) / (GYR 0x16) int2_lvl = ´1´ (´0´), then pin “INT3” / pin “INT4” is
active ´1´ (´0´). The characteristic of the output driver of the interrupt pins may be configured
with bits (GYR 0x16) int1_od and (GYR 0x16) int2_od. By setting bits (GYR 0x16) int1_od /
(GYR 0x16) int2_od to ´1´, the output driver shows open-drive characteristic, by setting the
configuration bits to ´0´, the output driver shows push-pull characteristic. When open-drive
characteristic is selected in the design, external pull-up or pull-down resistor should be applied
according the int_lvl configuration. When open-drive characteristic is selected in the design,
external pull-up or pull-down resistor should be applied according the int_lvl configuration.
7.7.4
New data interrupt
This interrupt serves for synchronous reading of angular rate data. It is generated after storing a
new value of z-axis angular rate data in the data register. The interrupt is cleared automatically
after 280-400 µs (depending on Interrupt settings).
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 89
The interrupt mode of the new data interrupt is fixed to non-latched.
It is enabled (disabled) by writing ´1´ (´0´) to bit (GYR 0x15) data_en. The interrupt status is
stored in bit (GYR 0x0A) data_int.
7.7.5
Any-motion detection / Interrupt
Any-motion (slope) detection uses the slope between successive angular rate signals to detect
changes in motion. An interrupt is generated when the slope (absolute value of angular rate
difference) exceeds a preset threshold. It is cleared as soon as the slope falls below the
threshold. The principle is made clear in Figure 17.
angular rate
rate(t0)
rate(t0−1/(4*fs))
time
slope(t0)=gyro(t0)−gyro(t0−1/(2*bw))
slope
slope_th
time
slope_dur
slope_dur
INT
time
Figure 17: Principle of gyroscope any-motion detection
The threshold is defined through register (GYR 0x1B) any_th. In terms of scaling 1 LSB of
(GYR 0x1B) any_th corresponds to 1 °/s in 2000°/s-range (0.5°/s in 1000°/s-range, 0.25°/s in
500°/s -range …). Therefore the maximum value is 125°/s in 2000°/s-range (62.5°/s 1000°/srange, 31.25°/s in 500°/s -range …).
The time difference between the successive angular rate signals depends on the selected
update rate(fs) which is coupled to the bandwidth and equates to 1/(4*fs) (t=1/(4*fs)). For
bandwidhth settings with an update rate higher than 400Hz (bandwidth =0, 1, 2) fs is set to
400Hz.
In order to suppress false triggers, the interrupt is only generated (cleared) if a certain number
N of consecutive slope data points is larger (smaller) than the slope threshold given by (GYR
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 90
0x1B) any_th. This number is set by the (GYR 0x1C) any_dursample bits. It is N = [(GYR 0x1C)
any_dursample+ 1]*4 for (GYR 0x1C). N is set in samples. Thus the time is scaling with the
update rate (fs). Example: (GYR 0x1C) slope_dur = 00b, …, 11b = 4 samples, …, 16 samples.
7.7.5.1
Enabling (disabling) for each axis
Any-motion detection can be enabled (disabled) for each axis separately by writing ´1´ (´0´) to
bits (GYR 0x1C) any_en_x, (GYR 0x1C) any_en_y, (GYR 0x1C) any_en_z. The criteria for
any-motion detection are fulfilled and the Any-Motion interrupt is generated if the slope of any of
the enabled axes exceeds the threshold (GYR 0x1B) any_th for [(GYR 0x1C) slope_dur +1]*4
consecutive times. As soon as the slopes of all enabled axes fall or stay below this threshold for
[(GYR 0x1C) slope_dur +1]*4 consecutive times the interrupt is cleared unless interrupt signal is
latched.
7.7.5.2
Axis and sign information of slope / any motion interrupt
The interrupt status is stored in bit (GYR 0x09) any_int. The Any-motion interrupt supplies
additional information about the detected slope. The axis which triggered the interrupt is given
by that one of bits (GYR 0x0B) any_first_x, (GYR 0x0B) any_first_y, (GYR 0x0B) any_first_z
that contains a value of ´1´. The sign of the triggering slope is held in bit (GYR 0x0B) any_sign
until the interrupt is retriggered. If (GYR 0x0B) slope_sign = ´1´ (´0´), the sign is positive
(negative).
7.7.6
High-Rate interrupt
This interrupt is based on the comparison of angular rate data against a high-rate threshold for
the detection of shock or other high-angular rate events. The principle is made clear in Figure
18 below:
Figure 18: High rate interrupt
The high-rate interrupt is enabled (disabled) per axis by writing ´1´ (´0´) to bits (GYR 0x22)
high_en_x, (GYR 0x24) high_en_y, and (GYR 0x26) high_en_z, respectively. The high-rate
threshold is set through the (GYR 0x22) high_th_x register, (GYR 0x24) high_th_y register and
(GYR 0x26) high_th_z for the corresponding axes. The meaning of an LSB of (GYR
0x22/24/26) high_th_x/y/z depends on the selected °/s-range: it corresponds to 62.5°/s in
2000°/s-range, 31.25°/s in 1000°/s-range, 15.625°/s in 500°/s -range …). The high_th_x/y/z
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 91
register setting 0 corresponds to 62.26°/s in 2000°/s-range, 31.13°/s in 1000°/s-range, 15.56°/s
in 500°/s-range …. Therefore the maximum value is 1999.76°/s in 2000°/s-range (999.87°/s
1000°/s-range, 499.93°/s in 500°/s -range …).
A hysteresis can be selected by setting the (GYR 0x22/24/26) high_hy_x/y/z bits. Analogously
to (GYR 0x22/24/26) high_th_x/y/z, the meaning of an LSB of (GYR 0x22/24/26) high_hy_x/y/z
bits is °/s-range dependent: The high_hy_x/y/z register setting 0 corresponds to an angular rate
difference of 62.26°/s in 2000°/s-range, 31.13°/s in 1000°/s-range, 15.56°/s in 500°/s-range ….
The meaning of an LSB of (GYR 0x22/24/26) high_hy_x/y/z depends on the selected °/s-range
too: it corresponds to 62.5°/s in 2000°/s-range, 31.25°/s in 1000°/s-range, 15.625°/s in 500°/s range …).
The high-rate interrupt is generated if the absolute value of the angular rate of at least one of
the enabled axes (´or´ relation) is higher than the threshold for at least the time defined by the
(GYR 0x23/25/27) high_dur_x/y/z register. The interrupt is reset if the absolute value of the
angular rate of all enabled axes (´and´ relation) is lower than the threshold minus the
hysteresis. In bit (GYR 0x09) high_int the interrupt status is stored. The relation between the
content of (GYR 0x23/25/27) high_dur_x/y/z and the actual delay of the interrupt generation is
delay [ms] = [(GYR 0x23/25727) high_dur_x/y/z + 1] * 2.5 ms. Therefore, possible delay times
range from 2.5 ms to 640 ms.
7.7.6.1
Axis and sign information of high-rate interrupt
The axis which triggered the interrupt is indicated by bits (GYR 0x0C) high_first_x, (GYR 0x0C)
high_first_y, and (GYR 0x0C) high_first_z. The bit corresponding to the triggering axis contains
a ´1´ while the other bits hold a ´0´. These bits are cleared together with clearing the interrupt
status. The sign of the triggering angular rate is stored in bit (GYR 0x0C) high_sign. If (GYR
0x0C) high_sign = ´1´ (´0´), the sign is positive (negative).
8 Register description gyroscope
8.1
General remarks
The entire communication with the device is performed by reading from and writing to registers.
Registers have a width of 8 bits; they are mapped to a common space of 64 addresses from
(GYR 0x00) up to (GYR 0x3F). Within the used range there are several registers which are
either completely or partially marked as ‘reserved’. Any reserved bit is ignored when it is written
and no specific value is guaranteed when read. It is recommended not to use registers at all
which are completely marked as ‘reserved’. Furthermore it is recommended to mask out (logical
and with zero) reserved bits of registers which are partially marked as reserved.
Registers with addresses from (GYR 0x00) up to (GYR 0x0E) are read-only. Any attempt to
write to these registers is ignored. There are bits within some registers that trigger internal
sequences. These bits are configured for write-only access, e. g. (GYR 0x21) reset_int or the
entire (GYR 0x14) softreset register, and read as value ´0´.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
8.2
Register
Address
0x3F
0x3E
0x3D
0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Page 92
Register map gyroscope
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
fifo_data[7]
mode[1]
tag
fifo_data[6]
mode[0]
h2o_mrk_lvl_trig_ret[6]
fifo_data[5]
fifo_data[4]
fifo_data[3]
fifo_data[2]
h2o_mrk_lvl_trig_ret[5]
h2o_mrk_lvl_trig_ret[3]
gp0[11]
gp0[3]
offset_z[11]
offset_y[11]
offset_x[11]
offset_x[3]
gp0[10]
gp0[2]
offset_z[10]
offset_y[10]
offset_x[10]
offset_x[2]
gp0[9]
gp0[1]
offset_z[9]
offset_y[9]
offset_x[9]
offset_y[3]
h2o_mrk_lvl_trig_ret[4]
rate_ok
gp0[8]
gp0[0]
offset_z[8]
offset_y[8]
offset_x[8]
offset_y[2]
gp0[7]
offset_x[1]
offset_z[7]
offset_y[7]
offset_x[7]
offset_y[1]
h2o_mrk_lvl_trig_ret[2]
bist_fail
gp0[6]
offset_x[0]
offset_z[6]
offset_y[6]
offset_x[6]
offset_z[3]
fifo_data[1]
data_select[1]
h2o_mrk_lvl_trig_ret[1]
bist_rdy
gp0[5]
offset_y[0]
offset_z[5]
offset_y[5]
offset_x[5]
offset_z[2]
fifo_data[0]
data_select[0]
h2o_mrk_lvl_trig_ret[0]
trig_bist
gp0[4]
offset_z[0]
offset_z[4]
offset_y[4]
offset_x[4]
offset_z[1]
Access Reset Value
nvm_remain[3]
auto_offset_wordlength[1]
slow_offset_th[1]
nvm_remain[2]
auto_offset_wordlength[0]
slow_offset_th[0]
ext_fifo_sc_en
nvm_remain[1]
fast_offset_wordlength[1]
slow_offset_dur[2]
ext_fifo_s_sel
nvm_remain[0]
fast_offset_wordlength[0]
slow_offset_dur[1]
burst_same_en
nvm_load
fast_offset_en
slow_offset_dur[0]
i2c_wdt_en
nvm_rdy
fast_offset_en_z
slow_offset_en_z
i2c_wdt_sel
nvm_prog_trig
fast_offset_en_y
slow_offset_en_y
spi3
nvm_prog_mode
fast_offset_en_x
slow_offset_en_x
high_dur_z[7]
high_hy_z[1]
high_dur_y[7]
high_hy_y[1]
high_dur_x[7]
high_hy_x[1]
reset_int
high_dur_z[6]
high_hy_z[0]
high_dur_y[6]
high_hy_y[0]
high_dur_x[6]
high_hy_x[0]
offset_reset
high_dur_z[5]
high_th_z[4]
high_dur_y[5]
high_th_y[4]
high_dur_x[5]
high_th_x[4]
high_dur_z[4]
high_th_z[3]
high_dur_y[4]
high_th_y[3]
high_dur_x[4]
high_th_x[3]
latch_status_bits
high_dur_z[3]
high_th_z[2]
high_dur_y[3]
high_th_y[2]
high_dur_x[3]
high_th_x[2]
latch_int[3]
high_dur_z[2]
high_th_z[1]
high_dur_y[2]
high_th_y[1]
high_dur_x[2]
high_th_x[1]
latch_int[2]
high_dur_z[1]
high_th_z[0]
high_dur_y[1]
high_th_y[0]
high_dur_x[1]
high_th_x[0]
latch_int[1]
high_dur_z[0]
high_en_z
high_dur_y[0]
high_en_y
high_dur_x[0]
high_en_x
latch_int[0]
awake_dur[1]
fast_offset_unfilt
awake_dur[0]
any_th[6]
any_dursample[1]
any_th[5]
slow_offset_unfilt
any_dursample[0]
any_th[4]
any_en_z
any_th[2]
any_en_x
any_th[0]
int2_data
int2_fast_offset
int2_fifo
int2_auto_offset
any_en_y
any_th[1]
any_unfilt_data
int2_any
int1_fast_offset
int1_any
int1_od
softreset[1]
softreset[0]
autosleep_dur[1]
sleep_dur[0]
bw[1]
range[1]
frame_counter[1]
autosleep_dur[0]
frame_counter[3]
autosleep_dur[2]
sleep_dur[1]
bw[2]
range[2]
frame_counter[2]
bw[0]
range[0]
frame_counter[0]
high_sign
any_sign
high_first_z
any_first_z
high_first_y
any_first_y
high_first_x
any_first_x
any_int
high_int
fifo_wm_en
data_en
softreset[7]
data_high_bw
fast_powerup
suspend
fifo_en
softreset[6]
shadow_dis
power_save_mode
Overrun
data_int
softreset[5]
softreset[4]
ext_trig_sel[1]
deep_suspend
ext_trig_sel[0]
frame_counter[6]
frame_counter[5]
frame_counter[4]
auto_offset_int
fast_ofsset_int
fifo_int
any_th[3]
high_unfilt_data
int2_high
int1_auto_offset
int1_high
int2_od
softreset[3]
sleep_dur[2]
bw[3]
int1_fifo
int2_lvl
auto_offset_en
softreset[2]
int1_data
int1_lvl
rate_z[15]
rate_z[7]
rate_y[15]
rate_y[7]
rate_x[15]
rate_x[7]
rate_z[14]
rate_z[6]
rate_y[14]
rate_y[6]
rate_x[14]
rate_x[6]
rate_z[13]
rate_z[5]
rate_y[13]
rate_y[5]
rate_x[13]
rate_x[5]
rate_z[12]
rate_z[4]
rate_y[12]
rate_y[4]
rate_x[12]
rate_x[4]
rate_z[11]
rate_z[3]
rate_y[11]
rate_y[3]
rate_x[11]
rate_x[3]
rate_z[10]
rate_z[2]
rate_y[10]
rate_y[2]
rate_x[10]
rate_x[2]
rate_z[9]
rate_z[1]
rate_y[9]
rate_y[1]
rate_x[9]
rate_x[1]
rate_z[8]
rate_z[0]
rate_y[8]
rate_y[0]
rate_x[8]
rate_x[0]
chip_id[7]
chip_id[6]
chip_id[5]
chip_id[4]
chip_id[3]
chip_id[2]
chip_id[1]
chip_id[0]
ro
w/r
w/r
ro
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
w/r
wo
w/r
w/r
w/r
w/r
wo
wo
w/r
w/r
w/r
w/r
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
0x00
0x00
0x00
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x00
0x00
0x00
0xC0
0x60
0xE8
0xE0
0x81
0x40
0x42
0x22
0xE8
0x19
0x24
0x19
0x02
0x19
0x02
0x19
0x02
0x00
0x00
0x28
0x08
0xC9
0xA0
0x04
0x00
0x00
0x00
0x00
0x0F
0x00
0x00
0x00
0x00
0x00
0x80
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0F
w/r
write only
read only
res. future use
common w/r registers: Application specific settings which are not equal to the default settings,
must be re-set to its designated values after POR, soft-reset and wake up from deep suspend.
user w/r registers: Initial default content = 0x00. Freely programmable by the user.
Remains unchanged after POR, soft-reset and wake up from deep suspend.
Figure 19: Register map gyroscope
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 93
GYR Register 0x00 (CHIP_ID)
The register contains the chip identification code.
Name
Bit
Read/Write
Reset
Value
Content
0x00
7
R
n/a
Bit
Read/Write
Reset
Value
Content
3
R
n/a
chip_id:
6
R
CHIP_ID
5
R
4
R
n/a
n/a
n/a
2
R
1
R
0
R
n/a
n/a
n/a
chip_id
chip_id
Fixed value b’0000’1111 =0x0F
GYR Register 0x01 is reserved
GYR Register 0x02 (RATE_X_LSB)
The register contains the least-significant bits of the X-channel angular rate readout value.
When reading out X-channel angular rate values, data consistency is guaranteed if the
RATE_X_LSB is read out before the RATE_X_MSB and shadow_dis=’0’. In this case, after the
RATE_X_LSB has been read, the value in the RATE_X_MSB register is locked until the
RATE_X_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Angular rate data may be read from register RATE_X_LSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x02
7
R
n/a
Bit
Read/Write
Reset
Value
Content
3
R
n/a
6
R
RATE_X_LSB
5
R
4
R
n/a
n/a
n/a
2
R
1
R
0
R
n/a
n/a
n/a
rate_x_lsb
rate_x_lsb
rate_x_lsb: Least significant 8 bits of rate read-back value; (two’s-complement format)
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 94
GYR Register 0x03 (RATE_X_MSB)
The register contains the most-significant bits of the X-channel angular rate readout value.
When reading out X-channel angular rate values, data consistency is guaranteed if the
RATE_X_LSB is read out before the RATE_X_MSB and shadow_dis=’0’. In this case, after the
RATE_X_LSB has been read, the value in the RATE_X_MSB register is locked until the
RATE_X_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Angular rate data may be read from register RATE_X_MSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x03
7
R
6
R
RATE_X_MSB
5
R
4
R
n/a
n/a
n/a
n/a
Bit
Read/Write
Reset
Value
Content
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
rate_x_msb
rate_x_msb
rate_x_msb: Most significant 8 bits of rate read-back value (two’s-complement format)
GYR Register 0x04 (RATE_Y_LSB)
The register contains the least-significant bits of the Y-channel angular rate readout value.
When reading out Y-channel angular rate values, data consistency is guaranteed if the
RATE_Y_LSB is read out before the RATE_Y_MSB and shadow_dis=’0’. In this case, after the
RATE_Y_LSB has been read, the value in the RATE_Y_MSB register is locked until the
RATE_Y_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Angular rate data may be read from register RATE_Y_LSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x04
7
R
n/a
Bit
Read/Write
Reset
Value
Content
3
R
n/a
6
R
RATE_Y_LSB
5
R
4
R
n/a
n/a
n/a
2
R
1
R
0
R
n/a
n/a
n/a
rate_y_lsb
rate_y_lsb
rate_y_lsb: Least significant 8 bits of rate read-back value; (two’s-complement format)
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 95
GYR Register 0x05 (RATE_Y_MSB)
The register contains the most-significant bits of the Y-channel angular rate readout value.
When reading out Y-channel angular rate values, data consistency is guaranteed if the
RATE_Y_LSB is read out before the RATE_Y_MSB and shadow_dis=’0’. In this case, after the
RATE_Y_LSB has been read, the value in the RATE_Y_MSB register is locked until the
RATE_Y_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Angular rate data may be read from register RATE_Y_MSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x05
7
R
6
R
RATE_Y_MSB
5
R
4
R
n/a
n/a
n/a
n/a
Bit
Read/Write
Reset
Value
Content
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
rate_y_msb
rate_y_msb
rate_y_msb: Most significant 8 bits of rate read-back value (two’s-complement format)
GYR Register 0x06 (RATE_Z_LSB)
The register contains the least-significant bits of the Z-channel angular rate readout value.
When reading out Z-channel angular rate values, data consistency is guaranteed if the
RATE_Z_LSB is read out before the RATE_Z_MSB and shadow_dis=’0’. In this case, after the
RATE_Z_LSB has been read, the value in the RATE_Z_MSB register is locked until the
RATE_Z_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Angular rate data may be read from register RATE_Z_LSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x06
7
R
n/a
Bit
Read/Write
Reset
Value
Content
3
R
n/a
6
R
RATE_Z_LSB
5
R
4
R
n/a
n/a
n/a
2
R
1
R
0
R
n/a
n/a
n/a
rate_z_lsb
rate_z_lsb
rate_z_lsb: Least significant 8 bits of rate read-back value; (two’s-complement format)
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 96
GYR Register 0x07 (RATE_Z_MSB)
The register contains the most-significant bits of the Z-channel angular rate readout value.
When reading out Z-channel angular rate values, data consistency is guaranteed if the
RATE_Z_LSB is read out before the RATE_Z_MSB and shadow_dis=’0’. In this case, after the
RATE_Z_LSB has been read, the value in the RATE_Z_MSB register is locked until the
RATE_Z_MSB has been read. This condition is inherently fulfilled if a burst-mode read access
is performed. Angular rate data may be read from register RATE_Z_MSB at any time except
during power-up and in DEEP_SUSPEND mode.
Name
Bit
Read/Write
Reset
Value
Content
0x07
7
R
6
R
RATE_Z_MSB
5
R
4
R
n/a
n/a
n/a
n/a
Bit
Read/Write
Reset
Value
Content
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
rate_z_msb
rate_z_msb
rate_z_msb: Most significant 8 bits of rate read-back value (two’s-complement format)
GYR Register 0x08 reserved
GYR Register 0x09 (INT_STATUS_0)
The register contains interrupt status bits.
Name
Bit
Read/Write
Reset
Value
Content
0x09
7
R
n/a
Bit
Read/Write
Reset
Value
Content
3
R
any_int:
high_int:
6
R
INT_STATUS_0
5
R
4
R
n/a
n/a
n/a
2
R
1
R
0
R
n/a
n/a
n/a
n/a
reserved
any_int
high_int
reserved
reserved
Any motion interrupt status
High rate interrupt status
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 97
GYR Register 0x0A (INT_STATUS_1)
The register contains interrupt status bits.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
data_int:
auto_offset_int:
fast_offset_int:
fifo_int:
0x0A
7
R
6
R
INT_STATUS_1
5
R
4
R
n/a
n/a
n/a
n/a
data_int
auto_offset_int
fast_offset_int
fifo_int
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
reserved
New data interrupt status
Auto Offset interrupt status
Fast Offset interrupt status
Fifo interrupt status
GYR Register 0x0B (INT_STATUS_2)
The register contains any motion interrupt status bits,
Name
Bit
Read/Write
Reset
Value
Content
0x0B
7
R
6
R
INT_STATUS_2
5
R
4
R
n/a
n/a
n/a
n/a
Bit
Read/Write
Reset
Value
Content
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
any_sign
any_first_z
any_first_y
any_first_x
any_sign:
any_first_z:
any_first_y:
any_first_x:
reserved
sign of any motion interrupt (‘1’= positive, ‘0’=negative)
‘1’ indicates that z-axis is triggering axis of any motion interrupt
‘1’ indicates that y-axis is triggering axis of any motion interrupt
‘1’ indicates that z-axis is triggering axis of any motion interrupt
GYR Register 0x0C (INT_STATUS_3)
The register contains high rate interrupt status bits.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Name
Bit
Read/Write
Reset
Value
Content
0x0C
7
R
n/a
Bit
Read/Write
Reset
Value
Content
3
R
high_sign:
high_first_z:
high_first_y:
high_first_x:
Page 98
6
R
INT_STATUS_3
5
R
4
R
n/a
n/a
n/a
2
R
1
R
0
R
n/a
n/a
n/a
n/a
high_sign
high_first_z
high_first_y
high_first_x
reserved
sign of high rate interrupt (‘1’= positive, ‘0’=negative)
‘1’ indicates that z-axis is triggering axis of high rate interrupt
‘1’ indicates that y-axis is triggering axis of high rate interrupt
‘1’ indicates that z-axis is triggering axis of high rate interrupt
GYR Register 0x0D is reserved
GYR Register 0x0E (FIFO_STATUS)
The register contains FIFO status flags.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
fifo_overrun:
0x0E
7
R
n/a
6
R
FIFO_STATUS
5
R
4
R
n/a
n/a
n/a
fifo_overrun
fifo_frame_counter
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
fifo_frame_counter
FIFO overrun condition has ‘1’ occurred, or ‘0’not occurred; flag can be
cleared by writing to the FIFO configuration register FIFO_CONFIG_1 only
fifo_frame_counter:
Current fill level of FIFO buffer. An empty FIFO corresponds to
0x00. The frame counter can be cleared by reading out all frames
from the FIFO buffer or writing to the FIFO configuration register
FIFO_CONFIG_1.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 99
GYR Register 0x0F (RANGE)
The gyroscope supports four different angular rate measurement ranges. A measurement
range is selected by setting the (0x0F) range bits as follows:
Name
Bit
Read/Write
Reset
Value
Content
0x0F
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
0
6
R/W
RANGE
5
R/W
4
R/W
0
0
0
2
R/W
1
R/W
0
R/W
0
0
0
reserved
0
reserved
range
range: Angular Rate Range and Resolution.
Table 29: Angular Rate Range and Resolution
range
‘000’
‘001’
‘010’
‘011’
‘100’
‘101’, ´110´, ´111´
reserved:
Full Scale
±2000°/s
±1000°/s
±500°/s
±250°/s
±125°/s
reserved
Resolution
16.4 LSB/°/s 61.0 m°/s / LSB
32.8 LSB/°/s 30.5 m°/s / LSB
65.6 LSB/°/s 15.3 m°/s / LSB
131.2 LSB/°/s 7.6 m°/s / LSB
262.4 LSB/°/s 3.8m°/s / LSB
write ‘0’
GYR Register 0x10 (BW)
The register allows the selection of the rate data filter bandwidth.
Name
Bit
Read/Write
Reset
Value
Content
0x10
7
R
1
Bit
Read/Write
Reset
Value
Content
3
R/W
0
6
R/W
BW
5
R/W
4
R/W
0
0
0
2
R/W
1
R/W
0
R/W
0
0
0
reserved
0
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
bw
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 100
bw:
Table 30: Gyroscope Output data rate and filter bandwidth
0x10 bits
Decimation Factor
ODR
Filter Bandwidth
‘0111’
20
100 Hz
32 Hz
‘0110’
10
200 Hz
64 Hz
‘0101’
20
100 Hz
12 Hz
‘0100’
10
200 Hz
23 Hz
‘0011’
5
400 Hz
47 Hz
‘0010’
2
1000 Hz
116 Hz
‘0001’
0
2000 Hz
230 Hz
‘0000’
0
2000 Hz
Unfiltered (523Hz)
‘1xxx’
Unused / Reserved
Unused / Reserved
Unused / Reserved
reserved:
write ‘0
GYR Register 0x11 (LPM1)
Selection of the main power modes.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
0x11
7
R/W
6
R/W
LPM1
5
R/W
4
R/W
0
0
0
0
suspend
reserved
deep_suspend
reserved
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
sleep_dur[2]
sleep_dur[1]
sleep_dur[0]
reserved
suspend, deep_suspend:
Main power mode configuration setting {suspend; deep_suspend}:
{0; 0}
NORMAL mode;
{0; 1}
DEEP_SUSPEND mode;
{1; 0}
SUSPEND mode;
{all other}
illegal
Please note that only certain power mode transitions are permitted.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 101
Please note, that all application specific settings which are not equal to the default settings
(refer to 8.2 register map gyroscope), must be re-set to its designated values after
DEEP_SUSPEND.
sleep_dur: time in ms in fast-power-up mode under advanced power-saving mode.
Table 31: Sleep duration time gyroscope
sleep_dur
‘000’
‘001’
‘010’
‘011’
‘100’
‘101’
‘110’
‘111’
reserved:
Time (ms)
2 ms
4 ms
5 ms
8 ms
10 ms
15 ms
18 ms
20 ms
write ‘0’
GYR Register 0x12 (LPM2)
Configuration settings for fast power-up and external trigger.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
fast powerup:
0x12
7
R/W
LPM2
5
R/W
6
R/W
0
0
0
0
fast_powerup
power_save_mode
ext_trig_sel[1]
ext_trig_sel[0]
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
reserved
autosleep_dur[2]
autosleep_dur[1]
autosleep_dur[0]
1 Drive stays active for suspend mode in order to have a short wake-up
time…..
0 Drive is switched off for suspend mode
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 102
ext_trig_sel:
Table 32: external trigger gyroscope
ext_trig_sel
‘00’
‘01’
‘10’
‘11’
Trigger source
No
INT1 pin
INT2 pin
SDO pin
(SPI3 mode)
autosleep: time in ms in normal mode under advanced power-saving mode.
Table 33: Autosleep duration gyroscope
autosleep_dur
‘000’
‘001’
‘010’
‘011’
‘100’
‘101’
‘110’
‘111’
reserved:
Time (ms)
Not allowed
4 ms
5 ms
8 ms
10 ms
15 ms
20 ms
40 ms
write ‘0’
GYR Register 0x13 (RATE_HBW)
Angular rate data acquisition and data output format.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
data_high_bw:
shadow_dis:
0x13
7
R/W
RATE_HBW
5
R/W
4
R/W
0
0
data_high_bw
6
R/W
0 (1 in 8-bit
mode)
shadow_dis
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
0
reserved
reserved
select whether ‘1´ unfiltered, or ‘0’ filtered data may be read from the
rate data registers.
‘1´ disable, or ‘0’ the shadowing mechanism for the rate data output
registers. When shadowing is enabled, the content of the rate data
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
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third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
reserved:
Page 103
component in the MSB register is locked, when the component in the LSB is
read, thereby ensuring the integrity of the rate data during read-out. The lock
is removed when the MSB is read.
write ‘0’
GYR Register 0x14 (BGW_SOFTRESET)
Controls user triggered reset of the sensor.
Name
Bit
Read/Write
Reset
Value
Content
0x14
7
W
6
W
BGW_SOFTRESET
5
W
4
W
0
0
0
0
Bit
Read/Write
Reset
Value
Content
3
W
2
W
1
W
0
W
0
0
0
0
softreset:
softreset
softreset
0xB6 trigger a reset. Other values are ignored. Following a delay, all user
configuration settings are overwritten with their default state or the setting
stored in the NVM, wherever applicable. This register is functional in all
operation modes. Please note, that all application specific settings which are
not equal to the default settings (refer to 8.2 register map gyroscope), must
be re-set to its designated values.
GYR Register 0x15 (INT_EN_0)
Controls which interrupts are enabled.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
data_en:
fifo_en :
auto_offset_en:
0x15
7
R/W
6
R/W
INT_EN_0
5
R/W
4
R/W
0
0
0
0
data_en
fifo_en
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
auto_offset_en
reserved
reserved
reserved
‘1’ (‘0’) enables (disables) new data interrupt
‘1’ (‘0’) enables (disables) fifo interrupt
‘1’ (‘0’) enables (disables) auto-offset compensation
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
reserved:
Page 104
write ‘0’
GYR Register 0x16 (INT_EN_1)
Contains interrupt pin configurations.
Name
Bit
Read/Write
Reset
Value
Content
0x16
7
R/W
6
R/W
INT_EN_1
5
R/W
4
R/W
0
0
0
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
1
1
1
1
int2_od
int2_lvl
int1_od
int1_lvl
int2_od:
int2_lvl:
int1_od:
int1_lvl:
reserved:
reserved
‘0’ (‘1’) selects push-pull, ‘1’ selects open drive for INT4
‘0’ (‘1’) selects active level ‘0’ (‘1’) for INT4
‘0’ (‘1’) selects push-pull, ‘1’ selects open drive for INT3
‘0’ (‘1’) selects active level ‘0’ (‘1’) for INT3
write ‘0’
GYR Register 0x17 (INT_MAP_0)
Controls which interrupt signals are mapped to the INT3 pin.
Name
Bit
Read/Write
Reset
Value
Content
0x17
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
int1_high:
int1_any:
reserved:
6
R/W
INT_MAP_0
5
R/W
4
R/W
0
0
0
2
R/W
1
R/W
0
R/W
0
0
0
0
int1_high
reserved
int1_any
reserved
reserved
map high rate interrupt to INT3 pin: ‘0’ disabled, or ‘1’ enabled
map Any-Motion to INT3 pin: ‘0’ disabled, or ‘1’ enabled
write ‘0’
GYR Register 0x18 (INT_MAP_1)
Controls which interrupt signals are mapped to the INT3 pin and INT4 pin.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
6
R/W
INT_MAP_1
5
R/W
4
R/W
0
0
0
0
int2_data
int2_fast_offset
int2_fifo
int2_auto_offset
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
Int1_auto_offset
int1_fifo
int1_fast_offset
int1_data
int2_data:
int2_fast_offset:
int2_fifo:
int2_auto_offset:
int1_auto_offset:
int1_fifo:
int1_fast_offset:
int1_data:
0x1B
7
R/W
Page 105
map new data interrupt to INT4 pin: ‘0’ disabled, or ‘1’ enabled
map FastOffset interrupt to INT4 pin: ‘0’ disabled, or ‘1’ enabled
map Fifo interrupt to INT4 pin: ‘0’ disabled, or ‘1’ enabled
map AutoOffset tap interrupt to INT4 pin: ‘0’ disabled, or ‘1’ enabled
map AutoOffset tap interrupt to INT3 pin: ‘0’ disabled, or ‘1’ enabled
map Fifo interrupt to INT3 pin: ‘0’ disabled, or ‘1’ enabled
map FastOffset interrupt to INT3 pin: ‘0’ disabled, or ‘1’ enabled
map new data interrupt to INT3 pin: ‘0’ disabled, or ‘1’ enabled
GYR Register 0x19 (INT_MAP_2)
Controls which interrupt signals are mapped to the INT4 pin.
Name
Bit
Read/Write
Reset
Value
Content
0x19
7
R/W
6
R/W
INT_MAP_2
5
R/W
4
R/W
0
0
0
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
Int2_high
reserved
Int2_any
reserved
Int2_high:
Int2_any:
reserved:
reserved
map high rate interrupt to INT4 pin: ‘0’ disabled, or ‘1’ enabled
map Any-Motion to INT4 pin: ‘0’ disabled, or ‘1’ enabled
write ‘0’
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 106
GYR Register 0x1A
Contains the data source definition of those interrupts with selectable data source.
Name
Bit
Read/Write
Reset
Value
Content
0x1A
7
R/W
6
R/W
5
R/W
4
R/W
0
0
0
0
slow_offset_unfilt
reserved
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
high_unfilt_data
reserved
any_unfilt_data
reserved
reserved
slow_offset_unfilt: ‘1’ (‘0’) seletects unfiltered (filtered) data for slow offset compensation
high_unfilt_data: ‘1’ (‘0’) seletects unfiltered (filtered) data for high rate interrupt
any_unfilt_data: ‘1’ (‘0’) seletects unfiltered (filtered) data for any motion interrupt
reserved:
write ‘0’
GYR Register 0x1B
Contains the data source definition of fast offset compensation and the any motion threshold.
Name
Bit
Read/Write
Reset
Value
Content
0x1B
7
R/W
6
R/W
5
R/W
4
R/W
0
0
0
0
fast_offset_unfilt
Bit
Read/Write
Reset
Value
Content
any_th
3
R/W
2
R/W
1
R/W
0
R/W
0
1
0
0
any_th
fast_offset_unfilt: ‘1’ (‘0’) selects unfiltered (filtered) data for fast offset compensation
any_th:
any_th = (1 + any_th(register value)) * 16 LSB
The any_th scales with the range setting
GYR Register 0x1C
Name
Bit
Read/Write
0x1C
7
R/W
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
6
R/W
5
R/W
4
R/W
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
awake_dur:
any_dursample:
any_en_z:
any_en_y:
any_en_x:
reserved:
1
0
Page 107
1
awake_dur
0
any_dursample
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
reserved
any_en_z
any_en_y
any_en_x
0=8 samples, 1=16 samples, 2=32 samples, 3=64 samples
0=4 samples, 1=8 samples, 2=12 samples, 3=16 samples
‘1’ (‘0’) enables (disables) any motion interrupt for z-axis
‘1’ (‘0’) enables (disables) any motion interrupt for y-axis
‘1’ (‘0’) enables (disables) any motion interrupt for z-axis
If one of the bits any_x/y/z is enabled, the any motion interrupt is enabled
write ‘0’
GYR Register 0x1D is reserved.
GYR Register 0x1E
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
fifo_wm_en:
reserved:
0x1E
7
R/W
6
R/W
5
R/W
4
R/W
1
0
0
0
fifo_wm_en
reserved
3
R/W
2
R/W
1
R/W
0
R/W
1
0
0
0
reserved
‘1’ (‘0’) enables (disables) fifo water mark level interrupt
write ‘0’
GYR Register 0x1F and 0x20 are reserved
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 108
GYR Register 0x21 (INT_RST_LATCH)
Contains the interrupt reset bit and the interrupt mode selection.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
reset_int:
offset_reset:
latch_int:
reserved:
0x21
7
W
6
R/W
INT_RST_LATCH
5
R/W
4
R/W
0
0
0
0
reset_int
offset_reset
reserved
latch_status_bit
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
latch_int
write ‘1’ clear any latched interrupts, or ‘0’ keep latched interrupts
active
write ‘1’ resets internal interrupt status of each interrupt
write ‘1’ resets the Offset value calculated with FastOffset, SlowOffset &
AutoOffset
´0000b´ non-latched,
´0001b´ temporary, 250 ms,
´0010b´ temporary, 500 ms, ´0011b´ temporary, 1 s,
´0100b´ temporary, 2 s,
´0101b´ temporary, 4 s,
´0110b´ temporary, 8 s,
´0111b´ latched,
´1000b´ non-latched,
´1001b´ temporary, 250 s,
´1010b´ temporary, 500 s, ´1011b´ temporary, 1 ms,
´1100b´ temporary, 12.5 ms, ´1101b´ temporary, 25 ms,
´1110b´ temporary, 50 ms, ´1111b´ latched
write ‘0’
GYR Register 0x22 (High_Th_x)
Contains the high rate threshold and high rate hysteresis setting for the x-axis
Name
Bit
Read/Write
Reset
Value
Content
0x22
7
R/W
0
6
R/W
High_Th_x
5
R/W
4
R/W
0
0
0
high_hy_x
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
high_th_x
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Bit
Read/Write
Reset
Value
Content
high_hy_x:
high_th_x
high_en_x
Page 109
3
R/W
2
R/W
1
R/W
0
R/W
0
0
1
0
high_th_x
high_en_x
high_hy_x = (255 + 256 * high_hy_x(register value)) *4 LSB
The high_hy_x scales with the range setting
high_th_x = (255 + 256 * high_th_x(register value)) *4 LSB
The high_th_x scales with the range setting
‘1’ (‘0’) enables (disables) high rate interrupt for x-axis
GYR Register 0x23 (High_Dur_x)
Contains high rate duration setting for the x-axis.
Name
Bit
Read/Write
Reset
Value
Content
0x23
7
R/W
0
Bit
Read/Write
Reset
Value
Content
high_dur_x:
6
R/W
High_Dur_x
5
R/W
4
R/W
0
0
1
3
R/W
2
R/W
1
R/W
0
R/W
1
0
0
1
high_dur_x
high_dur_x
high_dur time_x = (1 + high_dur_x(register value))*2.5ms
GYR Register 0x24 (High_Th_y)
Contains the high rate threshold and high rate hysteresis setting for the y-axis.
Name
Bit
Read/Write
Reset
Value
Content
0x24
7
R/W
0
6
R/W
High_Th_y
5
R/W
4
R/W
0
0
0
high_hy_y
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
high_th_y
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Bit
Read/Write
Reset
Value
Content
high_hy_y:
high_th_y
high_en_y
Page 110
3
R/W
2
R/W
1
R/W
0
R/W
0
0
1
0
high_th_y
high_en_y
high_hy_y = (255 + 256 * high_hy_y(register value)) *4 LSB
The high_hy_y scales with the range setting
high_th_x = (255 + 256 * high_th_y(register value)) *4 LSB
The high_th_y scales with the range setting
‘1’ (‘0’) enables (disables) high rate interrupt for y-axis
GYR Register 0x25 (High_Dur_y)
Contains high rate duration setting for the x-axis.
Name
Bit
Read/Write
Reset
Value
Content
0x25
7
R/W
0
Bit
Read/Write
Reset
Value
Content
high_dur_y:
6
R/W
High_Dur_y
5
R/W
4
R/W
0
0
1
3
R/W
2
R/W
1
R/W
0
R/W
1
0
0
1
high_dur_y
high_dur_y
high_dur time_y = (1 + high_dur_y(register value))*2.5ms
GYR Register 0x26 (High_Th_z)
Contains the high rate threshold and high rate hysteresis setting for the z-axis.
Name
Bit
Read/Write
Reset
Value
Content
0x26
7
R/W
6
R/W
High_Th_z
5
R/W
4
R/W
0
0
0
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
1
0
high_hy_z
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
high_th_z
high_th_z
high_en_z
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
high_hy_z:
Page 111
high_hy_z = (255 + 256 * high_hx_z(register value)) *4 LSB
The high_hy_x scales with the range setting
high_th_z = (255 + 256 * high_th_z(register value)) *4 LSB
The high_th_z scales with the range setting
‘1’ (‘0’) enables (disables) high rate interrupt for z-axis
high_th_z
high_en_z
GYR Register 0x27 (High_Dur_z)
Contains high rate duration setting for the z-axis.
Name
Bit
Read/Write
Reset
Value
Content
0x27
7
R/W
6
R/W
High_dur_z
5
R/W
4
R/W
0
0
0
1
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
1
0
0
1
high_dur_z
high_dur_z
high_dur_z:
high_dur time_z = (1 + high_dur_z(register value))*2.5ms
GYR Register 0x28 to 0x30 are reserved
GYR Register 0x31 (SOC)
Contains the slow offset cancellation setting.
Name
Bit
Read/Write
Reset
Value
Content
0x31
7
R/W
0
Bit
Read/Write
Reset
Value
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
Slow_offset_dur
slow_offset_en_z
slow_offset_en_y
slow_offset_en_x
Content
6
R/W
SOC
5
R/W
4
R/W
1
1
0
Slow_offset_th
Slow_offset_th:
Slow_offset_dur:
Slow_offset_dur
0=0.1°/s, 1=0.2°/s, 2=0.5°/s, 3=1°/s
0=40ms, 1=80ms, 2=160ms, 3=320ms, 4=640ms, 5=1280ms,
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
slow_offset_en_z:
slow_offset_en_y:
slow_offset_en_x:
Page 112
6 and 7=unused
‘1’ (‘0’) enables (disables) slow offset compensation for z-axis
‘1’ (‘0’) enables (disables) slow offset compensation for y-axis
‘1’ (‘0’) enables (disables) slow offset compensation for x-axis
GYR Register 0x32 (A_FOC)
Contains the fast offset cancellation setting.
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
0x32
7
R/W
1
6
R/W
A_FOC
5
R/W
4
R/W
1
0
0
auto_offset_wordlength
fast_offset_wordlength
3
R
2
R/W
1
R/W
0
R/W
0
0
0
0
fast_offset_en
fast_offset_en_z
fast_offset_en_y
fast_offset_en_x
auto_offset_wordlength:
fast_offset_wordlength:
fast_offset_en:
fast_offset_en_z:
fast _offset_en_y:
fast _offset_en_x:
0=32 samples, 1=64 samples, 2=128 samples, 3=256 samples
0=32 samples, 1=64 samples, 2=128 samples, 3=256 samples
write ‘1’ triggers the fast offset compensation for the enabled
axes
‘1’ (‘0’) enables (disables) fast offset compensation for z-axis
‘1’ (‘0’) enables (disables) fast offset compensation for y-axis
‘1’ (‘0’) enables (disables) fast offset compensation for x-axis
GYR Register 0x33 (TRIM_NVM_CTRL)
Contains the control settings for the few-time programmable non-volatile memory (NVM).
Name
Bit
Read/Write
Reset
Value
Content
0x33
7
R
6
R
TRIM_NVM_CTRL
5
R
4
R
n/a
n/a
n/a
n/a
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R
1
W
0
R/W
0
n/a
0
0
nvm_load
nvm_rdy
nvm_prog_trig
nvm_prog_mode
nvm_remain
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 113
nvm_remain:
number of remaining write cycles permitted for NVM; the number is
decremented each time a write to the NVM is triggered
nvm_load:
´1´ trigger, or ‘0’ do not trigger an update of all configuration registers
from NVM; the nvm_rdy flag must be ‘1’ prior to triggering the update
nvm_rdy:
status of NVM controller: ´0´ NVM write / NVM update operation is in
progress, ´1´ NVM is ready to accept a new write or update trigger
nvm_prog_trig:
‘1’ trigger, or ‘0’ do not trigger an NVM write operation; the trigger is
only accepted if the NVM was unlocked before and nvm_remain is
greater than ‘0’; flag nvm_rdy must be ‘1’ prior to triggering the write cycle
nvm_prog_mode: ‘1’ unlock, or ‘0’ lock NVM write operation
GYR Register 0x34 (BGW_SPI3_WDT)
Contains settings for the digital interfaces.
Name
Bit
Read/Write
Reset
Value
Content
0x34
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
ext_fifo_s_en:
ext_fifo_s_sel:
reserved:
i2c_wdt_en:
i2c_wdt_sel:
spi3:
6
R/W
BGW_SPI3_WDT
5
R/W
4
R/W
0
0
0
ext_fifo_s_en
ext_fifo_s_sel
2
R/W
1
R/W
0
R/W
0
0
0
0
reserved
i2c_wdt_en
i2c_wdt_sel
spi3
reserved
enables external FIFO synchronization mode, ‘1’ enable, ‘0’ disable
selects source for external FIFO synchronization
‘1’ source = INT4
‘0’ source = INT3
write ‘0’
if I²C interface mode is selected then ‘1´ enable, or ‘0’ disables the
watchdog at the SDI pin (= SDA for I²C)
select an I²C watchdog timer period of ‘0’ 1 ms, or ‘1’ 50 ms
select ´0´ 4-wire SPI, or ´1´ 3-wire SPI mode
GYR Register 0x35 is reserved
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 114
GYR Register 0x36 (OFC1)
Contains offset compensation values.
Name
Bit
Read/Write
Reset
Value
Content
0x36
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
offset_x:
offset_y:
offset_z:
6
R/W
OFC1
5
R/W
4
R/W
0
0
0
offset_x
offset_y
offset_y
offset_z
setting of offset calibration values X-channel
setting of offset calibration values Y-channel
setting of offset calibration values Z-channel
GYR Register 0x37 (OFC2)
Contains offset compensation values for X-channel.
Name
Bit
Read/Write
Reset
Value
Content
0x37
7
R/W
6
R/W
OFC2
5
R/W
4
R/W
0
0
0
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
offset_x :
offset_x
offset_x
offset value, which is subtracted from the internal filtered and unfiltered xaxis data; please refer to the following table for the scaling of the offset
register; the content of the offset_x may be written to the NVM; it is
automatically restored from the NVM after each power-on or softreset;
offset_x may be written directly by the user.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 115
Table 34: Scaling of the offset register gyroscope
Original readout value
0 ˚/s
0 ˚/s
0 ˚/s
Value in offset register
2047
0
-2048
Compensated readout value
-124.94 ˚/s
0 ˚/s
125 ˚/s
GYR Register 0x38 (OFC3)
Contains offset compensation values for Y-channel.
Name
Bit
Read/Write
Reset
Value
Content
0x38
7
R/W
6
R/W
OFC3
5
R/W
4
R/W
0
0
0
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
offset_y :
offset_y
offset_y
offset value, which is subtracted from the internal filtered and unfiltered yaxis data; please refer Table 34 for the scaling of the offset register; the
content of the offset_y may be written to the NVM; it is automatically
restored from the NVM after each power-on or softreset; offset_y may
be written directly by the user.
For reference see example at GYR Register 0x38 (OFC2)
GYR Register 0x39 (OFC4)
Contains offset compensation values for Z-channel.
Name
Bit
Read/Write
Reset
Value
Content
0x39
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
0
offset_z :
6
R/W
OFC4
5
R/W
4
R/W
0
0
0
2
R/W
1
R/W
0
R/W
0
0
0
offset_z
offset_z
offset value, which is subtracted from the internal filtered and unfiltered zaxis data; please Table 34 for the scaling of the offset register; the content of
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 116
the offset_z may be written to the NVM; it is automatically restored
from the NVM after each power-on or softreset; offset_z may be
written directly by the user.
For reference see example at GYR Register 0x38 (OFC2)
GYR Register 0x3A (TRIM_GP0)
Contains general purpose data register with NVM back-up.
Name
Bit
Read/Write
Reset
Value
Content
0x3A
7
R/W
X
Bit
Read/Write
Reset
Value
Content
3
R/W
X
GP0:
offset_x:
offset_y:
offset_z
6
R/W
TRIM_GP0
5
R/W
4
R/W
X
X
X
2
R/W
1
R/W
0
R/W
X
X
X
offset_y
offset_z
GP0
offset_x
general purpose NVM image register not linked to any sensor-specific
functionality; register may be written to NVM and is restored after each
power-up or software reset
setting of offset calibration values X-channel
setting of offset calibration values Y-channel
setting of offset calibration values Z-channel
GYR Register 0x3B (TRIM_GP1)
Contains general purpose data register with NVM back-up.
Name
Bit
Read/Write
Reset
Value
Content
0x3B
7
R/W
X
Bit
Read/Write
Reset
Value
Content
3
R/W
X
GP1:
6
R/W
TRIM_GP1
5
R/W
4
R/W
X
X
X
2
R/W
1
R/W
0
R/W
X
X
X
GP1
GP1
general purpose NVM image register not linked to any sensor-specific
functionality; register may be written to NVM and is restored after each
power-up or software reset
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 117
GYR Register 0x3C (BIST)
Contains Built in Self-Test (BIST) possibilities:
Name
Bit
Read/Write
Reset
Value
Content
Bit
Read/Write
Reset
Value
Content
0x3C
7
R/W
0
reserved
3
R/W
6
R/W
BIST
5
R/W
4
R/W
0
0
0
reserved
2
R/W
0
reserved
reserved
1
R/W
0
0
bist_fail
bist_rdy
rate_ok
0
R
0
trig_bist
Rate ok:
´1´ indicates proper sensor function, no trigger is needed for this
Trig_bist:
Bist_rdy:
write ´1´ in order to perform the bist test
if bist_rdy is `1` and bist_fail is ´0´ result of bist test is ok means “sensor ok”
If bist_rdy is `1` and bist_fail is ´1´ result of bist test is not ok means “sensor
values not in expected range”
GYR Register 0x3D (FIFO_CONFIG_0)
Contains the FIFO watermark level.
Name
Bit
Read/Write
Reset
Value
Content
0x3D
7
R/W
6
R/W
FIFO_CONFIG_0
5
R/W
4
R/W
n/a
n/a
0
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
tag:
tag
fifo_water_mark_level_trigger_retain
fifo_water_mark_level_trigger_retain
‘1’ (‘0’) enables (disables) fifo tag (interrupt)
Table 35: FIFO watermark level configuration
Address: 0x3D bit 7
tag
Interrupt data stored in FIFO
‘0’ Default)
Do not collect Interrupts
‘1’
collect Interrupts
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 118
fifo_water_mark_level_trigger_retain:
fifo_water_mark_level_trigger_retain defines the FIFO watermark level.
An interrupt will be generated, when the number of entries in the FIFO
exceeds fifo_water_mark_level_trigger_retain;
GYR Register 0x3E (FIFO_CONFIG_1)
Register 0x3 contains FIFO configuration settings. The FIFO buffer memory is cleared and the
fifo-full flag is cleared when writing to FIFO_CONFIG_1 register.
Name
Bit
Read/Write
Reset
Value
Content
0x3E
7
R/W
0
Bit
Read/Write
Reset
Value
Content
3
R/W
2
R/W
1
R/W
0
R/W
0
0
0
0
fifo_mode:
6
R/W
FIFO_CONFIG_1
5
R/W
4
R/W
0
0
0
fifo_mode
Reserved
Reserved
fifo_data_select
selects the FIFO operating mode:
´00b´ BYPASS (buffer depth of 1 frame; old data is discarded),
´01b´ FIFO (data collection stops when buffer is filled with 100 frames),
´10b´ STREAM (sampling continues when buffer is full; old is discarded),
´11b´ reserved, do not use
fifo_data_select:
Table 36: Gyroscope FIFO data selection
Address: 0x3E bits data_select
‘00’ (Default)
‘01’
‘10’
‘11’
reserved:
data of axis stored in FIFO
X,Y,Z
X only
Y only
Z only
write ‘0’
GYR Register 0x3F (FIFO_DATA)
FIFO data readout register. The format of the LSB and MSB components corresponds to that of
the angular rate data readout registers.. Read burst access may be used since the address
counter will not increment when the read burst is started at the address of FIFO_DATA. The
entire frame is discarded when a frame is only partially read out.
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Data sheet
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Name
Bit
Read/Write
Reset
Value
Content
0x3F
7
R
6
R
FIFO_DATA
5
R
4
R
n/a
n/a
n/a
n/a
Bit
Read/Write
Reset
Value
Content
3
R
2
R
1
R
0
R
n/a
n/a
n/a
n/a
fifo_data_output_register
fifo_data_output_register
fifo_data_output_register:
FIFO data readout; data format depends on the setting of register fifo_data_select:
if X+Y+Z data are selected, the data of frame n is reading out in the order of
X-lsb(n), X-msb(n), Y-lsb(n), Y-msb(n), Z-lsb(n), Z-msb(n);
if X-only is selected, the data of frame n and n+1 are reading out in the order
of X-lsb(n), X-msb(n), X-lsb(n+1), X-msb(n+1); the Y-only and Z-only modes
behave analogously
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9 Functional description magnetometer
9.1
Magnetometer power management
The device contains a power on reset (POR) generator. It resets the logic part and the register
values of the concerned ASIC after powering-on VDD and VDDIO. Please note, that all application
specific settings which are not equal to the default settings (refer to register maps chapter 10
and chapter 10.2), must be re-set to its designated values after POR.
9.2
Magnetometer power modes
The magnetometer features configurable power modes. It has four power modes: In the
following chapters, power modes are described.
9.2.1
Power off mode
In Power off mode, VDD and/or VDDIO are unpowered and the device does not operate. When
only one of VDD or VDDIO is supplied, the magnetic sensor will still be in Power off mode. Power
on reset is performed after both VDD and VDDIO have risen above their detection thresholds.
9.2.2
Suspend mode
Suspend mode is the default power mode of magnetometer after the chip is powered. When
VDD and VDDIO are turned on the POR (power on reset) circuits operate and the device’s
registers are initialized. After POR becomes inactive, a start up sequence is executed. In this
sequence NVM content is downloaded to shadow registers located in the device core. After the
start up sequence the device is put in the Suspend mode. In this mode only registers which
store power control bit information and SPI3 wire enable can be accessed by the user. No other
registers can be accessed in Suspend mode. All registers lose their content, except the control
register (0x4B). In particular, in this mode a Chip ID read (register 0x40) returns “0x00” (I²C) or
high-Z (SPI).
9.2.3
Sleep mode
The user puts device from suspend into Sleep mode by setting the Power bit to “1”, or from
active modes (normal or forced) by setting OpMode bits to “11”. In this state the user has full
access to the device registers. In particular, the Chip ID can be read. Setting the power control
bit to “0” (register 0x4B bit0) will bring the device back into Suspend mode. From the Sleep
mode the user can put the device back into Suspend mode or into Active mode.
9.2.4
Active mode
The device can switch into Active mode from Sleep mode by setting OpMode bits (register
0x4C). In this mode the magnetic field measurements are performed and all registers are
accessible.
In active mode, two operation modes can be distinguished:
Normal mode: selected channels are periodically measured according to settings set in
user registers. After measurements are completed, output data is put into data registers
and the device waits for the next measurement period, which is set by programmed
output data rate (ODR). From normal mode, the user can return to sleep mode by
setting OpMode to “11” or by performing a soft reset (see chapter 10.6). Suspend mode
can be entered by setting power control bit to “0”.
Forced mode (single measurement): When set by the host, the selected channels are
measured according to settings programmed in user registers. After measurements are
completed, output data is put into data registers, OpMode register value returns to “11”
and the device returns to sleep mode. The forced mode is useful to achieve
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synchronized operation between host microcontroller and magnetometer. Also, different
data output rates from the ones selectable in normal mode can be achieved using
forced mode.
Figure 20: Magnetometer power mode transition diagram
In Active Mode and normal operation, in principle any desired balance between output noise
and active time (hence power consumption) can be adjusted by the repetition settings for x/yaxis and z-axis and the output data rate ODR. The average power consumption depends on the
ratio of high current phase time (during data acquisition) and low current phase time (between
data acquisitions). Hence, the more repetitions are acquired to generate one magnetic field
data point, the longer the active time ratio in one sample phase, and the higher the average
current. Thanks to longer internal averaging, the noise level of the output data reduces with
increasing number of repetitions.
By using forced mode, it is possible to trigger new measurements at any rate. The user can
therefore trigger measurements in a shorter interval than it takes for a measurement cycle to
complete. If a measurement cycle is not allowed to complete, the resulting data will not be
written into the data registers. To prevent this, the manually triggered measurement intervals
must not be shorter than the active measurement time which is a function of the selected
number of repetitions. The maximum selectable read-out frequency in forced mode can be
calculated as follows:
f max,ODR
1
145µs nXY 500µs nZ 980µs
Hereby nXY is the number of repetitions on X/Y-axis (not the register value) and nZ the number
of repetitions on Z-axis (not the register value) (see description of REPXY and REPZ registers
in chapter 10.8).
Although the repetition numbers for X/Y and Z axis and the ODR can be adjusted independently
and in a wide range, there are four recommended presets (High accuracy preset, Enhanced
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regular preset, Regular preset, Low power preset) which reflect the most common usage
scenarios, i.e. required output accuracy at a given current consumption, of the magnetometer.
The four presets consist of the below register configurations, which are automatically set by the
magnetometer API or driver provided by Bosch Sensortec when a preset is selected. Table 37
shows the recommended presets and the resulting magnetic field output noise and current
consumption:
Table 37: Recommended presets for repetitions and output data rates
Preset
Rep.
X/Y
nXY
Rep. Z
nZ
recommended
ODR
[Hz]
Max ODR
in forced
mode
fmax,ODR
RMS Noise
x/y/z
[µT]
[Hz]
Low power
preset
Regular preset
Enhanced
regular preset
High accuracy
preset
9.3
Average current
consumption
at
recommended
ODR
[mA]
3
3
10
>300
1.0/1.0/1.4
0.17
9
15
10
100
0.6/0.6/0.6
0.5
15
27
10
60
0.5/0.5/0.5
0.8
47
83
20
20
0.3/0.3/0.3
4.9
Magnetometer output data
9.3.1
Magnetic field data
The representation of magnetic field data is different between X/Y-axis and Z-axis. The width of
X- and Y-axis magnetic field data is 13 bits each and stored in two’s complement.
DATAX_LSB (0x42) contains 5-bit LSB part [4:0] of the 13 bit output data of the X-channel.
DATAX_MSB (0x43) contains 8-bit MSB part [12:5] of the 13 bit output data of the X-channel.
DATAY_LSB (0x44) contains 5-bit LSB part [4:0] of the 13 bit output data of the Y-channel.
DATAY_MSB (0x45) contains 8-bit MSB part [12:5] of the 13 bit output data of the Y-channel.
The width of the Z-axis magnetic field data is 15 bit word stored in two’s complement.
DATAZ_LSB (0x46) contains 7-bit LSB part [6:0] of the 15 bit output data of the Z-channel.
DATAZ_MSB (0x47) contains 8-bit MSB part [14:7] of the 15 bit output data of the Z-channel.
For all axes, temperature compensation on the host is used to get ideally matching sensitivity
over the full temperature range. The temperature compensation is based on a resistance
measurement of the hall sensor plate. The resistance value is represented by a 14 bit unsigned
output word.
RHALL_LSB (0x48) contains 6-bit LSB part [5:0] of the 14 bit output data of the RHALLchannel.
RHALL_MSB (0x49) contains 8-bit MSB part [13:6] of the 14 bit output data of the RHALLchannel.
All signed register values are in two´s complement representation. Bits which are marked
“reserved” can have different values or can in some cases not be read at all (read will return
0x00 in I²C mode and high-Z in SPI mode).
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Data sheet
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Data register readout and shadowing is implemented as follows:
After all enabled axes have been measured; complete data packages consisting of DATAX,
DATAY, DATAZ and RHALL are updated at once in the data registers. This way, it is prevented
that a following axis is updated while the first axis is still being read (axis mix-up) or that MSB
part of an axis is updated while LSB part is being read.
While reading from any data register, data register update is blocked. Instead, incoming new
data is written into shadow registers which will be written to data registers after the previous
read sequence is completed (i.e. upon stop condition in I²C mode, or CSB going high in SPI
mode, respectively). Hence, it is recommended to read out at all data at once (0x42 to 0x49 or
0x4A if status bits are also required) with a burst read.
Single bytes or axes can be read out, while in this case it is not assured that adjacent registers
are not updated during readout sequence.
The “Data ready status” bit (register 0x48 bit0) is set “1” when the data registers have been
updated but the data was not yet read out over digital interface. Data ready is cleared (set “0”)
directly after completed read out of any of the data registers and subsequent stop condition
(I²C) or lifting of CSB (SPI).
In addition, when enabled the “Data overrun” bit (register 0x4A bit7) turns “1” whenever data
registers are updated internally, but the old data was not yet read out over digital interface (i.e.
data ready bit was still high). The “Data overrun” bit is cleared when the interrupt status register
0x4A is read out. This function needs to be enabled separately by setting the “Data overrun En”
bit (register 0x4D bit7)).
Note:
Please also see chapter 10.4 for detailed register descriptions.
9.3.2
Magnetic field data temperature compensation
The raw register values DATAX, DATAY, DATAZ and RHALL are read out from the host
processor using the MAGNETOMETER API/driver which is provided by Bosch Sensortec. The
API/driver performs an off-chip temperature compensation and outputs x/y/z magnetic field data
in 16 LSB/µT to the upper application layer:
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Data sheet
Software
application level
a
Software
driver level
Page 124
Application
Temperature and sensitivity compensated
magnetic field data x/y/z available in:
Config
- short int (16 LSB/µT, limited Z range)
- long int (16 LSB/µT)
- float (µT)
BMM150
API / driver
(provided by
Bosch Sensortec)
Config
Hardware level
Magnetometer raw register data
(DATAX, DATAY, DATAZ, RHALL)
BMM150
sensor
Figure 21: Calculation flow of magnetic field data from raw magnetometer register data
The API/driver performs all calculations using highly optimized fixed-point C-code arithmetic.
For platforms that do not support C code, a floating-point formula is available as well.
9.4
Self-test magnetometer
Magnetometer supports two self-tests modes: Normal self-test and advanced self-test.
9.4.1
Normal self test
During normal self-test, the following verifications are performed:
FlipCore signal path is verified by generating signals on-chip. These are processed through the
signal path and the measurement result is compared to known thresholds.
FlipCore (X and Y) connection to ASIC are checked for connectivity and short circuits
Hall sensor connectivity is checked for open and shorted connections
Hall sensor signal path and hall sensor element offset are checked for overflow.
To perform a self test, the sensor must first be put into sleep mode (OpMode = “11”). Self-test
mode is then entered by setting the bit “Self test” (register 0x4C bit0) to “1”. After performing
self test, this bit is set back to “0”. When self-test is successful, the corresponding self-test result
bits are set to “1” (“X-Self-Test” register 0x42 bit0, “Y-Self-Test” register 0x44 bit0, “Z-Self-Test”
register 0x46 bit0). If self-test fails for an axis, the corresponding result bit returns “0”.
9.4.2
Advanced self test
Advanced self test performs a verification of the Z channel signal path functionality and
sensitivity. An on-chip coil wound around the hall sensor can be driven in both directions with a
calibrated current to generate a positive or negative field of around 100 µT.
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Advanced self test is an option that is active in parallel to the other operation modes. The only
difference is that during the active measurement phase, the coil current is enabled. The
recommended usage of advanced self test is the following:
1. Set sleep mode
2. Disable X, Y axis
3. Set Z repetitions to desired level
4. Enable positive advanced self test current
5. Set forced mode, readout Z and R channel after measurement is finished
6. Enable negative advanced self test current
7. Set forced mode, readout Z and R channel after measurement is finished
8. Disable advanced self test current (this must be done manually)
9. Calculate difference between the two compensated field values. This difference should
be around 200 µT with some margins.
10. Perform a soft reset of manually restore desired settings
Please refer to the corresponding application note for the exact thresholds to evaluate
advanced self-test.
The table below describes how the advanced self-test is controlled:
Table 38: Magnetometer advanced self-test control
(0x4C)
Adv.ST
Configuration
00b
01b
10b
11b
Normal operation (no self-test), default
Reserved, do not use
Negative on-chip magnetic field generation
Positive on-chip magnetic field generation
The magnetometer API/driver provided by Bosch Sensortec provides a comfortable way to
perform both self-tests and to directly obtain the result without further calculations. It is
recommended to use this as a reference.
9.5
Non-volatile memory
Some of the memory of the magnetometer is non-volatile memory (NVM). This NVM is preprogrammed in Bosch Sensortec fabrication line and cannot be modified afterwards. It contains
trimming data which are required for sensor operation and sensor data compensation, thus it is
read out by the magnetometer API/driver during initialization.
9.6
Magnetometer interrupt controller
Four magnetometer based interrupt engines are integrated: Low-Threshold, High-Threshold,
Overflow and Data Ready (DRDY). Each interrupt can be enabled independently.
When enabled, an interrupt sets the corresponding status bit in the interrupt status register
(0x4A) when its condition is satisfied.
When the “Interrupt Pin Enable” bit (register 0x4E bit6) is set, any occurring activated interrupts
are flagged on the magnetometer’s INT output pin. By default, the interrupt pin is disabled (highZ status).
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Low-Threshold, High-Threshold and Overflow interrupts are mapped to the INT pin when
enabled, Data Ready (DRDY) interrupt is mapped to the DRDY pin of magnetometer when
enabled. For High- and Low-Threshold interrupts each axis X/Y/Z can be enabled separately for
interrupt detection in the registers “High Int Z en”, “High Int Y en”, “High Int X en”, “Low Int Z
en”, “Low Int Y En” and “Low Int X En” in register 0x4D bit5-bit0. Overflow interrupt is shared for
X, Y and Z axis.
When the “Data Ready Pin En” bit (register 0x4E bit7) is set, the Data Ready (DRDY) interrupt
event is flagged on the magnetometer’s DRDY output pin (by default the “Data Ready Pin En”
bit is not set and DRDY pin is in high-Z state).
The interrupt status registers are updated together with writing new data into the magnetic field
data registers. The status bits for Low-/High-Threshold interrupts are located in register 0x4A,
the Data Ready (DRDY) status flag is located at register 0x48 bit0.
If an interrupt is disabled, all active status bits and pins are reset after the next measurement
was performed.
9.6.1
General features
An interrupt is cleared depending on the selected interrupt mode, which is common to all
interrupts. There are two different interrupt modes: non-latched and latched. All interrupts
(except Data Ready) can be latched or non-latched. Data Ready (DRDY) is always cleared
after readout of data registers ends.
A non-latched interrupt will be cleared on a new measurement when the interrupt condition is
not valid anymore, whereas a latched interrupt will stay high until the interrupts status register
(0x4A) is read out. After reading the interrupt status, both the interrupt status bits and the
interrupt pin are reset. The mode is selected by the “Interrupt latch” bit (register 0x4A bit1),
where the default setting of “1” means latched. Figure 22shows the difference between the
modes for the example Low-Threshold interrupt.
INT and DRDY pin polarity can be changed by the “Interrupt polarity” bit (register 0x4E bit0) and
“DR polarity” (register 0x4E bit2) from the default high active (“1”) to low active (“0”).
Low threshold
a
a
measurements
INT pin (non-latched)
INT pin (latched)
Readings of interrupt status register (0x4A)
Figure 22: Interrupt latched and non-latched mode
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9.6.2
Electrical behavior of magnetic interrupt pins
Both interrupt pins INT and DRDY are push/pull when the corresponding interrupt pin enable bit
is set, and are floating (High-Z) when the corresponding interrupt pin enable bit is disabled
(default).
9.6.3
Data ready / DRDY interrupt
This interrupt serves for synchronous reading of magnetometer data. It is generated after
storing a new set of values (DATAX, DATAY, DATAZ, RHALL) in the data registers:
Active measurement time
Inactive time
Data write into
output registers
Preset time
Measurement
Measurement
Data
Dataprocessing
processing
DRDY =’1 ’
Measurement phase start
Data readout
Figure 23: Data acquisition and DRDY operation (DRDY in “high active” polarity)
The interrupt mode of the Data Ready (DRDY) interrupt is fixed to non-latched.
It is enabled (disabled) by writing “1” (“0”) to “Data Ready pin En” in register 0x4E bit7.
DRDY pin polarity can be changed by the “DR polarity” bit (register 0x4E bit2), from the default
high active (“1”) to low active (“0”).
9.6.4
Low-threshold interrupt
When the data registers’ (DATAX, DATAY and DATAZ) values drop below the threshold level
defined by the “Low Threshold register (0x4F), the corresponding interrupt status bits for those
axes are set (“Low Int X”, “Low Int Y” and “Low Int Z” in register 0x4A). This is done for each
axis independently. Please note that the X and Y axis value for overflow is -4096. However, no
interrupt is generated on these values. See chapter 10.7 for more information on overflow.
Hereby, one bit in “Low Threshold” corresponds to roughly 6µT (not exactly, as the raw
magnetic field values DATAX, DATAY and DATAZ are not temperature compensated).
The Low-threshold interrupt is issued on INT pin when one or more values of the data registers
DATAX, DATAY and DATAZ drop below the threshold level defined by the “Low Threshold”
register (0x4F), and when the axis where the threshold was exceeded is enabled for interrupt
generation:
Result =
(DATAX < “Low Threshold” x 16) AND “Low Int X en” is “0” OR
(DATAY < “Low Threshold” x 16) AND “Low Int Y en” is “0” OR
(DATAZ < “Low Threshold” x 16) AND “Low Int Z en” is “0”
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Data sheet
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Note: Threshold interrupt enable bits (“Low INT [XYZ] en”) are active low and “1” (disabled) by
default.
Low threshold
a
a
measurements
INT pin (non-latched)
INT pin (latched)
Read interrupt status
register (0x4A)
Figure 24: Low-threshold interrupt function
9.6.5
High-threshold interrupt
When the data registers’ (DATAX, DATAY and DATAZ) values exceed the threshold level
defined by the “High Threshold register (0x50), the corresponding interrupt status bits for those
axes are set (“High Int X”, “High Int Y” and “High Int Z” in register 0x4A). This is done for each
axis independently.
Hereby, one bit in “High Threshold” corresponds to roughly 6µT (not exactly, as the raw
magnetic field values DATAX, DATAY and DATAZ are not temperature compensated).
The High-threshold interrupt is issued on INT pin when one or more values of the data registers
DATAX, DATAY and DATAZ exceed the threshold level defined by the “High Threshold”
register (0x50), and when the axis where the threshold was exceeded is enabled for interrupt
generation:
Result =
(DATAX > “High Threshold” x 16) AND “High Int X en” is “0” OR
(DATAY > “High Threshold” x 16) AND “High Int Y en” is “0” OR
(DATAZ > “High Threshold” x 16) AND “High Int Z en” is “0”
Note:
Threshold interrupt enable bits (“High INT [XYZ] en”) are active low and “1” (disabled) by
default.
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High threshold
a
a
measurements
INT pin (non-latched)
INT pin (latched)
Read interrupt status
register (0x4A)
Figure 25: High-threshold interrupt function
9.6.6
Overflow
When a measurement axis had an overflow, the corresponding data register is saturated to the
most negative value. For X and Y axis, the data register is set to the value -4096. For the Z
axis, the data register is set to the value -16384.
The “Overflow” flag (register 0x4A bit6) indicates that the measured magnetic field raw data of
one or more axes exceeded maximum range of the device. The overflow condition can be
flagged on the INT pin by setting the bit “overflow int enable” (register 0x4D bit6, active high,
default value “0”). The channel on which overflow occurred can by determined by assessing the
DATAX/Y/Z registers.
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10 Register description magnetometer
10.1 General remarks
The entire communication with the device’s magnetometer part is performed by reading from
and writing to registers. Registers have a width of 8 bits; they are mapped to a common space
of 50 addresses from (0x40) up to (0x71). Within the used range there are several registers
which are marked as ‘reserved’. Any reserved bit is ignored when it is written and no specific
value is guaranteed when read. Especially, in SPI mode the SDO pin may stay in high-Z state
when reading some of these registers.
Registers with addresses from (0x40) up to (0x4A) are read-only. Any attempt to write to these
registers is ignored.
10.2 Register map magnetometer
Register Address
0x71
0x70
0x6F
0x6E
0x6D
0x6C
0x6B
0x6A
0x69
0x68
0x67
0x66
0x65
0x64
0x63
0x62
0x61
0x60
0x5F
0x5E
0x5D
0x5C
0x5B
0x5A
0x59
0x58
0x57
0x56
0x55
0x54
0x53
0x52
0x51
0x50
0x4F
0x4E
0X4D
0x4C
0x4B
0x4A
0x49
0x48
0x47
0x46
0x45
0x44
0x43
0x42
0x41
0x40
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x00
0x00
0x00
0x00
0x07
0x3F
0x06
0x01
0x00
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x32
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
reserved
Data Ready Pin En
Interrupt Pin En
Overflow Int En
Data Overrun En
Adv. ST [1:0]
Soft Reset '1'
fixed '0'
Data Overrun
Overflow
REPZ Number Of Repetitions (valid for Z) [7:0]
REPXY Number Of Repetitions (valid for XY) [7:0]
High Threshold [7:0]
Low Threshold [7:0]
Channel Z
Channel Y
Channel X
High Int Z en
High Int Y en
High Int X en
Data Rate [2:0]
fixed '0'
fixed '0'
fixed '0'
High Int Z
High Int Y
High Int X
RHALL [13:6] MSB
RHALL [5:0] LSB
DATA Z [14:7] MSB
DATA Z [6:0] LSB
DATA Y [12:5] MSB
DATA Y [4:0] LSB
DATA X [12:5] MSB
DATA X [4:0] LSB
reserved
Chip ID = 0x32 (can only be read if power control bit ="1")
DR Polarity
Interrupt Latch
Low Int Z en
Low Int Y en
Opmode [1:0]
SPI3en
Soft Reset '1'
Low Int Z
Low Int Y
Interrupt Polarity
Low Int X en
Self Test
Power Control Bit
Low Int X
fixed '0'
Data Ready Status
fixed '0'
fixed '0'
Y-Self-Test
fixed '0'
fixed '0'
X-Self-Test
Z-Self-Test
w/r
w/r accessible
in suspend mode
read only
reserved
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BMX055
Data sheet
Page 131
10.3 Chip ID magnetometer
MAG Register (0x40)
Chip ID contains the magnetometer chip identification number, which is 0x32. This number can
only be read if the power control bit (register 0x4B bit0) is enabled.
Table 39: Chip identification number, register (0x40)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
1
0
0
1
0
MAG Register (0x41) is reserved
10.4 Magnetic field data
MAG Register (0x42)
Register (0x42) contains the LSB part of x-axis magnetic field data and the self-test result flag
for the x-axis.
Table 40: LSB part of x-axis magnetic field, register (0x42)
(0x42) Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Description
DATAX_lsb
DATAX_lsb
DATAX_lsb
DATAX_lsb
DATAX_lsb
SelfTestX
Bit 4 of x-axis magnetic field data
Bit 3 of x-axis magnetic field data
Bit 2 of x-axis magnetic field data
Bit 1 of x-axis magnetic field data
Bit 0 of x-axis magnetic field data = x LSB
(fixed to 0)
(fixed to 0)
Self-test result flag for x-axis, default is “1”
MAG Register (0x43)
Register (0x43) contains the MSB part of x-axis magnetic field data.
Table 41: MSB part of x-axis magnetic field, register (0x43)
(0x43) Bit
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DATAX_msb
DATAX_msb
DATAX_msb
DATAX_msb
DATAX_msb
DATAX_msb
DATAX_msb
DATAX_msb
Bit 12 of x-axis magnetic field data = x MSB
Bit 11 of x-axis magnetic field data
Bit 10 of x-axis magnetic field data
Bit 9 of x-axis magnetic field data
Bit 8 of x-axis magnetic field data
Bit 7 of x-axis magnetic field data
Bit 6 of x-axis magnetic field data
Bit 5 of x-axis magnetic field data
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 132
MAG Register (0x44)
Register (0x44) contains the LSB part of y-axis magnetic field data and the self-test result flag
for the y-axis.
Table 42: LSB part of y-axis magnetic field, register (0x44)
(0x44) Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Description
DATAY_lsb
DATAY_lsb
DATAY_lsb
DATAY_lsb
DATAY_lsb
SelfTestY
Bit 4 of y-axis magnetic field data
Bit 3 of y-axis magnetic field data
Bit 2 of y-axis magnetic field data
Bit 1 of y-axis magnetic field data
Bit 0 of y-axis magnetic field data = y LSB
(fixed to 0)
(fixed to 0)
Self-test result flag for y-axis, default is “1”
MAG Register (0x45)
Register (0x45) contains the MSB part of y-axis magnetic field data.
Table 43: MSB part of y-axis magnetic field, register (0x45)
(0x45) Bit
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DATAY_msb
DATAY_msb
DATAY_msb
DATAY_msb
DATAY_msb
DATAY_msb
DATAY_msb
DATAY_msb
Bit 12 of y-axis magnetic field data = y MSB
Bit 11 of y-axis magnetic field data
Bit 10 of y-axis magnetic field data
Bit 9 of y-axis magnetic field data
Bit 8 of y-axis magnetic field data
Bit 7 of y-axis magnetic field data
Bit 6 of y-axis magnetic field data
Bit 5 of y-axis magnetic field data
MAG Register (0x46)
Register (0x46) contains the LSB part of z-axis magnetic field data and the self-test result flag
for the z-axis.
Table 44: LSB part of z-axis magnetic field, register (0x46)
(0x46) Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Description
DATAZ_lsb
DATAZ_lsb
DATAZ_lsb
DATAZ_lsb
DATAZ_lsb
DATAZ_lsb
DATAZ_lsb
SelfTestZ
Bit 6 of z-axis magnetic field data
Bit 5 of z-axis magnetic field data
Bit 4 of z-axis magnetic field data
Bit 3 of z-axis magnetic field data
Bit 2 of z-axis magnetic field data
Bit 1 of z-axis magnetic field data
Bit 0 of z-axis magnetic field data = z LSB
Self-test result flag for z-axis, default is “1”
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BMX055
Data sheet
Page 133
MAG Register (0x47)
Register (0x47) contains the MSB part of z-axis magnetic field data.
Table 45: MSB part of z-axis magnetic field, register (0x47)
(0x47) Bit
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DATAZ_msb
DATAZ_msb
DATAZ_msb
DATAZ_msb
DATAZ_msb
DATAZ_msb
DATAZ_msb
DATAZ_msb
Bit 14 of y-axis magnetic field data = z MSB
Bit 13 of y-axis magnetic field data
Bit 12 of y-axis magnetic field data
Bit 11 of y-axis magnetic field data
Bit 10 of y-axis magnetic field data
Bit 9 of y-axis magnetic field data
Bit 8 of y-axis magnetic field data
Bit 7 of y-axis magnetic field data
MAG Register (0x48)
Register (0x48) contains the LSB part of hall resistance and the Data Ready (DRDY) status bit.
Table 46: LSB part of hall resistance, register (0x48)
(0x48) Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Description
RHALL_lsb
RHALL_lsb
RHALL_lsb
RHALL_lsb
RHALL_lsb
RHALL_lsb
Data Ready Status
Bit 5 of hall resistance
Bit 4 of hall resistance
Bit 3 of hall resistance
Bit 2 of hall resistance
Bit 1 of hall resistance
Bit 0 of hall resistance = RHALL LSB
(fixed to 0)
Data ready (DRDY) status bit
MAG Register (0x49)
Register (0x49) contains the MSB part of hall resistance.
Table 47: MSB part of hall resistance, register (0x49)
(0x49) Bit
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RHALL_msb
RHALL_msb
RHALL_msb
RHALL_msb
RHALL_msb
RHALL_msb
RHALL_msb
RHALL_msb
Bit 13 of hall resistance = RHALL MSB
Bit 12 of hall resistance
Bit 11 of hall resistance
Bit 10 of hall resistance
Bit 9 of hall resistance
Bit 8 of hall resistance
Bit 7 of hall resistance
Bit 6 of hall resistance
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BMX055
Data sheet
Page 134
10.5 Interrupt status register magnetometer
MAG Register (0x4A)
Register (0x4A) contains the states of all interrupts.
Table 48: Interrupt status, register (0x4A)
(0x4A) Bit
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data overrun
Overflow
High Int Z
High Int Y
High Int X
Low Int Z
Low Int Y
Low Int X
Data overrun status flag
Overflow status flag
High-Threshold interrupt z-axis status flag
High-Threshold interrupt y-axis status flag
High-Threshold interrupt x-axis status flag
Low-Threshold interrupt z-axis status flag
Low-Threshold interrupt y-axis status flag
Low-Threshold interrupt x-axis status flag
10.6 Power and operation modes, self-test, data output rate control registers
MAG Register (0x4B)
Register (0x4B) contains control bits for power control, soft reset and interface SPI mode
selection. This special control register is also accessible in suspend mode.
Soft reset is executed when both bits (register 0x4B bit7 and bit1) are set “1”. Soft reset does
not execute a full POR sequence, but all registers are reset except for the “trim” registers above
register 0x54 and the power control register (0x4B). Soft reset always brings the device into
sleep mode. When device is in the suspend mode, soft reset is ignored and the device remains
in suspend mode. The two “Soft Reset” bits are reset to “0” automatically after soft reset was
completed. To perform a full POR reset, bring the device into suspend and then back into sleep
mode.
When SPI mode is selected, the “SPI3En” bit enables SPI 3-wire mode when set “1”. When
“SPI3En” is set “0” (default), 4-wire SPI mode is selected.
Setting the “Power Control bit” to “1” brings the device up from Suspend mode to Sleep mode,
when “Power Control bit” is set “0” the device returns to Suspend mode (see chapter 9.2 for
details of magnetometer power modes).
Table 49: Power control, soft reset and SPI mode control register (0x4B)
(0x4B) Bit
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Soft Reset ‘1’
SPI3en
Soft Reset ‘1’
Power Control bit
One of the soft reset trigger bits.
(fixed to 0)
(fixed to 0)
(fixed to 0)
(fixed to 0)
Enable bit for SPI3 mode
One of the soft reset trigger bits.
When set to “0”, suspend mode is selected
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BMX055
Data sheet
Page 135
MAG Register (0x4C)
Register (0x4C) contains control bits for operation mode, output data rate and self-test.
The two “Adv. ST” bits control the on-chip advanced self-test (see chapter 9.4 for details of the
magnetometer advanced self-test).
The three “Data rate” bits control the magnetometer output data rate according to below Table
51.
The two “Opmode” bits control the operation mode according to below Table 52 (see chapter
9.2 for a detailed description of magnetometer power modes).
Table 50: Operation mode, output data rate and self-test control register (0x4C)
(0x4C) Bit
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Adv. ST
Adv. ST
Data rate
Data rate
Data rate
Opmode
Opmode
Self Test
Advanced self-test control bit 1
Advanced self-test control bit 0
Data rate control bit 2
Data rate control bit 1
Data rate control bit 0
Operation mode control bit 1
Operation mode control bit 0
Normal self-test control bit
Three “Data rate” bits control the output data rate (ODR) of the magnetometer part:
Table 51: Output data rate (ODR) setting (0x4C)
(0x4C)
Data rate
Magnetometer output data rate
(ODR) [Hz]
000b
001b
010b
011b
100b
101b
110b
111b
10 (default)
2
6
8
15
20
25
30
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BMX055
Data sheet
Page 136
Two “Opmode” bits control the operation mode of the magnetometer part:
Table 52: Operation mode setting (0x4C)
(0x4C)
Opmode
Magnetometer operation mode
00b
01b
10b
11b
Normal mode
Forced mode
Reserved, do not use
Sleep Mode
9
10.7 Interrupt and axis enable settings control registers
MAG Register (0x4D)
Register (0x4D) contains control bits for interrupt settings. (Also refer to chapter 9.6 for the
details of magnetometer interrupt operation).
Table 53: Interrupt settings control register (0x4D)
(0x4D) Bit
Name
Description
Bit 7
Data Overrun En
Bit 6
Overflow Int En
Bit 5
High Int Z En
Bit 4
High Int Y En
Bit 3
High Int X En
Bit 2
Low Int Z En
Bit 1
Low Int Y En
Bit 0
Low Int X En
Enables data overrun indication in the “Data Overrun” flag
(active high, default is “0” disabled)
Activates mapping of Overflow flag status to the INT pin
(active high, default is “0” disabled)
Enables the z-axis detection for High-Threshold interrupts
(active low, default is “1” disabled)
Enables the y-axis detection for High-Threshold interrupts
(active low, default is “1” disabled)
Enables the x-axis detection for High-Threshold interrupts
(active low, default is “1” disabled)
Enables the z-axis detection for Low-Threshold interrupts
(active low, default is “1” disabled)
Enables the y-axis detection for Low-Threshold interrupts
(active low, default is “1” disabled)
Enables the x-axis detection for Low-Threshold interrupts
(active low, default is “1” disabled)
9
See chapter 9.2 for a detailed description of magnetometer power modes.
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BMX055
Data sheet
Page 137
MAG Register (0x4E)
Register (0x4E) contains control bits interrupt settings and axes enable bits. (Also refer to
chapter 9.6 for the details of magnetometer interrupt operation). If a magnetic measurement
channel is disabled, its last measured magnetic output values will remain in the data registers. If
the Z channel is disabled, the resistance measurement will also be disabled and the resistance
output value will be set to zero. If interrupts are set to trigger on an axis that has been disabled,
these interrupts will still be asserted based on the last measured value.
Table 54: Interrupt settings and axes enable bits control register (0x4E)
(0x4E) Bit
Name
Description
Bit 7
Data Ready Pin En
Bit 6
Interrupt Pin En
Bit 5
Channel Z
Bit 4
Channel Y
Bit 3
Channel X
Bit 2
DR Polarity
Bit 1
Interrupt Latch
Bit 0
Interrupt Polarity
Enables data ready status mapping on DRDY pin
(active high, default is “0” disabled)
Enables interrupt status mapping on INT pin
(active high, default is “0” disabled)
Enable z-axis and resistance measurement
(active low, default is “0” enabled)
Enable y-axis
(active low, default is “0” enabled)
Enable x-axis
(active low, default is “0” enabled)
Data ready (DRDY) pin polarity
(“0” is active low, “1” is active high, default is “1” active
high)
Interrupt latching
(“0” means non-latched - interrupt pin is on as long as the
condition is fulfilled, “1” means latched - interrupt pin is on
until interrupt status register 0x4A is read, default is ‘”1”
latched)
Interrupt pin INT polarity selection
(“1” – is active high, “0” is active low, default is “1” active
high)
MAG Register (0x4F)
Register (0x4F) contains the Low-Threshold interrupt threshold setting. (Also refer to
chapter 9.6 for the details of magnetometer interrupt operation and the threshold setting).
Table 55: Low-threshold interrupt threshold setting control register (0x4F)
(0x4F) Bit
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LowThreshold
LowThreshold
LowThreshold
LowThreshold
LowThreshold
LowThreshold
LowThreshold
LowThreshold
Bit 7 of Low-Threshold interrupt threshold setting
Bit 6 of Low-Threshold interrupt threshold setting
Bit 5 of Low-Threshold interrupt threshold setting
Bit 4 of Low-Threshold interrupt threshold setting
Bit 3 of Low-Threshold interrupt threshold setting
Bit 2 of Low-Threshold interrupt threshold setting
Bit 1 of Low-Threshold interrupt threshold setting
Bit 0 of Low-Threshold interrupt threshold setting
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 138
MAG Register (0x50)
Register (0x50) contains the High-Threshold interrupt threshold setting. (Also refer to
chapter 9.6 for the details of magnetometer interrupt operation and the threshold setting).
Table 56: High-threshold interrupt threshold setting control register (0x4F)
(0x50) Bit
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HighThreshold
HighThreshold
HighThreshold
HighThreshold
HighThreshold
HighThreshold
HighThreshold
HighThreshold
Bit 7 of High-Threshold interrupt threshold setting
Bit 6 of High-Threshold interrupt threshold setting
Bit 5 of High-Threshold interrupt threshold setting
Bit 4 of High-Threshold interrupt threshold setting
Bit 3 of High-Threshold interrupt threshold setting
Bit 2 of High-Threshold interrupt threshold setting
Bit 1 of High-Threshold interrupt threshold setting
Bit 0 of High-Threshold interrupt threshold setting
10.8 Number of repetitions control registers
MAG Register (0x51)
Register (0x51) contains the number of repetitions for x/y-axis. Table 58 below shows the
number of repetitions resulting out of the register configuration. The performed number of
repetitions nXY can be calculated from unsigned register value as nXY = 1+2xREPXY as
shown below, where b7-b0 are the bits 7 to 0 of register 0x51:
nXY 1 2 (b 7 2 7 b 6 2 6 b 5 25 b 4 2 4 b 3 23 b 2 2 2 b1 21 b 0 2 0 )
1 2 (REPXY )
Table 57: X/y-axis repetitions control register (0x51)
(0x51) Bit
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REPXY
REPXY
REPXY
REPXY
REPXY
REPXY
REPXY
REPXY
Bit 7 of number of repetitions (valid for XY)
Bit 6 of number of repetitions (valid for XY)
Bit 5 of number of repetitions (valid for XY)
Bit 4 of number of repetitions (valid for XY)
Bit 3 of number of repetitions (valid for XY)
Bit 2 of number of repetitions (valid for XY)
Bit 1 of number of repetitions (valid for XY)
Bit 0 of number of repetitions (valid for XY)
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BMX055
Data sheet
Page 139
Table 58: Numbers of repetition for x/y-axis depending on value of register (0x51)
(0x51) register (0x51) register value
value (binary)
(hex)
Number of repetitions for x- and y-axis each
00000000b
00000001b
00000010b
00000011b
…
11111111b
1
3
5
7
…
511
0x00h
0x01h
0x02h
0x03h
0xFFh
MAG Register (0x52)
Register (0x52) contains the number of repetitions for z-axis. Table 60 below shows the number
of repetitions resulting out of the register configuration. The performed number of repetitions nZ
can be calculated from unsigned register value as nZ = 1+REPZ as shown below, where b7-b0
are the bits 7 to 0 of register 0x52:
nZ 1 1 (b 7 27 b 6 26 b 5 25 b 4 24 b 3 23 b 2 22 b1 21 b 0 20 )
1 REPZ
Table 59: Z-axis repetitions control register (0x52)
(0x52) Bit
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REPZ
REPZ
REPZ
REPZ
REPZ
REPZ
REPZ
REPZ
Bit 7 of number of repetitions (valid for Z)
Bit 6 of number of repetitions (valid for Z)
Bit 5 of number of repetitions (valid for Z)
Bit 4 of number of repetitions (valid for Z)
Bit 3 of number of repetitions (valid for Z)
Bit 2 of number of repetitions (valid for Z)
Bit 1 of number of repetitions (valid for Z)
Bit 0 of number of repetitions (valid for Z)
Table 60: Numbers of repetition for z-axis depending on value of register (0x52)
(0x52) register
value (binary)
(0x52) register
value
(hex)
Number of repetitions for z-axis
00000000b
00000001b
00000010b
00000011b
…
11111111b
0x00h
0x01h
0x02h
0x03h
1
2
3
4
…
256
0xFFh
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BMX055
Data sheet
Page 140
11 Digital interface of the device
The BMX055 supports two serial digital interface protocols for communication as a slave with a
host device: SPI (4-wire and 3-wire) and I²C. The active interface is selected by the state of the
Pin#07 (PS) ‘protocol select’ pin: ´GND´ (´VDDIO´) selects SPI (I²C). For details please refer to
section 11.
By default, SPI operates in the standard 4-wire configuration. It can be re-configured by
software to work in 3-wire mode instead of standard 4-wire mode.
Both digital interfaces share partly the same pins. Additionally each inertial sensor
(accelerometer and gyroscope) provides specific interface pins which allow the user to operate
the inertial sensors independently of each other. The mapping for each interface and each
inertial sensor is given in the following table:
Table 61: Mapping of the interface pins
Pin
#
Name
use w/
SPI
use w/
I²C
Description
17
SDOAM
SDOAM
address
SPI: Accel&Mag Data Output (4-wire mode)
I²C: Used to set LSB of Accel&Mag I²C address
12
SDOG
SDOG
address
SPI: Gyro Data Output (4-wire mode)
I²C: Used to set LSB of Gyro I²C address
11
SDx
SDI
SDA
SPI: Data In (4-wire mode) & Data In/Out (3-wire
mode) I²C: Serial Data
16
CSBA
CSBA
unused
SPI: Accel Chip Select (enable)
5
CSBG
CSBG
unused
SPI: Gyro Chip Select (enable)
20
CSBM
CSBM
address
SPI:Mag Chip Select(enable)
I²C: Used to set LSB of Mag I²C address
9
SCx
SCK
SCL
SPI: Serial Clock SCK
I²C: Serial Clock SCL
The following table shows the electrical specifications of the interface pins:
Table 62: Electrical specification of the interface pins
Parameter
Symbol
Condition
Min
Typ
Max
Units
Pull-up Resistance,
CSB pin
Rup
Internal Pull-up
Resistance to
VDDIO
75
100
125
k
Input Capacitance
Cin
5
10
pF
I²C Bus Load
Capacitance (max.
drive capability)
CI2C_Load
400
pF
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 141
11.1 Serial peripheral interface (SPI)
The timing specification for SPI of the BMX055 is given in the following table:
Table 63: SPI timing
Parameter
Symbol
Condition
fSPI
Max. Load on
SDI or SDO =
25pF, VDDIO ≥
1.62V
VDDIO < 1.62V
Clock Frequency
SCK Low Pulse
SCK High Pulse
SDI Setup Time
SDI Hold Time
SDO Output Delay
CSB Setup Time
CSB Hold Time
Idle time between
write accesses,
normal mode,
standby mode, lowpower mode 2
Idle time between
write accesses,
suspend mode, lowpower mode 1
tSCKL
tSCKH
Max
Units
10
MHz
7.5
MHz
20
20
20
20
tSDI_setup
tSDI_hold
tSDO_OD
Min
Load = 25pF,
VDDIO ≥ 1.62V
Load = 25pF,
VDDIO < 1.62V
Load = 250pF,
VDDIO > 2.4V
ns
ns
ns
ns
30
ns
50
ns
40
ns
tCSB_setup
tCSB_hold
20
40
ns
ns
tIDLE_wacc_nm
2
µs
tIDLE_wacc_sum
450
µs
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 142
The following figure shows the definition of the SPI timings:
tCSB_setup
tCSB_hold
CSB
SCK
tSCKL tSCKH
SDI
SDO
tSDI_setup
tSDI_hold
tSDO_OD
Figure 26: SPI timing diagram
The SPI interface of the BMX055 is compatible with two modes, ´00´ and ´11´. The automatic
selection between [CPOL = ´0´ and CPHA = ´0´] and [CPOL = ´1´ and CPHA = ´1´] is controlled
based on the value of SCK after a falling edge of CSB (A,G or M).
Two configurations of the SPI interface are supported by the BMX055: 4-wire and 3-wire. The
same protocol is used by both configurations. The device operates in 4-wire configuration by
default. It can be switched to 3-wire configuration by writing ´1´ to (ACC 0x34) spi3 and to (GYR
0x34) spi3. Pin SDI is used as the common data pin in 3-wire configuration.
For single byte read as well as write operations, 16-bit protocols are used. The BMX055 also
supports multiple-byte read operations.
In SPI 4-wire configuration CSB (A,G or M - chip select low active), SCK (serial clock), SDI
(serial data input), and SDO (AM or G - serial data output) pins are used. The communication
starts when the CSB (1 or 2) is pulled low by the SPI master and stops when CSB (A,G or M) is
pulled high. SCK is also controlled by SPI master. SDI and SDO (AM or G) are driven at the
falling edge of SCK and should be captured at the rising edge of SCK.
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 143
The basic write operation waveform for 4-wire configuration is depicted in Figure 27. During the
entire write cycle SDO remains in high-impedance state.
CSB
SCK
SDI
R/W
AD6
AD5
AD4
AD3
AD2
AD1
SDO
AD0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Z
tri-state
Figure 27: 4-wire basic SPI write sequence (mode ´11´)
The basic read operation waveform for 4-wire configuration is depicted in Figure 28:
CSB
SCK
SDI
R/W
AD6
AD5
AD4
AD3
AD2
AD1
AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 tri-state
Figure 28: 4-wire basic SPI read sequence (mode ´11´)
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 144
The data bits are used as follows:
Bit0: Read/Write bit. When 0, the data SDI is written into the chip. When 1, the data SDO from
the chip is read.
Bit1-7: Address AD(6:0).
Bit8-15: when in write mode, these are the data SDI, which will be written into the address.
When in read mode, these are the data SDO, which are read from the address.
Multiple read operations are possible by keeping CSB low and continuing the data transfer.
Only the first register address has to be written. Addresses are automatically incremented after
each read access as long as CSB stays active low.
The principle of multiple read is shown in Figure 29:
Control byte
Start
RW
CSB
=
0
1
Register adress (02h)
0
0
0
0
0
1
0
X
X
Data byte
Data byte
Data byte
Data register - adress 02h
Data register - adress 03h
Data register - adress 04h
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Stop
X
Figure 29: SPI multiple read
In SPI 3-wire configuration CSB (A,G or M - chip select low active), SCK (serial clock), and
SDI (serial data input and output) pins are used. The communication starts when the CSB is
pulled low by the SPI master and stops when CSB is pulled high. SCK is also controlled by SPI
master. SDI is driven (when used as input of the device) at the falling edge of SCK and should
be captured (when used as the output of the device) at the rising edge of SCK.
The protocol as such is the same in 3-wire configuration as it is in 4-wire configuration. The
basic operation wave-form (read or write access) for 3-wire configuration is depicted in Figure
30.
CSB
SCK
SDI
RW
AD6
AD5
AD4
AD3
AD2
AD1
AD0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Figure 30: 3-wire basic SPI read or write sequence (mode ´11´)
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Note: Specifications within this document are preliminary and subject to change without notice.
X
CSB
=
1
BMX055
Data sheet
Page 145
11.2 Inter-Integrated Circuit (I²C)
The I²C bus uses SCL (= SCx pin, serial clock) and SDA (= SDx pin, serial data input and
output) signal lines. Both lines are connected to VDDIO externally via pull-up resistors so that they
are pulled high when the bus is free.
The I²C interface of the BMX055 is compatible with the I²C Specification UM10204 Rev. 03 (19
June 2007), available at http://www.nxp.com. The BMX055 supports I²C standard mode and
fast mode, only 7-bit address mode is supported. For VDDIO = 1.2V to 1.8V the guaranteed
voltage output levels are slightly relaxed as described in the Parameter Specification (Table 1).
When in I²C mode, the BMX055 will work effectively as three I²C-Slave devices. The BMX055 is
not addressed by a single I²C-Address. Instead, the I²C Master (Application processor) should
use a different I²C-Address for each component (Accel, Gyro and Magnet) depending on the
needed data.
In addition to that, the I²C-Address of each component (Accel, Gyro and Magnet) can be
configured by changing the levels in SDO1, SDO2 and CSB3.
The default I²C address of the accelerometer device is 0011000b (0x18) and of the gyro device
is 1101000b (0x68). It is used if the SDO1 (AM and G) pin is pulled to ´GND´. The alternative
accel address 0011001b (0x19) and/or the alternative gyro address 1101001b (0x69) is
selected by pulling the SDO2 (AM and/or G) pin to ´VDDIO´.
The default I2C address of the magnetic device is 0010000b (0x10). The five MSB are
hardwired to “00100”. Alternative addresses of the magnetic device can be selected fixing the
value of SDO or CSB lines. bit0 can be set to “1” by pulling the SDO1 pin to ´VDDIO´. bit1 can be
set to “1” by pulling the CSB3 line pin to ´VDDIO´.
For all I2C address combination of the BMX055, please refer to the following table.
SDO1
SDO2
GND
GND
GND
GND
Vddio
Vddio
Vddio
Vddio
GND
GND
Vddio
Vddio
GND
GND
Vddio
Vddio
Table 64 I2C address
I²CAddr_Accel
GND
0x18
Vddio
0x18
GND
0x18
Vddio
0x18
GND
0x19
Vddio
0x19
GND
0x19
Vddio
0x19
CSB3
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
I²CAddr_Gyro
0x68
0x68
0x69
0x69
0x68
0x68
0x69
0x69
I²CAddr_magnet
0x10
0x12
0x10
0x12
0x11
0x13
0x11
0x13
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 146
The timing specification for I²C of the BMX055 is given in Table 64:
Table 64: I²C timings
Parameter
Clock Frequency
SCL Low Period
SCL High Period
SDA Setup Time
SDA Hold Time
Setup Time for a
repeated Start
Condition
Hold Time for a Start
Condition
Setup Time for a Stop
Condition
Time before a new
Transmission can
start
Idle time between
write accesses,
normal mode, standby
mode, low-power
mode 2
Idle time between
write accesses,
suspend mode, lowpower mode 1
Symbol
fSCL
tLOW
tHIGH
tSUDAT
tHDDAT
tSUSTA
Condition
Min
Max
400
Units
kHz
1.3
0.6
0.1
0.0
0.6
s
tHDSTA
0.6
tSUSTO
0.6
tBUF
1.3
tIDLE_wacc_n
m
tIDLE_wacc_s
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
um
2
µs
450
µs
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BMX055
Data sheet
Page 147
shows the definition of the I²C timings given in Table 64:
SDA
tBUF
tf
tLOW
SCL
tHIGH
tr
tHDSTA
tHDDAT
tSUDAT
SDA
tSUSTA
tSUSTO
Figure 31: I²C timing diagram
The I²C protocol works as follows:
START: Data transmission on the bus begins with a high to low transition on the SDA line while
SCL is held high (start condition (S) indicated by I²C bus master). Once the START signal is
transferred by the master, the bus is considered busy.
STOP: Each data transfer should be terminated by a Stop signal (P) generated by master. The
STOP condition is a low to HIGH transition on SDA line while SCL is held high.
ACK: Each byte of data transferred must be acknowledged. It is indicated by an acknowledge
bit sent by the receiver. The transmitter must release the SDA line (no pull down) during the
acknowledge pulse while the receiver must then pull the SDA line low so that it remains stable
low during the high period of the acknowledge clock cycle.
In the following diagrams these abbreviations are used:
S
P
ACKS
ACKM
NACKM
RW
Start
Stop
Acknowledge by slave
Acknowledge by master
Not acknowledge by master
Read / Write
A START immediately followed by a STOP (without SCL toggling from ´VDDIO´ to ´GND´) is not
supported. If such a combination occurs, the STOP is not recognized by the device.
I²C write access:
I²C write access can be used to write a data byte in one sequence.
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BMX055
Data sheet
Page 148
The sequence begins with start condition generated by the master, followed by 7 bits slave
address and a write bit (RW = 0). The slave sends an acknowledge bit (ACK = 0) and releases
the bus. Then the master sends the one byte register address. The slave again acknowledges
the transmission and waits for the 8 bits of data which shall be written to the specified register
address. After the slave acknowledges the data byte, the master generates a stop signal and
terminates the writing protocol.
Example of an I²C write access to the accelerometer:
Control byte
Slave Adress
Start
S
0
0
1
1
0
Register adress (0x10)
RW ACKS
0
0
0
Data byte
0
0
0
1
0
0
Data (0x09)
ACKS
0
0
X
X
X
X
X
ACKS Stop
X
X
X
P
Figure 32: I²C write
I²C read access:
I²C read access also can be used to read one or multiple data bytes in one sequence.
A read sequence consists of a one-byte I²C write phase followed by the I²C read phase. The
two parts of the transmission must be separated by a repeated start condition (Sr). The I²C write
phase addresses the slave and sends the register address to be read. After slave
acknowledges the transmission, the master generates again a start condition and sends the
slave address together with a read bit (RW = 1). Then the master releases the bus and waits for
the data bytes to be read out from slave. After each data byte the master has to generate an
acknowledge bit (ACK = 0) to enable further data transfer. A NACKM (ACK = 1) from the
master stops the data being transferred from the slave. The slave releases the bus so that the
master can generate a STOP condition and terminate the transmission.
The register address is automatically incremented and, therefore, more than one byte can be
sequentially read out. Once a new data read transmission starts, the start address will be set to
the register address specified in the latest I²C write command. By default the start address is
set at 0x00. In this way repetitive multi-bytes reads from the same starting address are possible.
In order to prevent the I²C slave of the device to lock-up the I²C bus, a watchdog timer (WDT) is
implemented. The WDT observes internal I²C signals and resets the I²C interface if the bus is
locked-up by the BMX055. The activity and the timer period of the WDT can be configured
through the bits (ACC 0x34) plus (GYR 0x34) i2c_wdt_en and (ACC 0x34) plus (GYR 0x34)
i2c_wdt_sel.
Writing ´1´ (´0´) to (ACC 0x34) i2c_wdt_en plus (GYR 0x34) i2c_wdt_en activates (de-activates)
the WDT. Writing ´0´ (´1´) to (ACC 0x34) i2c_wdt_en plus (GYR 0x34) i2c_wdt_se selects a
timer period of 1 ms (50 ms).
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BMX055
Data sheet
Page 149
Example of an I²C read access to the accelerometer:
S
0
0
1
1
0
RW ACKS
0
0
0
dummy
Slave Adress
Start
Control byte
X
Register adress (0x02)
0
0
0
0
0
ACKS
1
0
Data byte
Slave Adress
Start
Sr
0
0
1
1
0
Read Data (0x02)
RW ACKS
0
0
1
Data byte
X
X
X
X
X
X
Read Data (0x03)
ACKM
X
X
X
X
X
Data byte
X
X
X
X
X
X
X
X
X
X
X
Data byte
X
X
X
X
X
X
X
…
X
Read Data (0x05)
ACKM
X
X
X
ACKM
X
…
X
Data byte
Read Data (0x06)
…
X
Data byte
Read Data (0x04)
…
X
ACKM
X
Read Data (0x07)
ACKM
X
X
X
X
X
X
X
X
NACK
X
X
Stop
P
Figure 33: I²C multiple read
11.2.1 SPI and I²C Access Restrictions
In order to allow for the correct internal synchronisation of data written to the BMX055, certain
access restrictions apply for consecutive write accesses or a write/read sequence through the
SPI as well as I2C interface. The required waiting period depends on whether the device is
operating in normal mode or other modes according to chapters 5.1, 7.1, 9.1.
As illustrated in Figure 34, an interface idle time of at least 2 µs is required following a write
operation when the device operates in normal mode. In suspend mode an interface idle time of
least 450 µs is required.
X-after-Write
Write-Operation
X-Operation
Register Update Period
(> 2us / 450us)
Figure 34: Post-Write Access Timing Constraints
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BMX055
Data sheet
Page 150
12 FIFO Operation
12.1 FIFO Operating Modes
The BMX055 features 2 integrated FIFO memories capable of storing up to 32 frames of
accelerometer data and 100 frames of gyroscope data in FIFO mode. Conceptually each frame
consists of three 16 bit words corresponding to the x, y and z- axis of the accelerometer and the
gyro, which are sampled at the same point in time. The FIFO is a buffer memory, which can be
configured to operate in the following modes:
FIFO Mode: In FIFO mode the X, Y and Z acceleration- and rate data of the selected
axes and sensors are stored in the buffer memory. If enabled, a watermark interrupt is
triggered when the buffer has filled up to a configurable level. The buffer will be
continuously filled until the fill level reaches 32 frames for the accelerometer and 100
frames for the gyroscope. When it is full the data collection is stopped, and all additional
samples are ignored. Once the buffer is full, a FIFO-full interrupt is generated if it has
been enabled.
STREAM Mode: In STREAM mode the X, Y and Z acceleration- and rate data of the
selected axes are stored in the buffer until it is full. The buffer has a depth of 31 frames
of accelerometer data and 99 frames of gyro data. When the buffer is full the data
collection continues and oldest entry is discarded. If enabled, a watermark interrupt is
triggered when the buffer is filled to a configurable level. Once the buffer is full, a FIFOfull interrupt is generated if it has been enabled.
BYPASS Mode: In bypass mode, only the current sensor data can be read out from the
FIFO address. Essentially, the FIFO behaves like the STREAM mode with a depth of 1.
Compared to reading the data from the normal data registers, the advantage to the user
is that the packages X, Y, Z are from the same timestamp, while the data registers are
updated sequentially and hence mixing of data from different axes can occur.
The primary FIFO operating mode is selected with register (ACC 0x3E) and (GYR 0x0E)
according to Table 65. When reading register (ACC 0x3E) and (GYR 0x0E)
the current operating mode is given. Writing to (ACC 0x3E) and (GYR 0x0E) clears
and resets the buffer and resets the FIFO-full and watermark interrupt.
Table 65: FIFO operating mode selection
Address: 0x3E
bits
mode
‘00’ (Default)
‘01’
BYPASS
FIFO
‘10’
STREAM
‘11’
Reserved
FIFO
Mode
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Function
buffer depth of 1 frame; old data are discarded
data collection stops when buffer is full
when buffer full: sampling continues, old data
discarded
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BMX055
Data sheet
Page 151
12.2 FIFO Data Readout
The FIFO stores the data that are also available at the read-out registers (ACC 0x02) to (ACC
0x07) for the accelerometer and/or (GYR 0x02) to (GYR 0x07) for the gyroscope. Thus, all
configuration settings apply to the FIFO data as well as the data readout registers. The FIFO
read out is possible through register (ACC 0x3F) bits and/or (GYR 0x3F) bits . The
readout can be performed using burst mode since the read address counter is no longer
incremented, when it has reached address (0x3F). This implies that the trapping also occurs
when the burst read access starts below address (0x3F). A single burst can read out one or
more frames at a time. If a frame is not read completely due to an incomplete read operation,
the remaining part of the frame is lost. In this case the FIFO aligns to the next frame during the
next read operation. The address (ACC 0x3E) bits (data_select) or (GYR 0x3E) bits
(data_select) allows the user to select the data stored in the FIFO according to Table 66.
Writing to data_select clears the FIFO buffer.
Table 66: FIFO data selection
12.2.1
Address: ACC 0x3E and GYR 0x3E
bits data_select
‘00’ (Default)
‘01’
‘10’
‘11’
X,Y,Z (plus INT_status0,1 for GYRO)
X only
Y only
Z only
Address: GYR 0x3D bit 7 tag
Interrupt data stored in FIFO
‘0’ (Default)
Do not collect Interrupts for Gyro
‘1’
Collect Interrupts for Gyro
data of axis stored in FIFO
Data readout Accelerometer
If all axes and tag are enabled, the format of the data read-out from (ACC 0x3F) fifo_data
is as follows:
If all axes are enabled, the format of the data read-out from (ACC 0x3F) is as follows:
…
X LSB
X MSB
Y LSB
Y MSB
Z LSB
Z MSB
…
Frame 1
If only one axis is enabled, the format of the data read-out from (ACC 0x3F) is as follows
(example shown: y-axis only, other axes are equivalent).
Y LSB
YSB
Frame 1
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Y LSB
Y MSB
…
Frame 2
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BMX055
Data sheet
Page 152
If a frame is not completely read due to an incomplete read operation, the remaining part of the
frame is discarded. In this case the FIFO aligns to the next frame during the next read
operation. In order for the discarding mechanism to operate correctly, there must be a delay of
at least 1.5 µs between the last data bit of the partially read frame and the first address bit of
the next FIFO read access. Otherwise frames must not be read out partially.
If the FIFO is read beyond the FIFO fill level zeroes (0) will be read. If the FIFO is read beyond
the FIFO fill level the read or burst read access time must not exceed the sampling time tSAMPLE.
Otherwise frames may be lost.
12.2.2
Data readout Gyroscope
If all axes and tag are enabled, the format of the data read-out from (GYR 0x3F) fifo_data
is as follows:
Int. status Bits
X LSB
X MSB
Y LSB
Y MSB
Z LSB
Z MSB
Int_status 0
Int_status 1
…
Frame 1 ( 8 Bytes)
If only one axis is enabled (and tag is disabled), the format of the data read-out from register
fifo_data is as follows (example shown: Y-axis only, other axis are equivalent). The buffer
depth of the FIFO is independent of the fact whether all or a single axis have been selected.
Y LSB
Y MSB
Frame 1
Y LSB
Y MSB
…
Frame 2
12.2.3 External FIFO synchronization (EFS) for the gyroscope
In addition to the explained data format for the angular rate and interrupt data, the FIFO of the
gyroscope features a mode that allows the precise synchronization of external event with the
gyroscope angular rate and gyroscope interrupts saved in the internal FIFO. This
synchronization can be used for example for image and video stabilization applications. The
EFS Mode can be used in the operating modes FIFO-Mode and STREAM-Mode but not in
BYPASS-Mode.
In order to use the EFS capability, any of the gyroscope interrupt pins (INT3 or INT4) can be
reconfigured to act as EFS-pin, but not both. In addition, the EFS-Mode has to be enabled. The
so configured interrupt pin will then behave as an input pin and not as an interrupt pin. The
working principle is shown in below figure:
EFS-pin
0
0
1
1
1
0
0
FIFO Z(0)
Figure 35: Timing diagram for external FIFO synchronization.
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 153
The EFS-pin depicted in Figure 35 is the Interrupt pin configured as EFS-Mode. FIFO z(0) is the
least significant bit of the z-axis gyro data stored in the FIFO.
In order to enable the EFS-Mode the register (GYR 0x34) bit must be set to “1”. To select
the INT4 pin as EFS-pin, set the register (GYR 0x34) bit to “1”. To select the INT3 pin as
EFS-pin, set the register (GYR 0x34) bit to “0”.
In this Mode, the least significant bit of the z-axis is used as tag-bit, therefore losing its meaning
as gyroscope data bit. The remaining 15 bits of the z-axis gyroscope data keep the same
meaning as in standard mode.
Once the EFS-pin is set to high level, the next FIFO word will be marked with an EFS-tag (zaxis LSB = 1). While the EFS-pin is kept at a High level, the corresponding FIFO words would
be always marked with an EFS-tag. After the EFS-pin is reset to low level, the immediate next
FIFO word could still be marked with the EFS-tag and only after this word, the next EFS-tag will
be reset (z-axis LSB=0). This is shown in the above diagram.
The EFS-tag synchronizes external events with the same time precision as the FIFO update
rate. Therefore update rate of the EFS-tag is determined by the output data rate and can be set
from 100Hz up to 2,000Hz. For more information consult the register (GYR 0x10) (BW) in the
register description.
12.2.3.1 Interface speed requirements for Gyroscope FIFO use
In order to use the FIFO effectively, larger blocks of data need to be read out quickly.
Depending on the output data rate of the sensor, this can impose requirements on the interface.
The output data rate of the gyroscope is determined by the filter configuration (see chapter 8.2).
What interface speed is required depends on the selected rate.
For an I2C speed of 400 kHz, every filter mode can be used.
2
For an I C speed of 200 kHz, only modes with an output data rate of 1 KHz and below
are recommended.
2
For an I C speed of 100 kHz, only modes with an output data rate of 400 Hz and below
are recommended.
12.3 FIFO Frame Counter and Overrun Flag
The address ACC and GYR 0x0E bits (frame_counter) indicate the current fill level
of the buffer. If additional frames are written to the buffer although the FIFO is full, the address
ACC and GYR 0x0E bit 7 (overrun flag) is set. If the FIFO is reset, the FIFO fill level indicated in
the frame_counter is set to ‘0’ and the overrun flag is reset each time a write operation
happens to the FIFO configuration registers. The overrun bit is not reset when the FIFO fill level
frame_counter has decremented to ‘0’ due to reading from the fifo_data register.
12.4 FIFO Interrupts
The FIFO controller has the capability to issue two different interrupt events, the FIFO-full and
the watermark event. Generally the FIFO-full and watermark interrupts are functional in all noncomposite modes, including BYPASS.
In order to enable (disable) the watermark and the FIFO-full- interrupt for the accelerometer the
(ACC 0x17) int_fwm_en bit, the int_ffull_en bit, as well as one or both of the int1_fwm or
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 154
Int2_fwm and int1_ffull or Int2_ffull and bits must be set to ‘1’ (‘0’). For the gyroscope, the
fifo_wm_en bit, the fifo_en bit, as well as one or both of the int1_fifo or int2_fifo bits must be set.
Details are given in Table 67 and Table 68.
The watermark interrupt is asserted when the fill level in the buffer has reached the frame
number defined by the water mark level trigger (ACC 0x30) and/or (GYR 0x3D). The status of
the watermark interrupt for the accelerometer may be read back through the address (ACC
0x0A) bit 6 (fifo_wm_int) status bit. For the gyroscope it may be read back through the address
(GYR 0x0A) bit 4 (fifo_int) status bit. Writing to water mark level trigger (ACC 0x30) and/or
(GYR 0x3D) register clears the FIFO buffer.
The FIFO-full interrupt is the second interrupt capability associated with the FIFO. The FIFOfull interrupt is asserted when the buffer has been fully filled with samples. In FIFO mode this
occurs:
for the accelerometer 32 samples, in STREAM mode 31 samples, and in BYPASS mode
1 sample after the buffer has been cleared.
for the gyroscope 100 samples, in STREAM mode 99 samples, and in BYPASS mode 1
sample after the buffer has been cleared.
The status of the FIFO-full interrupt for the accelerometer may be read back through the
address (ACC 0x0A) bit (fifo_full_int) status bit. For the gyroscope it may be read back through
the address (GYR 0x0A) bit 4 (fifo_int) status bit.
Table 67: Interrupt configuration bits relevant for the accelerometer FIFO controller
ACC Register
fifo_water_mark_level_trigger_retain
int_fwm_en
int_ffull_en
int1_fwm
int2_fwm
int1_ffull
int2_ffull
ACC Address
0x30 bits
0x17 bit 6
0x17 bit 5
0x1A bit 1
0x1A bit 6
0x1A bit 2
0x1A bit 5
Table 68: Interrupt configuration bits relevant for the gyroscope FIFO controller
GYR Register
h2o_mrk_lvl_trig_ret
fifo_wm_en
fifo_en
int1_fifo
int2_fifo
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
GYR Address
0x3D bits
0x1E bit 7
0x15 bit 6
0x18 bit 2
0x18 bit 5
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BMX055
Data sheet
Page 155
13 Pin-out and connection diagram
13.1 Pin-out
The pin-out of the LGA package is shown in Figure 36.
Figure 36: Pin-out top view (left) and
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Pin-out bottom view (right)
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 156
Table 69: Pin description
Pin#
Name
I/O Type
Description
1*
2*
3
INT2
DRDYM
VDD
Digital out
Digital out
Supply
4
GNDA
Ground
5
6
CSB2
GNDIO
Digital in
Ground
Interrupt pin 2 (accel int #2)
Data ready (magnet)
Power supply
analog & digital domain (2.4
- 3.6V)
Ground
for analog domain
SPI chip select gyro
Ground for I/O
7
PS
Digital in
8
9
NC
SCx
Digital in
10*
11
INT5
SDx
Digital out
Digital I/O
12
SDO2
Digital out
13
VDDIO
Supply
14*
15*
INT3
INT4
Digital I/O
Digital I/O
16
17
CSB1
SDO1
Digital in
Digital out
18
19*
20
NC
INT1
CSB3
Digital out
Digital in
Protocol select
(GND = SPI, VDDIO = I²C)
Not connected
SPI: serial clock SCK
I²C: serial clock SCL
Interrupt pin (magnet)
I²C: SDA serial data I/O
SPI 4W: SDI serial data I
SPI 3W: SDA serial data I/O
SPI serial data out gyro
Address select in I²C mode
see chapter 11.2
Digital I/O supply voltage
(1.2V … 3.6V)
Interrupt pin 3 (gyro int #1)
Interrupt pin 4 (gyro int #2)
SPI chip select accel
SPI serial data out accel /
magnet. sensor
I²C-Address[0] of accel /
magnet. sensor in I²C mode
see chapter 11.2
Not connected
Interrupt pin 1 (accel int #1)
SPI chip select magnet.
sensor
I²C-Address[1] of magnet.
sensor in I²C mode
see chapter 11.2
Connect to
in SPI 4W
In SPI 3W
in I²C
Accelerometer INT input (do not connect if unused)
Magnet sens. DRDY input (do not connect if unused)
VDD
VDD
VDD
GND
GND
GND
CSB2
GND
CSB2
GND
DNC (float) **
GND
GND
GND
VDDIO
SCK
Do not connect
SCK
SCL
Magnet INT input (do not connect if unused)
SDI
SDA
SDA
SDO2
DNC (float)
GND
for default addr.
VDDIO
VDDIO
VDDIO
Gyro INT1 input (do not connect if unused)
Gyro INT2 input (do not connect if unused)
CSB1
SDO1
CSB1
DNC (float)
DNC (float) **
GND
for default addr.
Do not connect
Accelerometer INT1 input (do not connect if unused)
CSB3
CSB3
GND
for default addr.
* If INT are not used, please do not connect them (DNC)!
** connecting to VDDIO also allowed
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 157
13.2 Connection diagram 4-wire SPI
Accel INT 1
(Do not connect if unused)
VDDIO
__
Magnet CS
Do not connect
18
SDO1
__
Accel CS
CSB1
16
2
INT3
Gyro INT 1
(Do not connect if unused)
14
SDO2
SDx
MOSI
20
1
15
MISO
19
17
Gyro INT 2
INT4
(Do not connect if unused)
VDDIO
CSB3
INT1
NC
VDD
3
BMX055
4
TOP VIEW
(pads not visible)
13
5
12
6
11
7
INT2
Accel INT 2
(Do not connect if unused)
DRDYM
Magnet Data ready
(Do not connect if unused)
VDD
GNDA
GND
CSB2
__
Gyro CS
C1
GNDIO
GND
PS
C2
Magnet INT
(Do not connect if unused)
9
10
INT5
SCx
8
NC
SCK
Do not connect
GND
GND
Figure 37: 4-wire SPI connection
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 158
13.3 Connection diagram 3-wire SPI
Accel INT 1
(Do not connect if unused)
VDDIO
__
Magnet CS
Do not connect
18
Do not connect
SDO1
__
Accel CS
CSB1
Gyro INT 2
(Do not connect if unused)
INT4
Gyro INT 1
(Do not connect if unused)
INT3
VDDIO
Do not connect
SISO
SDO2
SDx
CSB3
INT1
NC
19
20
17
1
16
2
15
3
BMX055
14
VDD
4
TOP VIEW
(pads not visible)
13
5
12
6
11
7
INT2
Accel INT 2
(Do not connect if unused)
DRDYM
Magnet Data ready
(Do not connect if unused)
VDD
GNDA
GND
CSB2
__
Gyro CS
C1
GNDIO
GND
PS
C2
Magnet INT
(Do not connect if unused)
9
10
INT5
SCx
8
NC
SCK
Do not connect
GND
GND
Figure 38: 3-wire SPI connection
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BMX055
Data sheet
Page 159
2
13.4 Connection diagram I C
Accel INT 1
(Do not connect if unused)
VDDIO
Do not connect
I²C-Addr[1] - Magnet
18
Do not connect
SDO1
CSB1
16
2
INT3
Gyro INT 1
(Do not connect if unused)
14
SDA
SDO2
SDx
20
1
15
I²C-Addr_LSB
(I²C-Addr[0]) - Gyro
19
17
Gyro INT 2
INT4
(Do not connect if unused)
VDDIO
R2
VDDIO
CSB3
INT1
NC
I²C-Addr_LSB (I²C-Addr[0])
– Accel / Magnet
VDD
3
BMX055
4
TOP VIEW
(pads not visible)
13
5
12
6
11
7
INT2
Accel INT 2
(Do not connect if unused)
DRDYM
Magnet Data ready
(Do not connect if unused)
VDD
GNDA
GND
CSB2
Do not connect
GNDIO
GND
PS
C2
R1
Magnet INT
(Do not connect if unused)
9
10
INT5
SCx
8
C1
NC
SCL
Do not connect
GND
GND
Figure 39: I²C connection
Note: the recommended value for C1, C2 is 100 nF.
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BMX055
Data sheet
Page 160
14 Package
14.1 Outline dimensions
The sensor housing is a standard LGA package. Its dimensions are the following.
Unit is mm. Note: Unless otherwise specified tolerance = decimal ± 0.05 mm.
Figure 40: Package outline dimensions in mm
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 161
14.2 Sensing axes orientation
If the sensor is accelerated and/or rotated in the indicated directions, the corresponding
channels of the device will deliver a positive acceleration and/or yaw rate signal (dynamic
acceleration). If the sensor is at rest without any rotation and the force of gravity is acting
contrary to the indicated directions, the output of the corresponding acceleration channel will be
positive and the corresponding gyroscope channel will be “zero” (static acceleration).
Example: If the sensor is at rest or at uniform motion in a gravity field and a static magnetic field
according to the figure given below, the output signals are:
Table 70: Example sensor signal output
ACC
± 0g
± 0g
+ 1g
X channel
Y channel
Z channel
GYR
± 0°/sec
± 0°/sec
± 0°/sec
MAG
0 µT
0 µT
-|B|
az, Bz
ωz
ax, -By
N
B
ωy
ωx
ay, Bx
force
of gravity
S
Figure 41: Orientation of sensor sensing axis
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BMX055
Data sheet
Page 162
The following Table 71 lists all corresponding register output signals on aX, aY, aZ and ΩX, ΩY, ΩZ
and BX, BY, BZ while the sensor is at rest or at uniform motion in a gravity field and subjected to
a constant vertical magnetic field under assumption of a ±2g range setting and a top down
gravity vector as shown above.
Table 71: Output signals depending on device orientation
o
Sensor Orientation
(gravity vector =
static acceleration vector ,
magnetic vector )
o
o
upright
Output Signal aX
0g
0LSB
+1g
+1024LSB
0g
0LSB
-1g
-1024LSB
0g
0LSB
0g
0LSB
Output Signal aY
-1g
-1024LSB
0g
0LSB
+1g
+1024LSB
0g
0LSB
0g
0LSB
0g
0LSB
Output Signal aZ
0g
0LSB
0g
0LSB
0g
0LSB
0g
0LSB
+1g
+1024LSB
-1g
-1024LSB
Output Signal ΩX
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
Output Signal ΩY
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
Output Signal ΩZ
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
0°/sec
0LSB
Output Signal BX
+|B| µT
0 µT
-|B| µT
0 µT
0 µT
0 µT
Output Signal BY
0 µT
+|B| µT
0 µT
-|B| µT
0 µT
0 µT
Output Signal BZ
0 µT
0 µT
0 µT
0 µT
-|B| µT
+|B| µT
o
upright
14.3 Android axes orientation
The Android coordinate system is shown in Figure 42. The origin is in the lower-left corner with
respect to the screen, with the X axis horizontal and pointing right, the Y axis vertical and
pointing up and the Z axis pointing outside the front face of the screen. In this system,
coordinates behind the screen have negative Z values.
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Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 163
Figure 42: Android coordinate system
Attitude terms are defined in the following way:
Heading / Azimuth – angle between the magnetic north direction and the Y axis, around
the Z axis (0° to 360°). 0° = North, 90° = East, 180° = South, 270° = West.
Pitch – rotation around X axis (-180° to 180°), with positive values when the z-axis
moves toward the y-axis.
Roll – rotation around Y axis (-90° to 90°), with positive values when the x-axis moves
toward the z-axis.
Figure 43: Heading, pitch and roll in Android coordinate frame
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BMX055
Data sheet
Page 164
14.4 Landing pattern recommendation
For the design of the landing patterns, we recommend the following dimensioning:
0.25
0.675
0.25
19
0.55
18
20
1
17
4.5
0.5
2
15
3
14
4
13
5
12
6
11
7
10
9
1.775
16
8
0.925
3.0
Figure 44: Landing patterns, dimensions are in mm
Same tolerances as given for the outline dimensions (chapter 14.1, Figure 40) should be
assumed.
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BMX055
Data sheet
Page 165
14.5 Marking
14.5.1
Mass production devices
Table 72: Marking of mass production parts
Labeling
BMX
LYWW
CCC
14.5.2
Name
Symbol
Remark
Product number
BMX
3 alphanumeric digits, fixed
to identify product type
Sub-con ID
L
1 alphanumeric digit, variable to identify
sub-con (L = “A” or L = “U” or L = “P”
Date-Code
YWW
3 numeric digits, fixed to identify
Y = “year” WW = “working week
Lot counter
CCC
3 alphanumeric digits, variable
to generate mass production trace-code
Pin 1 identifier
•
--
Engineering samples
Table 73: Marking of engineering samples
Labeling
X55N
AYYWW
CCCC
Name
Symbol
Eng. sample ID
N
1 alphanumeric digit, fixed to identify
engineering sample, N = “+” or “e” or “E”
Sample ID
AYYWW
1 alphanumeric digit (A) for trace-code
2 numeric digit (YY) for date-code
2 numeric digit (WW) for date-code
Counter ID
CCCC
4 alphanumeric digits, variable
to generate trace-code
Pin 1 identifier
•
--
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Remark
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BMX055
Data sheet
Page 166
14.6 Soldering guidelines
The moisture sensitivity level of the BMX055 sensors corresponds to JEDEC Level 1, see also
-
IPC/JEDEC J-STD-020C
"Joint Industry Standard: Moisture/Reflow Sensitivity
Classification for non-hermetic Solid State Surface Mount Devices"
IPC/JEDEC J-STD-033A "Joint Industry Standard: Handling, Packing, Shipping and Use of
Moisture/Reflow Sensitive Surface Mount Devices"
The sensor fulfils the lead-free soldering requirements of the above-mentioned IPC/JEDEC
standard, i.e. reflow soldering with a peak temperature up to 260°C.
Figure 45: Soldering profile recommendation
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BMX055
Data sheet
Page 167
14.7 Handling instructions
Micromechanical sensors are designed to sense acceleration with high accuracy even at low
amplitudes and contain highly sensitive structures inside the sensor element. The MEMS
sensor can tolerate mechanical shocks up to several thousand g's. However, these limits might
be exceeded in conditions with extreme shock loads such as e.g. hammer blow on or next to
the sensor, dropping of the sensor onto hard surfaces etc.
We recommend to avoid g-forces beyond the specified limits during transport, handling and
mounting of the sensors in a defined and qualified installation process.
This device has built-in protections against high electrostatic discharges or electric fields (e.g.
2kV HBM); however, anti-static precautions should be taken as for any other CMOS
component. Unless otherwise specified, proper operation can only occur when all terminal
voltages are kept within the supply voltage range. Unused inputs must always be tied to a
defined logic voltage level.
For more details on recommended handling, soldering and mounting please contact your local
Bosch Sensortec sales representative and ask for the “Handling, soldering and mounting
instructions” document.
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BMX055
Data sheet
Page 168
14.8 Tape and reel specification
The BMX055 is shipped in a standard cardboard box.
The box dimension for 1 reel is: L x W x H = 35cm x 35cm x 6cm.
BMX055 quantity: 5,000pcs per reel, please handle with care.
A0 = 4.85
B0 = 3.35
K0 = 1.20
14.8.1
Figure 46: Tape and reel dimensions in mm
Orientation within the reel
Processing direction
Figure 47: Orientation of the BMX055 devices relative to the tape
14.9 Environmental safety
The BMX055 sensor meets the requirements of the EC restriction of hazardous substances
(RoHS and RoHS2) directive, see also:
Directive 2002/95/EC of the European Parliament and of the Council of 27 January 2003
on the restriction of the use of certain hazardous substances in electrical and electronic
equipment.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 169
14.9.1 Halogen content
The BMX055 is halogen-free. For more details on the analysis results please contact your
Bosch Sensortec representative.
14.9.2 Internal package structure
Within the scope of Bosch Sensortec’s ambition to improve its products and secure the mass
nd
product supply, Bosch Sensortec qualifies additional sources (e.g. 2 source) for the LGA
package of the BMX055.
While Bosch Sensortec took care that all of the technical packages parameters are described
above are 100% identical for all sources, there can be differences in the chemical content and
the internal structural between the different package sources.
However, as secured by the extensive product qualification process of Bosch Sensortec, this
has no impact to the usage or to the quality of the BMX055 product.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 170
15 Legal disclaimer
15.1 Engineering samples
Engineering Samples are marked with an plus (+) or (e) or (E) or (N). Samples may vary from
the valid technical specifications of the product series contained in this data sheet. They are
therefore not intended or fit for resale to third parties or for use in end products. Their sole
purpose is internal client testing. The testing of an engineering sample may in no way replace
the testing of a product series. Bosch Sensortec assumes no liability for the use of engineering
samples. The Purchaser shall indemnify Bosch Sensortec from all claims arising from the use of
engineering samples.
15.2 Product use
Bosch Sensortec products are developed for the consumer goods industry. They may only be
used within the parameters of this product data sheet. They are not fit for use in life-sustaining
or security sensitive systems. Security sensitive systems are those for which a malfunction is
expected to lead to bodily harm or significant property damage. In addition, they are not fit for
use in products which interact with motor vehicle systems.
The resale and/or use of products are at the purchaser’s own risk and his own responsibility.
The examination of fitness for the intended use is the sole responsibility of the Purchaser.
The purchaser shall indemnify Bosch Sensortec from all third party claims arising from any
product use not covered by the parameters of this product data sheet or not approved by Bosch
Sensortec and reimburse Bosch Sensortec for all costs in connection with such claims.
The purchaser must monitor the market for the purchased products, particularly with regard to
product safety, and inform Bosch Sensortec without delay of all security relevant incidents.
15.3 Application examples and hints
With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Bosch Sensortec hereby disclaims any and
all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights or copyrights of any third party. The information given
in this document shall in no event be regarded as a guarantee of conditions or characteristics.
They are provided for illustrative purposes only and no evaluation regarding infringement of
intellectual property rights or copyrights or regarding functionality, performance or error has
been made.
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 171
16 Document history and modification
Rev. No
Chapter
Description of modification/changes
17
18
-
19
22
1.2
Table 2 updated
0.1
1.2
1.2
4
5.1
5.2.2
5.6.3
5.6.6.1
5.6.7
5.6.10
21
1.0
5.7
Acc reg
0x0F
Acc reg
0x10
Acc reg
0x12
Acc reg
0x14
Acc reg
0x2B
Acc reg
0x30
Acc reg
0x32
7.5.2
7.7
7.7.3
1.1
12.4
14.1
14.4
14.5.1
Initial release
Table 3 updated
Table 4 updated
Recommendation for power up sequence
updated
Description of suspend mode and deep suspend
mode updated; equations for LMP2 updated
Description of temperature sensor added
Recommendation to use pull-up, pull-down
resistors added
Recommendation of single tap usage added
orient_hyst description updated
Comment added on clearance of interrupt when
acceleration is lower than threshold.
Description of accelerometer soft reset updated
ACC Register 0x0F (PMU_RANGE) description
updated
ACC Register 0x10 (PMU_BW) description
updated
ACC Register 0x12 (PMU_LOW_POWER)
renamed
ACC Register 0x14 (BGW_SOFTRESET)
description updated
Date
20
30-March2013
04 October 2013
ACC Register 0x2B (INT_9) description updated
ACC Register 0x30 (FIFO_CONFIG_0)
description updated
ACC Register 0x32 (PMU_SELF_TEST)
description updated
Description of fast offset compensation updated
Description of gyro interrupts updated
Recommendation to use pull-up, pull-down
resistors added
Description of FIFO interrupts updated
Outline dimensions updated
Landing pattern recommendation updated
Correct chip marking
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
07 Nov. 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.
BMX055
Data sheet
Page 172
Bosch Sensortec GmbH
Gerhard-Kindler-Strasse 8
72770 Reutlingen / Germany
contact@bosch-sensortec.com
www.bosch-sensortec.com
Modifications reserved | Printed in Germany
Specifications are preliminary and subject to change
without notice
Document number: BST-BMX055-DS000-01
Revision_1.1_102014
BST-BMX055-DS000-02 | Revision 1.1 | November 2014
Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to
third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are preliminary and subject to change without notice.