SYR838PKC

Application Note: AN_SYR837/SYR838 High Efficiency 5.5V, 6A, 2.4MHz I C Programmable, Synchronous Step Down Regulator 2 General Description Features SYR837/SYR838 is a high efficiency 2.4MHz synchronous step down DC/DC regulator IC capable of delivering up to 6A output currents. It can operate over a wide input voltage range from 2.6V to 5.5V and integrate main switch and • Input voltage range: 2.6V to 5.5V • 2.4 MHz switching frequency minimizes the external components Typical 65uA quiescent current synchronous switch with very low RDS (ON) to minimize the conduction loss. The output voltage can be programmed from • Low RDS(ON) for internal switches (PFET/NFET): 28mΩ/17mΩ 0.7125V to 1.5V through I C interface. • SYR837/SYR838 is in a space saving, low profile CSP1.56*1.96-20 package. Programmable Output Voltage: 0.7125V to 1.5V in 12.5mV steps • 6A continuous output current capability. • Capable for 0.25uH inductor and 22uF Ceramic Capacitor. 2 Ordering Information SYR837/8□(□□)□ Temperature Code Package Code Optional Spec Code Ordering Number SYR837PKC Package Type CSP1.56*1.96-20 Note 0x40H SYR838PKC CSP1.56*1.96-20 0x41H • • Hic-cup mode protection for hard short condition • RoHS Compliant and Halogen Free • Compact package: CSP1.56*1.96-20 Applications • Smart-phone • Web-tablets Typical Applications L1:0.25uH VIN:2.6~5.5V C IN 22uF/6.3V VIN K1 K VOUT 2 V OUT LX COUT 22uF/6.3V VSEL EN SCL SDA R1 R2 1MΩ 1MΩ GND AGND Figure 1. Schematic Diagram AN_SYR837/SYR838 Rev.0.9A Figure2. Efficiency Silergy Corp. Confidential-Prepared for Customer Use Only 1 AN_SYR837/SYR838 Pinout (top view) Part Number SYR837PKC SYR838PKC Package type CSP1.56*1.96-20 CSP1.56*1.96-20 Top Mark① Jn xyz Jq xyz Note① ： x=year code, y=week code, z= lot number code. Pin Pin Name Pin Description D1,D2,E1,E2 VIN D3,D4,E3,E4 B2,B3,C1,C2,C3,C4 A1 SW GND VSEL A2 B1 B4 A3 A4 EN SDA AGND SCL VOUT Power input pin. These pins must be decoupled to ground with at least 22uF ceramic capacitor. The input capacitor should be placed as close as possible between VIN and GND pins. Switching node pin. Connect these pins to the switching node of inductor. Power ground pins. Voltage select pin. When this pin is low, VOUT is set by the VSEL0 register. When this pin is high, VOUT is set by the VSEL1 register. Enable control pin. Active high. Do not leave it floating. 2 I C interface Bi-directional Data line. Analog ground pin. 2 I C interface clock line. Sense pin for output. Connect to the output capacitor side. AN_SYR837/SYR838Rev. 0.9A Silergy Corp. Confidential- Prepared for Customer Use Only 2 AN_SYR837/SYR838 Absolute Maximum Ratings (Note 1) VIN--------------------------------------------------------------------------------------------------------------------------- All Other Pins-------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C CSP1.56*1.96-20----------------------------Package Thermal Resistance (Note 2) θ θ JA -----------------------------------------------------------------------------------------------------------JC ------------------------------------------------------------------------------------------------------------- Junction Temperature Range -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- Storage Temperature Range --------------------------------------------------------------------------------- 6.0V VIN + 0.6V --------------------------------- 2.6W 38°C/W 8°C/W 150°C 260°C -65°C to 150°C Recommended Operating Conditions (Note 3) Supply Input Voltage -------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------- AN_SYR837/SYR838Rev. 0.9A 2.6V to 5.5V -40°C to 125°C -40°C to 85°C Silergy Corp. Confidential- Prepared for Customer Use Only 3 AN_SYR837/SYR838 Electrical Characteristics (VIN = 5V, VOUT = 1.0V, L = 0.25uH, COUT = 22uF, TA = 25°C, unless otherwise specified) Parameter Input Voltage Range VIN UVLO VIN UVLO Hysteresis Quiescent Current Shutdown Current Symbol V IN V UVLO V IQ I SHDN_H/W I EN, VSEL, SDA, SCL Rising threshold Falling threshold Typ 2.45 150 65 0.1 30 IOUT=0, EN=1, FB=105%*VREF EN=0 EN=VIN, Buck_ENx=0 V REG R DS(ON) I I Forced PWM, VOUT=VSEL0, default value -1.5 DS(ON)P SS F OSC T SD T HYS R DSH OVP T V V +1.5 300 40 2.4 150 15 150 6.15 5.85 % mΩ mΩ A A us ns MHz °C °C Ω V V 20 us 7.5 6 LIM_PEAK LIM_VALLEY V µA 17 28 DS(ON)N t Unit V V mV µA 0.4 R DS(ON) Max 5.5 2.55 1.1 IL PFET R Over voltage protection blanking time VIN Rising V IH V VOUT Accuracy PMOS peak current limit NMOS peak current limit Internal soft-start time Min on time Oscillator Frequency Thermal Shutdown Temperature Thermal Shutdown Hysteresis LX node discharge resistor Input OVP shutdown Min 2.6 UVHYST SHDN_S/W NFET R Test Conditions Rising threshold Falling threshold Blanking 5.5 Note 1: Stresses beyond the “Absolute Maximum Ratings” ma y cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θ Note 2: JA is measured in the natural convection at TA = 25°C on a low effective single layer thermal con ductivity test board of JEDEC 51-3 thermal measurement standard. Note 3: The device is not guaranteed to function outside its operating conditions. AN_SYR837/SYR838Rev. 0.9A Silergy Corp. Confidential- Prepared for Customer Use Only 4 AN_SYR837/SYR838 Enabling Function The EN pin controls SYR837/SYR838 start up. EN pin low to high transition starts the power up sequence. If EN pin is low, the DC/DC converter will be turned off. SYR837/SYR838 allows software to enable of the regulator when EN is HIGH, via the BUCK_EN bits. BUCK_EN0 and BUCK_EN1 are both initialized HIGH in the registers. Hardware and Software Enable control table. Pins EN VSEL 0 x 1 0 1 0 1 1 1 1 Bits BUCK_EN0 x 0 1 x x BUCK_EN1 x x x 0 1 OUTPUT OFF OFF ON OFF ON Input Over Voltage Protection Function When the VIN exceeds over voltage protection threshold, SYR837/SYR838 will stop switching to protect the circuitry. An internal 20us blanking time helps to prevent the circuit from shutting down due to noise spikes. 2 I C Interface 2 SYR837/SYR838 features an I C interface that allow the HOST processor to control the output voltage achieve the 2 2 DVS function. The I C interface supports clock speeds of up to 3.4MHz and uses standard I C commands. th SYR837/SYR838 always operates as a slave device, and is addressed using a 7-bit slave address followed by an 8 bit, 2 which indicates whether the transaction is a read-operation or a write-operation. I C address of the SYR837 is set at the factory to 0x40h, the SYR838 is set to 0x41h.. START and STOP Conditions: 2 SYR837/SYR838 is controlled via an I C compatible interface. The START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The STOP condition is a LOW to HIGH transition on the SDA line while SCL is 2 HIGH. A STOP condition must be sent before each START condition. The I C master always generates the START and STOP conditions. Data Validity: The data on the SDA line must be stable during the HIGH period of the SCL, unless generating a START or STOP condition. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. AN_SYR837/SYR838Rev. 0.9A Silergy Corp. Confidential- Prepared for Customer Use Only 5 AN_SYR837/SYR838 Acknowledge: Each address and data transmission uses 9-clock pulses. The ninth pulse is the acknowledge bit (ACK). After the —— START condition, the master sends 7-slave address bits and an R/ W bit during the next 8-clock pulses. During the ninth clock pulse, the device that recognizes its own address holds the data line low to acknowledge. The acknowledge bit is also used by both the master and the slave to acknowledge receipt of register addresses and data. Data Transactions: 2 All transactions start with a control byte sent from the I C master device. The control byte begins with a START condition, followed by 7-bits of slave address (1000000x for the SYR837, 1000001x for the SYR838, this address —— —— th can be changed if necessary) followed by the 8 bit, R/ W bit. The R/ W bit is 0 for a write or 1 for a read. If any slave 2 devices on the I C bus recognize their address, they will acknowledge by pulling the SDA line low for the last clock cycle in the control byte. If no slaves exist at that address or are not ready to communicate, the data line will be 1, indicating a Not Acknowledge condition. Once the control byte is sent, and SYR837/SYR838 acknowledges it, the 2nd byte sent by the master must be a register address byte. The register address byte tells the SYR837/SYR838 which register the master will write or read. Once the SYR837/SYR838 receives a register address byte it responds with an acknowledge. AN_SYR837/SYR838Rev. 0.9A Silergy Corp. Confidential- Prepared for Customer Use Only 6 AN_SYR837/SYR838 Register Settings: 1. VSEL0 (0x00) Register Name VSEL0 Address 0x00 Field Bit R/W Default Description Software buck enable. When EN pin is low, the BUCK_EN0 7 R/W 1 regulator is off. When EN pin is high, BUCK_EN bit takes precedent. MODE0 6 R/W 0 0=Allow auto-PFM mode during light load. 1=Forced PWM mode NSEL0 5:0 R/W 010111 (VOUT=1.0V) 000000 = 0.7125V 000001 = 0.7250V 000010 = 0.7375V …… 010111 = 1.0000V …… 111111 =1.5000V 2. VSEL1 (0x01) Register Name VSEL1 Address 0x01 Field Bit R/W Default Description Software buck enable. When EN pin is low, the BUCK_EN1 7 R/W 1 regulator is off. When EN pin is high, BUCK_EN bit takes precedent. MODE1 6 R/W 0 0=Allow auto-PFM mode during light load. 1=Forced PWM mode NSEL1 5:0 R/W 010111 (VOUT=1.0V) 000000 = 0.7125V 000001 = 0.7250V 000010 = 0.7375V …… 010111 = 1.0000V …… 111111 =1.5000V AN_SYR837/SYR838Rev. 0.9A Silergy Corp. Confidential- Prepared for Customer Use Only 7 AN_SYR837/SYR838 3. Control Register (0x02) Register Name Control Register Address 0x02 Field Output Discharge Slew Rate Bit R/W Default 7 R/W 1 6:4 R/W 000=12.5mV/0.15us Description 0 = discharge resistor is disabled. 1 = discharge resistor is enabled. Set the slew rate for positive voltage transitions. 000 = 12.5mV/0.15us 001 = 12.5mV/0.3us 010 = 12.5mV/0.6us 011 = 12.5mV/1.2us 100 = 12.5mV/2.4us 101 = 12.5mV/4.8us 110 = 12.5mV/9.6us 111 = 12.5mV/19.2us Reserved 3 R/W 0 Always reads back 0. RESET 2 R/W 0 Setting to 1 resets all registers to default values. Reserved 1:0 R/W 00 Always reads back 0. 4. ID1 Register (0x03) Register Name ID1 Register Address 0x03 Field Bit R/W Default Description VENDOR 7:5 R 100 IC vendor Silergy code. Reserved 4 R 0 Always reads back 0. DIE_ID 3:0 R 1000 IC option code AN_SYR837/SYR838Rev. 0.9A Silergy Corp. Confidential- Prepared for Customer Use Only 8 AN_SYR837/SYR838 5. ID2 Register (0x04) Register Name ID2 Register Address 0x04 Field Bit R/W Default Description Reverved 7:4 R 0000 Always reads back 0. DIE_REV 3:0 R 0001 IC mask revision code 6. PGOOD Register (0x05) Register Name PGOOD Register Address 0x05 Field Bit R/W Default Description PGOOD 7 R 0 1: Buck is enabled and soft-start is completed. Reserved 6:0 R 000 0000 Always reads back 0. AN_SYR837/SYR838Rev. 0.9A Silergy Corp. Confidential- Prepared for Customer Use Only 9 AN_SYR837/SYR838 Typical Performance Characteristics Efficiency vs. Load Current Efficiency vs. Load Current 90 95 85 90 80 85 75 80 70 VIN=3.3V,VOUT=0.7125V VIN=3.3V,VOUT=1.0V 75 VIN=4.2V,VOUT=1.0V VIN=4.2V,VOUT=0.7125V VIN=5.0V,VOUT=0.7125V 65 60 10 100 1000 VIN=5.0V,VOUT=1.0V 10000 70 10 100 1000 10000 Load Current (mA) Load Current (mA) Load Transient Efficiency vs. Load Current (VIN=5.0V, VOUT=1.0V, IO=0.6 ~ 6.0A) 100 ∆VOUT 95 100mV/div 90 85 IL 80 5A/div VIN=3.3V,VOUT=1.5V VIN=4.2V,VOUT=1.5V VIN=5.0V,VOUT=1.5V 75 70 10 100 1000 10000 Time (200µs/div) Load Current (mA) Shutdown from Enable Startup from Enable (VIN=5.0V, VOUT=1.0V, IO=6.0A) (VIN=5.0V, VOUT=1.0V, IO=6.0A) EN 5V/div VOUT 1V/div VLX 5V/div EN 5V/div VOUT 1V/div VLX IL IL 5V/div 5A/div 5A/div Time (400µs/div) AN_SYR837/SYR838Rev. 0.9A Time (100µs/div) Silergy Corp. Confidential- Prepared for Customer Use Only 10 AN_SYR837/SYR838 Short Circuit Protection Short Circuit Protection (VIN=5.0V, VOUT=1.0V, IO=0A ~ short) (VIN=5.0V, VOUT=1.0V, IO=6A ~ short) VOUT1V/div IL 5A/div Time (2ms/div) AN_SYR837/SYR838Rev. 0.9A VOUT1V/div IL 5A/div Time (2ms/div) Silergy Corp. Confidential- Prepared for Customer Use Only 11 AN_SYR837/SYR838 Output Ripple (VIN=5.0V, VOUT=1.0V, IO=6.0A) ∆VOUT 50mV/div VLX 2V/div IL 5A/div Time (400ns/div) AN_SYR837/SYR838Rev. 0.9A Silergy Corp. Confidential- Prepared for Customer Use Only 12 AN_SYR837/SYR838 average input current. The inductance is calculated as: Operation SYR837/SYR838 is a high efficiency 2.4MHz synchronous step down DC/DC regulator IC capable of delivering up to 6A output currents. It can operate over a wide input voltage range from 2.6V to 5.5V and integrate main switch and synchronous switch with very low RDS (ON) to minimize the conduction loss. The output voltage can be programmed from 0.7125V 2 to 1.5V through I C interface. Applications Information Because of the high integration in SYR837/SYR838, the application circuit based on this regulator IC is rather simple. Only input capacitor CIN, output capacitor COUT, inductor L need to be selected for the targeted applications. Input capacitor CIN This ripple current through input capacitor is calculated as: I C IN _ R M S = I O U T × D (1 -D ) (A) This formula has a maximum at VIN=2×V OUT condition, where ICIN_RMS=IOUT/2. With the maximum load current at 6A, a typical X5R or better grade ceramic capacitor with 6.3V rating and greater than 22uF capacitance can handle this ripple current well. To minimize the potential noise problem, place this ceramic capacitor really close to the VIN and GND pins. Care should be taken to minimize the loop area formed by CIN, and VIN/GND pins. Output capacitor COUT Both steady state ripple and transient requirements must be taken into account when selecting this capacitor. For the best performance, it is recommended to use X5R or better grade ceramic capacitor with 6.3V rating and more than one 22µF capacitor. Output inductor L: There are several considerations in choosing this inductor. 1) Choose the inductance to provide the desired ripple current. It is suggested to choose the ripple current to be about 40% of the maximum AN_SYR837/SYR838Rev. 0.9A L= (1 − V V OUT /V OUT F ×I SW ) IN_MAX × 40% (H) OUT_MAX where FSW is the switching frequency and IOUT_MAX is the maximum load current. SYR837/SYR838 is less sensitive to the ripple current variations. Consequently, the final choice of inductance can be slightly off the calculation value without significantly impacting the performance. 2) The saturation current rating of an inductor must be selected to guarantee an adequate margin to the peak inductor current under full load conditions. ISAT , MIN > IOUT , 3) MAX + VOUT (1-VOUT/VIN,MAX) 2 ⋅ FSW ⋅ L The DCR of the inductor and the core loss at the switching frequency must be low enough to achieve the desired efficiency requirement. It is desirable to choose an inductor with DCR