DLP-USB232M-G

DLP-USB232M User’s Manual DLP-USB232M-G USB – SERIAL UART Interface Module The DLP-USB232M-G lead free module uses FTDI’s 2nd generation FT232BM USB-UART chip that adds extra functionality to its predecessor (the FT8U232AM) and reduces external component count. HARDWARE FEATURES • Single Chip USB Asynchronous Serial Data Transfer • EEPROM programmable on-board via USB • Full Handshaking & Modem Interface Signals VIRTUAL COM PORT ( VCP ) DRIVERS for • UART I/F Supports 7 / 8 Bit Data, 1 / 2 Stop Bits and - Windows 98 and Windows 98 SE Odd/Even/Mark/Space/No Parity - Windows 2000 / ME / XP • Data rate 300 => 3M Baud ( TLL ) - Windows CE ** • Data rate 300 => 1M Baud ( RS232 ) - MAC OS-8 and OS-9 • Data rate 300 => 3M Baud ( RS422/RS485 ) - MAC OS-X ** • 384 Byte Receive Buffer / 128 Byte Transmit Buffer - Linux 2.40 and greater for high data throughput D2XX ( USB Direct Drivers + DLL S/W Interface ) • Adjustable RX buffer timeout - Windows 98 and Windows 98 SE • Full hardware assisted hardware or X-On / X-Off - Windows 2000 / ME / XP handshaking [ ** = In planning or under development ] • In-built support for event characters and line break APPLICATION AREAS condition • Auto Transmit Buffer control for RS485 - USB - RS232 Converters • Support for USB Suspend / Resume through SLEEP# - USB - RS422 / RS485 Converters and RI# pins • Support for high power USB Bus powered devices through PWREN# pin • Integrated level converter on UART and control signals for interfacing to 5v and 3.3v logic - Upgrading RS232 Legacy Peripherals to USB - Cellular and Cordless Phone USB data transfer cables and interfaces - Interfacing MCU based designs to USB - USB Audio and Low Bandwidth Video data transfer • Integrated 3.3v regulator for USB IO - PDA - USB data transfer • Integrated Power-On-Reset circuit - USB Smart Card Readers • Integrated 6MHz – 48Mhz clock multiplier PLL - Set Top Box (S.T.B ) PC - USB interface • USB Bulk or Isocronous data transfer modes - USB Hardware Modems • 4.4v to 5.25v single supply operation - USB Wireless Modems • UHCI / OHCI / EHCI host controller compatible - USB Instrumentation • USB 1.1 and USB 2.0 compatible - USB Bar Code Readers • USB VID, PID , Serial Number and Product Description strings in external EEPROM Copyright © DLP Design 2002 Page 1 of 12 DLP-USB232M User’s Manual ENHANCEMENTS This section summarizes the enhancements of the 2nd generation silicon from FTDI compared to its FT8U232AM predecessor. For further details, consult the device pin-out description and functional descriptions. • Integrated Level Converter on UART interface and control signals The previous devices would drive the UART and control signals at 5v CMOS logic levels. The new device has • Lower Suspend Current a separate VCC-IO pin allowing the device to directly Integration of RCCLK within the device and internal interface to 3.3v and other logic families without the need design improvements reduce the suspend current of the for external level converter i.c.’s. FT232BM to under 200uA ( excluding the 1.5k pull-up on USB DP ) in USB suspend mode. This allows greater • Improved Power Management control for USB Bus margin for peripherals to meet the USB Suspend current Powered, high current devices limit of 500uA. The previous devices had a USBEN pin, which became active when the device was enumerated by USB. To • Support for USB Isocronous Transfers provide power control, this signal had to be externally While USB Bulk transfer is usually the best choice for gated with SLEEP# and RESET#. This gating is now data transfer, the scheduling time of the data is not done on-chip. USBEN has now been replaced with the guaranteed. For applications where scheduling latency new PWREN# signal which can be used to directly drive takes priority over data integrity such as transferring a transistor or P-Channel MOSFET in applications where audio and low bandwidth video data, the new device now power switching of external circuitry is required. A new offers an option of USB Isocronous transfer via an option EEPROM based option makes the device pull gently bit in the EEPROM. down its UART interface lines when the power is shut off (PWREN# is High ). In this mode, any residual • Programmable Receive Buffer Timeout voltage on external circuitry is bled to GND when power In the previous device, the receive buffer timeout used is removed thus ensuring that external circuitry controlled to flush remaining data from the receive buffer was fixed by PWREN# resets reliably when power is restored. at 16ms timeout. This timeout is now programmable over USB in 1ms increments from 1ms to 255ms, thus allowing the device to be better optimized for protocols requiring faster response times from short data packets. Copyright © DLP Design 2002 Page 2 of 12 DLP-USB232M User’s Manual • TXDEN Timing fix FPGA as supplied by vendors such as Altera and Xilinx. TXDEN timing has now been fixed to remove the external The FPGA device would normally be un-configured ( i.e. delay that was previously required for RS485 applications have no defined function ) at power-up. at high baud rates. TXDEN now works correctly during a Application software on the PC could use Bit Bang Mode transmit send-break condition. to download configuration data to the FPGA which would define it’s hardware function, then after the FPGA device • Improved PreScaler Granularity is configured the FT232BM can switch back into UART The previous version of the Prescaler supported division interface mode to allow the programmed FPGA device by ( n + 0 ), ( n + 0.125 ), ( n + 0.25 ) and ( n + 0.5 ) to communicate with the PC over USB. This approach where n is an integer between 2 and 16,384 ( 214 ). To allows a customer to create a “generic” USB peripheral these have been added ( n + 0.375 ), ( n + 0.625 ), ( n whose hardware function can be defined under control of + 0.75 ) and ( n+ 0.875 ) which can be used to improve the application software. The FPGA based hardware can the accuracy of some baud rates and generate new baud be easily upgraded or totally changed simply by changing rates which were previously impossible ( especially with the FPGA configuration data file. Application notes, higher baud rates ). software and development modules for this application area will be available from FTDI and other 3rd party • PreScaler Divide By 1 Fix developers. The previous device had a problem when the integer part of the divisor was set to 1. In the 2nd generation device, • USB 2.0 (full speed option) setting the prescaler value to 1 gives a baud rate of 2 A new EEPROM based option allows the FT232BM to million baud and setting it to zero gives a baud rate of 3 return a USB 2.0 device descriptor as opposed to USB million baud. Non-integer division is not supported with 1.1. Note: The device would be a USB 2.0 Full Speed divisor values of 0 and 1. device (12Mb/s) as opposed to a USB 2.0 High Speed device (480Mb/s). • Bit Bang Mode The 2nd generation device has a new option referred to as “Bit Bang” mode. In Bit Bang mode, the eight UART interface control lines can be switched between UART interface mode and an 8-bit Parallel IO port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by the prescaler setting. As well as allowing the device to be used standalone as a general purpose IO controller for example controlling lights, relays and switches, some other interesting possibilities exist. For instance, it may be possible to connect the device to an SRAM configurable Copyright © DLP Design 2002 Page 3 of 12 DLP-USB232M User’s Manual Table 1 - DLP-USB232M PINOUT DESCRIPTION Pin# Description 1 BOARD ID (Out) Identifies the board as either a DLP-USB245M or DLP-USB232M. High for DLPUSB232M and low for DLP-USB245M. 2 Ground 3 RESET# (In) Can be used by an external device to reset the FT245BM. If not required, this pin must be tied to VCC. 4 RESETO# (Out) Output of the internal Reset Generator. Stays high impedance for ~ 2ms after VCC > 3.5v and the internal clock starts up, then clamps it’s output to the 3.3v output of the internal regulator. Taking RESET# low will also force RSTOUT# to go high impedance. RSTOUT# is NOT affected by a USB Bus Reset. 5 Ground 6 3V3OUT (Out) Output from the integrated L.D.O. regulator. It’s primary purpose is to provide the internal 3.3v supply to the USB transceiver cell and the RSTOUT# pin. A small amount of current ( RS232 converter designs. 9 RXLED# (O.C.) LED Drive - Pulses Low when Receiving Data via USB Copyright © DLP Design 2002 Page 4 of 12 DLP-USB232M User’s Manual 10 VCC-IO (In) 3.0 volt to +5.25 volt VCC to the UART interface pins 10..12, 14..16 and 18..25. When interfacing with 3.3v external logic connect VCC-IO to the 3.3v supply of the external logic, otherwise connect to VCC to drive out at 5v CMOS level. This pin must be connected to VCC from the target electronics or EXTVCC. 11 EXTVCC – (In) Use for applying main power (4.4 to 5.25 Volts) to the module. Connect to PORTVCC if module is to be powered by the USB port (typical configuration) 12 PORTVCC - (Out) Power from USB port. Connect to EXTVCC if module is to be powered by the USB port (typical configuration). 500mA maximum current available to USB adapter and target electronics if USB device is configured for high power. 13 TXLED# - (O.C.) LED Drive - Pulses Low when Transmitting Data via USB 14 PWRCTL (IN) Bus Powered – Tie Low / Self Powered – Tie High 15 POWEREN# (OUT) Goes Low after the device is configured via USB, then high during USB suspend. Can be used to control power to external logic using a P-Channel Logic Level MOSFET switch. Enable the Interface Pull-Down Option in EEPROM when using the PWREN# pin in this way. 16 TXDEN (OUT) Enable Transmit Data for RS485 17 RI# (IN) Ring Indicator Control Input. When the Remote Wakeup option is enabled in the EEPROM, taking RI# low can be used to resume the PC USB Host controller from suspend. 18 DCD# (IN)Data Carrier Detect Control Input 19 DSR# (IN)Data Set Ready Control Input / Handshake signal 20 DTR# (OUT)Data Terminal Ready Control Output / Handshake signal 21 CTS# (IN) Clear To Send Control Input / Handshake signal 22 RTS# (OUT) Request To Send Control Output / Handshake signal 23 RXD (IN) Receive Asynchronous Data Input 24 TXD (OUT)Transmit Asynchronous Data Output Copyright © DLP Design 2002 Page 5 of 12 DLP-USB232M User’s Manual DEVICE CONFIGURATION EXAMPLES USB Bus Powered and Self Powered Configuration Figure 1 illustrates a typical USB bus powered configuration. A Figure 1 USB Bus Powered device gets its power from the USB bus. Basic rules for USB Bus power devices are as follows – a) On plug-in, the device must draw no more than 100mA b) On USB Suspend the device must draw no more than 500uA. c) A Bus Powered High Power Device (one that draws more than 100mA) should use the SLEEP# pin to keep the current below 100mA on plug-in and 500uA on USB suspend. d) A device that consumes more than 100mA can not be plugged into a USB Bus Powered Hub e) No device can draw more that 500mA from the USB Bus. f) The power descriptor in the EEPROM should be programmed to a value of zero. Figure 2 Figure 2 illustrates a typical USB self powered configuration. A USB Self Powered device gets its power from its own Power Supply and does not draw current from the USB bus. Basic rules for USB Self power devices are as follows – a) A Self-Powered device should not force current down the USB bus when the USB Host or Hub Controller is powered down. b) A Self Powered Device can take as much current as it likes during normal operation and USB suspend as it has its own Power Supply. c) A Self Powered Device can be used with any USB Host and both Bus and Self Powered USB Hubs. Copyright © DLP Design 2002 Page 6 of 12 DLP-USB232M User’s Manual Figure 3 shows how to configure the DLP-USB232M to interface with a 3.3v logic device in Bus-Powered configuration. In this example, a LDO regulator provides 3.3 volts from the USB Bus to the target microcontroller and the VCCIO line (pin 10) which in turn will cause the UART interface IO pins to drive out at 3.3v level. Figure 3 Bus Powered Circuit with Power Control USB Bus powered circuits need to be able to power down Figure 4 in USB suspend mode in order to meet the