Rabbit 2000® Microprocessor
User’s Manual
019–0069
• 070831–P
Rabbit 2000 Microprocessor User’s Manual
Part Number 019-0069 • 070831–P • Printed in U.S.A.
©2002–2007 Rabbit Semiconductor Inc. • All rights reserved.
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Rabbit and Dynamic C are registered trademarks of Rabbit Semiconductor Inc.
Rabbit 2000 is a trademark of Rabbit Semiconductor Inc.
The latest revision of this manual is available on the Rabbit Semiconductor Web site,
www.rabbit.com, for free, unregistered download.
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www.rabbit.com
Rabbit 2000 Microprocessor User’s Manual
TABLE OF CONTENTS
Chapter 1. Introduction
1
1.1 Features and Specifications ...............................................................................................1
1.2 Summary of Rabbit Advantages .........................................................................................5
Chapter 2. Rabbit Design Features
7
2.1 The Rabbit 8-bit Processor vs. 16-bit and 32-bit Processors .....................................................8
2.2 Overview of On-Chip Peripherals.......................................................................................8
2.2.1 Serial Ports ...................................................................................................................................8
2.2.2 System Clock ...............................................................................................................................8
2.2.3 Time/Date Oscillator ....................................................................................................................9
2.2.4 Parallel I/O ...................................................................................................................................9
2.2.5 Slave Port ...................................................................................................................................10
2.2.6 Timers ........................................................................................................................................10
2.3 Design Standards ..........................................................................................................12
2.3.1 Programming Port ......................................................................................................................12
2.3.2 Standard BIOS ...........................................................................................................................12
2.4 Dynamic C Support for the Rabbit ...................................................................................12
Chapter 3. Details on Rabbit
Microprocessor Features
13
3.1 Processor Registers .......................................................................................................13
3.2 Memory Mapping .........................................................................................................15
3.2.1 Extended Code Space .................................................................................................................18
3.2.2 Extending Data Memory ............................................................................................................19
3.2.3 Practical Memory Considerations ..............................................................................................21
3.3 Instruction Set Outline ...................................................................................................22
3.3.1 Load Immediate Data To a Register ..........................................................................................23
3.3.2 Load or Store Data from or to a Constant Address ....................................................................23
3.3.3 Load or Store Data Using an Index Register .............................................................................24
3.3.4 Register to Register Move ..........................................................................................................25
3.3.5 Register Exchanges ....................................................................................................................25
3.3.6 Push and Pop Instructions ..........................................................................................................26
3.3.7 16-bit Arithmetic and Logical Ops ............................................................................................26
3.3.8 Input/Output Instructions ...........................................................................................................29
3.4 How to Do It in Assembly Language—Tips and Tricks ........................................................31
3.4.1 Zero HL in 4 Clocks ...................................................................................................................31
3.4.2 Exchanges Not Directly Implemented .......................................................................................31
3.4.3 Manipulation of Boolean Variables ...........................................................................................31
3.4.4 Comparisons of Integers ............................................................................................................32
3.4.5 Atomic Moves from Memory to I/O Space ...............................................................................34
3.5 Interrupt Structure .........................................................................................................35
3.5.1 Interrupt Priority ........................................................................................................................35
3.5.2 Multiple External Interrupting Devices .....................................................................................37
3.5.3 Privileged Instructions, Critical Sections and Semaphores .......................................................37
3.5.4 Critical Sections .........................................................................................................................38
3.5.5 Semaphores Using Bit B,(HL) ...................................................................................................38
3.5.6 Computed Long Calls and Jumps ..............................................................................................39
Table of Contents
Chapter 4. Rabbit Capabilities
41
4.1 Precisely Timed Output Pulses ........................................................................................41
4.1.1 Pulse Width Modulation to Reduce Relay Power ..................................................................... 43
4.2 Open-Drain Outputs Used for Key Scan ............................................................................44
4.3 Cold Boot ....................................................................................................................45
4.4 The Slave Port ..............................................................................................................46
4.4.1 Slave Rabbit As A Protocol UART ........................................................................................... 47
Chapter 5. Pin Assignments and Functions
49
5.1 Package Schematic and Pinout .........................................................................................49
5.2 Package Mechanical Dimensions .....................................................................................50
5.3 Rabbit Pin Descriptions ..................................................................................................52
5.4 Bus Timing ..................................................................................................................58
5.5 Description of Pins with Alternate Functions ......................................................................59
5.6 DC Characteristics ........................................................................................................61
5.6.1 5.0 Volts .................................................................................................................................... 62
5.6.2 3.3 Volts .................................................................................................................................... 63
5.7 I/O Buffer Sourcing and Sinking Limit ..............................................................................64
Chapter 6. Rabbit Internal I/O Registers
65
6.1 Default Values for all the Peripheral Control Registers .........................................................65
Chapter 7. Miscellaneous I/O Functions
71
7.1 Processor Identification ..................................................................................................71
7.2 Rabbit Oscillators and Clocks ..........................................................................................72
7.3 Clock Doubler ..............................................................................................................74
7.4 Controlling Power Consumption ......................................................................................76
7.5 Output Pins CLK, STATUS, /WDTOUT, /BUFEN..............................................................77
7.6 Time/Date Clock (Real-Time Clock) ................................................................................78
7.7 Watchdog Timer ...........................................................................................................80
7.8 System Reset................................................................................................................82
7.9 Rabbit Interrupt Structure ...............................................................................................84
7.9.1 External Interrupts ..................................................................................................................... 86
7.9.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08 .............................................................. 87
7.10 Bootstrap Operation .....................................................................................................88
Chapter 8. Memory Mapping and Interface
91
8.1 Memory-Mapping Unit ..................................................................................................91
8.2 Memory Interface Unit ...................................................................................................93
8.3 Memory Control Unit Registers .......................................................................................94
8.3.1 Memory Bank Control Registers ............................................................................................... 94
8.3.2 MMU Instruction/Data Register ................................................................................................ 95
8.3.3 Memory Timing Control Register ............................................................................................. 95
8.4 Allocation of Extended Code and Data ..............................................................................96
8.5 How Compiler Compiles to Memory ................................................................................97
Chapter 9. Parallel Ports
9.1
9.2
9.3
9.4
9.5
99
Parallel Port A ............................................................................................................100
Parallel Port B ............................................................................................................101
Parallel Port C ............................................................................................................102
Parallel Port D ............................................................................................................103
Parallel Port E ............................................................................................................106
Chapter 10. I/O Bank Control Registers
109
Rabbit 2000 Microprocessor User’s Manual
Chapter 11. Timers
111
11.1 Timer A...................................................................................................................112
11.1.1 Timer A I/O Registers ............................................................................................................113
11.1.2 Practical Use of Timer A .......................................................................................................114
11.2 Timer B ...................................................................................................................115
11.2.1 Using Timer B ........................................................................................................................117
Chapter 12. Rabbit Serial Ports
119
12.1 Serial Port Register Layout ..........................................................................................120
12.2 Serial Port Interrupt ...................................................................................................123
12.3 Transmit Serial Data Timing........................................................................................124
12.4 Receive Serial Data Timing .........................................................................................124
12.5 Clocked Serial Ports...................................................................................................125
12.6 Clocked Serial Timing ................................................................................................128
12.6.1 Clocked Serial Timing With Internal Clock ..........................................................................128
12.6.2 Clocked Serial Timing with External Clock ..........................................................................128
12.7 Serial Port Software Suggestions ..................................................................................129
12.7.1 Controlling an RS-485 Driver and Receiver ..........................................................................131
12.7.2 Transmitting Dummy Characters ...........................................................................................131
12.7.3 Transmitting and Detecting a Break ......................................................................................131
12.7.4 Using A Serial Port to Generate a Periodic Interrupt .............................................................131
12.7.5 Extra Stop Bits, Sending Parity, 9th Bit Communication Schemes .......................................132
12.7.6 Supporting 9th Bit Communication Protocols .......................................................................134
12.7.7 Rabbit-Only Master/Slave Protocol .......................................................................................135
12.7.8 Data Framing/Modbus ...........................................................................................................135
Chapter 13. Rabbit Slave Port
137
13.1 Hardware Design of Slave Port Interconnection...............................................................143
13.2 Slave Port Registers ...................................................................................................143
13.3 Applications and Communications Protocols for Slaves ....................................................145
13.3.1 Slave Applications .................................................................................................................145
13.3.2 Master-Slave Messaging Protocol .........................................................................................146
Chapter 14. Rabbit 2000 Clocks
149
14.1 Low-Power Design ....................................................................................................150
14.2 Clock Spectrum Spreader Module.................................................................................150
Chapter 15. AC Timing Specifications
151
15.1 Memory Access and I/O Read/Write Times ....................................................................154
15.2 Current Consumption .................................................................................................162
Chapter 16. Rabbit BIOS and Virtual Driver
165
16.1 The BIOS ................................................................................................................165
16.1.1 BIOS Services ........................................................................................................................165
16.1.2 BIOS Assumptions .................................................................................................................166
16.2 Virtual Driver ...........................................................................................................166
16.2.1 Periodic Interrupt ...................................................................................................................166
16.2.2 Watchdog Timer Support .......................................................................................................166
Chapter 17. Other Rabbit Software
169
17.1 Power Management Support ........................................................................................169
17.2 Reading and Writing I/O Registers................................................................................170
17.2.1 Using Assembly Language ....................................................................................................170
17.2.2 Using Library Functions ........................................................................................................170
17.3 Shadow Registers ......................................................................................................171
17.3.1 Updating Shadow Registers ...................................................................................................171
Table of Contents
17.3.2 Interrupt While Updating Registers ....................................................................................... 171
17.3.3 Write-only Registers Without Shadow Registers .................................................................. 172
17.4 Timer and Clock Usage ..............................................................................................172
Chapter 18. Rabbit Instructions
175
18.1 Load Immediate Data .................................................................................................178
18.2 Load & Store to Immediate Address..............................................................................178
18.3 8-bit Indexed Load and Store .......................................................................................178
18.4 16-bit Indexed Loads and Stores ...................................................................................178
18.5 16-bit Load and Store 20-bit Address ............................................................................179
18.6 Register to Register Moves ..........................................................................................179
18.7 Exchange Instructions ................................................................................................180
18.8 Stack Manipulation Instructions ...................................................................................180
18.9 16-bit Arithmetic and Logical Ops ................................................................................180
18.10 8-bit Arithmetic and Logical Ops ................................................................................181
18.11 8-bit Bit Set, Reset and Test .......................................................................................182
18.12 8-bit Increment and Decrement...................................................................................182
18.13 8-bit Fast A register Operations ..................................................................................183
18.14 8-bit Shifts and Rotates .............................................................................................183
18.15 Instruction Prefixes ..................................................................................................184
18.16 Block Move Instructions ...........................................................................................184
18.17 Control Instructions - Jumps and Calls .........................................................................185
18.18 Miscellaneous Instructions ........................................................................................185
18.19 Privileged Instructions ..............................................................................................186
Chapter 19. Differences Rabbit vs. Z80/Z180 Instructions
187
Chapter 20. Instructions in Alphabetical Order
With Binary Encoding
189
Appendix A.
The Rabbit Programming Port
A.1
A.2
A.3
A.4
197
The Rabbit Programming Port ......................................................................................197
Use of the Programming Port as a Diagnostic/Setup Port....................................................198
Alternate Programming Port .........................................................................................198
Suggested Rabbit Crystal Frequencies ............................................................................199
Appendix B. Rabbit 2000 Revisions
201
B.1 Rabbit 2000 Revisions .................................................................................................201
B.2 Discussion of Fixes and Improvements ...........................................................................203
B.2.1 Rabbit Internal I/O Registers .................................................................................................. 204
B.2.2 Revision-Level ID Register .................................................................................................... 205
B.2.3 Serial Port Changes ................................................................................................................. 207
B.2.4 Improved Battery-Backup Circuit .......................................................................................... 209
B.2.5 Added Support for Instruction/Data Split ............................................................................... 211
B.2.6 Write Inhibit (/WE0) After Reset ........................................................................................... 213
B.2.7 Chip Selects Inactive During Internal I/O .............................................................................. 213
B.2.8 External Interrupt Input Bug Fix ............................................................................................ 213
B.2.9 IOI/IOE Prefix Bug Fix .......................................................................................................... 213
B.2.10 DDCB/FDCB Instruction Page and Wait State Bug Fixes ................................................... 214
B.2.11 LDIR/LDDR Instruction/Data Split Bug Fix ........................................................................ 214
B.2.12 Clock Spectrum Spreader Module ........................................................................................ 215
B.2.13 Early Memory Output-Enable Feature ................................................................................. 218
Index
219
Rabbit 2000 Microprocessor User’s Manual
1. INTRODUCTION
Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in
small and medium-scale controllers. The first product is the Rabbit 2000 microprocessor.
The Rabbit 2000 designers have had years of experience using Z80, Z180 and HD64180
microprocessors in small controllers. The Rabbit shares a similar architecture and a high
degree of compatibility with these microprocessors, but it is a vast improvement.
The Rabbit has been designed in close cooperation with Z-World, Inc., a long-time manufacturer of low-cost single-board computers. Z-World and Rabbit Semiconductor products
are supported by an innovative C-language development system (Dynamic C).
The Rabbit 2000 is easy to use. Hardware and software interfaces are as uncluttered and
are as foolproof as possible. The Rabbit 2000 has outstanding computation speed for a
microprocessor with an 8-bit bus. This is because the Z80-derived instruction set is very
compact and the design of the memory interface allows maximum utilization of the memory bandwidth. The Rabbit races through instructions.
Traditional microprocessor hardware and software development is simplified for Rabbit
users. In-circuit emulators are not needed and will not be missed by the Rabbit developer.
Software development is accomplished by connecting a simple interface cable from a PC
serial port to the Rabbit-based target system.
1.1 Features and Specifications
• 100-pin PQFP package. Operating voltage 2.7 V to 5 V. Clock speed to 30 MHz. All
specifications are given for both industrial and commercial temperature and voltage
ranges. Rabbit microprocessors cost under $10 in moderate quantities.
• Industrial specifications are for a voltage variation of 10% and a temperature range
from –40°C to +85°C. Commercial specifications are for a voltage variation of 5% and
a temperature range from 0°C to 70°C.
• 1-megabyte code space allows C programs with up to 50,000+ lines of code. The
extended Z80-style instruction set is C-friendly, with short and fast instructions for
most common C operations.
• Four levels of interrupt priority make a fast interrupt response practical for critical
applications. The maximum time to the first instruction of an interrupt routine is about
1 µs at a clock speed of 25 MHz.
Chapter 1 Introduction
1
• Access to I/O devices is accomplished by using memory access instructions with an I/O
prefix. Access to I/O devices is thus faster and easier compared to processors with a
restricted I/O instruction set.
• The hardware design rules are simple. Up to six static memory chips (such as RAM and
flash EPROM) connect directly to the microprocessor with no glue logic. Even larger
amounts of memory can be handled by using parallel I/O lines as high-order address
lines. The Rabbit runs with no wait states at 24 MHz with a memory having an access
time of 70 ns. There are two clocks per memory access. Most I/O devices may be connected without glue logic.
The memory cycle is two clocks long. A clean memory and I/O cycle completely avoid
the possibility of tri-state fights. Peripheral I/O devices can usually be interfaced in a
glueless fashion using pins programmable as I/O chip selects, I/O read strobes or I/O
write strobe pins. A built-in clock doubler allows ½-frequency crystals to be used to
reduce radiated emissions.
• The Rabbit may be cold-booted via a serial port or the parallel access slave port. This
means that flash program memory may be soldered in unprogrammed, and can be
reprogrammed at any time without any assumption of an existing program or BIOS. A
Rabbit that is slaved to a master processor can operate entirely with volatile RAM,
depending on the master for a cold program boot.
• There are 40 parallel I/O lines (shared with serial ports). Some I/O lines are timer synchronized, which permits precisely timed edges and pulses to be generated under combined hardware and software control.
• There are four serial ports. All four serial ports can operate asynchronously in a variety
of customary operating modes; two of the ports can also be operated synchronously to
interface with serial I/O devices. The baud rates can be very high—1/32 the clock
speed for asynchronous operation, and 1/6 the clock speed externally or 1/4 the clock
speed internally in synchronous mode. In asynchronous mode, the Rabbit, like the
Z180, supports sending flagged bytes to mark the start of a message frame. The flagged
bytes have 9 data bits rather than 8 data bits; the extra bit is located after the first 8 bits,
where the stop bit is normally located, and marks the start of a message frame.
• A slave port allows the Rabbit to be used as an intelligent peripheral device slaved to a
master processor. The 8-bit slave port has six 8-bit registers, 3 for each direction of
communication. Independent strobes and interrupts are used to control the slave port in
both directions. Only a Rabbit and a RAM chip are needed to construct a complete
slave system if the clock and reset are shared with the master processor
• The built-in battery-backable time/date clock uses an external 32.768 kHz crystal. The
time/date clock can also be used to provide periodic interrupts every 488 µs. Typical
battery current consumption is 25 µA with the suggested battery circuit. An alternative
circuit provides means for substantially reducing this current.
• Numerous timers and counters (six all together) can be used to generate interrupts,
baud rate clocks, and timing for pulse generation.
2
Rabbit 2000 Microprocessor User’s Manual
• The built-in main clock oscillator uses an external crystal or more usually a ceramic
resonator. Typical resonator frequencies are in the range of 1.8 MHz to 29.5 MHz.
Since precision timing is available from the separate 32.768 kHz oscillator, a low-cost
ceramic resonator with ½ percent error is generally satisfactory. The clock can be doubled or divided by 8 to modify speed and power dynamically. The I/O clock, which
clocks the serial ports, is divided separately so as not to affect baud rates and timers
when the processor clock is divided or multiplied. For ultra low power operation, the
processor clock can be driven from the separate 32.768 kHz oscillator and the main
oscillator can be powered down. This allows the processor to operate at approximately
100 µA and still execute instructions at the rate of approximately 10,000 instructions
per second. This is a powerful alternative to sleep modes of operation used by other
processors. The current is approximately 65 mA at 25 MHz and 5 V. The current is proportional to voltage and clock speed—at 3.3 V and 7.68 MHz the current would be 13
mA, and at 1 MHz the current is reduced to less than 2 mA. Flash memory with automatic power down (from AMD) should be used for operation at the lowest power.
• The excellent floating-point performance is due to a tightly coded library and powerful
processing capability. For example, a 25 MHz clock takes 14 µs for a floating add,
13 µs for a multiply, and 40 µs for a square root. In comparison, a 386EX processor
running with an 8-bit bus at 25 MHz and using Borland C is about 10 times slower.
• There is a built-in watchdog timer.
• The standard 10-pin programming port eliminates the need for in-circuit emulators. A
very simple 10 pin connector can be used to download and debug software using Rabbit
Semiconductor’s Dynamic C and a simple connection to a PC serial port. The incremental cost of the programming port is extremely small.
Chapter 1 Introduction
3
D0D7
Data
Buffer
CLK
/WDTOUT
STATUS
SMODE1
SMODE0
/BUFEN
/IORD
/IOWR
/RESET
Figure 1-1 shows a block diagram of the Rabbit.
External Interface
CPU
A0A19
XTALB1
Main
Oscillator
Memory Chip
Interface
PA0PA7
Parallel
Port B
PB0PB7
Parallel
Port C
PC0PC7
Timer A
Parallel
Port D
PD0PD7
Timer B
Parallel
Port E
PE0PE7
Global
Control
(8 bits)
XTALA1
XTALA2
32.768 kHz
Oscillator
Serial Port A
Real-Time
Clock
Asynch Synch
Serial
Serial
Asynch Synch
Bootstrap Bootstrap
Asynchronous
Serial
Synchronous
Serial
Serial Port C
Periodic
Interrupts
INT0A, INT1A
INT0B, INT1B
TXA, RXA, CLKA,
ATXA, ARXA
Serial Port B
Watchdog
Timer
I0I7
/CS0, /CS1, /CS2
/OE0, /OE1
/WE0, /WE1
Parallel
Port A
DATA BUS
XTALB2
Memory
Management/
Control
Address
Buffer
Asynchronous
Serial
External I/O
Chip Interface
Serial Port D
External
Interrupts
Slave Port
Asynchronous
Serial
ADDRESS BUS
Slave Interface
Bootstrap Interface
TXB, RXB, CLKB,
ATXB, ARXB
TXC, RXC
TXD, RXD
SD0SD7,
SA0SA1,
/SCS, /SRD, /SWR,
/SLAVEATTN
(8 bits)
Figure 1-1. Block Diagram of the Rabbit Microprocessor
4
Rabbit 2000 Microprocessor User’s Manual
1.2 Summary of Rabbit Advantages
• The glueless architecture makes it is easy to design the hardware system.
• There are a lot of serial ports and they can communicate very fast.
• Precision pulse and edge generation is a standard feature.
• Interrupts can have multiple priorities.
• Processor speed and power consumption are under program control.
• The ultra low power mode can perform computations and execute logical tests since the
processor continues to execute, albeit at 32 kHz.
• The Rabbit may be used to create an intelligent peripheral or a slave processor. For
example, protocol stacks can be off loaded to a Rabbit slave. The master can be any
processor.
• The Rabbit can be cold booted so unprogrammed flash memory can be soldered in
place.
• You can write serious software, be it 1,000 or 50,000 lines of C code. The tools are
there and they are low in cost.
• If you know the Z80 or Z180, you know most of the Rabbit.
• A simple 10-pin programming interface replaces in-circuit emulators and PROM programmers.
• The battery backable time/date clock is included.
• The standard Rabbit chip is made to industrial temperature and voltage specifications.
Chapter 1 Introduction
5
6
Rabbit 2000 Microprocessor User’s Manual
2. RABBIT DESIGN FEATURES
The Rabbit is an evolutionary design. The instruction set and the register layout is that of
the Z80 and Z180. The instruction set has been augmented by a substantial number of new
instructions. Some obsolete or redundant Z180 instructions have been dropped to make
available efficient 1-byte opcodes for important new instructions. (see “Differences Rabbit
vs. Z80/Z180 Instructions” on page 187.) The advantage of this evolutionary approach is
that users familiar with the Z80 or Z180 can immediately understand the Rabbit. Existing
source code can be assembled or compiled for the Rabbit with minimal changes.
Changing technology has made some features of the Z80/Z180 family obsolete, and these
have been dropped. For example, the Rabbit has no special support for dynamic RAM but
it has extensive support for static memory. This is because the price of static memory has
decreased to the point that it has become the preferred choice for medium-scale embedded
systems. The Rabbit has no support for DMA (direct memory access) because most of the
uses for which DMA is traditionally used do not apply to embedded systems, or they can
be accomplished better in other ways, such as fast interrupt routines, external state
machines or slave processors.
Our experience in writing C compilers has revealed the shortcomings of the Z80 instruction set for executing the C language. The main problem is the lack of instructions for handling 16-bit words and for accessing data at a computed address, especially when the stack
contains that data. New instructions correct these problems.
Another problem with many 8-bit processors is their slow execution and a lack of numbercrunching ability. Good floating-point arithmetic is an important productivity feature in
smaller systems. It is easy to solve many programming problems if an adequate floatingpoint capability is available. The Rabbit’s improved instruction set provides fast floatingpoint and fast integer math capabilities.
The Rabbit supports four levels of interrupt priorities. This is an important feature that
allows the effective use of super fast interrupt routines for real-time tasks.
Chapter 2 Rabbit Design Features
7
2.1 The Rabbit 8-bit Processor vs. 16-bit and 32-bit Processors
The Rabbit is an 8-bit processor with an 8-bit external data bus and an 8-bit internal data
bus. Because the Rabbit makes the most of its external 8-bit bus and because it has a compact instruction set, its performance is as good as many 16-bit processors. Thus the Rabbit
can handle many 16-bit operations.
We hesitate to compare the Rabbit to 32-bit processors, but there are undoubtedly occasions where the user can use a Rabbit instead of a 32-bit processor and save a vast amount
of money. Many Rabbit instructions are 1 byte long. In contrast, the minimum instruction
length on most 32-bit RISC processors is 32 bits.
2.2 Overview of On-Chip Peripherals
The on-chip peripherals were chosen based on our experience as to what types of peripheral devices are most useful in small embedded systems. The major on-chip peripherals
are the serial ports, system clock, time/date oscillator, parallel I/O, slave port, and timers.
These are described below.
2.2.1 Serial Ports
There are four serial ports designated ports A, B, C, and D. All four serial ports can operate in an asynchronous mode up to the baud rate of the system clock divided by 32. The
asynchronous ports can handle 7 or 8 data bits. A 9th bit address scheme, where an additional bit is sent to mark the first byte of a message, is also supported. The software can
tell when the last byte of a message has finished transmitting from the output shift register
- correcting an important defect of the Z180. This is important for RS-485 communication
because the line driver cannot have the direction of transmission reversed until the last bit
has been sent. In many UARTs, including those on the Z180, it is difficult to generate an
interrupt after the last bit is sent. Parity bits and multiple stop bits are not supported
directly by the Rabbit, but can be accomplished with appropriate driving software.
Serial ports A and B can be operated alternately in the clocked serial mode. In this mode, a
clock line synchronously clocks the data in or out. Either device of the two devices communicating can supply the clock. When the Rabbit provides the clock, the baud rate can be
up to 1/4 of the system clock frequency, or more than 7,375,000 bps for a 29.5 MHz clock
speed.
Serial port A has special features. It can be used to cold boot the system after reset. Serial
port A is the normal port that is used for software development under Dynamic C.
2.2.2 System Clock
The main oscillator uses an external crystal with a frequency typically in the range from
1.8 MHz to 29.5 MHz. The processor clock is derived from the oscillator output by either
doubling the frequency, using the frequency directly, or dividing the frequency by 8. The
processor clock can also be driven by the 32.768 kHz oscillator for very low power operation, in which case the main oscillator can be shut down under software control.
8
Rabbit 2000 Microprocessor User’s Manual
Table 2-1 provides estimates of the operating power for selected clock speeds.
Table 2-1. Operating Power Estimates at Selected Clock Speeds
Clock Speed
(MHz)
Voltage
(V)
Current
Clock Speed
(MHz)
Voltage
(V)
Current
(mA)
Power
(mW)
(mA)
Power
(mW)
25.0
5.0
80
400
6.0
2.5
10
25
12.5
5.0
40
200
3.0
2.5
5
12
12.5
3.3
26
87
1.5
2.5
2.5
6
6.0
3.3
13
42
0.032
2.5
0.054
0.135
2.2.3 Time/Date Oscillator
The 32.768 kHz oscillator drives an external 32.768 kHz quartz crystal. The 32.768 kHz
clock is used to drive a battery-backable (there is a separate power pin) internal 48-bit
counter that serves as a real-time clock (RTC). The counter can be set and read by software and is intended for keeping the date and time. There are enough bits to keep the date
for more than 100 years. The 32.768 kHz oscillator is also used to drive the watchdog
timer and to generate the baud clock for serial port A during the cold boot sequence.
2.2.4 Parallel I/O
There are 40 parallel input/output lines divided among five 8-bit ports designated A
through E. Most of the port lines have alternate functions, such as serial data or chip select
strobes. Parallel ports D and E have the capability of timer-synchronized outputs. The output registers are cascaded.
Load Data
Port Output
Load Clock
Timer Clock
Figure 2-1. Cascaded Output Registers for Parallel Ports D and E
Stores to the port are loaded in the first-level register. That register in turn is transferred to
the output register on a selected timer signal. The timer signal can also cause an interrupt
that can be used to set up the next bit to be output on the next timer pulse. This feature can
be used to generate precisely controlled pulses whose edges are positioned with high accuracy in time. Applications include communications signaling, pulse width modulation and
driving stepper motors.
Chapter 2 Rabbit Design Features
9
2.2.5 Slave Port
The slave port is designed to allow the Rabbit to be a slave to another processor, which
could be another Rabbit. The port is shared with parallel port A and is a bidirectional data
port. The master can read any of three registers selected via two select lines that form the
register address and a read strobe that causes the register contents to be output by the port.
These same registers can be written as I/O registers by the Rabbit slave. Three additional
registers transmit data in the opposite direction. They are written by the master by means
of the two select lines and a write strobe.
Figure 2-2 shows the data paths in the slave port.
Rabbit
Master
Processor
Input Register
CPU
Output Registers
Control
Slave Interface Registers
Figure 2-2. Slave-Port Data Paths
The slave Rabbit can read the same registers as I/O registers. When incoming data bits are
written into one of the registers, status bits indicate which registers have been written, and
an optional interrupt can be programmed to take place when the write occurs. When the
slave writes to one of the registers carrying data bits outward, an attention line is enabled
so that the master can detect the data change and be interrupted if desired. One line tells
the master that the slave has read all the incoming data. Another line tells the master that
new outgoing data bits are available and have not yet been read by the master. The slave
port can be used to direct the master to perform tasks using a variety of communication
protocols over the slave port.
2.2.6 Timers
The Rabbit has several timer systems. The periodic interrupt is driven by the 32.768 kHz
oscillator divided by 16, giving an interrupt every 488 µs if enabled. This is intended to be
used as a general-purpose clock interrupt. Timer A consists of five 8-bit countdown and
reload registers that can be cascaded up to two levels deep. Each countdown register can
be set to divide by any number between 1 and 256. The output of four of the timers is used
to provide baud clocks for the serial ports. Any of these registers can also cause interrupts
and clock the timer-synchronized parallel output ports. Timer B consists of a 10-bit
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Rabbit 2000 Microprocessor User’s Manual
counter that can be read but not written. There are two 10-bit match registers and comparators. If the match register matches the counter, a pulse is output. Thus the timer can be
programmed to output a pulse at a predetermined count in the future. This pulse can be
used to clock the timer-synchronized parallel-port output registers as well as cause an
interrupt. Timer B is convenient for creating an event at a precise time in the future under
program control.
Figure 2-3 illustrates the Rabbit timers.
A1
A4
perclk/2
A5
A6
Timer A System
A7
10-bit counter
f/8
Timer B System
10 bits
compare
match reg
Timer_B1
next match
Timer_B2
match reg
next match
Figure 2-3. Rabbit Timers
Chapter 2 Rabbit Design Features
11
2.3 Design Standards
The same functionality can be accomplished in many ways using the Rabbit. By publishing design standards, or standard ways to accomplish common objectives, software and
hardware support become easier.
2.3.1 Programming Port
Rabbit Semiconductor publishes a specification for a standard programming port (see
Appendix A.1, “The Rabbit Programming Port,”) and provides a converter cable that may
be used to connect a PC serial port to the standard programming interface. The interface is
implemented using a 10-pin connector with two rows of pins on 2 mm centers. The port is
connected to Rabbit serial port A, to the startup mode pins on the Rabbit, to the Rabbit
reset pin, and to a programmable output pin that is used to signal the PC that attention is
needed. With proper precautions in design and software, it is possible to use serial port A
as both a programming port and as a user-defined serial port, although this will not be necessary in most cases.
Rabbit Semiconductor supports the use of the standard programming port and the standard
programming cable as a diagnostic and setup port to diagnosis problems or set up systems
in the field.
2.3.2 Standard BIOS
Rabbit Semiconductor provides a standard BIOS for the Rabbit. The BIOS is a software
program that manages startup and shutdown, and provides basic services for software running on the Rabbit.
2.4 Dynamic C Support for the Rabbit
Dynamic C is Rabbit Semiconductor’s interactive C language development system.
Dynamic C runs on a PC under Windows 95/98/Me/XP or Windows NT. It provides a
combined compiler, editor and debugger. The usual method for debugging a target system
based on the Rabbit is to implement the 10-pin programming connector that connects to
the PC serial port via a standard converter cable. Dynamic C libraries contain highly perfected software to control the Rabbit. These includes drivers, utility and math routines and
the debugging BIOS for Dynamic C.
In addition, the internationally-known real-time operating system, uC/OS-II, has been
ported to the Rabbit and is available starting with Dynamic C Premier v. 6.50.
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Rabbit 2000 Microprocessor User’s Manual
3. DETAILS ON RABBIT
MICROPROCESSOR FEATURES
3.1 Processor Registers
The Rabbit’s registers are nearly identical to those of the Z180 or the Z80. The figure
below shows the register layout. The XPC and IP registers are new. The EIR register is the
same as the Z80 I register, and is used to point to a table of interrupt vectors for the externally generated interrupts. The IIR register occupies the same logical position in the
instruction set as the Z80 R register, but its function is to point to an interrupt vector table
for internally generated interrupts.
A
F
H
L
D
E
B
C
IP
IX
8 / 16 bit
registers
IY
SP
IIR
PC
XPC
A'
F'
H'
L'
D'
E'
B'
C'
Alternate Registers
S Z x x
x V x C
F - flag register layout
S-sign, Z-zero, V-overflow, C-carry
Bits marked "x" are read/write.
EIR
A- 8-bit accumulator
F - flags register
HL- 16-bit accumulator
IX, IY - Index registers/alt accum’s
SP - stack pointer
PC- program counter
XPC - extension of program counter
IIR - internal interrupt register
EIR-external interrupt register
IP - interrupt priority register
Figure 3-1. Rabbit Registers
Chapter 3 Details on Rabbit Microprocessor Features
13
The Rabbit (and the Z80/Z180) processor has two accumulators—the A register serves as
an 8-bit accumulator for 8-bit operations such as ADD or and. The 16-bit register HL register serves as an accumulator for 16-bit operations such as ADD HL,DE, which adds the 16bit register DE to the 16-bit accumulator HL. For many operations IX or IY can substitute
for HL as accumulators.
The register marked F is the flags register or status register. It holds a number of flags that
provide information about the last operation performed. The flag register cannot be
accessed directly except by using the POP AF and PUSH AF instructions. Normally the
flags are tested by conditional jump instructions. The flags are set to mark the results of
arithmetic and logic operations according to rules that are specified for each instruction.
There are four unused read/write bits in the flag register that are available to the user via
the PUSH AF and POP AF instructions. These bits should be used with caution since newgeneration Rabbit processors could use these bits for new purposes.
The registers IX, IY and HL can also serve as index registers. They point to memory
addresses from which data bits are fetched or stored. Although the Rabbit can address a
megabyte or more of memory, the index registers can only directly address 64K of memory (except for certain extended addressing LDP instructions). The addressing range is
expanded by means of the memory mapping hardware (see “Memory Mapping” on
page 15) and by special instructions. For most embedded applications, 64K of data memory (as opposed to code memory) is sufficient. The Rabbit can efficiently handle a megabyte of code space.
The register SP points to the stack that is used for subroutine and interrupt linkage as well
as general-purpose storage.
A feature of the Rabbit (and the Z80/Z180) is the alternate register set. Two special
instructions swap the alternate registers with the regular registers. The instruction
EX AF,AF' exchanges the contents of AF with AF'. The instruction EXX exchanges HL,
DE, and BC with HL', DE', and BC'. Communication between the regular and alternate
register set in the original Z80 architecture was difficult because the exchange instructions
provided the only means of communication between the regular and alternate register sets.
The Rabbit has new instructions that greatly improve communication between the regular
and alternate register set. This effectively doubles the number of registers that are easily
available for the programmer’s use. It is not intended that the alternate register set be used
to provide a separate set of registers for an interrupt routine, and Dynamic C does not support this usage because it uses both registers sets freely.
The IP register is the interrupt priority register. It contains four 2-bit fields that hold a history of the processor’s interrupt priority. The Rabbit supports four levels of processor priority, something that exists only in a very restricted form in the Z80 or Z180.
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Rabbit 2000 Microprocessor User’s Manual
3.2 Memory Mapping
Except for a handful of special instructions (see Section 18.5, “16-bit Load and Store 20bit Address”), the Rabbit instructions directly address a 64K data memory space. This
means that the address fields in the instructions are 16 bits long and that the registers that
may be used as pointers to memory addresses (index registers (IX, IY), program counter
and stack pointer (SP)) are also 16 bits long.
Because Rabbit instructions use 16-bit addresses, the instructions are shorter and can execute much faster than, for example, 32-bit addresses. The executable code is also very
compact. Even though these 16-bit addresses are a valuable asset, they do create some
complications because a memory-mapping unit is needed in order to access a reasonable
amount of memory for modern C programs.
The Rabbit memory-mapping unit is similar to, but more powerful than, the Z180 memory-mapping unit. Figure 3-2 illustrates the relationship among the major components
related to addressing memory.
Processor
16
bits
Memory
Mapping
Unit
Memory
Interface
20
bits
Memory
Chips
20 bits plus control
Figure 3-2. Addressing Memory Components
The memory-mapping unit receives 16-bit addresses as input and outputs 20-bit addresses.
The processor (except for certain LDP instructions) sees only a 16-bit address space. That
is, it sees 65536 distinctly addressable bytes that its instructions can manipulate. Three
segment registers are used to map this 16-bit space into a 1-megabyte space. The 16-bit
space is divided into four separate zones. Each zone, except the first or root zone, has a
segment register that is added to the 16-bit address within the zone to create a 20-bit
address. The segment register has eight bits and those eight bits are added to the upper
four bits of the 16-bit address, creating a 20-bit address. Thus, each separate zone in the
16-bit memory becomes a window to a segment of memory in the 20-bit address space.
The relative size of the four segments in the 16-bit space is controlled by the SEGSIZE
register. This is an 8-bit register that contains two 4-bit registers. This controls the boundary between the first and the second segment and the boundary between the second and
the third segment. The location of the two movable segment boundaries is determined by a
4-bit value that specifies the upper four bits of the address where the boundary is located.
These relationships are illustrated in Figure 3-3.
Chapter 3 Details on Rabbit Microprocessor Features
15
10000
85
XPC register
80
STACKSEG register
79
DATASEG register
0E000
85
93000
0D000
80
8D000
10000
XPC
segment
E000
stack segment
D000
data segment
D
7
SEGSIZE
register
07000
79
80000
7000
root segment
07000
0000
16-bit
address space
00000
20-bit
address space
Figure 3-3. Example of Memory Mapping Operation
The names given to the segments in the figure are evocative of the common uses for each
segment. The root segment is mapped to the base of flash memory and contains the startup code as well as other code that may happen to be stored there. The data segment usage
varies depending on the overall strategy for setting up memory. It may be an extension of
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Rabbit 2000 Microprocessor User’s Manual
the root segment or it may contain data variables. The stack segment is normally 4K long
and it holds the system stack. The XPC segment is normally used to execute code that is
not stored in the root segment or the data segment. Special instructions support executing
code that is visible in the XPC segment.
The memory interface unit receives the 20-bit addresses generated by the memory-mapping unit. The memory interface unit conditionally modifies address lines A16, A18 and
A19. The other address lines of the 20-bit address are passed unconditionally. The memory interface unit provides control signals for external memory chips. These interface signals are chip selects (/CS0, /CS1, /CS2), output enables (/OE0, /OE1), and write enables
(/WE0, /WE1). These signals correspond to the normal control lines found on static memory chips (chip select or /CS, output enable or /OE, and write enable or /WE). In order to
generate these memory control signals, the 20-bit address space is divided into four quadrants of 256K each. A bank control register for each quadrant determines which of the
chip selects and which pair of output enables, and write enables (if any) is enabled when a
memory read or write to that quadrant takes place. For example, if a 512K x 8 flash memory is to be accessed in the first 512K of the 20-bit address space, then /CS0, /WE0, /OE0
could be enabled in both quadrants.
Figure 3-4 shows a memory interface unit.
Axxin—from processor
Axx—out from memory
control unit
Address lines not shown
are passed directly.
A19in
A19in
A19
A18in
A18
A18, A19 invertible
by quadrant
/CS0
A19in'
/CS1
A18in
/CS2
Optional A19 inversion
memory
control
Read/Write
Synchronization
memory
control
lines
/OE0
/WE0
/OE1
/WE1
Figure 3-4. Memory Interface Unit
Chapter 3 Details on Rabbit Microprocessor Features
17
3.2.1 Extended Code Space
A crucial element of the Rabbit memory mapping scheme is the ability to execute programs containing up to a megabyte of code in an efficient manner. This ability is absent in
a pure 16-bit address processor, and it is poorly supported by the Z180 through its memory
mapping unit. On paged processors, such as the 8086, this capability is provided by paging
the code space so that the code is stored in many separate pages. On the 8086 the page size
is 64K, so all the code within a given page is accessible using 16-bit addressing for jumps,
calls and returns. When paging is used, a separate register (CS on the 8086) is used to
determine where the active page currently resides in the total memory space. Special
instructions make it possible to jump, call or return from one page to another. These special instructions are called long calls, long jumps and long returns to distinguish them
from the same operations that only operate on 16-bit variables.
The Rabbit also uses a paging scheme to expand the code space beyond the reach of a 16bit address. The Rabbit paging scheme uses the concept of a sliding page, which is 8K
long. This is the XPC segment. The 8-bit XPC register serves as a page register to specify
the part of memory where the window points. When a program is executed in the XPC
segment, normal 16-bit jumps, calls and returns are used for most jumps within the window. Normal 16-bit jumps, calls and returns may also be used to access code in the other
three segments in the 16-bit address space. If a transfer of control to code outside the window is required, then a long jump, long call or long return is used. These instructions modify both the program counter (PC) and the XPC register, causing the XPC window to point
to a different part of memory where the target of the long jump, call or return is located.
The XPC segment is always 8K long. The granularity with which the XPC segment can be
positioned in memory is 4K. Because the window can be slid by one-half of its size, it is
possible to compile continuously without unused gaps in memory.
As the compiler generates code resident in the XPC window, the window is slid down by
4K when the code goes beyond F000. This is accomplished by a long jump that repositions the window 4K lower. This is illustrated by Figure 3-5. The compiler is not presented
with a sharp boundary at the end of the page because the window does not run out of space
when code passes F000 unless 4K more of code is added before the window is slid down.
All code compiled for the XPC window has a 24-bit address consisting of the 8-bit XPC
and the 16-bit address. Short jumps and calls can be used, provided that the source and target instructions both have the same XPC address. Generally this means that each instruction belongs to a window that is approximately 4K long and has a 16-bit address between
E000+n and F000+m, where n and m are on the order of a few dozen bytes, but can be up
to 4096 bytes in length. Since the window is limited to no more than 8K, the compiler is
unable to compile a single expression that requires more than 8K or so of code space. This
is not a practical consideration since expressions longer than a few hundred bytes are in
the nature of stunts rather than practical programs.
Program code can reside in the root segment or the XPC segment. Program code may also
be resident in the data segment. Code can be executed in the stack segment, but this is usually restricted to special situations. Code in the root, meaning any of the segments other
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Rabbit 2000 Microprocessor User’s Manual
than the XPC segment, can call other code in the root using short jumps and calls. Code in
the XPC segment can also call code in the root using short jumps and calls. However, a
long call must be used when code in the XPC segment is called. Functions located in the
root have an efficiency advantage because a long call and a long return require 32 clocks
to execute, but a short call and a short return require only 20 clocks to execute. The difference is small, but significant for short subroutines.
Compiler notices that
code has passed F000.
Compiler inserts
long jump in code.
10000
XPC segment
E000
D000
F000
Stack segment
Data segment
short
calls
returns
E000
XPC=N
PC=F000+K
Root segment
XPC=N+1
PC=E000+K+4
Illustration of sliding XPC window
Figure 3-5. Use of XPC Segment
3.2.2 Extending Data Memory
In the normal memory model, the data space must share a 64K space with root code, the
stack, and the XPC window. Typically, this leaves a potential data space of 40K or less.
The XPC requires 8K, the stack requires 4K, and most systems will require at least 12K of
root code. This amount of data space is more than sufficient for most embedded applications.
One approach to getting more data space is to place data in RAM or in flash memory that
is not mapped into the 64K space, and then access this data using function calls or in
assembly language using the LDP instructions that can access memory using a 20-bit
address. This is satisfactory for accessing simple data structures or buffers.
Another approach to extending data memory is to use the stack segment to access data,
placing the stack in the data segment so as to free up the stack segment. This approach
works well for a software system that uses data groupings that are self-contained and are
accessed one at a time rather than randomly between all the groupings. An example would
Chapter 3 Details on Rabbit Microprocessor Features
19
be the software structures associated with a TCP/IP communication protocol connection
where the same code accesses the data structures associated with each connection in a pattern determined by the traffic on each connection.
The advantage of this approach is that normal C data access techniques, such as 16-bit
pointers, may be used. The stack segment register has to be modified to bring the data
structure into view in the stack segment before operations are performed on a particular
data structure. Since the stack has to be moved into the data area, it is important that the
number of stacks required be kept to a minimum when using the stack segment to view
data. Of course, tasks that don’t need to see the data structures can have their stack located
in the stack segment. Another possibility is to have a data structure and a stack located
together in the stack segment, and to use a different stack segment for different tasks, each
task having its own data area and stack bound to it.
These approaches are shown in Figure 3-6 below.
Stack Segment used as
data window
Data Segment
used as data
window
Stacks in data
segment
Data
(RAM)
Root Segment
mapped to
RAM has both
root code and
data.
Root
Code
(flash)
Stack Segment used for
stack
Data
(RAM)
Root
Code
(RAM)
Using Stack Segment
for a Data Window
Using Data Segment for
a Data Window (Code must
be copied to RAM on startup.)
Figure 3-6. Schemes for Data Memory Windows
A third approach is to place the data and root code in RAM in the root segment, freeing the
data segment to be a window to extended memory. This requires copying the root code to
RAM at startup time. Copying root code to RAM is not necessarily that burdensome since
the amount of RAM required can be quite small, say 12K for example.
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Rabbit 2000 Microprocessor User’s Manual
The XPC segment at the top of the memory can also be used as a data segment by programs that are compiled into root memory. This is handy for small programs that need to
access a lot of data.
3.2.3 Practical Memory Considerations
The simplest Rabbit configurations have one flash memory chip interfaced using /CS0 and
one RAM memory chip interfaced using /CS1. Typical Rabbit-based systems use 256K of
flash and 128 K of RAM, but smaller or larger memories may be used.
Although the Rabbit can support code size approaching a megabyte, it is anticipated that
the great majority of applications will use less then 250K of code, equivalent to approximately 10,000–20,000 C statements. This reflects both the compact nature of Rabbit code
and the typical size of embedded applications.
Directly accessible C variables are limited to approximately 44K of memory, split
between data stored in flash and RAM. This will be more than adequate for many embedded applications. Some applications may require large data arrays or tables that will
require additional data memory. For this purpose Dynamic C supports a type of extended
data memory that allows the use of additional data memory, even extending far beyond a
megabyte.
Requirements for stack memory depend on the type of application and particularly
whether preemptive multitasking is used. If preemptive multitasking is used, then each
task requires its own stack. Since the stack has its own segment in 16-bit address space, it
is easy to use available RAM memory to support a large number of stacks. When a preemptive change of context takes place, the STACKSEG register can be changed to map
the stack segment to the portion of RAM memory that contains the stack associated with
the new task that is to be run. Normally the stack segment is 4K, which is typically large
enough to provide space for several (typically four) stacks. It is possible to enlarge the
stack segment if stacks larger than 4K are needed. If only one stack is needed, then it is
possible to eliminate the stack segment entirely and place the single stack in the data segment. This option is attractive for systems with only 32K of RAM that don’t need multiple
stacks.
Chapter 3 Details on Rabbit Microprocessor Features
21
3.3 Instruction Set Outline
“Load Immediate Data To a Register” on page 23
“Load or Store Data from or to a Constant Address” on page 23
“Load or Store Data Using an Index Register” on page 24
“Register to Register Move” on page 25
“Register Exchanges” on page 25
“Push and Pop Instructions” on page 26
“16-bit Arithmetic and Logical Ops” on page 26
“Input/Output Instructions” on page 29—these include a fix for a bug that manifests itself
if an I/O instruction (prefix IOI or IOE) is followed by one of 12 single-byte op codes that
use HL as an index register.
In the discussion that follows, we give a few example instructions in each general category
and contrast the Z80/ Z180 with the Rabbit. For a detailed description of every instruction,
see Chapter 18, “Rabbit Instructions,”
The Rabbit executes instructions in fewer clocks then the Z80 or Z180. The Z180 usually
requires a minimum of four clocks for 1-byte opcodes or three clocks for each byte for
multi-byte op codes. In addition, three clocks are required for each data byte read or written. Many instructions in the Z180 require a substantial number of additional clocks. The
Rabbit usually requires two clocks for each byte of the op code and for each data byte
read. Three clocks are needed for each data byte written. One additional clock is required
if a memory address needs to be computed or an index register is used for addressing.
Only a few instructions don’t follow this pattern. An example is mul, a 16 x 16 bit signed
two’s complement multiply. mul is a 1-byte op code, but requires 12 clocks to execute.
Compared to the Z180, not only does the Rabbit require fewer clocks, but in a typical situation it has a higher clock speed and its instructions are more powerful.
The most important instruction set improvements in the Rabbit over the Z180 are in the
following areas.
• Fetching and storing data, especially 16-bit words, relative to the stack pointer or the
index registers IX, IY, and HL.
• 16-bit arithmetic and logical operations, including 16-bit and’s, or’s, shifts and 16-bit
multiply.
• Communication between the regular and alternate registers and between the index registers and the regular registers is greatly facilitated by new instructions. In the Z180 the
alternate register set is difficult to use, while in the Rabbit it is well integrated with the
regular register set.
• Long calls, long returns and long jumps facilitate the use of 1M of code space. This
removes the need in the Z180 to utilize inefficient memory banking schemes for larger
programs that exceed 64K of code.
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Rabbit 2000 Microprocessor User’s Manual
• Input/output instructions are now accomplished by normal memory access instructions
prefixed by an op code byte to indicate access to an I/O space. There are two I/O
spaces, internal peripherals and external I/O devices.
Some Z80 and Z180 instructions have been deleted and are not supported by the Rabbit
(see Chapter 19, “Differences Rabbit vs. Z80/Z180 Instructions,”). Most of the deleted
instructions are obsolete or are little-used instructions that can be emulated by several
Rabbit instructions. It was necessary to remove some instructions to free up 1-byte op
codes needed to implement new instructions efficiently. The instructions were not reimplemented as 2-byte op codes so as not to waste on-chip resources on unimportant
instructions. Except for the instruction EX (SP),HL, the original Z180 binary encoding of
op codes is retained for all Z180 instructions that are retained.
3.3.1 Load Immediate Data To a Register
A constant that follows the op code in the instruction stream can generally be loaded to
any register, except PC, AF, IP and F. (Load to the PC is a jump instruction.) This includes
the alternate registers on the Rabbit, but not on the Z180. Some example instructions
appear below.
LD
LD
LD
LD
LD
LD
A,3
HL,456
BC',3567
H',0x4A
IX,1234
C,54
; not possible on Z180
; not possible on Z180
Byte loads require four clocks, word loads require six clocks. Loads to IX, IY or the alternate registers generally require two extra clocks because the op code has a 1-byte prefix.
3.3.2 Load or Store Data from or to a Constant Address
LD
LD
LD
LD
LD
LD
A,(mn)
A',(mn)
(mn),A
HL,(mn)
HL',(mn)
(mn),HL
; loads 8 bits from address mn
; not possible on Z180
; load 16 bits from the address specified by mn
; to alternate register, not possible Z180
Similar 16-bit loads and stores exist for DE, BC, SP, IX and IY.
It is possible to load data to the alternate registers, but it is not possible to store the data in
the alternate register directly to memory.
LD A',(mn)
; allowed
** LD (mn),D' ; **** not a legal instruction!
** LD (mn),DE' ; **** not a legal instruction!
Chapter 3 Details on Rabbit Microprocessor Features
23
3.3.3 Load or Store Data Using an Index Register
An index register is a 16-bit register, usually IX, IY, SP or HL, that is used for the address
of a byte or word to be fetched from or stored to memory. Sometimes an 8-bit offset is
added to the address either as a signed or unsigned number. The 8-bit offset is a byte in the
instruction word. BC and DE can serve as index registers only for the special cases below.
LD
LD
LD
LD
LD
LD
A,(BC)
A',(BC)
(BC),A
A,(DE)
A',(DE)
(DE),A
Other 8-bit loads and stores are the following.
LD r,(HL)
LD g,(HL)
LD (HL),r
**
LD
LD
LD
LD
LD (HL),g
r,(IX+d)
g,(IX+d)
(IX+d),r
(IY+d),r
; r is any of 7 registers A, B, C, D, E, H, L
; same but alternate register destination
; r is any of the 7 registers above
; or an immediate data byte
;**** not a legal instruction!
; r is any of 7 registers, d is -128 to +127 offset
; same but alternate destination
; r is any of 7 registers or an immediate data byte
; IX or IY can have offset d
The following are 16-bit indexed loads and stores. None of these instructions exists on the
Z180 or Z80. The only source for a store is HL. The only destination for a load is HL or HL'.
LD HL,(SP+d)
LD (SP+d),HL
LD HL,(HL+d)
LD HL',(HL+d)
LD (HL+d),HL
LD (IX+d),HL
LD HL,(IX+d)
LD HL',(IX+d)
LD (IY+d),HL
;
;
;
;
;
;
d is an offset from 0 to 255.
16-bits are fetched to HL or HL'
corresponding store
d is an offset from -128 to +127,
uses original HL value for addressing
l=(HL+d), h=(HL+d+1)
; store HL at address pointed to
; by IX plus -128 to +127 offset
; store HL at address pointed to
; by IY plus -128 to +127 offset
LD HL,(IY+d)
LD HL',(IY+d)
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Rabbit 2000 Microprocessor User’s Manual
3.3.4 Register to Register Move
Any of the 8-bit registers, A, B, C, D, E, H, and L, can be moved to any other 8-bit register, for example:
LD A,c
LD d,b
LD e,l
The alternate 8-bit registers can be a destination, for example:
LD a',c
LD d',b
These instructions are unique to the Rabbit and require 2 bytes and four clocks because of
the required prefix byte. Instructions such as LD A,d' or LD d',e' are not allowed.
Several 16-bit register-to-register move instructions are available. Except as noted, these
instructions all require 2 bytes and four clocks. The instructions are listed below.
LD
LD
LD
LD
LD
LD
LD
LD
LD
dd',BC
dd',DE
IX,HL
IY,HL
HL,IY
HL,IX
SP,HL
SP,IX
SP,IY
; where dd' is any of HL', DE', BC' (2 bytes, 4 clocks)
; 1-byte, 2 clocks
Other 16-bit register moves can be constructed by using 2-byte moves.
3.3.5 Register Exchanges
Exchange instructions are very powerful because two (or more) moves are accomplished
with one instruction. The following register exchange instructions are implemented.
EX af,af'
EXX
EX DE,HL
; exchange af with af'
; exchange HL, DE, BC with HL', DE', BC'
; exchange DE and HL
The following instructions are unique to the Rabbit.
EX DE',HL
EX DE, HL'
EX DE', HL'
; 1 byte, 2 clocks
; 2 bytes, 4 clocks
; 2 bytes, 4 clocks
The following special instructions (Rabbit and Z180/Z80) exchange the 16-bit word on
the top of the stack with the HL, the IX, or the IY register. These three instructions are
each 2 bytes and 15 clocks.
EX (SP),HL
EX (SP),IX
EX (SP),IY
Chapter 3 Details on Rabbit Microprocessor Features
25
3.3.6 Push and Pop Instructions
There are instructions to push and pop the 16-bit registers AF, HL, DC, BC, IX, and IY.
The registers AF', HL', DE', and BC' can be popped. Popping the alternate registers is
exclusive to the Rabbit, and is not allowed on the Z80 / Z180.
Examples
POP HL
PUSH BC
PUSH IX
PUSH af
POP DE
POP DE'
POP HL'
3.3.7 16-bit Arithmetic and Logical Ops
The HL register is the primary 16-bit accumulator. IX and IY can serve as alternate accumulators for many 16-bit operations. The Z180/Z80 has a weak set of 16-bit operations,
and as a practical matter the programmer has to resort to combinations of 8-bit operations
in order to perform many 16-bit operations. The Rabbit has many new op codes for 16-bit
operations, removing some of this weakness.
The basic Z80/Z180 16-bit arithmetic instructions are
ADD
ADC
SBC
INC
HL,ww
HL,ww
HL,ww
ww
;
;
;
;
where ww is HL, DE, BC, SP
ADD and ADD carry
sub and sub carry
increment the register (without affecting flags)
In the above op codes, IX or IY can be substituted for HL. The ADD and ADC instructions
can be used to left-shift HL with the carry. An alternate destination prefix (ALTD) may be
used on the above instructions. This causes the result and its flags to be stored in the corresponding alternate register. If the ALTD flag is used when IX or IY is the destination register, then only the flags are stored in the alternate flag register.
The following new instructions have been added for the Rabbit.
;Shifts
RR HL
RR
RL
RR
RR
DE
DE
IX
IY
;
;
;
;
;
;
;
rotate HL right with carry, 1 byte, 2 clocks
note use ADC HL,HL for left rotate, or add HL,HL if
no carry in is needed.
1 byte, 2 clocks
rotate DE left with carry, 1-byte, 2 clocks
rotate IX right with carry, 2 bytes, 4 clocks
rotate IY right with carry
;Logical Operations
AND HL,DE ; 1 byte, 2 clocks
AND IX,DE ; 2 bytes, 4 clocks
AND IY,DE
OR HL,DE
; 1 byte, 2 clocks
OR IX,DE
; 2 bytes, 4 clocks
OR IY,DE
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Rabbit 2000 Microprocessor User’s Manual
The BOOL instruction is a special instruction designed to help test the HL register. BOOL
sets HL to the value 1 if HL is non zero, otherwise, if HL is zero its value is not changed.
The flags are set according to the result. BOOL can also operate on IX and IY.
BOOL HL
BOOL IX
BOOL IY
ALTD BOOL HL
ALTD BOOL IY
; set HL to 1 if non- zero, set flags to match HL
; set HL' an f' according to HL
; modify IY and set f' with flags of result
The SBC instruction can be used in conjunction with the BOOL instruction for performing
comparisions. The SBC instruction subtracts one register from another and also subtracts
the carry bit. The carry out is inverted compared to the carry that would be expected if the
number subtracted was negated and added. The following examples illustrate the use of
the SBC and BOOL instructions.
; Test if HL>=DE - HL and DE unsigned numbers 0-65535
OR a
; clear carry
SBC HL,DE ; if C==0 then HL>=DE else if C==1 then HL=DE where HL and DE are signed numbers
; invert sign bits on both
ADD HL,HL ; shift left
CCF
; invert carry
RR HL
; rotate right
RL DE
CCF
RR DE
; invert DE sign
SBC HL,DE ; no carry if HL>=DE
; generate boolean variable true if HL>=DE
SBC HL,HL ; zero if no carry else -1
INC HL
; 1 if no carry, else zero
BOOL
; use this instruction to set flags if needed
Chapter 3 Details on Rabbit Microprocessor Features
27
The SBC instruction can also be used to perform a sign extension.
; extend sign of l to HL
LD A,l
rla
SBC A,a
LD h,a
; sign to carry
; a is all 1’s if sign negative
; sign extended
The multiply instruction performs a signed multiply that generates a 32-bit signed result.
MUL
; signed multiply of BC and DE,
; result in HL:BC - 1 byte, 12 clocks
If a 16-bit by 16-bit multiply with a 16-bit result is performed, then only the low part of
the 32-bit result (BC) is used. This (counter intuitively) is the correct answer whether the
terms are signed or unsigned integers. The following method can be used to perform a 16
x 16 bit multiply of two unsigned integers and get an unsigned 32-bit result. This uses the
fact that if a negative number is multiplied the sign causes the other multiplier to be subtracted from the product. The method shown below adds double the number subtracted so
that the effect is reversed and the sign bit is treated as a positive bit that causes an addition.
LD BC,n1
LD HL',BC
LD DE,n2
LD A,b
MUL
OR a
JR p,x1
ADD HL,DE
x1:
RL DE
JR nc,x2
; save BC in HL'
;
;
;
;
;
save sign of BC
form product in HL:BC
test sign of BC multiplier
if plus continue
adjust for negative sign in BC
; test sign of DE
; if not negative
; subtract other multiplier from HL
EX DE,HL'
ADD HL,DE
x2:
; final unsigned 32 bit result in HL:BC
This method can be modified to multiply a signed number by an unsigned number. In that
case only the unsigned number has to be tested to see if the sign is on, and in that case the
signed number is added to the upper part of the product.
The multiply instruction can also be used to perform left or right shifts. A left shift of n
positions can be accomplished by multiplying by the unsigned number 2^^n. This works
for n # 15, and it doesn’t matter if the numbers are signed or unsigned. In order to do a
right shift by n (0 < n < 16), the number should be multiplied by the unsigned number
2^^(16 – n), and the upper part of the product taken. If the number is signed, then a signed
by unsigned multiply must be performed. If the number is unsigned or is to be treated as
unsigned for a logical right shift, then an unsigned by unsigned multiply must be performed. The problem can be simplified by excluding the case where the multiplier is
2^^15.
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Rabbit 2000 Microprocessor User’s Manual
3.3.8 Input/Output Instructions
The Rabbit uses an entirely different scheme for accessing input/output devices. Any
memory access instruction may be prefixed by one of two prefixes, one for internal I/O
space and one for external I/O space. When so prefixed, the memory instruction is turned
into an I/O instruction that accesses that I/O space at the I/O address specified by the 16bit memory address used. For example
IOI LD A,(0x85)
LD IY,0x4000
IOE LD HL,(IY+5)
; loads A register with contents
; of internal I/O register at location 0x85.
; get word from external I/O location 0x4005
By using the prefix approach, all the 16-bit memory access instructions are available for
reading and writing I/O locations. The memory mapping is bypassed when I/O operations
are executed.
I/O writes to the internal I/O registers require only two clocks, rather than the minimum of
three clocks required for writes to memory or external I/O devices.
In certain conditions where an I/O operation is followed by a special one-byte instruction,
a bug in the original Rabbit 2000 chip causes an I/O access to take place instead of a memory access operation. The problem was corrected in revisions A–C of the Rabbit 2000.
(Refer to Appendix B for further information to determine which version of the Rabbit
2000 chip you are using.)
The bug is manifested if an I/O instruction (prefix IOI or IOE) is followed by one of 12
single-byte op codes that use HL as an index register. The 12 instructions are:
ADC A,(HL)
ADD A, (HL)
AND (HL)
CP (HL)
OR (HL)
SBC A,(HL)
SUB (HL)
XOR (HL)
DEC (HL)
INC (HL)
LD r,(HL)
LD (HL),r
where r, an 8-byte register, is one of A, B, C, D, E, H, or L.
The only combination that is very likely to occur in user written assembly language programs is an I/O instruction followed by LD (HL),r.
The nature of the failure is that the memory address translation does not take place and so
the appropriate memory chip select will not be enabled for the second instruction. In the
case of external I/O operations where the I/O strobes on Port E may be enabled, an I/O
“chip select” (I/O strobe) will take place instead of a memory chip select. If one of the
above instructions follows an internal I/O operation and the memory access takes place in
the base region where address translation does not take place, the memory operation will
take place properly because the appropriate memory chip select is enabled for internal I/O
operations.
Chapter 3 Details on Rabbit Microprocessor Features
29
The bug may be easily avoided by placing a NOP between the I/O instruction and a following instruction from the above list.
Rabbit users are unlikely to encounter this problem because the sequence of instructions
that exhibit the bug is never generated by the Dynamic C compiler or in any of the standard libraries.
Beginning with the 6.57 release, the Dynamic C compiler and assembler will correct for
this anomaly by inserting NOPs where necessary in generated code.
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Rabbit 2000 Microprocessor User’s Manual
3.4 How to Do It in Assembly Language—Tips and Tricks
3.4.1 Zero HL in 4 Clocks
BOOL HL
RR HL
; 2 clocks, clears carry, HL is 1 or 0
; 2 clocks, 4 total - get rid of possible 1
This sequence requires four clocks compared to six clocks for LD HL,0.
3.4.2 Exchanges Not Directly Implemented
HLHL' - eight clocks
EX DE',HL
EX DE',HL'
EX DE',HL
; 2 clocks
; 4 clocks
; 2 clocks, 8 total
DEDE' - six clocks
EX DE',HL
EX DE,HL
EX DE',HL
; 2 clocks
; 2 clocks
; 2 clocks, 6 total
BCBC' - 12 clocks
EX DE',HL
EX DE,HL'
EX DE,HL
EXX
EX DE,HL
;
;
;
;
;
2 clocks
4
2
2
2
Move between IX, IY and DE, DE'
IX/IY->DE / DE->IX/IY
;IX, IX --> DE
EX DE,HL
LD HL,IX/IY / LD IX/IY,HL
EX DE,HL
; 8 clocks total
; DE --> IX/ IY
EX DE,HL
LD IX/IY,HL
EX DE,HL
; 8 clocks total
3.4.3 Manipulation of Boolean Variables
Logical operations involving HL when HL is a logical variable with a value of 1 or 0—
this is important for the C language where the least bit of a 16-bit integer is used to represent a logical result
Logical not operator—invert bit 0 of HL in four clocks (also works for IX, IY in eight
clocks)
DEC HL
BOOL HL
; 1 goes to zero, zero goes to -1
; -1 to 1, zero to zero. 4 clocks total
Logical xor operator—xor HL,DE when HL/DE are 1 or 0.
ADD HL,DE
RES 1,l
; 6 clocks total, clear bit 1 result of
Chapter 3 Details on Rabbit Microprocessor Features
if 1+1=2
31
3.4.4 Comparisons of Integers
Unsigned integers may be compared by testing the zero and carry flags after a subtract
operation. The zero flag is set if the numbers are equal. With the SBC instruction the carry
cleared is set if the number subtracted is less than or equal to the number it is subtracted
from. 8-bit unsigned integers span the range 0–255. 16-bit unsigned integers span the
range 0–65535.
OR a
SBC HL,DE
A>=B
AB
AB
SBC HL,HL
; HL-HL-C - result -1 if carry set, else zero
BOOL HL
; 14 total clocks - true if HL>B
; HL>=B
B is constant not zero
LD DE,(65536-B)
ADD HL,DE
SBC HL,HL
BOOL HL
; 14 clocks
; HL>=B
LD HL,1
and B is zero
; 6 clocks
; HL 4.75 V since the instantaneous clock frequency bursts to 38.5 MHz when the spectrum spreader and clock asymmetry together produce maximum shortening of a clock cycle.
Appendix B Rabbit 2000 Revisions
217
B.2.13 Early Memory Output-Enable Feature
The early I/O enable feature was added to the Rabbit 2000C revision to relax the tight timing requirements for memory access when using the clock spectrum spreader. The early
I/O option extends the output enable time for the /OEx strobes and the write enable time
for the /WEx strobes by a half clock cycle. The Memory Timing Control Register
(MTCR) enables the extended timing for the memory output enable and write enable
strobes.
Table B-12. Memory Timing Control Register
Memory Timing Control Register
Bit(s)
Value
(MTCR)
(Address = 0x19)
Description
7:4
xxxx
These bits are reserved and should not be used.
3
0
Normal timing for /OE1B (rising edge to rising edge, one clock minimum).
1
Extended timing for /OE1B (one-half clock earlier than normal).
0
Normal timing for /OE0B (rising edge to rising edge, one clock minimum).
1
Extended timing for /OE0B (one-half clock earlier than normal).
0
Normal timing for /WE1B (rising edge to falling edge, one and one-half clocks
minimum).
1
Extended timing for /WE1B (falling edge to falling edge, two clocks
minimum).
0
Normal timing for /WE0B (rising edge to falling edge, one and one-half clocks
minimum).
1
Extended timing for /WE0B (falling edge to falling edge, two clocks
minimum).
2
1
0
Memory read and write timing are discussed further in Chapter 15, “AC Timing Specifications.”
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Rabbit 2000 Microprocessor User’s Manual
INDEX
A
assembly language
instructions ...... 31, 32, 33, 34
reading/writing to I/O registers .............................. 170
B
battery-backup circuit ......... 209
bootstrap operation ......... 88, 89
C
chip selects .......................... 213
clocks ............................ 72, 149
32.768 kHz ........................ 72
32.768 kHz oscillator ...... 149
clock doubler ............... 74, 75
distribution ........................ 72
low-power 32.768 kHz oscillator ............................. 209
low-power design ............ 150
main clock ................. 78, 149
oscillator circuits ............. 149
power consumption ........... 76
spectrum spreader ... 150, 215
timer and clock use ......... 172
cold boot ............................... 45
comparison Rabbit 2000 vs.
Z80/Z180 .................... 187
compiler ................................ 97
crystal frequencies .............. 199
D
DDCB/FDCB instruction ... 214
design features ........................ 7
BIOS ................................. 12
cold boot ........................... 45
instruction set ...................... 7
interrupt priorities ............... 7
memory support .................. 7
parallel I/O .......................... 9
programming port ............. 12
Index
serial ports ........................... 8
slave port ..................... 10, 46
system clock ........................ 8
time/date clock .................... 9
timed output pulses ........... 41
timers ................................ 10
Dynamic C ........................ 1, 12
BIOS ............................... 165
library functions .............. 170
periodic interrupts ........... 166
power consumption ......... 169
virtual drivers .................. 166
watchdog ......................... 166
E
extended memory ................. 19
data memory windows ...... 20
practical considerations ..... 21
external bus
read and write timing ........ 58
external interrupts
control registers ................. 86
G
generating pulses .................. 42
I
instructions .................... 22, 175
alphabetic order ............... 189
arithmetic and logical ops . 26
I/O instructions ................. 29
load to constant address .... 23
load to register .................. 23
load using index register ... 24
push and pop ..................... 26
register exchanges ............. 25
register-to-register move ... 25
interrupts ................... 35, 39, 84
Dynamic C ...................... 166
external interrupts ..... 86, 213
generating with Serial Port A
..................................... 131
interrupt latency ................ 41
interrupt service vector
addresses ....................... 84
interrupt vectors ................ 87
multiple interrupts ............. 37
priorities ...................... 35, 85
privileged instructions and
semaphores ................... 37
semaphores ....................... 38
serial port ........................ 123
updating registers ............ 171
IOI/IOE prefix .................... 213
L
LDIR/LDDR Instruction/Data
split ............................. 214
low-power design ............... 150
M
memory
A16, A19 inversions (/CS1
enable) .......................... 95
access time ...... 151, 154, 155
allocation of extended code
and data space ............... 96
compiler operation ............ 97
early output enable .......... 218
I and D space .................... 95
I/O access time (no extra wait
state) ........................... 159
I/O access time (one extra wait
state) ........................... 160
I/O read time delays ........ 158
I/O read/write times ........ 154
I/O write time delays ...... 158
Iand D space ................... 211
parameters ....................... 161
read time delays .............. 156
write time delays ............. 156
memory interface ............ 17, 93
memory mapping .................. 91
memory mapping unit 15, 16, 91
Modbus ............................... 135
219
O
open-drain outputs .................44
operating frequency vs. temperature ..............................153
operating frequency vs. voltage ...............................153
operating power estimates .......9
oscillator ..............................149
main oscillator .................149
oscillators
32.768 kHz ................72, 149
main clock .................72, 149
output pins
alternate assignment ..........77
P
parallel ports ..........................99
Parallel Port A .................100
Parallel Port B .................101
Parallel Port C .................102
Parallel Port D .................103
open-drain outputs .........44
Parallel Port E ..................106
pin descriptions
alternate functions .............59
pinout
PQFP package ...................49
ports
Rabbit slave port ..............137
slave port lines .................142
slave port registers ...........143
power .......................................9
power consumption .......76, 162
Dynamic C .......................169
power management .............169
power usage, standby mode 150
PQFP package
LAND pattern ....................51
mechanical dimensions .....50
pinout .................................49
programming port ...............197
alternate programming port
......................................198
use as diagnostic port ......198
PWM output ....................42, 43
R
Rabbit 2000
block diagram ......................4
comparison with Z80/Z180
......................................187
crystal frequencies ...........199
design features .....................7
220
features ................................1
list of advantages .................5
on-chip peripherals ..............8
programing port ...............197
revision history ........201, 203
specifications ...............1, 2, 3
Rabbit 3000
revision history ................201
Rabbit Semiconductor
history ..................................1
registers .................................13
accumulators .....................14
alternate registers ..............14
default values ....................65
GCDR ................................74
GCM0R ...........................216
GCM1R ...........................216
GCMxR ...........................204
GCPU ......................204, 205
GCSR ................................73
GOCR ................................77
GREV ..............204, 205, 206
I/O bank control ..............109
I/O registers .......................65
IBxCR .............................109
index registers ...................14
interrupt priority register ...14
interrupts ...........................35
MB0CR ...................204, 213
MBxCR .............................94
memory bank control ........94
memory mapping segments 92
MMIDR ...........................212
MTCR .....................204, 218
PADR ..............................100
PBDR ..............................101
PCDR ..............................102
PCFR ...............................102
PDBxR ............................103
PDCR ......................103, 105
PDDCR ...........................103
PDDDR ...........................103
PDDR ..............................103
PDFR ...............................103
PEBxR .............................107
PECR .......................107, 108
PEDDR ............................107
PEDR ...............................107
PEFR ...............................107
processor identification .....71
GCPU ............................71
GREV ............................71
reading/writing to I/O registers ...............................170
revision-level ID ..............205
RTCCR ..............................79
RTCxR ..............................78
serial port control registers 122
serial port status registers 121
serial ports .......................121
SxAR ...........................121
SxCR ...........................121
SxDR ...........................121
SxLR ............................121
SxSR ............................121
shadow registers ..............171
SPCR ...............100, 143, 144
SPDxR .............................143
SPSR .......................143, 145
stack pointer ......................14
status register .....................14
SxCR ...............................208
SxLR .......................204, 207
TACR ......................113, 114
TACSR ............................113
TATxR ............................113
TBCR ..............................116
TBCSR ............................116
TBLxR .............................116
TBMxR ...........................116
Timer A ...........................113
WDTCR ............................80
WDTTR .............................81
XPC register ................18, 19
reset .................................82, 83
revision history ............201, 203
chip selects ......................203
clock spectrum spreader ..203
clocked serial command ..203
DDCB/FDCB instructions 203
early I/O enable ...............203
external interrupts ............203
I and D space ...................203
ID registers for version ....203
improved battery backup .203
IOI/IOE prefix .................203
LDIR/LDDR Instruction/Data
split ..............................203
Long Stop Register ..........203
RoHS ...............................202
wait states ........................203
S
serial ports .......................8, 119
9th bit protocols ...............134
asynchronous serial port ..207
baud rates ........................119
Rabbit 2000 Microprocessor User’s Manual
clocked serial ports
(Ports A–B) ................. 125
clocked serial timing ....... 128
controlling RS-485 driver and
receiver ....................... 131
data and parity bits .......... 119
data framing/Modbus ...... 135
extra stop bits, parity ....... 132
generating periodic interrupts ............................ 131
interrupt service routines 129
interrupts ......................... 123
master/slave protocol ...... 135
receive serial data timing 124
registers ........................... 120
software recommendations 129
synchronous serial port ... 208
transmit serial data timing 124
transmitting and detecting
breaks .......................... 131
transmitting dummy characters .............................. 131
Index
slave port ....................... 46, 137
applications ..................... 145
hardware design .............. 143
messaging protocol ......... 146
protocols .......................... 145
R/W cycles ...................... 139
registers ........................... 143
typical connections ......... 142
specifications
DC characteristics ............. 61
3.3 V .............................. 63
5.0 V .............................. 62
I/O buffer sinking and sourcing limits ....................... 64
memory access times ...... 151
power consumption ......... 162
spectrum spreader ....... 150, 215
system clock ........................... 8
T
timers .................................. 111
Timer A ........................... 113
Timer B ........................... 115
W
watchdog timer ..................... 80
X
XPC register ......................... 18
221
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