ISD5216
8 to 16 minutes
voice record/playback device
with integrated codec
-1-
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
1. GENERAL DESCRIPTION
The ChipCorder ISD5216 is an 8 to 16 minute Voice and Data Record and Playback system with
integrated Voice band CODEC. The device works on a single 2.7V to 3.3V supply, and has fully
integrated system functions, including: AGC, microphone preamplifier, speaker driver, memory and
CODEC. The CODEC meets the PCM conformance specification of the G.714 recommendation. Its μLaw and A-Law compander meets the specification of the ITU-T G.711 recommendation.
2. FEATURES
•
Single Supply 2.7 to 3.3 Volt operation
•
Voice and digital data record and playback system on a single chip
•
Industry-leading sound quality
•
Low voltage operation
•
Message management
•
Fully integrated system functions
•
Flexible architecture
•
Nonvolatile message storage
•
Configurable ChipCorder sampling rates of 4 kHz, 5.3kHz, 6.4 kHz and 8kHz
•
8, 10, 12 and 16 minutes duration
•
External or internal Voice recorder clock
• I2C
serial interface (400kHz)
•
Configurable analog paths
•
2.2V Microphone Bias Pin
•
100 year message retention (typical)
100K analog record cycles (typical)
10K digital record cycles (typical)
Full-duplex (not in I2S mode) single channel speech CODEC with:
o
External 13.824 MHz, 27.648 MHz, 20.48 MHz or 40.96 MHz master clock
2
o I S and PCM digital audio interface ports
o Serial transfer data rate from 64 to 3072 Kbps
o Short and Long frame sync formats
o 2s complement and signed magnitude data format
o Complete μ-Law and A-Law companding
o Linear 14 bit ΔΣ PCM CODEC-filter for A/D and D/A converter
o 8 kHz or 44.1 kHz – 48 kHz digital audio sampling rate options
•
•
•
o Analog receive and transmit gain adjust
o Configurable setup through the I2C interface
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ISD5216
3. BLOCK DIAGRAM
I5216 Block Diagram
2.2V Voltage
reference
MICBS
1
MICROPHONE
(AGPD)
MIC IN
MIC -
1
(AGPD)
AGCCAP
2
1
( S1M0
S1M1 )
ARRAY
1
DAO
(AXPD)
( AXG0
AXG1)
ARRAY
1
1 (FLS0)
(AMT0)
1
Σ
AUX IN
(FLPD)
2
Internal
Clock
( S2M0
S2M1)
Multilevel
Storage Array
2
SUM2
2
(ANALOG)
CTRL
1 (CKD2)
(DIGITAL)
ARRAY OUT
SUM2
A/D
Program/Read Control
VOL
2 x 64-bit reg.
(ANALOG)
AUX
OUT
AMP
FILTO
Array I/O Mux
2 x 64 S/H
ARRAY OUT
(DIGITAL)
Output MUX
MIC+
MIC-
2
SUM2
Summing
AMP
FILTO
Low Pass
Filter
Auto mute
Auto gain
( OSPD
) 2 ( FLD0 )
CKDV
FLD1
( S1S0
S1S1 )
÷2
MCLK
SUM1
SUM1
FILTO
(INS0)
AUX IN
AMP
Σ
SUM1 MUX
SUM1 MUX
1.0 / 1.4 / 2.0 / 2.8
AUX IN
AUX IN
SUM1
Summing
AMP
INP
Filter
MUX
AGC
Input Source MUX
MIC+
SPEAKER
SUM2
SP2
SUM1
CDI0
CDI1
INP
DAO
2
SUM2
2
μ-Law / A-Law /
Linear 14 bit
CODEC
(ADPD
)
DAPD
VSSA
1 (VLPD)
3
( OPS0
OPS1 )
( )
VOL0
VOL1
VOL2
(
2
OPA0
OPA1
)
( VLS0
VLS1 )
2
Power Conditioning
VCCA
Volume
Control
Vol MUX
CODEC
Mux
( )
SP+
Spkr.
AMP
DAO
INP
AUX OUT
VSSA
VSSD
VSSD
VCCD
Device Control
PCM / I2S Interface
VCCD
WS
SCK
SDIO
SDI
SCL
SDA
INT
RAC
A0
A1
5/22/01
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION ......................................................................................................... 2
2. FEATURES ................................................................................................................................. 2
3. BLOCK DIAGRAM ...................................................................................................................... 3
4. TABLE OF CONTENTS .............................................................................................................. 4
5. PIN CONFIGURATION ............................................................................................................... 7
6. PIN DESCRIPTION..................................................................................................................... 8
7. FUNCTIONAL DESCRIPTION.................................................................................................... 9
7.1. MEMORY ORGANIZATION...............................................................................................11
7.2. CODEC............................................................................................................................... 11
7.2.1. Analog Input to Digital Output Path ..........................................................................12
7.2.2. Digital Input to Analog Output Path ..........................................................................13
7.2.3. CODEC External Clock Configuration ......................................................................13
7.2.4. ChipCorder Analog Array Sampling Frequency With External Clock....................... 14
7.3. I2C INTERFACE .................................................................................................................15
7.3.1. System configuration ................................................................................................15
7.3.2. Start and stop conditions ..........................................................................................15
7.3.3. Bit transfer................................................................................................................. 16
7.3.4. ACKNOWLEDGE .....................................................................................................16
7.3.5. Additional ISD5216 flow control................................................................................17
7.3.6. I2C Protocol Addressing............................................................................................17
7.3.7. I2C Slave Address.....................................................................................................19
7.4. I2S SERIAL INTERFACE...................................................................................................20
7.4.1. Serial Data ................................................................................................................ 20
7.4.2. Word Select .............................................................................................................. 21
7.4.3. Timing ....................................................................................................................... 21
7.5. CONTROL REGISTERS ....................................................................................................22
7.5.1. Command Byte .........................................................................................................22
7.5.2. Function Bits ............................................................................................................. 23
7.5.3. Register Bits.............................................................................................................. 23
7.5.4. OPCODE Command Byte Table ..............................................................................24
7.5.5. Power-up................................................................................................................... 25
7.5.6. Read Status .............................................................................................................. 25
7.5.7. Attaching an Address to a Command.......................................................................25
7.5.8. Playback Mode .........................................................................................................26
7.5.9. Record Mode ............................................................................................................26
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ISD5216
7.5.10. Message Cueing.....................................................................................................26
7.6. digital mode ........................................................................................................................ 26
7.6.1. Writing Data .............................................................................................................. 26
7.6.2. Reading Data ............................................................................................................26
7.6.3. Erasing Data ............................................................................................................. 27
7.6.4. Load Configuration Registers ...................................................................................27
7.7. ISD5216 ANALOG STRUCTURE (Left Half) description ..................................................31
7.7.1 Speaker, AUX OUT and Volume Control Description ...............................................33
7.7.2. Microphone and Auxiliary Inputs ..............................................................................34
7.7.3. CODEC Configuration (First Page) ..........................................................................35
7.8. PIN DETAILS...................................................................................................................... 37
7.8.1. Power and Ground Pins............................................................................................37
7.8.2. Digital I/O Pins: ......................................................................................................... 37
7.8.3. CODEC Iinterface Pincs ...........................................................................................39
7.8.4. ANALOG I/O PINS....................................................................................................39
7.9. AUTO MUTE AND AUTO GAIN FUNCTIONS ..................................................................41
7.10 PROGRAMMING THE ISD 5216 ......................................................................................41
7.10 PROGRAMMING THE ISD 5216 ......................................................................................42
7.10.1. Sending a byte on the I2C interface .......................................................................42
7.10.2. POWER-UP SEQUENCE.......................................................................................42
7.10.3. Read Status command ...........................................................................................42
7.10.4. Load Command Byte Register (Single Byte Load):................................................ 43
7.10.5. Load Command Byte Register (Address Load):.....................................................43
7.10.6. Digital Erase............................................................................................................ 44
7.10.7. Digital Write............................................................................................................. 45
7.10.8. Digital Read ............................................................................................................ 45
7.10.9. Feed Through Mode ...............................................................................................45
7.10.10. Call Record ...........................................................................................................48
7.10.11. Memo Record .......................................................................................................49
7.10.12. Memo and Call Playback ......................................................................................50
7.11. SAMPLE PC LAYOUT FOR PDIP ...................................................................................51
8. TIMING DIAGRAMS.................................................................................................................. 52
9. ABSOLUTE MAXIMUM RATINGS............................................................................................ 60
10. ELECTRICAL CHARACTERISTICS....................................................................................... 61
11. TYPICAL APPLICATION CIRCUIT......................................................................................... 67
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
12. PACKAGE SPECIFICATIONG ............................................................................................... 70
12.1. PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE E DIMENSIONS.............. 70
12.2. Plastic Small Outline Integrated Circuit (SOIC) DIMENSIONS .......................................71
12.3. Plastic Dual Inline Package (PDIP) Dimensions..............................................................72
13. ORDERING INFORMATION................................................................................................... 73
14. VERSION HISTORY ............................................................................................................... 74
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ISD5216
5. PIN CONFIGURATION
V
V
V
CCD
1
28
V
SCL
2
27
MCLK
A1
3
26
INT
SDA
4
25
RAC
SSD
5
24
SDIO
6
23
V
22
SDI
NC
SSD
7
A0
ISD5216
SSA
MICBS
8
21
MIC-
9
20
AUXOUT
MIC+
10
19
SCK
ISD5216
11
18
WS
ACAP
12
17
AUX IN
SP-
13
16
V
14
15
SP+
V
V
TSOP
CCD
SSA
SSA
CCA
SOIC
VCCD
1
28
VCCD
SCL
2
27
MCLK
A1
3
26
INT
SDA
4
25
RAC
24
SDIO
23
SDI
22
VSSA
A0
5
VSSD
6
VSSD
7
VSSA
8
21
WS
MIC-
9
20
SCK
MIC+
10
19
NC
MICBS
11
18
AUXOUT
ACAP
12
17
AUX IN
SP-
13
16
VCCA
VSSA
14
15
SP+
ISD5216
PDIP
Please note that the pin assignments are different for the PDIP and the SOIC packages.
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
6. PIN DESCRIPTION
Pin Name
Pin No.
28-pin
TSOP
Pin No.
28-pin
PDIP
Pin No.
28-pin
SOIC
RAC
4
25
25
Row Address Clock; an open drain output. The RAC pin goes LOW TRACLO 1
before the end of each row of memory, and returns HIGH at exactly the end
of each row of memory.
5
26
26
Interrupt Output; an open drain output indicating that a set EOM bit has
been found during Playback, or that the chip is in an Overflow (OVF)
condition. This pin remains LOW until a Read Status command is executed.
MCLK
6
27
27
This pin allows the internal clock of the Voice record/playback system to be
externally driven for enhanced timing precision. This pin is grounded for
most applications. It is required for the CODEC operation.
SCL
9
2
2
SDA
11
4
4
A0
A1
MIC+
MICMICBS
ACAP
SP+
SP-
12
10
16
17
18
19
22
20
5
3
9
10
11
12
15
13
7
3
10
9
8
12
15
13
AUX IN
AUX OUT
24
25
17
18
17
20
SDI
SDIO
WS
SCK
VCCD
2
3
28
27
7,8
23
24
21
20
1,28
22
24
18
19
1,28
Serial Clock Line is part of the I2C serial bus. It is used to clock the data into
and out of the I2C interface.
Serial Data Line is part of the I2C serial bus. Data is passed between
devices on the bus over this line.
Input pin that supplies the LSB for the I2C Slave Address.
Input pin that supplies the LSB +1 bit for the I2C Slave Address.
Differential positive Input to the microphone amplifier.
Differential negative Input to the microphone amplifier.
Microphone Bias Voltage
AGC Capacitor connection. Required for the on-chip AGC amplifier.
Differential Positive Speaker Driver Output.
Differential Negative Speaker Driver Output. When the speaker outputs are
in use, the AUX OUT output is disabled.
Auxiliary Input.
Auxiliary Output. This is one the analog outputs for the device. When this
output is in use, the SP+ and SP- outputs are disabled.
Serial Digital Audio PCM Input.
Serial Digital Audio PCM Output or I2S Input/Output.
Digital audio PCM Frame sync (FS) or I2S Word Sync (WS).
Digital audio PCM or I2S Serial Clock.
Positive Digital Supply pins. These pins carry noise generated by internal
clocks in the chip. They must be carefully bypassed to Digital Ground to
ensure correct device operation.
VSSD
VSSA
VCCA
13,14
1,15,21
23
6,7
8,14,22
16
5,6
11,14,23
16
NC
26
19
21
INT
1
Functionality
Digital Ground pins.
Analog Ground pins.
Positive Analog Supply pin. This pin supplies the low level audio sections for
the device. It should be carefully bypassed to Analog Ground to ensure
correct device operation.
No Connection
See parameters section of the datasheet.
-8-
ISD5216
7. FUNCTIONAL DESCRIPTION
The ISD5216 ChipCorder Product provides high quality, fully integrated, single-chip Record/Playback
solutions for 8- to 16-minute messaging applications that are ideal for use in PBX systems, cellular
phones, automotive communications, GPS/navigation systems, and other portable products. The
ISD5216 product is an enhancement to the ISD5116 architecture, providing: 1) A full-duplex Voice
CODEC with μ-Law and A-Law compander using the I2S and PCM interface ports; 2) A 2.2V
microphone bias supply for reduced noise coupling. This supply can also be used to power down the
external microphone with the system.
Analog functions and audio gating have also been integrated into the ISD5216 product to allow for
easy interfacing with integrated chip sets on the market. Audio paths have been designed to enable
full duplex conversation record, voice memo and answering machine (including outgoing message
playback).
Logic Interface Options of 2.0V and 3.0V are supported by the ISD5216 to accommodate both
portable communication (2.0- and 3.0-volt required) and automotive product customers (5.0-volt
required).
Like other ChipCorder products, the ISD5216 integrates the sampling clock, anti-aliasing and
smoothing filters, and multi-level storage array on a single chip. For enhanced voice features, the
ISD5216 eliminates external circuitry by integrating automatic gain control (AGC), a power
amplifier/speaker driver, volume control, summing amplifiers, analog switches, and a Voice CODEC.
Input level adjustable amplifiers are also included, providing a flexible interface for multiple
applications.
Recordings are stored in on-chip nonvolatile memory cells, providing zero-power message storage.
This unique, single-chip solution is made possible through Winbond’s patented multilevel storage
technology. Voice and audio signals are stored directly into solid-state memory in their natural,
uncompressed form, providing superior quality voice and music reproduction.
SPEECH/SOUND QUALITY
The ISD5216 ChipCorder product can be software configured to operate at 4.0, 5.3, 6.4, and 8.0 kHz
sampling frequencies, allowing the user a choice of speech quality options. Increasing the duration
decreases the sampling frequency and bandwidth, which affects sound quality. The "Input Sample
Duration" table below compares filter pass band and product durations.
DURATION
To meet end-system requirements, the ISD5216 device is a single-chip solution, which provides 8 to
16 minutes of voice record and playback, depending on the sample rates defined by the customer's
software.
Input Sample Rate to Duration Input Sample
Rate (kHz)
Duration1 (Minutes)
Typical Filter Pass Band (kHz)
8.0
8 min 3 sec
3.7
6.4
10 min 4 sec
2.9
5.3
12 min 9 sec
2.5
4.0
16 min 6 sec
1.8
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
1.
Minus any pages selected for digital storage
FLASH STORAGE
One of the benefits of Winbond’s ChipCorder technology is the use of on-chip nonvolatile memory,
which provides zero-power message storage. A message is retained for up to 100 years (typically)
without power. In addition, the device can be re-recorded over 10,000 times (typically) for digital
messages and over 100,000 times (typically) for analog messages.
Memory space can be allocated to either digital or analog storage, when recording. The system micro
controller stores this information in the Message Address Table.
MICROCONTROLLER INTERFACE
The ISD5216 is controlled through an I2C 2-wire interface. This synchronous serial port allows
commands, configurations, address data, and digital data to be loaded to the device, while allowing
status, digital data and current address information to be read back from the device. In addition to the
serial interface, two other pins can be connected to the microcontroller for enhanced interface: the
RAC timing pin and the INT pin for interrupts to the controller. Communications with all of the internal
registers is through the serial bus, as well as digital memory Read and Write operations.
PROGRAMMING
The ISD5216 series is also ideal for playback-only applications, whereas single or multiple messages
may be played back when desired. Playback is controlled through the I2C port. Once the desired
message configuration is created, duplicates can easily be generated via a Winbond or third-party
programmer. For more information on available application tools and programmers, please see the
Winbond web site at http://www.winbond-usa.com/.
AUDIO PATHS
The ISD5216 has extremely powerful audio routing functionality where all audio signals can be routed
and multiplexed to multiple destinations. A few examples are
-
Simultaneous recording of microphone input and CODEC DAC output for recording both parties
of a phone call.
- 10 -
ISD5216
7.1. MEMORY ORGANIZATION
The ISD5216 memory array is arranged as 1888 rows (or pages) of 2048 bits, for a total memory of
3,866,624 bits. The primary addressing for the 2048 pages is handled by 11 bits of address data in
the analog mode. At the 8 kHz sample rate, each page contains 256 milliseconds of audio. Thus, at 8
kHz there is actually room for 8 minutes and 3 seconds of audio.
A memory page is 2048 bits organized as thirty-two 64-bit "blocks" when used for digital storage.
The contents of a page are either analog or digital. This is determined by instruction (op code) at the
time the data is written. A record of what is analog and what is digital, and where, is stored by the
system microcontroller in the message address table (MAT). The MAT is a table kept in the
microcontroller memory that defines the status of each message “block.” It can be stored back into the
ISD5216 if the power fails or the system is turned off. Use of this table allows for efficient message
management. Segments of messages can be stored wherever there is available space in the
memory array.
When a page is used for analog storage, the same 32 blocks are present, but there are 8 EOM (Endof-Message) markers. This means that for each 4 blocks there is an EOM marker at the end. Thus,
when recording, the analog recording will stop at any one of eight positions. At 8 kHz, this results in a
resolution of 32 msec when ENDING an analog recording. Beginning an analog recording is limited to
the 256 msec resolution provided by the 11-bit address. A recording does not immediately stop when
the Stop command is issued, but continues until the 32-millisecond block is filled. Then a bit is placed
into the EOM memory to develop the interrupt that signals a message is finished playing in the
Playback mode.
2
Digital data is sent and received, serially, over the I C interface. The data is serial-to-parallel
converted and stored in one of two alternating (commutating) 64-bit shift registers. When an input
register is full, it becomes the register that is parallel written into the array. The prior write register
becomes the new serial input register. A mechanism is built in to ensure there is always a register
available for storing new data.
Storing data in the memory is accomplished by accepting data, one byte at a time, and issuing an
acknowledgement. If data is coming in faster than it can be written, then the chip will not issue an
acknowledgement to the host microcontroller until it is ready.
The read mode is the opposite of the write mode. Data is read into one of two 64-bit registers from the
array and serially sent to the I2C port. (See Digital Mode on page 26 for details).
7.2. CODEC
The CODEC built into the ISD5216 supports both the I2S and PCM digital interface using μ-Law and
A-Law companding as well as 2’s complement and signed magnitude data. The CODEC meets the
PCM conformance specification of the G.714 recommendation. Its μ-Law and A-Law compander
meets the specification of the ITU-T G.711 recommendation.
The CODEC operates in full duplex in PCM mode and half duplex in I2S mode. Operating the CODEC
requires an external master clock running at 13.824 MHz, 20.48 MHz, 27.648 MHz or 40.96 MHz. This
provides a sampling frequency ranging from 8kHz to 48kHz.
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
The following diagram shows the functional blocks in the CODEC:
7.2.1. Analog Input to Digital Output Path
A 200 kHz anti-aliasing filter processes the analog input signal before entering the amplifier for the
A/D converter. The gain of this amplifier is adjustable through the configuration registers bits (CIG2 –
CIG0) for a gain from 0.80 to 2.00.
The Sigma Delta modulator is a Linear 14 bit ΣΔ modulator running at a sampling frequency
determined by the external clock input and the internal clock dividers (CKD2, CKDV). The standard
telecom frequency of 8kHz and digital audio of 44.1kHz and 48 kHz as well as intermediate
frequencies as shown in the table on the next page are supported. The A/D converter can be turned
off to save power and reduce noise by setting the A/D power down bit (ADPD).
The A/D converter feeds a 3.4 kHz digital anti aliasing filter which can be muted to suppress noise, the
mute bit controls both the A/D and D/A filter simultaneously. The following high pass filter is enabled
by bit (HPF0) in the configuration register. The High Sampling Rate bit (HSR0) needs to be set to
enable operation at 44.1kHz – 48 kHz.
The digital audio signal can be companded using μ - Law and A-Law companding or go to the output
uncompressed using 2’s complement or signed magnitude output selected with bits (LAW1 – LAW0)
in the configuration registers.
2
Finally the digital output interface is selected to be either full-duplex PCM or half duplex I S using the
2
interface selector bit (I S0) in the configuration register. The PCM interface uses the SDIO and SDI
pins, the half-duplex I2S format uses the SDIO pin as both input and output.
- 12 -
ISD5216
7.2.2. Digital Input to Analog Output Path
The digital input interface must be selected to either PCM or I2S using the interface selector bit (I2S0)
in the configuration register. The compression format must also be selected with bits (LAW1 – LAW0)
in the configuration registers.
The external clock input signal on pin MCLK and the internal clock dividers must be set to values
supporting the selected digital input signal.
The digital smoothing and interpolation filter runs at 3.4 kHz and feeds the ΣΔ D/A converter that can
be switched off to conserve power and reduce noise using the D/A power down bit (DAPD).
The analog output amplifier gain is controlled from configuration registers bits (COG2 – COG0) from 8 dB to +6 dB.
7.2.3. CODEC External Clock Configuration
The ISD5216 has two Master Clock configuration bits that allow four possible Master Clock
frequencies. Bits CKD2 and CKDV set the Master Clock Division ratios. These are bits D12 and D8 of
CFG2, respectively. The combination of these bits, with the sample rate bit HSR0, also set the
CODEC sample frequency as shown in the following table.
Master Clock Possible Settings
FMCLK
HSR0 (D5)
(CFG2)
CKD2 (D12)
(CFG2)
CKDV (D8)
(CFG2)
FSCODEC
13.824 MHz
0
0
0
8 kHz
20.48 MHz
0
0
1
11.852 kHz*
27.648 MHz
0
1
0
8 kHz
40.96 MHz
0
1
1
11.852 kHz*
13.824 MHz
1
0
0
32 kHz*
20.48 MHz
1
0
1
44.1 - 48 kHz
27.648 MHz
1
1
0
32 kHz*
40.96 MHz
1
1
1
44.1-48 kHz
*not tested
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
7.2.4. ChipCorder Analog Array Sampling Frequency With External Clock
If an external master clock is used, the clock dividers must be set according to the following table to
get the filter cut-off frequency and sample rate setup correctly. The duty cycle on the input clock is not
critical when CKD2 is set to ONE as the clock is immediately divided by two internally. See the Analog
Structure (Right Half) description on page 32.
FMCLK
FLD
1
FLD0
CKD2
CKDV
Sample Rate
Filter Knee
13.824 MHz
0
0
0
0
8.0 kHz
3.7 kHz
20.48 MHz
0
0
0
1
8.0 kHz
3.7 kHz
27.648 MHz
0
0
1
0
8.0 kHz
3.7 kHz
40.96 MHz
0
0
1
1
8.0 kHz
3.7 kHz
13.824 MHz
0
1
0
0
6.4 kHz
2.9 kHz
20.48 MHz
0
1
0
1
6.4 kHz
2.9 kHz
27.648 MHz
0
1
1
0
6.4 kHz
2.9 kHz
40.96 MHz
0
1
1
1
6.4 kHz
2.9 kHz
13.824 MHz
1
0
0
0
5.3 kHz
2.5 kHz
20.48 MHz
1
0
0
1
5.3 kHz
2.5 kHz
27.648 MHz
1
0
1
0
5.3 kHz
2.5 kHz
40.96 MHz
1
0
1
1
5.3 kHz
2.5 kHz
13.824 MHz
1
1
0
0
4.0 kHz
1.8 kHz
20.48 MHz
1
1
0
1
4.0 kHz
1.8 kHz
27.648 MHz
1
1
1
0
4.0 kHz
1.8 kHz
40.96 MHz
1
1
1
1
4.0 kHz
1.8 kHz
- 14 -
ISD5216
7.3. I2C INTERFACE
The I2C interface is for bi-directional, two-line communication between different ICs or modules. The
two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a
positive supply via a pull-up resistor. Data transfer may be initiated only when the interface bus is not
busy.
7.3.1. System configuration
A device generating a message is a ‘transmitter’; a device receiving a message is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices that are controlled by the master are
the ‘slaves’.
LSD
DRIVER
MICROCONTROLLER
STATIC
RAM OR
EEPROM
SDA
SCL
GATE
ARRAY
ISD 5116
2
Example of an I C-bus configuration using two microcontrollers
7.3.2. Start and stop conditions
Both data and clock lines remain HIGH when the interface bus is not busy. A HIGH-to-LOW transition
of the data line while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH
transition of the data line while the clock is HIGH is defined as the stop condition (P)
SDA
SCL
SDA
S
P
START condition
SCL
STOP condition
Definition of START and STOP conditions
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
7.3.3. Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse, as changes in the data line at this time will be interpreted
as a control signal. The same timing applies to both read and write.
SDA
SCL
changed
of data
allowed
data line
stable;
data valid
Bit transfer on the I2C-Bus
7.3.4. ACKNOWLEDGE
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is
a HIGH level signal put on the interface bus by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. In addition, a master receiver must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so
that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (setup and hold times must be taken into consideration). A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a
stop condition.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
9
2
S
dock pulse for
acknowledgement
START
condition
2
Acknowledge on the I C-bus
- 16 -
ISD5216
7.3.5. Additional ISD5216 flow control
2
The I C Interface in the ISD5216 differs from the standard implementation in the way the SCL line is
also used for flow control. The ISD5216 will hold the clock line low until it is ready to accept another
command/data. The SCL line must be implemented as a bi-directional line like the SDA line.
For example, the sequence of sending the slave address will be as follows:
1. Send one byte 10000000 {Slave Address, R/W = 0} 80h.
2. Wait for slave to acknowledge (ACK)
3. Next time the clock is pulled high by the master, wait for SCL to actually go high.
7.3.6. I2C Protocol Addressing
Since the I2C protocol allows multiple devices on the bus, each device must have an address. This
address is known as a “Slave Address”. A Slave Address consists of 7 bits, followed by a single bit
that indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is
being sent from the current bus master to the device being addressed. This single bit is a 0 for a Read
cycle, which indicates that the data is being sent from the device being addressed to the current bus
master.
Before any data is transmitted on the I2C interface, the current bus master must address the slave it
wishes to transfer data to or from. The Slave Address is always sent out as the 1st byte following the
Start Condition sequence. An example of a Master transmitting an address to a ISD5216 slave is
shown below. In this case, the Master is writing data to the slave and the R/W bit is “0”, i.e. a Write
cycle. All the bits transferred are from the Master to the Slave, except for the indicated Acknowledge
bits.
Master Transmits to Slave Receiver (Write) Mode
acknowledgement
from slave
S
Start Bit
SLAVE ADDRESS
W A
acknowledgement
from slave
COMMAND BYTE
A
acknowledgement
from slave
High ADDR. BYTE
A
acknowledgement
from slave
Low ADDR. BYTE
A
P
Stop Bit
R/W
A common procedure in the ISD5216 is the reading of the Status Bytes. The Read Status condition in
the ISD5216 is triggered when the Master addresses the chip with its proper Slave Address,
immediately followed by the R/W bit set to a “0” and without the Command Byte being sent. This is an
example of the Master sending to the Slave, immediately followed by the Slave sending data back to
the Master. The “N” not-acknowledge cycle from the Master ends the transfer of data from the Slave.
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
Master Reads from Slave immediately after first byte (Read Mode)
acknowledgement
from slave
From Slave
S
SLAVE ADDRESS
R
A
From Slave
STATUS W ORD
A
From Slave
High ADDR. BYTE
A
Low ADDR BYTE
N
P
From Master
Start Bit
From
Master
acknowledgement
from Master
acknowledgement
from Master
R/W
From
Master
Stop Bit
From
Master
not-acknowledged
from Master
Another common operation in the ISD5216 is the reading of digital data from the chip’s memory array
at a specific address. This requires the I2C interface Master to first send an address to the ISD5216
Slave device, and then receive data from the Slave in a single I2C operation. To accomplish this, the
data direction R/W bit must be changed in the middle of the command. The following example shows
the Master sending the Slave address, then sending a Command Byte and 2 bytes of address data to
the ISD5216, and then immediately changing the data direction and reading some number of bytes
from the chip’s digital array. An unlimited number of bytes can be read in this operation. The “N” notacknowledge cycle from the Master forces the end of the data transfer from the Slave. The following
example details the transfer explained in the section on page 22 of this datasheet.
Master Reads from the Slave after setting data address in Slave
(Write data address, READ Data)
acknowledgement
from slave
S
SLAVE ADDRESS
Start Bit
From
Master
W A
acknowledgement
from slave
COMMAND BYTE
A
acknowledgement
from slave
High ADDR. BYTE
A
acknowledgement
from slave
Low ADDR. BYTE
A
R/W
From
Master
acknowledgement
from slave
From Slave
S
SLAVE ADDRESS
R
A
8 BITS of DATA
From Slave
A
8 BITS of DATA
From Slave
A
8 BITS of DATA
N
P
From Master
Start Bit
From
Master
R/W
From
Master
acknowledgement
from Master
acknowledgement
from Master
Stop Bit
From
Master
not-acknowled
from Master
- 18 -
ISD5216
7.3.7. I2C Slave Address
The ISD5216 has a 7 bit slave address of where x and y are equal to the state,
respectively, of the external address pins A1 and A0. Because all data bytes are required to be 8 bits,
the LSB of the address byte is the Read/Write selection bit that tells the slave whether to transmit or
receive data. Therefore, there are eight possible slave addresses for the ISD5216. To use more than
four ISD5216 devices in an application requires some external switching of the I2C link.
A1
A0
Slave
Address
R/W\ Bit
HEX Value
0
0
0
80
0
1
0
82
1
0
0
84
1
1
0
86
0
0
1
81
0
1
1
83
1
0
1
85
1
1
1
87
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
7.4. I2S SERIAL INTERFACE
As shown in the following figure, the bus has three lines:
•
continuous serial clock (SCK)
•
word select (WS)
•
serial data (SDIO)and the device generating SCK and WS is the master.
Simple System Configurations and Basic Interface Timing
7.4.1. Serial Data
Serial data is transmitted in two’s complement with the MSB first. The MSB is transmitted first
because the transmitter and receiver may have different word lengths. It isn’t necessary for the
transmitter to know how many bits the receiver can handle, nor does the receiver need to know how
many bits are being transmitted.
When the system word length is greater than the transmitter word length, the word is truncated (least
significant data bits are set to ‘0’) for data transmission. If the receiver is sent more bits than its word
length, the bits after the LSB are ignored. On the other hand, if the receiver is sent fewer bits than its
word length, the missing bits are set to zero internally. And so, the MSB has a fixed position, whereas
the position of the LSB depends on the word length. The transmitter always sends the MSB of the
next word one clock period after the WS changes.
Serial data sent by the transmitter may be synchronized with either the trailing (HIGH-to-LOW) or the
leading (LOW-to-HIGH) edge of the clock signal. However, the serial data must be latched into the
receiver on the leading edge of the serial clock signal, and so there are some restrictions when
- 20 -
ISD5216
transmitting data that is synchronized with the leading edge (see the timing specifications at the back
of this data sheet).
Note that the specifications are defined by the transmitter speed. The specification of the receiver has to be able to match the
performance of the transmitter.
7.4.2. Word Select
The word select line indicates the channel being transmitted:
• WS = 0; channel 1 (left)
• WS = 1; channel 2 (right)
WS may change either on a trailing or leading edge of the serial clock, but it doesn’t need to be
symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The WS line
changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive
synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the
receiver to store the previous word and clear the input for the next word (see figure Timing for I2S
Transmitter on previous page.)
7.4.3. Timing
2
In the I S format, any device can act as the system master by providing the necessary clock signals. A
slave will usually derive its internal clock signal from an external clock input. This means, taking into
account the propagation delays between master clock and the data and/or word-select signals, the
total delay is simply the sum of:
• the delay between the external (master) clock and the slave’s internal clock; and
• the delay between the internal clock and the data and/or word-select signals.
For data and word-select inputs, the external to internal clock delay is of no consequence because it
only lengthens the effective set-up time (see figure Timing for I2S Transmitter on previous page.) The
major part of the time margin is to accommodate the difference between the propagation delay of the
transmitter, and the time required to set up the receiver.
All timing requirements are specified relative to the clock period or to the minimum allowed clock
period of a device. This means that higher data rates can be used in the future.
Timing for I2S Receiver
T
tLC > 0.35T
tHC > 0.35
VH = 2.0V
VL = 0.8V
SCK
tar > 0.2T
tar > 0
SD
and
WS
T = clock period
TR = minimum allowed clock period for transmitter
T > TR
Note that the specifications are defined by the transmitter speed. The specification of the receiver has to be able to match the
performance of the transmitter.
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
7.5. CONTROL REGISTERS
The ISD5216 is controlled by loading commands to, or reading commands from the internal command,
configuration and address registers. The Command byte sent is used to start and stop recording, write
or read digital data and perform other functions necessary for the operation of the device.
7.5.1. Command Byte
Control of the ISD5216 is implemented through an 8-bit command byte that is sent after the 7-bit
device address and the 1-bit Read/Write selection bit. The 8 bits are:
Global power up bit (PU)
DAB bit: determines whether device is performing an analog or digital function
3 function bits: these determine which function the device is to perform in conjunction with
the DAB bit.
3 register address bits: these determine if and when data is to be loaded to a register
C7
C6
C5
C4
C3
C2
C1
C0
PU
DAB
FN2
FN1
FN0
RG2
RG1
RG0
Function Bits
Register Bits
- 22 -
ISD5216
7.5.2. Function Bits
The command byte function bits are
detailed in the table to the right. C6, the
DAB bit, determines whether the device is
performing an analog or digital function.
The other bits are decoded to produce the
individual commands. Note that not all
decode combinations are currently used;
they are reserved for future use. Out of 16
possible codes, the ISD5216 uses 7 for
normal operation. The other 9 are No Ops.
7.5.3. Register Bits
The register load may be used to modify
a command sequence (such as load an
address) or used with the null command
sequence to load a configuration or test
register. Not all registers are accessible
to the user. [The remaining three codes
are No Ops.]
Command Bits
Function
C6
C5
C4
C3
DAB
FN2
FN1
FN0
0
0
0
0
STOP (or do nothing)
0
1
0
1
Analog Play
0
0
1
0
Analog Record
0
1
1
1
Analog MC
1
1
0
0
Digital Read
1
0
0
1
Digital Write
1
0
1
0
Erase (row)
Function
RG2
RG1
RG0
C2
C1
C0
0
0
0
No action
0
0
1
Load Address
0
1
0
Load CFG0
0
1
1
Load CFG1
1
0
1
Load CFG2
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
7.5.4. OPCODE Command Byte Table
Pwr
Function Bits
Register Bits
OPCODE
HEX
PU
DA
B
FN
2
FN
1
FN
0
RG
2
RG
1
RG0
COMMAND BIT NUMBER
CMD
C7
C6
C5
C4
C3
C2
C1
C0
POWER UP
80
1
0
0
0
0
0
0
0
POWER DOWN
00
0
0
0
0
0
0
0
0
STOP (DO NOTHING) STAY ON
80
1
0
0
0
0
0
0
0
STOP (DO NOTHING) STAY OFF
00
0
0
0
0
0
0
0
0
LOAD ADDRESS
81
1
0
0
0
0
0
0
1
LOAD CFG0
82
1
0
0
0
0
0
1
0
LOAD CFG1
83
1
0
0
0
0
0
1
1
LOAD CFG2
85
1
0
0
0
0
1
0
1
RECORD ANALOG
90
1
0
0
1
0
0
0
0
RECORD ANALOG @ ADDR
91
1
0
0
1
0
0
0
1
PLAY ANALOG
A8
1
0
1
0
1
0
0
0
PLAY ANALOG @ ADDR
A9
1
0
1
0
1
0
0
1
MSG CUE ANALOG
B8
1
0
1
1
1
0
0
0
MSG CUE ANALOG @ ADDR
B9
1
0
1
1
1
0
0
1
ERASE DIGITAL PAGE
D0
1
1
0
1
0
0
0
0
ERASE DIGITAL PAGE @ ADDR
D1
1
1
0
1
0
0
0
1
WRITE DIGITAL
C8
1
1
0
0
1
0
0
0
WRITE DIGITAL @ ADDR
C9
1
1
0
0
1
0
0
1
READ DIGITAL
E0
1
1
1
0
0
0
0
0
READ DIGITAL @ ADDR
E1
1
1
1
0
0
0
0
1
READ STATUS REGISTER
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
- 24 -
ISD5216
7.5.5. Power-up
The ISD5216 must be powered up before sending any other commands. Wait for Tpud time before
sending the next command.
7.5.6. Read Status
When the device is polled with the Read Status command, it will return three bytes of data. The first
byte is the status byte, the next is the upper address byte and the last is the lower address byte. The
status register is one byte long and its bit function is:
BIT#
NAME
FUNCTION
7
EOM
Indicates whether an EOM interrupt has occurred.
6
OVF
Indicates whether an overflow interrupt has occurred.
5
READY
Indicates the internal status of the device – if READY is LOW no new
commands should be sent to device.
4
PD
Device is powered down if PD is HIGH.
3
PRB
Play/Record mode indicator. HIGH=Play/LOW=Record.
DEVICE_ID
An internal device ID. This is 001 for the ISD5216.
2
1
0
The lower address byte will always return the block address bits as zero, either in digital or analog
mode.
It is good practice to read the status register after a Write or Record operation to ensure that the
device is ready to accept new commands. Depending upon the design and the number of pins
available on the controller, the polling overhead can be reduced. If INT and RAC are tied to the
microcontroller, the controller does not have to poll as frequently to determine the status of the
ISD5216
7.5.7. Attaching an Address to a Command
In the I2C write mode, the device can accept data sent after the command byte. If a register load
option is selected, the next two bytes are loaded into the selected register. The format of the data is
MSB first, as specified by the I2C standard. Thus to load DATA into the device, DATA is
sent first, the byte is acknowledged, and DATA is sent next. The address register consists of two
bytes. The format of the address is as follows:
ADDRESS = PAGE_ADDRESS, BLOCK_ADDRESS
If an analog function is selected, the block address bits must be set to 00000. Digital Read and Write
are block addressable.
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
7.5.8. Playback Mode
The command sequence for an analog playback operation from a given address is the Slave Address
(80h), the Command Byte (A9h) for Play Analog @ Address, and the two address bytes. If The Play
Analog (A8h) is sent, playback starts from the current address pointer. The current address pointer is
returned when the three status bytes are read.
7.5.9. Record Mode
The command sequence for an Analog Record is a four byte sequence consisting of the Slave
Address (80h), the Command Byte (91h) for Record Analog @ Address, and the two address bytes. If
The Record Analog (90h) is sent, recording starts from the current address pointer.
7.5.10. Message Cueing
Message cueing allows the user to skip through messages, without having to know the actual physical
location of each message. This operation is used during playback. In this mode, the messages are
skipped 512 times faster than in normal playback mode. This operation will stop when an EOM marker
is reached. Then, the internal address counter will be pointing to the next message.
7.6. DIGITAL MODE
7.6.1. Writing Data
The Digital Write function allows the user to select a portion of the array to be used as digital memory.
The partition between analog and digital memory is left up to the user. A page can only be either
Digital or Analog, but not both. The minimum addressable block of memory in the digital mode is 1
block, or 64 bits, when reading or writing. The address sent to the device is the 11-bit row (or page)
address with the 5-bit scan (or block) address. However, one must send a Digital Erase before
attempting to change digital data on a page. This means that even when changing only one of the 32
blocks, all 32 will need to be rewritten to the page.
After the address is entered, the data is sent in one-byte packets followed by an I2C acknowledge
generated by the chip. Data for each block is sent MSB first. The data transfer is ended when the
master generates an I2C STOP condition. If only a partial block of data is sent before the STOP
condition, zero is “written” in the remaining bytes; that is, they are left at the erase level. An erased
page (row) will be read as all zeros. The device can buffer up to two blocks of data.
If the device is unable to accept more data due to the internal write process, the SCL line will be held
LOW indicating, to the master, to halt data transfer. If the device encounters an overflow condition, it
will respond by generating an interrupt condition and an I2C Not Acknowledge signal after the last
valid byte of data. Once data transfer is terminated, the device needs up to two cycles (64 us) to
complete its internal write cycle before another command is sent. If an active command is sent before
the internal cycle is finished, the ISD5216 will hold SCL LOW until the current command is finished.
7.6.2. Reading Data
The Digital Read command utilizes the combined I2C command format. That is, a command is sent to
the chip using the write data direction. Then the data direction is reversed by sending a repeated start
condition and the slave address with R/W set to one. After this, the slave device (ISD5216) begins to
send data to the master until the master generates a Not Acknowledge. If the part encounters an
overflow condition, the INT pin is pulled LOW. No other communication with the master is possible
due to the master generating ACK signals.
- 26 -
ISD5216
As with Digital Write, Digital Read can be done a “block” at a time. Thus, only 64 bits need to be read
in each Digital Read command sequence.
7.6.3. Erasing Data
The Digital Erase command can only erase an entire page at a time. This means that the D0 or D1
command only needs to include the 11-bit page address; the 5-bit for block address are left at 00000.
Once a page has been erased, each block may be written separately, 64 bits at a time. But, if a block
has been previously written, then the entire page of 2048 bits must be erased in order to re-write (or
change) a block.
While erasing data, the RAC pin will have a pulse at the end of each erased page, when the stop
erase command is sent, the device will stop erasing at the end of the current page. To erase a single
page, the stop command should be sent immediately after the start erase command. To erase multiple
pages, count pulses on the RAC pin and send the stop command after n-1 RAC pulses have been
detected where n is the number of pages to erase.
A sequence might look like:
- read the entire page
- store it in RAM
- change the desired bit(s)
- erase the page
- write the new data from RAM to the entire page
7.6.4. Load Configuration Registers
To load the configuration registers, send the LOAD CFG command followed by the two configuration
bytes with the most significant byte first.
The following tables provide a summary of the bits. There are three configuration registers: CFG0,
CFG1 and CFG2. Thus, there are six 8-bit bytes to be loaded during the set-up of the device.
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Publication Release Date: July 17, 2007
Revision B.5
ISD5216
CFG0
Bit no.
Signal
Description
D0 (LSB)
VLPD
Power down the Volume Control.
D1
OPA0
Power down Speaker driver and/or Auxiliary output.
D2
OPA1
Power down Speaker driver and/or Auxiliary output.
D3
OPS0
Select speaker output multiplexer.
D4
OPS1
Select speaker output multiplexer.
D5
CDI0
Analog to digital converter input selector.
D6
CDI1
Analog to digital converter input selector.
D7
AMT0
Compress the filter signal.
D8
OSPD
Power down the internal ChipCorder oscillator.
D9
INS0
Select Microphone input or Auxiliary input.
D10
AXPD
Power down Auxiliary input amplifier.
D11
AXG0
Auxiliary input amplifier gain setting.
D12
AXG1
Auxiliary input amplifier gain setting.
D13
CIG0
Input gain setting for the Analog to digital converter.
D14
CIG1
Input gain setting for the Analog to digital converter.
D15 (MSB)
CIG2
Input gain setting for the Analog to digital converter.
- 28 -
ISD5216
CFG1
Bit no.
Signal
Description
D0 (LSB)
AGPD
Power down the Microphone AGC
D1
FLPD
Power down the Filter
D2
FLD0
Set the duration and sample rate of the ChipCorder
D3
FLD1
Set the duration and sample rate of the ChipCorder
D4
FLS0
Select the filter input signal
D5
S2M0
Select Sum Amplifier 2 input
D6
S2M1
Select Sum Amplifier 2 input
D7
S1M0
Select Sum Amplifier 1 input
D8
S1M1
Select Sum Amplifier 1 input
D9
S1S0
Select Sum Amplifier 1 multiplexer
D10
S1S1
Select Sum Amplifier 1 multiplexer
D11
VOL0
Volume Control Setting
D12
VOL1
Volume Control Setting
D13
VOL2
Volume Control Setting
D14
VLS0
Select Volume Control input
D15 (MSB)
VLS1
Select Volume Control input
- 29 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
CFG2
Bit no.
Signal
Description
D0 (LSB)
ADPD
Power down the Analog to Digital converter
D1
DAPD
Power down the Digital to Analog converter
D2
LAW0
Select digital μ-Law or A-Law input/output format
D3
LAW1
Select digital μ-Law or A-Law input/output format
D4
I2S0
Select the I2S interface
D5
HSR0
Enable the high sample rate mode
D6
HPF0
Enable High Pass Filter
D7
MUTE
Mute the CODEC A/D and D/A path
D8
CKDV
Divide MCLK by 2560 or 1728 for 8 kHz ChipCorder sample rate
D9
COG0
Output gain setting for the Digital to Analog converter
D10
COG1
Output gain setting for the Digital to Analog converter
D11
COG2
Output gain setting for the Digital to Analog converter
D12
CKD2
Divide MCLK frequency by 2 or 1
D13
-
Reserved
D14
-
Reserved
D15 (MSB)
-
Reserved
- 30 -
ISD5216
7.7. ISD5216 ANALOG STRUCTURE (LEFT HALF) description
INP
AUX IN
Input Source MUX
AGC AMP
Σ
SUM1 MUX
( S1M0
S1M1 )
SUM1
2
FILTO
ARRAY
DAC OUT
SUM1 MUX
1
(INS0)
SUM1
Summing
AMP
INP
S1M1
S1M0
0
0
BOTH
0
1
SUM1 MUX ONLY
1
0
INP Only
1
1
POWER DOWN
2
( S1S0
)
S1S1
INSO
Select whether to
send the AUX input or
the microphone signal
to the summing amp
0
AGC AMP
1
AUX IN AMP
This summing amp allows the signal
from the input mux or sum 1 mux to
be selected or added together. Set the
amp to OFF to switch off completely
S1S1
S1S0
Select whether to send the
FILTO
signal,
the
MLS
playback signal or the output
of the CODEC DAC to the
summing amp. Set to OFF to
disable the signal
0
0
DAC OUT (DAO)
0
1
ARRAY
1
0
FILTO
1
1
OFF
Configuration Register CFG0, CFG1 and CFG2. The bits described on this page are highlighted.
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
- 31 -
Publication Release Date: July 17, 2007
Revision B.5
CFG0
CFG1
CFG2
ISD5216
ISD5216 ANALOG STRUCTURE (Right Half) description
FLS0
Select input from MLS
array or sum 1 amp
AMT0
Switch on or off the auto gain
circuit
FLPD
0
SUM1
0
Uncompressed
0
Power Up
Compressed
1
Power Down
1
ARRAY
1
FLD1
FLD0
SAMPLE
RATE
PASS
BAND
Control power to the
low pass filter
S2M1
S2M0
0
0
SOURCE
BOTH
0
0
8 KHz
3.7 KHz
0
1
AUX IN ONLY
0
1
6.4 KHz
2.9 KHz
1
0
FILTO ONLY
1
0
5.3 KHz
2.5 KHz
1
1
Power Down
1
1
4.0 KHz
1.8 KHz
CKD2
Divide Master Clock
by 1 or 2
CKDV
Divide Master Clock
by 1728 or 2560
OSPD
Power Up Internal
Oscillator
0
Divide by 1
0
Divide by 1728
0
Power up
1
Divide by 2
1
Divide by 2560
1
Power Down
Configuration Register CFG0, CFG1 and CFG2. The bits described on this page are highlighted.
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
- 32 -
CFG0
CFG1
CFG2
ISD5216
7.7.1 Speaker, AUX OUT and Volume Control Description
OPA1
VLPD
0
DAC OUT
0
1
SUM2
1
0
SUM1
State of aux out
0
0
Power Down
0
Power Up
0
1
Power Down
1
Power Down
3.6 VP-P @ 150 Ω
1
0
23.5 mW @ 8 Ω
Power Down
1
1
Power Down
1 VP-P Max @ 5 KΩ
VLS1 VLS0 Select input
source to the
volume mux
0
OPA0 State
of
the
speaker output
Switch volume
control on or off
VOL2
VOL1
VOL
0
Attenuation
0
0
0
0 dB
0
0
1
4 dB
0
1
0
8 dB
0
0
VOL
0
1
1
12 dB
0
1
DAC OUT
1
0
0
16 dB
1
0
FILTO
1
0
1
20 dB
1
1
SUM2
1
1
0
24 dB
1
1
1
28 dB
OPS1
OPS0
Power Down
Select input source
to
the
analog
output mux
Configuration Register CFG0, CFG1 and CFG2. The bits described on this page are highlighted.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
- 33 -
Publication Release Date: July 17, 2007
Revision B.5
CFG0
CFG1
CFG2
ISD5216
7.7.2. Microphone and Auxiliary Inputs
Internal to the device
Rb
CCOUP = 0.1 ìF
Ra
ANA IN
Input
ANA IN
Input Amplifier
NOTE: fCUTTOFF
1
2xRaCCCUP
2.2V Voltage
AXPD
Power up the AUX in
input amplifier
0
Power Up
1
Power Down
(
AXG1
AXG0
Gain (dB) of the
aux input
amplifier
0
0
0
0
1
3
1
0
6
1
1
9
AGPD
Power up the AGC
control and the MIC bias
voltage
0
Power Up
1
Power Down
CDI1
CDI0
Select input to
the CODEC A/D
converter
0
0
INP
0
1
SUM2
1
0
MIC
1
1
No Input
Configuration Register CFG0, CFG1 and CFG2. The bits described on this page are highlighted.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
- 34 -
CFG0
CFG1
CFG2
ISD5216
7.7.3. CODEC Configuration (First Page)
CIG2
CIG1
CIG0
ADC GAIN
COG2
COG1
COG0
DAC GAIN (dB)
0
0
0
0.80
0
0
0
0
0
0
1
1.00
0
0
1
+2
0
1
0
1.20
0
1
0
+4
0
1
1
1.25
0
1
1
+6
1
0
0
1.40
1
0
0
-8
1
0
1
1.60
1
0
1
-6
1
1
0
1.80
1
1
0
-4
1
1
1
2.00
1
1
1
-2
Configuration Register CFG0, CFG1 and CFG2. The bits described on this page are highlighted.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
- 35 -
Publication Release Date: July 17, 2007
Revision B.5
CFG0
CFG1
CFG2
ISD5216
LAW1
LAW0
Data Format
MUTE
State
DAPD
Power up the CODEC DAC
0
0
Two’s
Complement
0
Unmuted
0
Power Up
0
1
A-Law
1
muted
1
Power Down
1
0
μ - Law
1
1
Signed
Magnitude
CODEC Configuration (Second Page)
ADPD
CODEC ADC
I2S0
Digital
Interface
HPF0
High
Filter
0
Power Up
0
PCM
0
1
Power Down
1
I2S
1
Pass
HSR0
Sample Rate
Mode
Bypassed
0
Low
Enabled
1
High
Configuration Register CFG0, CFG1 and CFG2. The bits described on this page are highlighted.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
- 36 -
CFG0
CFG1
CFG2
ISD5216
7.8. PIN DETAILS
7.8.1. Power and Ground Pins
VCCA, VCCD (Voltage Inputs)
To minimize noise, the analog and digital circuits in the Winbond ISD5216 device use separate power
busses. These +3 V busses lead to separate pins. Tie the VCCD pins together as close as possible,
and decouple both supplies as near to the package as possible.
VSSA, VSSD (Ground Inputs)
The Winbond ISD5216 series utilizes separate analog and digital ground busses. The analog ground
(VSSA) pins should be tied together as close to the package as possible, and connected through a lowimpedance path to power supply ground. The digital ground (VSSD) pin should be connected through a
separate low impedance path to power supply ground. These ground paths should be large enough to
ensure that the impedance between the VSSA pins and the VSSD pin is less than 3Ω. The backside of
the die is connected to VSSD through the substrate resistance. In a chip-on-board design, the die
attach area must be connected to VSSD.
NC (No Connect)
These pins should not be connected to the board at any time. Connection of these pins to any signal,
ground or VCC, may result in incorrect device behavior or cause damage to the device.
7.8.2. Digital I/O Pins:
SCL (SERIAL CLOCK LINE)
The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor to
Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged over
the Serial Data Line.
SDA (SERIAL DATA LINE)
The Serial Data Line carries the data between devices on the I2C interface. Data must be valid on this
line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is a bidirectional line requiring a pull-up resistor to Vcc.
A0, A1 (Address Pins)
These two pins are normally strapped for the desired address that the Winbond ISD5216 will have on
the I2C serial interface. If there are four of these devices on the bus, then each must be strapped
differently in order to allow the master device to address them individually. The possible addresses
range from 80h to 87h, depending upon whether the device is being written to, or read from, by the
host.
The Winbond ISD5216 has a 7-bit slave address of which only A0 and A1 are pin programmable. The
eighth bit (LSB) is the R/W bit. Thus, the address will be 1000 0xy0 or 1000 0xy1
- 37 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
RAC (ROW ADDRESS CLOCK)
RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency
the duration of this period is 256 ms. there are 1888 pages of memory in the Winbond ISD5216
device. RAC stays HIGH for 248 ms and goes LOW for the remaining 8 ms before it reaches the end
of the page.
1 ROW
RAC Waveform
During 8 KHz Operation
256 msec
TRAC
8 msec
TRACLO
The RAC pin remains HIGH for 500 µsec and stays LOW for 15.6 µsec under the Message Cueing
mode. See the Timing Parameters table on page 63 for RAC timing information at other sample rates.
When a record command is first initiated, the RAC pin remains HIGH for an extra TRACLO period in
order to load sample and hold circuits internal to the device. The RAC pin can be used for message
management techniques.
1 ROW
RAC Waveform
During Message Cueing
500 usec
TRAC
15.6 us
TRACLO
RAC Waveform
During Digital Erase
1.25 µsec
.25 µsec
- 38 -
ISD5216
INT (Interrupt)
INT is an open drain output pin. The Winbond ISD5216 Interrupt pin goes LOW and stays LOW when
an Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends in an
EOM or OVF generates an interrupt, including the message cueing cycles. The interrupt is cleared by
a READ STATUS instruction that gives a status byte on the SDA line.
MCLK (Master Clock Input)
This is the Master clock input for the Winbond ISD5216 device. Normally, the Winbond ISD5216
ChipCorder section is operated at one of four internal rates selected for its internal oscillator by the
Sample Rate Select bits. If the internal oscillator is powered down (configuration bit OSPD set to
ONE), the device is clocked through the MCLK pin as shown in the section ISD5216 Analog Structure
(right half) description on page 32. If an external clock is not used, this input must be connected to
VSSD.
7.8.3. CODEC Iinterface Pincs
SCK
Bit clock for PCM or I2S audio data
WS
The Word Sync (Frame Sync) signal is used to differentiate between data for left and right channel in
I2S. For PCM it signals the beginning of the word.
SDIO
For PCM, this is the output signal from the CODEC, it should be connected to the input pin of the
receiving device.
In I2S mode, this is a bi-directional pin that should be connected to the bi-directional I2S data pin on
the other device connected to the I2S bus.
SDI
This pin is only used when the CODEC is in PCM mode, this signal provides digital audio input to the
CODEC it should be connected to the output pin of the transmitting device.
7.8.4. ANALOG I/O PINS
MIC+, MIC-
(Microphone Input +/-)
The microphone inputs transfer the voice signal to the on-chip AGC preamplifier, or directly to the
CODEC INPUT MUX, depending on the selected path. The AGC circuit has a range of 45 dB in order
to deliver a nominal 694 mV p-p into the storage array from a typical electret microphone output of 2 to
20 mV p-p. The input impedance is typically 20 kΩ differential and 13.3 kΩ differential when the
CODEC INPUT MUX MICIN path is selected.
The MICBS pin provides a 2.2V bias voltage for the external microphone only when the AGC is
powered up. Using this regulated bias voltage results in less supply noise coupling into the MIC+ and
- 39 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
MIC- pins compared to the situation in which the external microphone is powered up through the
power supply. It also saves current during power down.
ACAP (AGC Capacitor)
This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It
should have a 4.7 µF capacitor connected to ground. It cannot be left floating. This is because the
capacitor is also used in the playback mode for the AutoMute circuit or when signal compression is
chosen (AMT0 is set to ONE). This circuit reduces the amount of noise present in the output during
quiet pauses. Tying this pin to ground gives maximum gain. Tying it to VCCA gives minimum gain for
the AGC amplifier, but cancels the AutoMute function. Connect the capacitor to low noise ground as
ground noise directly affects the microphone performance
SP +, SP-
(Speaker +/-)
This is the speaker differential output circuit. It is designed to drive an 8Ω speaker connected across
the speaker pins, up to a maximum of 23.5 mW RMS power. This stage has two selectable gains,
1.32 and 1.6, which can be chosen through the configuration registers. These pins are biased to approximately 1.2 VDC and, if used single-ended, must be capacitively coupled to their load. Do NOT
ground the unused pin.
AUX OUT (Auxiliary Output)
The AUX OUT is an additional audio output pin to be used, for example, to drive the speaker circuit in
a “car kit.” It drives a minimum load of 5 kΩ and up to a maximum of 1 V p-p. The AC signal is
superimposed on approximately 1.2 VDC bias and must be capacitively coupled to the load.
AUX IN (Auxiliary Input)
The AUX IN is an additional audio input to the Winbond ISD5216, such as from the microphone circuit
in a mobile phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting
(0 dB). (See Aux In Amplifier Gain Settings Table below). Additional gain is available in 3 dB steps
(controlled by the I2C interface) up to 9 dB.
(2)
0TLP Input VP-P
Gain Setting
Gain
(1)
(dB)
Gain
(1)
Array In/Out VP-P
Speaker Out VP(3)
P
0.694
00
0
1.00
0.694
0.694
0.491
01
3
1.41
0.694
0.694
0.347
10
6
2.00
0.694
0.694
0.245
11
9
2.82
0.694
0.694
1.
Gain from AUX IN to ARRAY IN
2.
0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB
below clipping
3.
Differential
- 40 -
ISD5216
7.9. AUTO MUTE AND AUTO GAIN FUNCTIONS
During playback, the signal passes through the Automatic Attenuator before it is filtered. The
Automatic Attenuator will attenuate all signals at the noise level in order to reduce the noise during
quiet pauses.
During record, low level input signals are brought up by the Auto Gain function if the configuration bit
D7 of CFG0 (AMT0) is set. This improves the signal to noise ratio of recorded low level input signals.
If the configuration bit CFG0 (AMT0) is set to ZERO, all input levels are recorded with the same
gain setting. The attack and release time of the Auto Gain and Auto Mute functions is set by the
capacitor on the ACAP pin. The AGC cannot be used if the Auto Gain or Auto Mute function is
enabled.
Tattack ≈ 0,1504 x Vpeak
Trelease ≈ 6.58 x Vpeak
Expand
Compres
0
Gain
(dB)
@ Cattcap=4.7 μF
Gain
(dB)
12
0
-12
0
Vpp
0
- 41 -
Vpp
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
7.10 PROGRAMMING THE ISD 5216
7.10.1. Sending a byte on the I2C interface
When reading or writing a byte of data on the I2C bus, two different
mechanisms for flow control are used, the first is the standard ACK
that the slave or master sends after reading or writing a byte, but the
ISD5216 also uses flow control by holding the clock line (SCL) low
until the chip is ready to transmit data,
For example, the sequence of sending the slave address will be as
follows:
1. Send one byte 10000000 {Slave Address, R/W = 0} 80h.
Conventions used in I2C Data
Transfer Diagrams
S
= START Condition
P
= STOP Condition
DATA = 8 bit data transfer
2. Slave ACK.
3. Next time the clock is pulled high by the master, wait for SCL
to actually go high.
7.10.2. POWER-UP SEQUENCE
This sequence prepares the ISD5216 for an operation to follow, and
waits for the Tpud time before sending the next command sequence.
1.
2.
3.
4.
S
R
= “1” in the R/W bit
W
= “0” in the R/W bit
A
= ACK (Acknowledge)
N
= No ACK
2
Send I C Start.
Send one byte 10000000 {Slave Address, R/W = 0} 80h.
Send one byte 10000000 {Command Byte = Power Up} 80h.
Send I2C Stop.
SLAVE ADDRESS
W
A
A
P
SLAVE ADDRESS
= 7 bit Slave
Address
The Box color indicates the
direction of data flow
= Host to Slave (Gray)
Power up (80h)
= Slave to Host (White)
7.10.3. Read Status command
The read status command is a read request from the Host processor to the ISD5216 without
delivering a Command Byte. The Host supplies all of the clocks (SCL). The ISD5216 drives the data
line (SDA). During the read commands, to read status, send the following sequence.
1. Host executes I2C START
2. Send Slave Address with R/W bit = “1” (Read) 81h.
3. Read one byte of data and send ACK, the read data is the status byte
4. Read one byte of data and send ACK, the read data is the upper address byte
5. Read one byte of data and send NACK, the read data is the lower address byte
2
6. Host sends I C STOP
2
Note: The processor could have sent an I C STOP after the Status Word data transfer, and thus aborted the transfer of the
Address bytes
- 42 -
ISD5216
A graphical representation of this operation is found below. See the caption box above for more
explanation.
S
SLAVE ADDRESS
R
A
DATA
A
DATA
A
DATA
High Addr. Byte
Status Word
N
P
Low Addr. Byte
7.10.4. Load Command Byte Register (Single Byte Load):
A single byte may be written to the Command Byte Register in order to power up the device, start or
stop Analog Record (if no address information is needed), or perform a Message Cueing function. The
Command Byte Register is loaded as follows:
S
SLAVE ADDRESS
1.
Host executes I2C START.
2.
Send Slave Address with R/W bit = “0” (Write) [80h].
3.
Host sends a command byte to Slave.
4.
Host executes I2C STOP.
W
A
DATA
A
P
Command Byte
7.10.5. Load Command Byte Register (Address Load):
For the normal addressed mode the Registers are loaded as follows:
1.
Host executes I2C START.
2.
Send Slave Address with R/W bit = “0” (Write).
3.
Host sends a byte to Slave - (Command Byte).
4.
Host sends a byte to Slave - (High Address Byte).
5.
Host sends a byte to Slave - (Low Address Byte).
6.
Host executes I2C STOP.
S
SLAVE ADDRESS
W
A
DATA
Command
A
DATA
A
High Addr. Byte
- 43 -
DATA
A
P
Low Addr. Byte
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
7.10.6. Digital Erase
Host executes I2C START.
Send Slave Address with /W bit = “0” (Write).
Send Digital Erase command (d1h)
Send high address byte (00h)
Send low address byte (a0h) - erase row 5 in this example. Erase operations must be
addressed on a page boundary. The 5 LSB bits of the Low Address Byte will be
ignored.
Host executes I2C STOP.
Wait until the desired number of pages have been erased. There will be a pulse on the RAC
pin for each page that is erased. After the stop command (described below) has been
received, erasing will stop at the end of the page currently being erased. To erase one page
only, issue the stop command immediately after the start erase command.
Host executes I2C START.
Send Slave Address with /W bit = “0” (Write).
Send the Stop command (c0h).
Host executes I2C STOP
Erase starts on falling
edge of Slave
acknowledge
S
SLAVE ADDRESS
W
A
D1h
Command Byte
"N" RAC cycles
Last erased row
Note 3.
Note 4.
A
DATA
A
High Addr. Byte
S
DATA
A
P
Note 2
Low Addr. Byte
SLAVE ADDRESS
W
A
80h
A
P
Command Byte
Notes:
1. I2C bus is released while erase proceeds. Other devices may use the bus until it is
time to execute the STOP command that causes the end of the Erase operation.
2. Host processor must count RAC cycles to determine where the chip is in the erase
process, one row per RAC cycle. RAC pulses LOW for 0.25 microsecond at the end of
each erased row. The erase of the “next” row begins with the rising edge of RAC.
See the Digital Erase RAC timing diagram on page 46.
3. 4.When the erase of the last desired row begins, the following STOP command
(Command Byte = 80 hex) must be issued. This command must be completely given,
including receiving the ACK from the Slave before the RAC pin goes HIGH .25
microseconds before the end of the row .
- 44 -
ISD5216
8.
7.10.7. Digital Write
Send I2C START.
Send Slave Address with /W bit = “0” (Write).
Send Digital Write command (c9h)
Send high address byte (00h)
Send low address byte (a0h) - erase row 5 in this example.
Write all bytes that needs to be written
Send I2C STOP.
Read status byte, see example above, until ready bit is set.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
7.10.8. Digital Read
Send I2C START.
Send Slave Address with /W bit = “0” (Write).
Send Digital Read command (e1h)
Send high address byte (00h)
Send low address byte (a0h) - erase row 5 in this example.
Send I2C START.
Send Slave Address with /W bit = “1” (Read).
Send I2C Read commands until all bytes have been read.
After the last byte has been read, send NACK.
Send I2C STOP.
1.
2.
3.
4.
5.
6.
7.
7.10.9. Feed Through Mode
To set up the device for the various paths requires loading the three 16-bit Configuration Registers
with the correct data. For example, in the Feed Through Mode, the device only needs to be powered
up and a few paths selected. This mode enables the ISD5216 to connect to a cellular or cordless
baseband phone chip set without affecting the audio source or destination. There are two paths
involved: the transmit path and the receive path. The transmit path connects the Winbond chip’s
microphone source through to the digital audio input on the baseband chip set. The receive path
connects the baseband chip set’s digital output through to the speaker driver on the Winbond chip.
This allows the Winbond chip to substitute for Analog to Digital and Digital to Analog conversion, and
incidentally gain access to the audio, both to and from the baseband chip set.
To setup the environment described above, a series of commands need to be sent to the ISD5216.
First, the chip needs to be powered up as described in Power-Up Sequence on page 25. Then the
Configuration Registers need to be filled with the specific data to connect the desired paths. In the
case of the Feed Through Mode, most of the chip can remain powered down. The Feed Through
Mode diagram illustrates the affected paths.
The following example shows the setup for a full-duplex feed-through path at 8 kHz sampling rate. The
twos complement data format is enabled. The High Pass filter is also enabled. The Master Clock input
is running at 13.824MHz.
To select the Feed Through mode, the following control bits must be configured in the ISD5216
configuration register
- 45 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
FILTO+
SDIO
1
(I2S0)
2
(LAW1,LAW0)
DAO+
Output
GAIN
DAC
SUM2VOL-
3
Spkr.
AMP
AMP
DAO-
3
(DAPD,HSR0,MUTE) (COG2,COG1,COG0)
FILTO-
SP+
SP-
2
(OPA1,O PA0)
2
(OPS1,O PS0)
μ/A-Law
Compressor
2
(LAW1,LAW0)
Input
GAIN
ADC
4
(ADPD,HSR0,HPF0,MUTE)
3
(CIG2,CIG1,CIG0)
CODEC In Mux
SCK
μ/A-Law
Expander
MUX
WS
PCM Interface
SDI
SPEAKER
Output
VOL+
SUM2+
SUM2+
INP+
MIC+
MIC INPSUM2-
2
(CDI1,CDI0)
1. Connect the microphone to the CODEC input - Bits CDI1 and CDI0 control the state of the
CODEC INPUT MUX. These are the D6 and D5 bits, respectively, of Configuration Register 0
(CFG0) and they should be set to ONE and ZERO.
2. Power up the ADC—Bit ADPD controls the power up state of ADC. This is bit D0 of CFG2
and it should be a ZERO to power up the ADC.
3. Set the CODEC input gain - The input gain setting will depend on the input level at the
MIC+/- pins and can be set by the CODEC INPUT GAIN Bits CIG2, CIG1 and CIG0. These
are the D15, D14 and D13 bits, respectively, of Configuration Register 0 (CFG0).
4. Set audio interface - Set the interface mode to PCM-interface by setting bit I2S0, bit D4 of
CFG2, to ZERO. This will also enable full duplex mode.
5. Set data format- Set the digital data format through bits LAW1 and LAW0. These are bits D3
and D2 of CFG2, respectively.
6. Set Master Clock Division - Set the Master Clock division ratios as described in Set Master
Clock Division Ratio on page 25.
7. Power up the DAC — Bit DAPD controls the power up state of the DAC. This is bit D1 of
CFG2 and should be a ZERO to power up the DAC.
8. Send DAC output to speaker - Select the DAC path through the OUTPUT MUX—Bits OPS0
and OPS1 control the state of the OUTPUT MUX. These are bits D3 and D4, respectively, of
CFG0 and they should be set to the state where D3 is ONE and D4 is ZERO to select the
DAC path.
9. Power up the Speaker Amplifier—Bits OPA0 and OPA1 control the state of the Speaker
and AUX amplifiers. These are bits D1 and D2, respectively, of CFG0. They should be set to
the state where D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and
configures it for a higher gain setting (for use with a piezo speaker element) and also powers
down the AUX output stage.
- 46 -
ISD5216
10. Power down the Volume Control Element—Bit VLPD controls the power up state of the
Volume Control. This is bit D0 of CFG0 and it should be set to a ONE to power down this
stage.
11. Power down the internal oscillator—Bit PDOS controls the power up state of the internal
ChipCorder oscillator. This is bit D8 of CFG0 and it should be set to a ONE to power down
this oscillator
12. Power down the AUX IN amplifier—Bit AXPD controls the power up state of the AUX IN
input amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this
stage.
13. Power down the SUM1 and SUM2 Mixer amplifiers—Bits S1M0 and S1M1 control the
SUM1 mixer and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in
CFG1, and bits D5 and D6 in CFG1, respectively. All four bits should be set to a ONE in order
to power down these two amplifiers.
14. Power down the FILTER stage—Bit FLPD controls the power up state of the FILTER stage
in the device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage.
15. Power down the AGC amplifier—Bit AGPD controls the power up state of the AGC
amplifier. This is bit D0 in CFG1 and should be set to a ONE to power down this stage.
16. Don’t Care bits—All other bits are not used in Feed Through Mode. Their bits may be set to
either level. In this example, we will set all the "Don’t Care" bits to a ZERO.
This setup should result in the following configuration register values:
CFG0=0010 0101 0100 1011 (hex 254B)
CFG1=0000 0001 1110 0011 (hex 01E3).
CFG2=0000 0000 0100 0000 (hex 0040).
The three registers must be loaded with CFG0 first followed by CFG1 and CFG2. The internal set up
for these registers will take effect synchronously, with the rising edge of SCL.
- 47 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
7.10.10. Call Record
The call record mode adds the ability to record the incoming phone call. In most applications, the
ISD5216 would first be set up for Feed Through Mode as described above. When the user wishes to
record the incoming call, the set up of the chip is modified to add that ability. For the purpose of this
explanation, we will use the 6.4 kHz ChipCorder sample rate during recording.
The block diagram of the ISD5216 shows that the Multilevel Storage array is always driven from the
SUM2 SUMMING amplifier. The path traces back from there, through the LOW PASS Filter, the
FILTER MUX, the SUM1 SUMMING amplifier, the SUM1 MUX, back to the origin CODEC. Feed
Through Mode has already powered up the CODEC, so we only need to power up and enable the
path to the Multilevel Storage array from that point:
1. Setup the feed through mode described in the previous section
2. Select the CODEC path through the SUM1 MUX—Bits S1S0 and S1S1 control the state of
the SUM1 MUX. These are bits D9 and D10, respectively, of CFG1 and they should be set to
the state where both D9 and D10 are ZERO to select the CODEC path.
3.
Select the SUM1 MUX input (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1
control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8, respectively, of
CFG1 and they should be set to the state where D7 is ONE and D8 is ZERO to select the
SUM1 MUX (only) path.
4. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls
the state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the
SUM1 SUMMING amplifier path.
5. Deselect the signal compression-Bit AMT0 controls the signal compression. This is bit D7
of CFG0 and it must be set to ZERO.
6. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
7. Select the 6.4 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 6.4 kHz sample rate, D2 must be set to ONE and D3 set to ZERO.
8. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier—Bits S2M0 and
S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6,
respectively, of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE
to select the LOW PASS FILTER (only) path.
The configuration settings in the call record mode are:
CFG0=0100 0100 0000 1011 (hex 440B).
CFG1=0000 0000 1100 0101 (hex 00C5).
CFG2=0000 0000 0100 0000 (hex 0040).
- 48 -
ISD5216
7.10.11. Memo Record
The Memo Record mode sets the chip up to record from the local microphone into the chip’s Multilevel
Storage Array. A connected cellular telephone or cordless phone chip set may remain powered down
since they are not active in this mode. The path to be used is microphone input to AGC amplifier, then
through to the INPUT SOURCE MUX, to the SUM1 SUMMING amplifier. From there, the path goes
through the FILTER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the
MULTILEVEL STORAGE ARRAY. In this example, we will select the 5.3 kHz sample rate. The rest of
the chip may be powered down.
1. Power up the AGC amplifier - Bit AGPD controls the power up state of the AGC amplifier. This is
bit D0 of CFG1 and must be set to ZERO to power up this stage.
2. Select the AGC amplifier through the INPUT SOURCE MUX—Bit INS0 controls the state of the
INPUT SOURCE MUX. This is bit D9 of CFG0 and must be set to a ZERO to select the AGC amplifier.
3. Select the INPUT SOURCE MUX (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1
control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8, respectively, of
CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the INPUT
SOURCE MUX (only) path.
4. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the
state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1
SUMMING amplifier path.
5. Deselect the signal compression-Bit AMT0 controls the signal compression. This is bit D7 of
CFG0 and it must be set to ZERO.
6. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
7. Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE.
8. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier – BITS S2M0 and
S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6,
respectively, of CFG1, set D5 to ZERO and D6 to ONE to select the LOW PASS FILTER (only)
path.
9. Power up the Internal Oscillator—Bit OSPD controls the power up state of the Internal
Oscillator. This is bit D8 of CFG0 and it must be set to ZERO to power up the Internal Oscillator.
To set up the chip for Memo Record, the configuration registers are set up as follows:
CFG0=0000 0100 0000 0001 (hex 0401).
CFG1=0000 0001 0100 1000 (hex 0148).
CFG2=0000 0000 0000 0011 (hex 0003).
- 49 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
7.10.12. Memo and Call Playback
This mode sets the chip up for local playback of recorded messages. The playback path is from the
MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage. From
there, the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX, through the
VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are driving a piezo
speaker element and that this audio was recorded at 8 kHz. All unnecessary stages will be powered
down.
1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX—Bit FLS0, the
state of the FILTER MUX. This is bit D4 of CFG1 and must be set to ONE
2. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO.
3. Select the 8.0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable 8.0 kHz sample rate, D2 and D3 must be set to ZERO.
4. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier —Bits S2M0 and
S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6, respectively,
of CFG1. Set D5 to ZERO and D6 to ONE to select the LOW PASS FILTER (only) path.
5. Select the SUM2 SUMMING amplifier path through the VOLUME MUX—Bits VLS0 and VLS1
control the VOLUME MUX stage. These bits are D14 and D15, respectively, of CFG1. Set D14 to
ONE and D15 to ZERO to select the SUM2 SUMMING amplifier.
6. Power up the VOLUME CONTROL LEVEL—Bit VLPD controls the power-up state of the
VOLUME CONTROL attenuator. This is Bit D0 of CFG0. Set this bit to a ZERO.
7. Select a VOLUME CONTROL LEVEL—Bits VOL0, VOL1 and VOL2 control the state of the VOLUME CONTROL LEVEL. These are bits D11, D12, and D13, respectively, of CFG1. A binary
count of 000 through 111 controls the amount of attenuation through that stage. To set an
attenuation of –12 dB, D11 should be set to ONE, D12 should be set to ONE, and D13 should be
set to a ZERO.
8. Select the VOLUME CONTROL path through the OUTPUT MUX—These are bits D3 and D4,
respectively, of CFG0. Set D3 to ZERO and D4 is a ZERO to select the VOLUME CONTROL.
9. Power up the SPEAKER amplifier and select the HIGH GAIN mode—Bits OPA0 and OPA1
control the state of the speaker (SP+ and SP–) and AUX OUT outputs. These are bits D1 and D2
of CFG0. Set D1 to ONE and D2 to ZERO to power-up the speaker outputs in the HIGH GAIN
mode and to power-down the AUX OUT.
10. Power up the Internal Oscillator—Bit OSPD controls the power up state of the Internal
Oscillator. This is bit D8 of CFG0 and it must be set to ZERO to power up the Internal Oscillator.
To set up the chip for Memo or Call Playback, the configuration registers are set up as follows:
CFG0 = 0010 0100 0010 0010 (hex 2422).
CFG1 = 0101 1001 1101 0001 (hex 59D1).
CFG2 = 0000 0000 0000 0011 (hex 0003).
- 50 -
ISD5216
7.11. SAMPLE PC LAYOUT FOR PDIP
The PDIP package is illustrated from the top. PC board traces and the three chip capacitors are on
the bottom side of the board.
Note 2
1
C1
V
C
C
D
C2
MCLK
V
S
S
D
Note 3
Note 1
VSSA
(Digital Ground)
C1=C2=C3=0.1 uF chip Capacitors
Note 1: VSSD traces should be kept
separated back to the VSS supply feed
point.
Note 2: VCCD traces should be kept
separated back to the VCC supply feed
point.
Note 3: The Digital and Analog grounds
tie together at the power supply. The
VCCA and VCCD supplies will also need
filter capacitors (typ. 50 to 100 uF).
C3
To
VCCA
Analog Ground
- 51 -
Note 3
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
8. TIMING DIAGRAMS
2
I C TIMING DIAGRAM
STOP
START
t
t
t
f
r
SU;DAT
SDA
SCL
t
t
f
HIGH
t
t
LOW
SU;STO
t
SCLK
PLAYBACK AND STOP CYCLE
tSTOP
tSTART
SDA
PLAY AT ADDR
STOP
SCL
DATA CLOCK PULSES
STOP
AUX IN
AUX OUT
- 52 -
ISD5216
Example of power up command ON THE I2C BUS
- 53 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
I2C INTERFACE TIMING
STANDARD-MODE
FAST-MODE
SYMBOL
MIN.
MAX.
MIN.
MAX.
UNIT
fSCL
0
100
0
400
kHz
tHD; STA
4.0
-
0.6
-
ns
LOW period of the SCL clock
tLOW
4.7
-
1.3
-
ns
HIGH period of the SCL clock
tHIGH
4.0
-
0.6
-
ns
tSU; STA
4.7
-
0.6
-
ns
tSU; DAT
250
-
100(1)
-
ns
tr
-
1000
20 + 0.1Cb(2)
300
ns
(2)
300
ns
PARAMETER
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
Set-up time
condition
for
a
repeated
START
Data set-up time
Rise time of both SDA and SCL signals
tf
-
300
tSU; STO
4.0
-
0.6
-
ns
Bus-free time between a STOP and
START condition
tBUF
4.7
-
1.3
-
ns
Capacitive load for each bus line
Cb
-
400
-
400
pF
Noise margin at the LOW level for each
connected device (including hysteresis)
VnL
0.1 VDD
-
0.1 VDD
-
V
Noise margin at the HIGH level for each
connected device (including hysteresis)
VnH
0.2 VDD
-
0.2 VDD
-
V
Fall time of both SDA and SCL signals
Set-up time for STOP condition
1.
20 + 0.1Cb
A Fast-mode I2C-interface device can be used in a Standard-mode I2C-interface system, but the
requirement tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line; tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode
I2C -interface specification) before the SCL line is released.
2.
Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times
are allowed.
- 54 -
ISD5216
I2S TIMING DIAGRAMS
- 55 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
CODEC Parameters
The internal CODEC meets the specification of the ITU-T G.714 recommendation in 8 kHz sampling
mode. This specification is verified, using the MIC+/- and SPEAKER+/- pins as analog input and
output.
The CODEC μ/A-Law Compander meets the specification of the ITU-T G.711 μ/A-Law companding
recommendation
Symbol
Parameters
Min
Typ
Max
Units
Conditions
Vrms
0 dBm0 = -2.5dBm @ 600 Ω
2
Vpp
Mic+/Mic- differential
LABS
Absolute level
TXMAX
Max. Transmit level
fch1
High
pass
frequency
filter
cut-off
300
Hz
@WS=8kHz,
MCLK=13.824MHz
fcl1
Low
pass
frequency
filter
cut-off
3400
Hz
@WS=8kHz,
MCLK=13.824MHz
fcl2
Low
pass
frequency
filter
cut-off
4686
5037
5100
Hz
@ WS=44.1kHz
MCLK=20.48MHz
ΔfMCLK
Master
clock
accuracy
frequency
-500
0
+500
ppm
DMCLK
Master Clock Duty Cycle
48
50
52
%
I2S PARAMETERS (all values in nano seconds)
Parameter
Bit Clock period T
Transmitter
Receiver
Lower Limit
Upper Limit
Lower Limit
Upper Limit
MIN
MIN
MIN
MIN
MAX
MAX
325
MAX
325
High time tHC
114
114
Low time tLC
114
114
Rise time tRC
49
Delay tdtr
Hold time thtr
260
100
Set-up time tsr
65
Hold time thr
0
- 56 -
MAX
NOTE
S
–
48kHz,
ISD5216
- 57 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
- 58 -
ISD5216
PCM PARAMETERS
PARAMETER
Bit Clock Frequency
Bit Clock Duty Cycle
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1/TSCK
SCK
64
---
3072
kHz
DC
SCK
---
50
---
%
Word Sync. Frequency
1/TWSl
WS @ low rate
---
8000
---
Hertz
Word Sync. Frequency
1/TWSh
WS @ high rate
44.1
---
48
kHz
TIR
SCK,SDI,SDIO,WS
---
---
50
nsec
Rise Time
Fall Time
TIF
SCK,SDI,SDIO,WS
---
---
50
nsec
THLD
SCK low to WS low
50
---
---
nsec
TXS
SCK to WS
20
---
---
nsec
TSX
WS to SCK
100
---
---
nsec
TRS
SCK to WS
20
---
---
nsec
TSR
WS to SCK
100
---
---
nsec
Setup Time for SDI valid
TSTSDI
---
20
---
---
nsec
Hold Time for SDI valid
THDSDI
---
50
---
---
nsec
Output Delay Time for SDIO
valid
TDV
SCK to SDIO
10
---
120
nsec
Output Delay Time for SDIO
High Impedance
TDHI
SCK to SDIO
10
---
120
nsec
Hold Time for 2
clock
nd
cycle of Bit
Transmit Sync. Timing
Receive Sync. Timing
- 59 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
9. ABSOLUTE MAXIMUM RATINGS
ABSOLUTE MAXIMUM RATINGS (Packaged Parts) [1]
Condition
Value
Junction temperature
1500C
Storage temperature range
-650C to +1500C
Voltage Applied to any pin
(VSS - 0.3V) to (VCC + 0.3V)
Voltage applied to any pin (Input current limited to +/-20 mA)
(VSS – 1.0V) to (VCC + 1.0V)
Lead temperature (soldering
3000C
– 10 seconds)
VCC - VSS
-0.3V to +5.5V
[1] Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
OPERATING CONDITIONS (Packaged Parts)
Condition
Commercial operating temperature range
Value
[1]
0
0
0 C to +70 C
[1]
-200C to +700C
Industrial operating temperature [1]
-400C to +850C
Supply voltage (VCC) [2]
+2.7V to +3.3V
Extended operating temperature
Ground voltage (VSS)
[1]
Case temperature
[3]
0V
[2]
VCC = VCCA = VCCD
- 60 -
[3]
VSS = VSSA = VSSD
ISD5216
10. ELECTRICAL CHARACTERISTICS
General Parameters
Min [2]
Typ [1]
Max [2]
Unit
s
VCC x
0.2
V
Symbol
Parameters
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
SCL, SDA, SDIO Output Low
Voltage
0.4
V
IOL = 3 mA
VOL1
RAC, INT Output Low Voltage
0.4
V
IOL = 1 mA
VOH
Output High Voltage
V
IOL = -10 μA
ICC
VCC Current (Operating)
VCC x 0.8
Conditions
V
VCC – 0.4
- Playback & A/D + D/A
30
50
mA
No Load [3]
- Record & A/D + D/A
36
56
mA
No Load [3]
- CODEC A/D + D/A
20
30
mA
No Load [3]
ISB
VCC Current (Standby)
1
10
μA
[3]
IIL
Input Leakage Current
+/-1
μA
[1]
Typical values: TA = 25°C and Vcc = 3.0 V.
[2]
All min/max limits are guaranteed by Winbond via electrical
characterization. Not all specifications are 100 percent tested.
[3]
VCCA and VCCD summed together.
- 61 -
testing
or
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
TIMING PARAMETERS
Symbol
Parameters
FS
Sampling Frequency
FCF
TREC
TPLAY
TPUD
TSTOP OR PAUSE
Min [2]
Typ [1]
Max [2]
Units
Conditions
8.0
kHz
[5]
6.4
kHz
[5]
5.3
kHz
[5]
4.0
kHz
[5]
8.0 kHz (sample rate)
3.7
kHz
Knee Point [3][7]
6.4 kHz (sample rate)
2.9
kHz
Knee Point [3][7]
5.3 kHz (sample rate)
2.5
kHz
Knee Point [3][7]
4.0 kHz (sample rate)
1.8
kHz
Knee Point [3][7]
8.0 kHz (sample rate)
8.05
min
[6]
6.4 kHz (sample rate)
10.06
min
[6]
5.3 kHz (sample rate)
12.15
min
[6]
4.0 kHz (sample rate)
16.1
min
[6]
8.0 kHz (sample rate)
8.05
min
[6]
6.4 kHz (sample rate)
10.06
min
[6]
5.3 kHz (sample rate)
12.15
min
[6]
4.0 kHz (sample rate)
16.1
min
[6]
8.0 kHz (sample rate)
1
msec
6.4 kHz (sample rate)
1
msec
5.3 kHz (sample rate)
1
msec
4.0 kHz (sample rate)
1
msec
8.0 kHz (sample rate)
32
msec
6.4 kHz (sample rate)
40
msec
5.3 kHz (sample rate)
48
msec
4.0 kHz (sample rate)
64
msec
Filter Knee
Record Duration
Playback Duration
Power-Up Delay
Stop or Pause
Record or Play
- 62 -
ISD5216
Symbol
Parameters
TRAC
RAC Clock Period
TRACLO
TRACM
TRACML
Min (2)
Max (2)
Units
Conditions
8.0 kHz (sample rate)
256
msec
[9]
6.4 kHz (sample rate)
320
msec
[9]
5.3 kHz (sample rate)
386
msec
[9]
4.0 kHz (sample rate)
512
msec
[9]
8.0 kHz (sample rate)
8
msec
6.4 kHz (sample rate)
10
msec
5.3 kHz (sample rate)
12.1
msec
4.0 kHz (sample rate)
16
msec
8.0 kHz (sample rate)
500
msec
6.4 kHz (sample rate)
625
msec
5.3 kHz (sample rate)
750
msec
4.0 kHz (sample rate)
1000
msec
15.6
msec
19.5
msec
23.4
msec
31.2
msec
RAC Clock Low Time
RAC Clock Period
Message Cueing Mode
in
RAC Clock Low Time in
Message Cueing Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
THD
Typ (1)
Total Harmonic Distortion
AUX IN to ARRAY,
1
2
ARRAY to SPKR
1
2
- 63 -
%
%
@1 KHz at 0TLP,
sample rate = 5.3
KHz
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
ANALOG PARAMETERS
MICROPHONE INPUT [14]
Min (2)
Symbol
Parameters
VMIC+/-
MIC +/- Input Voltage
VMIC (0TLP)
MIC +/- input reference
transmission level point
(0TLP)
AMIC (GT)
MIC +/- Gain Tracking
RMIC
Microphone input resistance
AAGC
Microphone AGC Amplifier
Range
VMICBS
Microphone Bias Voltage
RMICBS
MICBS Output Resistance
Typ( 1)(14)
Max (2)
Units
300
mV
Peak-to-Peak [4][8]
208
mV
Peak-to-Peak [4][10]
+/-0.1
dB
1 kHz, +3 to –40 dB
0TLP Input
10
kΩ
MIC- and MIC+ pins
dB
Over 3-300 mV Range
2.2
V
IMICBS = 0.0 mA
700
Ω
6
40
Conditions
AUX IN [14]
Symbol
Min (2)
Parameters
VAUX IN
AUX IN Input Voltage
VAUX IN (0TLP)
AUX IN
Voltage
AAUX IN (GA)
AUX IN Gain Accuracy
AAUX IN (GT)
AUX IN Gain Tracking
RAUX IN
AUX IN Input Resistance
(0TLP)
Input
Max (2)
Units
Conditions
1.0
V
Peak-to-Peak
gain setting)
(0
dB
mV
Peak-to-Peak
gain setting)
(0
dB
dB
[11]
+/-0.1
dB
1000 Hz, +3 to –45 dB
0TLP Input, 0 dB setting
10 to 100
kΩ
Depending on AUX IN
Gain
Typ
(1)(14)
694.2
-0.5
- 64 -
+0.5
ISD5216
SPEAKER OUTPUTS [14]
Symbol
Min [2]
Parameters
VSPHG
SP+/- Output Voltage (High
Gain Setting)
RSPLG
SP+/- Output
(Low Gain)
Load
Imp.
8
RSPHG
SP+/- Output
(High Gain)
Load
Imp.
70
CSP
SP+/- Output Load Cap.
VSPAG
SP+/- Output Bias Voltage
(Analog Ground)
VSPDCO
Speaker Output DC Offset
PSRR
Power
Ratio
FR
Frequency Response (3003400 Hz)
-0.25
POUTLG
Power Output (Low Gain
Setting)
23.5
Supply
Typ [1][14]
Max [2]
Units
3.6
V
Peak-to-Peak,
differential load = 150Ω,
OPA1, OPA0 = 01
Ω
OPA1, OPA0 = 10
Ω
OPA1, OPA0 = 01
150
100
1.2
pF
VDC
+/-100
Rejection
Conditions
-55
+0.25
mV
DC
With CODEC D/A IN to
Speaker.
dB
Measured with a 1 kHz,
100 map sine wave
input at VCC and VCC
pins
dB
With 0TLP input to AUX
IN, 6 dB setting (12)
mW
RMS
Differential load at 8Ω
Max [2]
Units
Conditions
1.0
V
AUX OUT [14]
Min [2]
Symbol
Parameters
VAUX OUT
AUX OUT – Maximum
Output Swing
RL
Minimum Load Impedance
CL
Maximum
Capacitance
VBIAS
AUX OUT
Typ [1][14]
5
5kΩ Load
KΩ
Load
100
1.2
- 65 -
pF
VDC
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
VOLUME CONTROL [14]
Symbol
Parameters
AOUT
Output Gain
Absolute Gain
Min [2]
Typ [1][14]
Max [2]
-28 to 0
-0.5
+0.5
Units
Conditions
dB
8 steps of 4 dB,
referenced to output
dB
AUX IN 1.0 kHz 0TLP,
6 dB gain setting
measured differentially
at SP+/-
[1] Typical values: TA = 25°C and Vcc = 3.0V.
[2] All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not
all specifications are 100 percent tested.
[3] Low-frequency cut off depends upon the value of external capacitors (see Pin
Descriptions).
[4] Differential input mode. Nominal differential input is 208 mV p-p. (0TLP)
[5] Sampling frequency can vary as much as –6/+4 percent over the industrial temperature
and voltage ranges. For greater stability, an external clock can be utilized (see Pin
Descriptions).
[6] Playback and Record Duration can vary as much as –6/+4 percent over the industrial
temperature and voltage ranges. For greater stability, an external clock can be utilized
(see Pin Descriptions).
[7] Filter specification applies to the low pass filter.
[8] For optimal signal quality, this maximum limit is recommended.
[9] When a record command is sent, TRAC = TRAC + TRACLO on the first page addressed.
[10] The maximum signal level at any input is defined as 3.17 dB higher than the reference
transmission level point. (0TLP) This is the point where signal clipping may begin.
[11] Measured at 0TLP point for each gain setting. See AUX IN table.
[12] 0TLP is the reference test level through inputs and outputs. See AUX IN table.
[13] Referenced to 0TLP input at 1 kHz, measured over 300 to 3,400 Hz bandwidth.
[14] For die, only typical values are applicable.
- 66 -
ISD5216
11. TYPICAL APPLICATION CIRCUIT
APPLICATIONS
The ISD5216 is a single chip solution for voice and analog storage that also includes the capability to
store digital information in the memory array. The array may be divided between analog and digital
storage, as the user chooses, when configuring the device.
Looking at the block diagram on the following page, one can see that the ISD5216 may be very easily
designed into a cellular phone. Placing the device between the microphone and the existing baseband
chip takes care of the transmit path. The SDI/SDIO of the baseband chip is connected to the
SDIO/SDI of the ISD5216. Two pins are needed for the I2C digital control and digital information for
storage.
INT
SCL
SDA
Starting at the MICROPHONE inputs, the input signal at the MICROPHONE inputs can be routed in
the following ways:
•
directly through the Voice band CODEC of the ISD5216 chip, then through the SDIO pin, to
output the digital PCM signal.
•
through the AGC amplifier, before it is routed to the voice band CODEC.
•
through the AGC amplifier to the storage array
•
through the AGC amplifier and mixed with an analog voice band CODEC signal coming from
the digital SDI pin
In addition, if the phone is inserted into a "hands-free" car kit, then the signal from the pickup
microphone in the car can be passed through to the same places from the AUX IN pin and the
phone's microphone is switched off. In this scenario, the other party's voice from the phone would be
played into the PCM IN input and passed through to the AUX OUT pin that would drive the car kit's
loudspeaker.
- 67 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
Depending upon whether one desires recording one side (simplex) or both sides (duplex) of a
conversation, the various paths will also be switched through to the low pass filter (for antialiasing)
and into the storage array. Later, the cell phone owner can play back the messages from the array.
When this happens, the Array Output MUX is connected to the volume control, through the Output
MUX, to the Speaker Amplifier. For applications other than a cell phone, the audio paths can be
switched into many different and flexible configurations. Some examples follow.
TRANSFORMER APPLICATION
To Microcontroller
2
I C interface and
Vcc
Address setting
.1μF
.1μF
3
4
5
6
7
8
9
1.5kΩ
.1μF
Electret Microphone
10
11
12
13
14
WM-54B Panasonic
.1μF
1.5kΩ
1
2
1μF
VCCD
VCCD
SCL
MCLK
INT
A1
28
27
26
25
SDA
RAC
A0
SDIO 24
23
22
ISD5216
VSSA
WS 21
MIC+
SCK 20
MICNC 19
18
MICBS
AUX OUT
ACAP
AUX IN 17
16
VCCA
SP15
VSSD
SDI
VSSD
VSSA
SP+
VSSA
600Ω
PDIP
N=1
TIP
N=1
600Ω
- 68 -
4.7KΩ
4.7KΩ
RING
13.824 MHz
Vcc
Vcc
PCM OUT
PCM IN
8 KHz
2.048 MHz
TO AUXILIARY INPUT
.1μF
.1μF
ISD5216
HANDSET APPLICATION
To Microcontroller
2
I C interface and
Vcc
Address setting
.1μF
.1μF
1.5kΩ
.1μF
1
2
3
4
5
6
7
8
9
Electret Microphone
10
11
12
13
14
WM-54B Panasonic
.1μF
1.5kΩ
.1μF
VCCD
VCCD
28
MCLK 27
SCL
INT 26
RAC 25
SDIO 24
23
SDI
A1
SDA
A0
VSSD
VSSD
ISD5216
VSSA
MIC+
MIC-
4.7KΩ
4.7KΩ
13.824 MHz
Vcc
Vcc
PCM OUT
PCM IN
22
21
WS
20
SCK
19
VSSA
8 KHz
2.048 MHz
NC
AUX OUT 18
MICBS
17
VCCA 16
SP+ 15
ACAP
TO RINGER
AUXILIARY INPUT
AUX IN
SP
VSSA
.1μF
PDIP
RECEIVE
- 69 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
12. PACKAGE SPECIFICATIONG
12.1. PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE E DIMENSIONS
A
A
B
B
G
G
1
22
33
44
55
66
77
88
99
10
10
11
11
12
12
13
13
14
14
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
F
F
C
C
E
E
D
JJ
H
H
I
PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE E DIMENSIONS
INCHES
MILLIMETERS
Min
Nom
Max
Min
Nom
Max
A
0.520
0.528
0.535
13.20
13.40
13.60
B
0.461
0.465
0.469
11.70
11.80
11.90
C
0.311
0.315
0.319
7.90
8.00
8.10
D
0.002
0.006
0.05
E
0.007
0.011
0.17
G
0.037
0
I
0
0.020
J
0.004
H
Note:
0.009
0.0217
F
0.039
0
3
0.022
0.15
0.22
0.27
0.55
0.041
0
0.95
0
6
0.028
0
0.50
0.008
0.10
Lead coplanarity to be within 0.004 inches.
- 70 -
1.00
0
3
0.55
1.05
0
6
0.70
0.21
ISD5216
12.2. PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) DIMENSIONS
28 27 26 25 24 23 22 21 20 19 18 17 16 15
2 3 4 5
1
6 7 8 9 10 11 12 13 14
A
G
C
B
D
E
H
F
Plastic Small Outline Integrated Circuit (SOIC) Dimensions
INCHES
MILLIMETERS
Min
Nom
Max
Min
Nom
Max
A
0.701
0.706
0.711
17.81
17.93
18.06
B
0.097
0.101
0.104
2.46
2.56
2.64
C
0.292
0.296
0.299
7.42
7.52
7.59
D
0.005
0.009
0.0115
0.127
0.22
0.29
E
0.014
0.016
0.019
0.35
0.41
0.48
0.050
F
1.27
G
0.400
0.406
0.410
10.16
10.31
10.41
H
0.024
0.032
0.040
0.61
0.81
1.02
Note:
Lead coplanarity to be within 0.004 inches.
- 71 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
12.3. PLASTIC DUAL INLINE PACKAGE (PDIP) DIMENSIONS
Plastic Dual Inline Package (PDIP) (P) Dimensions
INCHES
A
B1
B2
C1
C2
D
D1
E
F
G
H
J
S
0
Min
1.445
0.065
0.600
0.530
0.015
0.125
0.015
0.055
0.008
0.070
0°
Nom
1.450
0.150
0.070
0.540
0.018
0.060
0.100
0.010
0.075
MILLIMETERS
Max
1.455
Min
36.70
0.075
0.625
0.550
0.19
1.65
15.24
13.46
0.135
0.022
0.065
0.38
3.18
0.38
1.40
0.012
0.080
15°
0.20
1.78
0°
- 72 -
Nom
36.83
3.81
1.78
13.72
0.46
1.52
2.54
0.25
1.91
Max
36.96
1.91
15.88
13.97
4.83
3.43
0.56
1.65
0.30
2.03
15°
ISD5216
13. ORDERING INFORMATION
Winbond Ordering Number Description
I5216 x x x
Product Family
Special Temperature Field:
ISD5216 Product
(8- to 16-minute durations)
Blank
=
Commercial Packaged (0°C to +70°C)
I
=
Industrial (–40°C to +85°C)
Package Option:
Y
= Lead-free
Package Type:
E
=
28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1
S
=
28-Lead 0.300-Inch Plastic Small Outline Package (SOIC)
P
=
28-Lead
0.600-Inch Plastic Dual Inline Package (PDIP)
When ordering, please refer to the above valid part number. Contact the local Winbond Sales
Representative or Distributor for availability information.
For the latest product information, access Winbond’s worldwide website at http://www.winbondusa.com
- 73 -
Publication Release Date: July 17, 2007
Revision B.5
ISD5216
14. VERSION HISTORY
VERSION
DATE
DESCRIPTION
A1
Nov. 2001
Initial issue
B.1
Aug. 2002
Overall updates, not available in die form
B.2
Jun. 2003
Update cover page
Replace all I5216 by ISD5216
B.3
Apr. 2005
Revise disclaim section
B.4
Jan. 2006
Ordering information: add Pb-free option
B.5
Jul. 2007
Remove the leaded package option
Revise the MCLK description
- 74 -
ISD5216
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment
intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or
sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could
result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Winbond for any damages resulting from such improper use or sales.
The contents of this document are provided only as a guide for the applications of Winbond products. Winbond makes no
representation or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice.
No license, whether express or implied, to any intellectual property or other right of Winbond or others is granted by this
publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond assumes no liability
whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or
infringement of any Intellectual property.
The contents of this document are provided “AS IS”, and Winbond assumes no liability whatsoever and disclaims any
express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual
property. In no event, shall Winbond be liable for any damages whatsoever (including, without limitation, damages for
loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this
documents, even if Winbond has been advised of the possibility of such damages.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only
and Winbond makes no representation or warranty that such applications shall be suitable for the use specified.
The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in
the Winbond Reliability Report, and are neither warranted nor guaranteed by Winbond. This product incorporates
SuperFlash®.
Information contained in this ISD® ChipCorder® datasheet supersedes all data for the ISD ChipCorder products
published by ISD® prior to August, 1998.
This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD® ChipCorder®
product specifications. In the event any inconsistencies exist between the information in this and other product
documentation, or in the event that other product documentation contains information in addition to the information in
this, the information contained herein supersedes and governs such other information in its entirety. This datasheet is
subject to change without notice.
Copyright© 2005, Winbond Electronics Corporation. All rights reserved. ChipCorder® and ISD® are trademarks of
Winbond Electronics Corporation. SuperFlash® is the trademark of Silicon Storage Technology, Inc. All other trademarks
are properties of their respective owners.
- 75 -
Publication Release Date: July 17, 2007
Revision B.5
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