74HC165PW,118

74HC165; 74HCT165 8-bit parallel-in/serial out shift register Rev. 5 — 21 August 2017 1 Product data sheet General description The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. 2 Features and benefits • • • • Asynchronous 8-bit parallel load Synchronous serial input Complies with JEDEC standard no. 7A Input levels: – For 74HC165: CMOS level – For 74HCT165: TTL level • ESD protection: – HBM JESD22-A114F exceeds 2000 V – MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3 Applications • Parallel-to-serial data conversion 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register 4 Ordering information Table 1. Ordering information Type number 74HC165D Package Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 -40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 -40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 74HCT165D 74HC165DB 74HCT165DB 74HC165PW 74HCT165PW 74HC165BQ 74HCT165BQ 5 SOT763-1 Functional diagram 1 SRG8 C2[LOAD] G1[SHIFT] 15 10 11 12 13 14 3 4 5 6 1 2 DS D0 10 D1 11 D2 12 D3 13 D4 D6 Q7 D7 Q7 9 3 7 4 2 Product data sheet C3/ 3D 2D 2D 5 PL CP CE 74HC_HCT165 1 14 D5 Figure 1. Logic symbol ≥1 15 9 6 mna985 7 mna986 Figure 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 2 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register 11 12 13 14 3 4 5 6 D0 D1 D2 D3 D4 D5 D6 D7 1 PL 10 DS 2 CP 15 CE 8-BIT SHIFT REGISTER PARALLEL-IN/SERIAL-OUT Q7 9 Q7 7 mna992 Figure 3. Functional diagram 6 Pinning information 6.1 Pinning 1 PL terminal 1 index area CP 2 15 CE D4 3 14 D3 D5 4 13 D2 D6 5 12 D1 D7 6 11 D0 Q7 7 10 DS GND 8 9 4 13 D2 D6 5 12 D1 D7 6 Q7 7 GND(1) 11 D0 10 DS 001aah565 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad.However, if it is soldered, the solder land should remain floating or be connected to GND. Q7 Figure 4. Pin configuration (SO16 and (T)SSOP16) Product data sheet D5 Transparent top view 001aah564 74HC_HCT165 14 D3 9 16 VCC 15 CE 3 8 1 2 D4 Q7 PL CP GND 74HC165 74HCT165 16 VCC 74HC165 74HCT165 Figure 5. Pin configuration (DHVQFN16) All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 3 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register 6.2 Pin description Table 2. Pin description Symbol Pin Description PL 1 asynchronous parallel load input (active LOW) CP 2 clock input (LOW-to-HIGH edge-triggered) Q7 7 complementary output from the last stage GND 8 ground (0 V) Q7 9 serial output from the last stage DS 10 serial data input D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn) CE 15 clock enable input (active LOW) VCC 16 positive supply voltage 7 Functional description Table 3. Function table [1] Operating modes Inputs parallel load serial shift hold "do nothing" [1] Qn registers Outputs PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7 L X X X L L L to L L H L X X X H H H to H H L H L ↑ l X L q0 to q5 q6 q6 H L ↑ h X H q0 to q5 q6 q6 H ↑ L l X L q0 to q5 q6 q6 H ↑ L h X H q0 to q5 q6 q6 H H X X X q0 q1 to q6 q7 q7 H X H X X q0 q1 to q6 q7 q7 H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care; ↑ = LOW-to-HIGH clock transition. 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 4 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register CP CE DS PL D0 D1 D2 D3 D4 D5 D6 D7 Q7 Q7 inhibit serial shift mna993 load Figure 6. Timing diagram 8 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC Conditions supply voltage IIK input clamping current Min Max Unit -0.5 +7 V VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA [1] - ±20 mA - ±25 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V IO output current -0.5 V < VO < VCC + 0.5 V ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C - 500 mW Ptot [1] [2] total power dissipation Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO16 Packages: Ptot derates linearly with 8 mW/K above 70 °C. For (T)SSOP16 Packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN16 Packages: Ptot derates linearly with 4.5 mW/K above 60 °C. 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 5 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register 9 Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC165 74HCT165 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VCC supply voltage VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 - +125 -40 - +125 °C Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 10 Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Min Typ Max Min Max Min Max Unit 74HC165 VIH VIL VOH HIGH-level input VCC = 2.0 V voltage VCC = 4.5 V 1.5 1.2 - 1.5 - 1.5 - V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V LOW-level input VCC = 2.0 V voltage VCC = 4.5 V - 0.8 0.5 - 0.5 - 0.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V HIGH-level output voltage 74HC_HCT165 Product data sheet VI = VIH or VIL All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 6 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register Symbol Parameter VOL LOW-level output voltage Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 μA CI input capacitance - 3.5 - - - - - pF 74HCT165 VIH HIGH-level input VCC = 4.5 V to 5.5 V voltage 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input VCC = 4.5 V to 5.5 V voltage - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 μA ΔICC additional supply per input pin; VI = VCC - 2.1 V; current other inputs at VCC or GND; VCC = 4.5 V to 5.5 V Dn and DS inputs - 35 126 - 157.5 - 171.5 μA CP CE, and PL inputs - 65 234 - 292.5 - 318.5 μA - 3.5 - - - - CI input capacitance 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 - pF © Nexperia B.V. 2017. All rights reserved. 7 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register 11 Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 52 165 - 205 - 250 ns VCC = 4.5 V - 19 33 - 41 - 50 ns VCC = 6.0 V - 15 28 - 35 - 43 ns VCC = 5.0 V; CL = 15 pF - 16 - - - - - ns VCC = 2.0 V - 50 165 - 205 - 250 ns VCC = 4.5 V - 18 33 - 41 - 50 ns VCC = 6.0 V - 14 28 - 35 - 43 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns VCC = 2.0 V - 36 120 - 150 - 180 ns VCC = 4.5 V - 13 24 - 30 - 36 ns VCC = 6.0 V - 10 20 - 26 - 31 ns - 11 - - - - - ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns 74HC165 tpd propagation delay [1] CP or CE to Q7, Q7; see Figure 7 PL to Q7, Q7; see Figure 8 D7 to Q7, Q7; see Figure 9 VCC = 5.0 V; CL = 15 pF tt tW transition time Q7, Q7 output; see Figure 7 pulse width [2] CP input HIGH or LOW; see Figure 7 PL input LOW; see Figure 8 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 8 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register Symbol Parameter trec tsu recovery time set-up time Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 100 22 - 125 - 150 - ns VCC = 4.5 V 20 8 - 25 - 30 - ns VCC = 6.0 V 17 6 - 21 - 26 - ns VCC = 2.0 V 80 11 - 100 - 120 - ns VCC = 4.5 V 16 4 - 20 - 24 - ns VCC = 6.0 V 14 3 - 17 - 20 - ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 5 2 - 5 - 5 - ns VCC = 4.5 V 5 2 - 5 - 5 - ns VCC = 6.0 V 5 2 - 5 - 5 - ns VCC = 2.0 V 5 -17 - 5 - 5 - ns VCC = 4.5 V 5 -6 - 5 - 5 - ns VCC = 6.0 V 5 -5 - 5 - 5 - ns VCC = 2.0 V 6 17 - 5 - 4 - MHz VCC = 4.5 V 30 51 - 24 - 20 - MHz VCC = 6.0 V 35 61 - 28 - 24 - MHz - 56 - - - - - MHz - 35 - - - - - pF PL to CP, CE; see Figure 8 DS to CP, CE; see Figure 10 CE to CP and CP to CE; see Figure 10 Dn to PL; see Figure 11 th hold time DS to CP, CE and Dn to PL; see Figure 10 CE to CP and CP to CE; see Figure 10 fmax maximum frequency CP input; see Figure 7 VCC = 5.0 V; CL = 15 pF CPD power dissipation capacitance 74HC_HCT165 Product data sheet per package; VI = GND to VCC [3] All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 9 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 4.5 V - 17 34 - 43 - 51 ns VCC = 5.0 V; CL = 15 pF - 14 - - - - - ns VCC = 4.5 V - 20 40 - 50 - 60 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns - 14 28 - 35 - 42 ns - 11 - - - - - ns - 7 15 - 19 - 22 ns 16 6 - 20 - 24 - ns 20 9 - 25 - 30 - ns 20 8 - 25 - 30 - ns 20 2 - 25 - 30 - ns 20 7 - 25 - 30 - ns 20 10 - 25 - 30 - ns 7 -1 - 9 - 11 - ns 0 -7 - 0 - 0 - ns 74HCT165 tpd propagation delay [1] CE, CP to Q7, Q7; see Figure 7 PL to Q7, Q7; see Figure 8 D7 to Q7, Q7; see Figure 9 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt transition time Q7, Q7 output; see Figure 7 VCC = 4.5 V tW pulse width [2] CP input; see Figure 7 VCC = 4.5 V PL input; see Figure 8 VCC = 4.5 V trec recovery time PL to CP, CE; see Figure 8 VCC = 4.5 V tsu set-up time DS to CP, CE; see Figure 10 VCC = 4.5 V CE to CP and CP to CE; see Figure 10 VCC = 4.5 V Dn to PL; see Figure 11 VCC = 4.5 V th hold time DS to CP, CE and Dn to PL; see Figure 10 VCC = 4.5 V CE to CP and CP to CE; see Figure 10 VCC = 4.5 V 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 10 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register Symbol Parameter fmax maximum frequency Conditions 25 °C [1] [2] [3] power dissipation capacitance -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 26 44 - 21 - 17 - MHz - 48 - - - - - MHz - 35 - - - - - pF CP input; see Figure 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF CPD -40 °C to +85 °C [3] per package; VI = GND to VCC - 1.5 V tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi + Σ (CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; 2 Σ (CL × VCC × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 11.1 Waveforms and test circuit 1/fmax VI CP or CE input VM GND tW tPHL VOH tPLH 90 % 90 % VM Q7 or Q7 output VOL 10 % tTHL 10 % tTLH mna987 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the maximum clock frequency and the output transition times 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 11 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register VI VM PL input GND tW trec VI CE, CP input VM GND tPHL VOH VM Q7 or Q7 output VOL mna988 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 8. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) recovery time VI VM D7 input GND tPLH tPHL VOH VM Q7 output VOL tPLH tPHL VOH VM Q7 output VOL mna989 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 9. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 12 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register (1) VI VM CP, CE input GND th th tsu tsu VI VM DS input GND tsu tW VI VM CP, CE input GND mna990 (1) CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output performance Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 10. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE) VI Dn input VM VM GND tsu th tsu th VI PL input VM VM GND mna991 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL) Table 8. Measurement points Type Output Input VI VM VM 74HC165 VCC 0.5VCC 0.5VCC 74HCT165 3V 1.3 V 1.3 V 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 13 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI VCC VO DUT RT RL S1 open CL 001aad983 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Figure 12. Test circuit for measuring switching times Table 9. Test data Type Input S1 position Load VI tr, tf CL RL tPHL, tPLH 74HC165 VCC 6 ns 15 pF, 50 pF 1 kΩ open 74HCT165 3V 6 ns 15 pF, 50 pF 1 kΩ open 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 14 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register 12 Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Figure 13. Package outline SOT109-1 (SO16) 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 15 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Figure 14. Package outline SOT338-1 (SSOP16) 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 16 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Figure 15. Package outline SOT403-1 (TSSOP16) 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 17 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm B D A A E A1 c detail X terminal 1 index area terminal 1 index area C e1 e b 2 y y1 C v M C A B w M C 7 L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Figure 16. Package outline SOT763-1 (DHVQFN16) 74HC_HCT165 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 18 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register 13 Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT165 v.5 20170821 Product data sheet - 74HC_HCT165 v.4 Modifications: • Hold time for 74HC165 has been updated. See Paragraph hold time. • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. 74HC_HCT165 v.4 20151228 Modifications: • Type numbers 74HC165N and 74HCT165N (SOT38-4) removed. 74HC_HCT165 v.3 20080314 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Package SOT763-1 (DHVQFN16) added to Section 4 and Section 12. • Family data added, see Section 10 74HC_HCT165_CNV v.2 December 1990 74HC_HCT165 Product data sheet Product data sheet Product data sheet Product specification - - All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 74HC_HCT165 v.3 74HC_HCT165_CNV v.2 - © Nexperia B.V. 2017. All rights reserved. 19 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register 15 Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical 74HC_HCT165 Product data sheet systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 20 / 22 74HC165; 74HCT165 Nexperia 8-bit parallel-in/serial out shift register Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer 74HC_HCT165 Product data sheet design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 21 August 2017 © Nexperia B.V. 2017. All rights reserved. 21 / 22 Nexperia 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 11.1 12 13 14 15 General description ............................................ 1 Features and benefits .........................................1 Applications .........................................................1 Ordering information .......................................... 2 Functional diagram ............................................. 2 Pinning information ............................................ 3 Pinning ............................................................... 3 Pin description ................................................... 4 Functional description ........................................4 Limiting values .................................................... 5 Recommended operating conditions ................ 6 Static characteristics .......................................... 6 Dynamic characteristics .....................................8 Waveforms and test circuit .............................. 11 Package outline .................................................15 Abbreviations .................................................... 19 Revision history ................................................ 19 Legal information .............................................. 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2017. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 21 August 2017 Document identifier: 74HC_HCT165