Winbond Clock Generator
W83195CG-NP
For Intel Napa Platform
Date:
Dec./2007
Revision: 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
W83195CG-NP Datasheet Revision History
Pages
Dates
Version
Web
Version
1
n.a.
11/01/2005
0.5
n.a.
All of the versions before 0.50 are for
internal use.
2
n.a.
01/27/2006
1.0
1.0
All of the versions before 1.0 are
preliminary version.
12/20/2007
1.1
n.a.
Update Winbond logo, and the package
drawing.
3
Main Contents
4
5
6
7
8
9
Please note that all data and specifications are subject to change without notice. All
the trademarks of products and companies mentioned in this data sheet belong to
their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result
in personal injury. Winbond customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
-I-
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
Table of Content1.
GENERAL DESCRIPTION ......................................................................................................... 1
2.
PRODUCT FEATURES .............................................................................................................. 1
3.
PIN CONFIGURATION ............................................................................................................... 2
4.
BLOCK DIAGRAM ...................................................................................................................... 3
5.
PIN DESCRIPTION..................................................................................................................... 4
5.1
Crystal I/O .................................................................................................................................4
5.2
CPU, SRC, and PCIEX, PCI, Clock Outputs ..........................................................................4
5.3
Fixed Frequency Outputs.........................................................................................................5
5.4
I2C Control Interface ................................................................................................................5
5.5
Power Management Pins .........................................................................................................6
5.6
Power Pins................................................................................................................................6
6.
FREQUENCY SELECTION BY HARDWARE ............................................................................ 6
7.
I2C CONTROL AND STATUS REGISTERS ............................................................................... 8
8.
9.
7.1
Register 0: ( Default : FFh )......................................................................................................8
7.2
Register 1: ( Default : FEh ) .....................................................................................................8
7.3
Register 2: ( Default : FFh).......................................................................................................9
7.4
Register 3: ( Default : 00h )..................................................................................................10
7.5
Register 4: ( Default : 87) .......................................................................................................10
7.6
Register 5: ( Default : 00h ) ....................................................................................................11
7.7
Register 6: ( Default : XXh ) ...................................................................................................13
7.8
Register 7: Winbond Chip ID – Project Code Register ( Default : 11h )...............................13
ACCESS INTERFACE .............................................................................................................. 14
8.1
Block Write protocol ...............................................................................................................14
8.2
Block Read protocol ...............................................................................................................14
8.3
Byte Write protocol .................................................................................................................14
8.4
Byte Read protocol .................................................................................................................14
SPECIFICATIONS .................................................................................................................... 15
9.1
ABSOLUTE MAXIMUM RATINGS .......................................................................................15
9.2
General Operating Characteristics ........................................................................................15
9.3
Skew Group timing clock........................................................................................................16
9.4
CPU 0.7V Electrical Characteristics ......................................................................................16
9.5
SRC 0.7V Electrical Characteristics ......................................................................................16
- II -
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
9.6
PCIE 0.7V Electrical Characteristics......................................................................................17
9.7
PCI Electrical Characteristics .................................................................................................17
9.8
48M Electrical Characteristics................................................................................................17
9.9
REF Electrical Characteristics ...............................................................................................18
9.10
DOT 0.7V Electrical Characteristics ......................................................................................18
10.
ORDERING INFORMATION..................................................................................................... 19
11.
TOP MARKING SPECIFICATION ............................................................................................ 19
12.
PACKAGE DRAWING AND DIMENSIONS .............................................................................. 20
- III -
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
1. GENERAL DESCRIPTION
The W83195CG-NP is a CK410M compliant Clock Synthesizer for Intel P4 processors. W83195CG-NP
provides all clocks required for high-speed microprocessor and provides, 8 different frequencies of
CPU, PCI, PCI-Express clocks setting. Simultaneously W83195CG-NP supports DOT 96MHz clock
outputs for integrated graphic chipsets. All clocks are externally selectable with smooth transitions.
The W83195CG-NP programs the registers to enable or disable each clock outputs through I2C serial
bus interface and provides -0.5% spread spectrum or programmable spread spectrum scale to reduce
EMI.
The W83195CG-NP is driven with a 14.318 MHz reference crystal and runs on a 3.3V supply.
2. PRODUCT FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
2 pair 0.7 V current mode Differential clock outputs for CPU
6 pair 0.7V current mode Differential clock outputs for SRC and PCIEX.
1 pair 0.7V current mode Differential clock outputs for SATA.
1 pair 0.7 V current mode Differential clock outputs select for CPUCLK_ITP/SRC.
1 pair 0.7V current mode Differential 96MHz clock outputs for DOT.
4 PCI clock outputs for PCI
2 PCI clock free running outputs for PCI
1 48 MHz clock output for USB.
1 14.318MHz REF clock outputs.
I2C 2-Wire serial interface and support byte read/write and block read/write.
-0.5% spread spectrum
Programmable spread spectrum scale to reduce EMI
Programmable registers to enable/stop each output.
• 56 pin TSSOP package
1
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
3. PIN CONFIGURATION
VDDPCI
GND
PCI3
PCI4
PCI5
GND
VDDPCI
&ITP_EN/PCICLK_F0
PCICLK_F1
Vtt_PWRGd#/PD
VDD48
48MHZ/*FS_A
GND
DOTT_96MHZ
DOTC_96MHZ
&FS_B
SRCT0
SRCC0
SRCT1
SRCC1
VDDSRC
SRCT2
SRCC2
SRCT3
SRCC3
SRCT4_SATA
SRCC4_SATA
VDDSRC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PCI2
PCI/SRC_STOP#
CPU_STOP#
&FS_C
REF
GND
X1
X2
VDDREF
SDATA
SCLK
GND
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
IREF
GNDA
VDDA
CPUCLKT2_ITP/SRCT7
CPUCLKC2_ITP/SRCC7
VDDSRC
SRCT6
SRCC6
SRCT5
SRCC5
GND
#: Active low
*: Internal pull up resistor 120KΩ to VDD
&
: Internal Pull-down resistor 120KΩ to GND
2
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
4. BLOCK DIAGRAM
48MHz
PLL2
Divider
DOTT
DOTC
XIN
XOUT
XTAL
OSC
REF
2
PLL1
Spread
Spectrum
CPUT 0:1
CPUC 0:1
2
VCOCLK
CPUCLKT2_ITP
/SRCT7
CPUCLKC2_ITP
/SRCC7
8
M/N/Ratio
ROM
Divider
8
SRCT 0:6
SRCC 0:6
2
PCI_F 0:1
FS(A:C)
VTT_PWRGD#
SDATA
SCLK
4
PCI 2:5
Control
Logic
&Config
Register
IREF
PCI/SRC_STOP#
CPU_STOP#
PD
&
ITP_EN
Latch
&POR
475
I2C
Interface
3
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
5. PIN DESCRIPTION
Buffer type symbol
Description
IN
Input
IN tp120k
Latched input at power up, internal 120kΩ pull up.
IN td120k
Latched input at power up, internal 120kΩ pull down.
OUT
5.1
Output
OD
Open Drain
I/OD
Bi-directional Pin, Open Drain.
#
Active Low
*
Internal 120kΩ pull-up
&
Internal 120kΩ pull-down
Crystal I/O
PIN
Pin Name
Type
Description
50
XIN
IN
Crystal input with internal loading capacitors (18pF) and
feedback resistors.
49
XOUT
OUT
Crystal output at 14.318MHz nominally with internal
loading capacitors (18pF).
5.2
CPU, SRC, and PCIEX, PCI, Clock Outputs
4
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
PIN
Pin Name
44,43,41,40
5.3
Type
Description
CPUT [0:1]
CPUC [0:1]
OUT
Low skew (< 85ps) 0.7V Current mode differential
clock outputs for host frequencies of CPU
17,18,19,20,
22,23,24,25, SRCT[0:6]
26,27,31,30, SRCC[0:6]
33,32
OUT
0.7V current mode differential clock outputs for
SRC. SRC4_SATA is fixed 100MHz for serial ATA.
SRCT/C 7
OUT
36,35
CPUCLKT/C2_ITP OUT
PCI_F0
OUT
0.7V Current mode differential clock outputs for
SRC (default), select by ITP_EN pin =0.
0.7V Current mode differential clock outputs for
host frequency, select by ITP_EN pin =1.
3.3V free running PCI clock output.
9
PCI_F1
OUT
Latched input for at initial power up to select
CPUCLK2_ITP/SRC7 output.
1: CPUCLK2 clock output.
0: SRC7 clock output.
This pin has internal 120K pull down.
3.3V free running PCI clock output.
56,3,4,5
PCI [2:5]
OUT
Low skew (< 250ps) 3.3V PCI clock outputs
8
&
ITP_EN
IN td120k
puts
PIN
Pin Name
Type
Description
52
REF
OUT
3.3V REF 14.318Mhz clock output.
48MHz
OUT
48MHz clock output for USB.
12
*
FSA
IN tp120k
14,15
DOTT/C
OUT
16
&
IN td120k
53
&
IN td120k
5.4
PIN
FSB
FSC
Latched iNQut for FSA at initial power up for H/W
selecting the output frequency. Latched voltage
level refers to Vil_FS and Vih_FS voltage level.
This is internal 120K pull up.
0.7V current mode 96MHz differential clock
outputs for DOT
Latched iNQut for FSB at initial power up for H/W
selecting the output frequency. Latched voltage
level refers to Vil_FS and Vih_FS voltage level.
This is internal 120K pull down.
Latched input for FS2 at initial power up for H/W
selecting the output frequency. Latched voltage
level refers to Vil_FS and Vih_FS voltage level.
This is internal 120K pull down.
I2C Control Interface
Pin Name
Type
Description
5
Publication Release Date: December, 2007
Revision 1.1
F
i
x
e
d
F
r
e
q
u
e
n
c
y
O
u
t
W83195CG-NP
FOR INTEL NAPA PLATFORM
47
SDATA
I/O
Serial data of I2C 2-wire control interface
46
SCLK
IN
Serial clock of I2C 2-wire control interface
5.5
Power Management Pins
PIN
Pin Name
Type
Description
39
IREF
OUT
Deciding the reference current for the differential
pairs. The pin was connected to the precision
resistor tied to ground to decide the appropriate
current; 475 ohm is the standard value.
54
CPU_STOP#*
IN
CPU clock stop control pin, This pin is low active.
Internal 120kΩ pull-up.
55
PCI/SRC_STOP#* IN
PCI clock stop control pin, This pin is low active.
Internal 120kΩ pull-up.
VTT_PWRGD#
IN
Power good is a low active input signal used to
determine when FS [2:0] are valid to be sample.
PD
IN td120k
Power Down Function. This is power down pin, high
active (PD). Internal 120K pull down
10
5.6
Power Pins
PIN
Pin Name
37
VDDA
1,7
VDDP
21,28,34
VDDS
11
VDD48
42
VDDC
48
VDDR
38
GNDA
2,6,13,29,45,51 GND
Type
Description
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
3.3V power supply for PLL core.
3.3V power supply for PCI.
3.3V power supply for SRC pair.
3.3V power supply for 48MHz.
3.3V power supply for CPU.
3.3V power supply for REF.
Ground pin for PLL core.
Ground pin
6. FREQUENCY SELECTION BY HARDWARE
FS4
FS3
FS2
FS1
FS0
CPU (MHZ)
DOT (MHZ)
6
SRC (MHZ)
PCI (MHZ)
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
0
0
0
0
0
0
0
0
0
1
266.66
133.33
96.00
96.00
100.00
100.00
33.33
33.33
0
0
0
1
0
200.00
96.00
100.00
33.33
0
0
0
1
1
166.66
96.00
100.00
33.33
0
0
1
0
0
333.33
96.00
100.00
33.33
0
0
1
0
1
100.00
96.00
100.00
33.33
0
0
1
1
0
400.00
96.00
100.00
33.33
0
0
1
1
1
200.00
96.00
100.00
33.33
7
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
7. I2C CONTROL AND STATUS REGISTERS
7.1
BIT
Register 0: ( Default : FFh )
AFFECTED PIN/
FUNCTION NAME(S)
PWD
7
CPUEN
1
6
SRCEN
1
5
SRCEN
1
4
SRCEN
1
3
SRCEN
1
2
SRCEN
1
1
SRCEN
1
0
SRCEN
1
7.2
BIT
AFFECTED PIN / FUNCTION DESCRIPTION
CPUCLK2_ITP/SRCCLK7 output control
1: Enable
0: Disable
SRCCLK6 output control
1: Enable
0: Disable
SRCCLK5 output control
1: Enable
0: Disable
SRCCLK4 output control
1: Enable
0: Disable
SRCCLK3 output control
1: Enable
0: Disable
SRCCLK2 output control
1: Enable
0: Disable
SRCCLK1 output control
1: Enable
0: Disable
SRCCLK0 output control
1: Enable
0: Disable
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register 1: ( Default : FEh )
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
7
PCIFEN
1
PCI_F0 output control
1: Enable
0: Disable
R/W
6
F96EN
1
DOT96_T/C output control
1: Enable
0: Disable
R/W
8
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
5
F48EN
1
USB48M output control
1: Enable
0: Disable
R/W
R/W
4
REFEN
1
REFOUT output control
1: Enable
0: Disable
3
Reserved
1
Reserved
R/W
2
CPUEN
1
CPUCLK1 output control
1: Enable
0: Disable
R/W
1
CPUEN
1
0
SPSPEN
0
7.3
BIT
7
6
5
CPUCLK0 output control
1: Enable
0: Disable
Enable spread spectrum mode under clock
output.
0 = Spread Spectrum mode disable
1 = Spread Spectrum mode enable
R/W
R/W
Register 2: ( Default : FFh)
AFFECTED PIN/
FUNCTIONNAME(S)
PCIEN
PCIEN
PCIEN
PWD
FUNCTION DESCRIPTION
TYPE
1
PCICLK5 output control
1: Enable
0: Disable
R/W
1
PCICLK4 output control
1: Enable
0: Disable
R/W
1
PCICLK3 output control
1: Enable
0: Disable
R/W
R/W
4
PCIEN
1
PCICLK2 output control
1: Enable
0: Disable
3
Reserved
1
Reserved
R/W
2
Reserved
1
Reserved
R/W
9
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
1
0
7.4
BIT
7
6
5
4
3
2
1
0
7.5
BIT
Reserved
PCIFEN
1
Reserved
R/W
1
PCI_F1 output control
1: Enable
0: Disable
R/W
Register 3: ( Default : 00h )
AFFECTED PIN/
FUNCTIONNAME(S)
SRC7_STOP
SRC6_STOP
SRC5_STOP
SRC4_STOP
SRC3_STOP
SRC2_STOP
SRC1_STOP
SRC0_STOP
PWD
FUNCTION DESCRIPTION
TYPE
0
PCI_SRC_STOP# for SRC7 control.
1: Stoppable
0:Free-Running
R/W
0
PCI_SRC_STOP# for SRC6 control.
1: Stoppable
0:Free-Running
R/W
0
PCI_SRC_STOP# for SRC5 control.
1: Stoppable
0:Free-Running
R/W
0
PCI_SRC_STOP# for SRC4 control.
1: Stoppable
0:Free-Running
R/W
0
PCI_SRC_STOP# for SRC3 control.
1: Stoppable
0:Free-Running
R/W
0
PCI_SRC_STOP# for SRC2 control.
1: Stoppable
0:Free-Running
R/W
0
PCI_SRC_STOP# for SRC1 control.
1: Stoppable
0:Free-Running
R/W
0
PCI_SRC_STOP# for SRC0 control.
1: Stoppable
0:Free-Running
R/W
FUNCTION DESCRIPTION
TYPE
Register 4: ( Default : 87)
AFFECTED PIN/
FUNCTIONNAME(S)
PWD
10
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
7
Reserved
1
Reserved
R/W
6
Reserved
0
Reserved
R/W
5
Reserved
0
Reserved
R/W
0
PCI_SRC_STOP# for PCIF1 control.
1: Stoppable
0:Free-Running
R/W
R/W
4
PCIF
3
PCIF
0
PCI_SRC_STOP# for PCIF0 control.
1: Stoppable
0:Free-Running
2
CPUCLK2_FS_ITP
1
1: Enable CPUCLK2_ITP stop feature
0: Disable stop feature
R/W
1
CPUCLK1_FS
1
1: Enable CPUCLK1 stop feature
0: Disable stop feature
R/W
0
CPUCLK0_FS
1
1: Enable CPUCLK0 stop feature
0: Disable stop feature
R/W
7.6
BIT
Register 5: ( Default : 00h )
AFFECTED PIN/
FUNCTIONNAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
CPUT / SRCT / PCI_EXP / DOT96_T output
state in during POWER DOWN assertion.
1: Driven
(2*Iref)
0: Tristate (Floating)
7
DRI_CONT
(Reserved)
0
CPUT / SRCT / PCI_EXP / DOT96_T output
state in during STOP Mode assertion.
1: Driven
R/W
(6*Iref)
0: Tristate (Floating)
Complementary parts always tri-state (floating)
in power down or stop mode.
6
Reserved
0
Reserved
R/W
5
Reserved
0
Reserved
R/W
4
Reserved
0
Reserved
R/W
11
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
3
Reserved
0
Reserved
R/W
2
Reserved
0
Reserved
R/W
1
Reserved
0
Reserved
R/W
Power on latched value of ITP_EN/PCICLK_F0 pin.
0
SEL_ITP
0
SRCCLK/CPU_ITP output clock selection :
1: CPU_ITP clock output
0: SRCCLK clock output
12
R/W
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
7.7
BIT
Register 6: ( Default : XXh )
AFFECTED PIN/
FUNCTIONNAME(S)
PWD
7
Reserved
1
6
Reserved
0
5
Reserved
0
4
Reserved
0
FUNCTION DESCRIPTION
TYPE
Reserved
R/W
R/W
3
PCI/SRCCLK_STOP
1
To stop all PCICLK and SRCCLK output
1: Disable
0: Enable
2
FSC_BACK
X
Power on latched value of FSC pin.
R
1
FSB_BACK
X
Power on latched value of FSB pin.
R
0
FSA_BACK
X
Power on latched value of FSA pin.
R
7.8
BIT
Register 7: Winbond Chip ID – Project Code Register ( Default : 11h )
AFFECTED PIN/
FUNCTIONNAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
7
CHPI_ID [7]
0
Winbond Chip ID.
R
6
CHPI_ID [6]
0
Winbond Chip ID.
R
5
CHPI_ID [5]
0
Winbond Chip ID.
R
4
CHPI_ID [4]
1
Winbond Chip ID.
R
3
CHPI_ID [3]
0
Winbond Chip ID.
R
2
CHPI_ID [2]
0
Winbond Chip ID.
R
1
CHPI_ID [1]
0
Winbond Chip ID.
R
0
CHPI_ID [0]
1
Winbond Chip ID.
R
13
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
8. ACCESS INTERFACE
The W83195CG-NP provides I2C Serial Bus for microprocessor to read/write internal registers. In the
W83195CG-NP is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C
address is defined at 0xD2.
Block Read and Block Write Protocol
8.1
Block Write protocol
8.2
Block Read protocol
## In block mode, the command code must filled 8’h00
8.3
Byte Write protocol
8.4
Byte Read protocol
14
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
9. SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.
Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
Parameter
Rating
Absolute 3.3V Core Supply Voltage
-0.5V to +4.6V
Absolute 3.3V I/O Supple Voltage
- 0.5V to + 4.6V
Operating 3.3V Core Supply Voltage
3.135V to 3.465V
Operating 3.3V I/O Supple Voltage
3.135V to 3.465V
Storage Temperature
- 65°C to + 150°C
Ambient Temperature
- 55°C to + 125°C
Operating Temperature
0°C to + 70°C
Input ESD protection (Human body model)
2000V
9.2 General Operating Characteristics
VDD= 3.3V ± 5 %, TA = 0°C to +70°C,
Parameter
Symbol
Input Low Voltage
V IL
Input High Voltage
V IH
Output Low Voltage
V OL
Output High Voltage
V OH
Min
Max
Units
0.8
V dc
2.0
V dc
0.4
V dc
2.4
V dc
Operating Supply
Current
I dd
350
mA
Input pin capacitance
Cin
5
pF
Cout
6
pF
Lin
7
nH
Output pin capacitance
Input pin inductance
Test Conditions
15
CPU = 100 to 400 MHz
PCI = 33.3 Mhz with load 10pF
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
9.3 Skew Group timing clock
VDD = 3.3V ± 5 %, TA = 0°C to +70°C, Cl=10pF
Parameter
Min
Max
Units
Test Conditions
CPU pair to CPU pair Skew
100
ps
Measure Crossing point
PCIE pair to PCIE pair
Skew
85
ps
Measure Crossing point
PCI to PCI Skew
500
ps
Measured at 1.5V
48MHz to 48MHz Skew
1000
ps
Measured at 1.5V
9.4 CPU 0.7V Electrical Characteristics
VDDC= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V,
Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF
Parameter
Min
Max
Units
Test Conditions
Rise Time
175
700
ps
Measure Single Ended waveform
Fall Time
175
700
ps
Measure Single Ended waveform
Absolute crossing point
Voltages
250
550
mV
Measure Single Ended waveform
Voltage High
660
850
mV
Measure Single Ended waveform
Voltage Low
-150
mV
Measure Single Ended waveform
125
ps
Measure Differential waveform
55
%
Measure Differential waveform
Cycle to Cycle jitter
Duty Cycle
45
9.5 SRC 0.7V Electrical Characteristics
VDDS= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V,
Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF
Parameter
Min
Max
Units
Test Conditions
Rise Time
175
700
ps
Measure Single Ended waveform
Fall Time
175
700
ps
Measure Single Ended waveform
Absolute crossing point
Voltages
250
550
mV
Measure Single Ended waveform
Voltage High
660
850
mV
Measure Single Ended waveform
Voltage Low
-150
mV
Measure Single Ended waveform
85
ps
Measure Differential waveform
55
%
Measure Differential waveform
Cycle to Cycle jitter
Duty Cycle
45
16
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
9.6
PCIE 0.7V Electrical Characteristics
VDDPE= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V,
Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF
Parameter
Min
Max
Units
Test Conditions
Rise Time
175
700
ps
Measure Single Ended waveform
Fall Time
175
700
ps
Measure Single Ended waveform
Absolute crossing point
Voltages
250
550
mV
Measure Single Ended waveform
Voltage High
660
850
mV
Measure Single Ended waveform
Voltage Low
-150
mV
Measure Single Ended waveform
85
ps
Measure Differential waveform
55
%
Measure Differential waveform
Cycle to Cycle jitter
Duty Cycle
45
9.7 PCI Electrical Characteristics
VDDP= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,
Parameter
Min
Max
Units
Rise Time
500
2000
ps
Vol=0.4V, Voh=2.4V
Fall Time
500
2000
ps
Voh=2.4V, Vol=0.4V
250
ps
Measured at 1.5V
55
%
Measured at 1.5V
Cycle to Cycle jitter
Duty Cycle
45
Pull-Up Current Min
-33
Pull-Up Current Max
Pull-Down Current Min
-33
30
Pull-Down Current Max
38
Test Conditions
mA
Vout=1.0V
mA
Vout=3.135V
mA
Vout=1.95V
mA
Vout=0.4V
9.8 48M Electrical Characteristics
VDD48= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,
Parameter
Min
Max
Units
Rise Time
500
2000
ps
Vol=0.4V, Voh=2.4V
Fall Time
500
2000
ps
Voh=2.4V, Vol=0.4V
500
ps
Measured at 1.5V
55
%
Measured at 1.5V
Long term jitter
Duty Cycle
45
Pull-Up Current Min
-33
mA
17
Test Conditions
Vout=1.0V
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
Pull-Up Current Max
Pull-Down Current Min
-33
30
Pull-Down Current Max
38
mA
Vout=3.135V
mA
Vout=1.95V
mA
Vout=0.4V
9.9 REF Electrical Characteristics
VDD= 3.3V ± 5 %, TA = 0°C to +70°C, Test load, Cl=10pF,
Parameter
Min
Max
Units
Rise Time
500
2000
ps
Vol=0.4V, Voh=2.4V
Fall Time
500
2000
ps
Voh=2.4V, Vol=0.4V
1000
ps
Measured at 1.5V
55
%
Measured at 1.5V
Cycle to Cycle jitter
Duty Cycle
45
Pull-Up Current Min
-29
Pull-Up Current Max
Pull-Down Current Min
-23
29
Pull-Down Current Max
27
Test Conditions
mA
Vout=1.0V
mA
Vout=3.135V
mA
Vout=1.95V
mA
Vout=0.4V
9.10 DOT 0.7V Electrical Characteristics
VDD= 3.3V ± 5 %, TA = 0°C to +70°C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V,
Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF
Parameter
Min
Max
Units
Test Conditions
Rise Time
175
700
ps
Measure Single Ended waveform
Fall Time
175
700
ps
Measure Single Ended waveform
Absolute crossing point
Voltages
250
550
mV
Measure Single Ended waveform
Voltage High
660
850
mV
Measure Single Ended waveform
Voltage Low
-150
mV
Measure Single Ended waveform
250
ps
Measure Differential waveform
55
%
Measure Differential waveform
Cycle to Cycle jitter
Duty Cycle
45
18
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
10. ORDERING INFORMATION
Part Number
Package Type
56 PIN TSSOP
W83195CG-NP
(Lead free part)
Production Flow
Commercial, 0°C to +70°C
11. TOP MARKING SPECIFICATION
W83195CG-NP
28051234
504GAABA
1st line: Winbond logo and the part number: W83195CG-NP(Lead free)
2nd line: Tracking code 2 8051234
2: wafers manufactured in Winbond FAB 2
8051234: wafer production series lot number
3rd line: Tracking code
504 G A A BA
504: packages made in '2005, week 04
G: assembly house ID; O means OSE, G means GR
A: Internal use code
A: IC revision
BA: Internal use code
All the trademarks of products and companies mentioned in this data sheet belong to their
respective owners.
19
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
12. PACKAGE DRAWING AND DIMENSIONS
56 PIN TSSOP-240mil
20
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
21
Publication Release Date: December, 2007
Revision 1.1
W83195CG-NP
FOR INTEL NAPA PLATFORM
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper
use or sales.
22
Publication Release Date: December, 2007
Revision 1.1
工商网监
湘ICP备2023018690号
