WMS7110050P

PRELIMINARY DATASHEET WMS7110 / 7111 NON-VOLATILE DIGITAL POTENTIOMETERS WITH UP/DOWN (3-WIRE) INTERFACE, 10KOHM, 50KOHM, 100KOHM RESISTANCE 128 TAPS WITHOUT / WITH OUTPUT BUFFER -1- Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 1. GENERAL DESCRIPTION The WMS7110/7111 is a single channel 128-tap non-volatile linear digital potentiometer available in 10KΩ, 50KΩ and 100KΩ resistance. The device consists of Up/Down serial interface, tap register, decoder, resistor array, wiper switches, NV memory and control logics. The WMS7110 device can be configured as a two-terminal variable resistor or a three-terminal voltage divider without an output buffer, but the WMS7111 device, which has a built-in output buffer, can only be configured as a three-terminal voltage divider. Both devices can be used in a wide variety of applications. The output of the potentiometer is determined by its wiper position, which varies linearly between its end terminals, RA/VA and RB/VB. The wiper position, Rw/Vw, is controlled by Up/Down serial interface ( CS , INC and U/ D ) through the Tap Register (TR). In addition, the wiper position can also be stored into a non-volatile memory location (NVMEM0), which is then automatically recalled upon power up. 2. FEATURES • Drop-in replacement for many popular parts • Single linear-taper channel • 128 taps • 10K, 50K and 100K end-to-end resistance • VSS to VDD terminal voltages • Automatic recall of wiper position when power-on • Potentiometer control through Up/Down (3-wire) serial interface • Endurance 100,000 cycles • Data retention 100 years • Package options: - 8-pin PDIP, SOIC or MSOP • Industrial temperature range: -40° to 85°C • Single supply operation : 2.7V to 5.5V -2- WMS7110 / 7111 CS U/D Up/Down Serial RA/VA Decoder INC Tap Register 3. BLOCK DIAGRAM RW /VW RB/VB Interface NV Memory VSS NVMEM0 NV Memory Control VDD CS U/D Up/Down Serial VA Decoder INC Tap Register FIGURE 1 – WMS7110 BLOCK DIAGRAM (Rheostat/Divider Mode) VW VB Interface NV Memory VSS NVMEM0 NV Memory Control VDD FIGURE 2 – WMS7111 BLOCK DIAGRAM (Divider Mode) -3- Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM............................................................................................................................... 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 5 6. PIN DESCRIPTION ............................................................................................................................. 6 7. FUNCTIONAL DESCRIPTION............................................................................................................ 7 7.1. Rheostat And Divider Operations ........................................................................................... 7 7.1.1. Rheostat Configuration .......................................................................................................... 7 7.1.2. Divider Configuration.............................................................................................................. 7 7.2. Non-Volatile Memory (NVMEM0) ........................................................................................... 7 7.3. Serial Data Interface ................................................................................................................. 8 7.4. Operation Overview .................................................................................................................. 8 8. TIMING DIAGRAMS............................................................................................................................ 9 9. ABSOLUTE MAXIMUM RATINGS & OPERATING CONDITIONS .................................................. 11 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 12 10.1 Test Circuits ............................................................................................................................ 14 11. TYPICAL APPLICATION CIRCUITS............................................................................................... 15 11.1. Layout Considerations.......................................................................................................... 17 12. PACKAGE DRAWINGS AND DIMENSIONS.................................................................................. 18 13. ORDERING INFORMATION........................................................................................................... 21 14. VERSION HISTORY ....................................................................................................................... 22 -4- WMS7110 / 7111 5. PIN CONFIGURATION INC 1 8 VDD U/D 2 7 CS R A /V A 3 6 R B /V B V SS 4 5 R w /V W 8-M SOP INC 1 8 V DD U/D 2 7 CS R A /V A 3 6 R B /V B V SS 4 5 R w /V W 8-SOIC INC 1 8 V DD U/D 2 7 CS R A /V A 3 6 R B /V B V SS 4 5 R w /V W 8-PDIP -5- Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 6. PIN DESCRIPTION TABLE 1 – PIN DESCRIPTION Pin Name Description Chip Select: When CS is LOW, the device is enabled. CS U/ D When CS is HIGH, the part is deselected and is in standby mode Up/Down Control: HIGH state enables the wiper to move towards the RA / VA terminal, while LOW state implies the wiper moves towards the RB / VB terminal Increment Control: When CS is LOW, a HIGH-LOW INC transition on INC will move the wiper one increment either up or down based on the U/ D input RA/VA High terminal of the device RB/VB Low terminal of the device RW/VW Wiper Terminal: Output of the resistor array is determined by the INC , U/ D and CS inputs VSS Ground pin, logic ground reference VDD Power Supply Notes: The terminology of high and low terminals above references to the relative position of the terminal with respect to the wiper moving direction and not the voltage potential of the terminal. -6- WMS7110 / 7111 7. FUNCTIONAL DESCRIPTION 7.1. RHEOSTAT AND DIVIDER OPERATIONS The WMS7110 device can operate as either a two-terminal variable resistor or a three-terminal voltage divider without an output buffer. However, the WMS7111 can only operate in a three-terminal voltage divider with an output buffer. 7.1.1. Rheostat Configuration In the rheostat mode, the WMS7110 can be configured as a two-terminal resistive element, where one terminal is connected to one end of the resistor (RA or RB) and the other terminal is the wiper (RW). The moving direction of the wiper depends upon the setting of U/ D control signal. When the U/ D is set to Up, then the wiper moves towards RA. Conversely, when the U/ D is set to Down, then the wiper moves towards RB. The wiper movement to either direction is controlled by toggling the INC signal from HIGH to LOW. This configuration controls the resistance between the wiper and either end. The wiper resistance can be adjusted by either changing the wiper position or loading a stored wiper position value from NVMEM0 upon power up. 7.1.2. Divider Configuration Additionally, the WMS7110 can also be configured as a voltage divider. With an input voltage applied to one end (usually VA ), the ground is connected to the other end (usually VB). These input voltages cannot exceed the VDD level or go below the VSS level. The voltage on the wiper, VW, is proportional to the wiper position with respect to the voltage difference between VA and VB. The moving direction of the wiper depends upon the setting of the U/ D control signal. When the U/ D is set to Up, then the wiper moves towards VA. Conversely, when the U/ D is set to Down, then the wiper moves towards VB. The wiper movement to either direction is controlled by toggling the INC signal from HIGH to LOW. Nevertheless, the WMS7111 can only be configured as a voltage divider and operate similarly as the WMS7110 device. The only difference is WMS7111 has an output buffer, but WMS7110 doesn’t have. Besides, the resistance cannot be directly measured in this configuration. 7.2. NON-VOLATILE MEMORY (NVMEM0) The WMS7110/7111 has one NVMEM0 location available for storing the current wiper position via the Up/Down serial interface. This stored value is automatically recalled and loaded into the tap register upon power up. -7- Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 7.3. SERIAL DATA INTERFACE The WMS7110/7111 device has a 3-wire Up/Down Serial Interface consisting of CS , INC and U/ D control signals. The key features of this interface include: • Enabling the device • Determining the moving direction of the wiper • Increment/Decrement operation on the wiper • Non-volatile storage of the present wiper position into the NVMEM0 for automatic recall at power up • Entering into the standby mode 7.4. OPERATION OVERVIEW The wiper position can be changed either up or down by operating the CS , U/ D and INC control signals. When CS is LOW, the device is selected and the wiper can be moved by toggling the INC . As a result, the wiper moves up when U/ D is HIGH and moves down when U/ D is LOW. The status of the U/ D can be changed even though the CS remains LOW. This allows the system to enable the device and then move the wiper position either up or down until the desired position is reached. When the wiper is already at the lowest position, further Down operation won’t change the wiper position. Similarly, when the wiper is at the highest position, further Up operation won’t change the wiper position too. The current wiper position can be automatically stored into the NVMEM0 each time the CS goes from LOW to HIGH while the INC remains HIGH. Adversely, if the INC is LOW when the CS goes HIGH, the wiper position cannot be stored. Meanwhile, the NVMEM0 content is automatically loaded into the wiper during power on. When the CS is held HIGH, the device enters into Standby mode and the wiper position cannot be changed. Changing the CS to LOW exits the Standby mode and enables the device again. The operating modes of Up/Down interface are summarized in the table below: Operation CS U/ D LOW HIGH HIGH to LOW Move Wiper toward RA /VA LOW LOW HIGH to LOW Move Wiper toward RB /VB INC LOW to HIGH x HIGH Store Current Wiper Position LOW to HIGH x LOW No Store, Return to Standby x x Standby HIGH Note: x means don’t care -8- WMS7110 / 7111 8. TIMING DIAGRAMS Conditions: VDD = +2.7V to 5.5V, VA = VDD, VB = 0V, T = 25°C t PUD [1] CS tCYC tCI tIL tCI tIH (store) tCPH 90% INC 90% 10% tDI tID tF tR U/D tIW [2] MI VW FIGURE 3 –WMS7110/1 TIMING DIAGRAM Note: [1] This only applies to the Power-Up sequence. [2] MI in the AC Timing diagram (Figure 3) refers to the minimum incremental change in the wiper output due to a change in the wiper position. -9- Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 TABLE 10 – TIMING PARAMETERS PARAMETERS SYMBOL MIN. CS to INC Setup tCI 100 ns U/ D to INC Setup tDI 50 ns U/ D to INC Hold tID 100 ns INC LOW Period tIL 250 ns INC HIGH Period tIH 250 ns INC Inactive to CS Inactive tIC 1 µs CS Deselect Time (NO STORE) tCPH 100 ns tCPH 15 (2.7V) ms CS Deselect Time (STORE) INC to Wiper Change tIW INC Cycle Time tCYC INC Input Rise and Fall Time tR, tF 500 µs Power-Up Delay tPUD 1 ms 0.2 50 V/ms (13ms (54µs 0-2.7V) 0-2.7V) VCC Power-Up rate tR VCC - 10 - MAX. UNITS 30 (5.5V) 5 µs µs 1 WMS7110 / 7111 9. ABSOLUTE MAXIMUM RATINGS & OPERATING CONDITIONS TABLE 11 – ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) [1] Conditions Values Junction temperature 150ºC Storage temperature -65º to +150ºC Voltage applied to any pad (Vss – 0.3V) to (VDD + 0.3V) Lead temperature (soldering – 10 seconds) 300ºC VSS – VDD -0.3 to 7.0V TABLE 12 – OPERATING CONDITIONS (PACKAGED PARTS) Conditions [1] Values Industrial operating temperature -40ºC to +85ºC Supply voltage (VDD) +2.7V to +5.5V Ground voltage (VSS) 0V Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device performance and reliability. Functional operation is not implied at these conditions. - 11 - Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 10. ELECTRICAL CHARACTERISTICS TABLE 12 – ELECTRICAL CHARACTERISTICS (Packaged parts) PARAMETERS SYMBOL MIN. R -20 R-DNL -1 R-INL -1 TYP. CONDITIONDS [5] MAX. UNITS +20 % ±0.3 +1 LSB [6] ±0.5 +1 LSB [6] Rheostat Mode Nominal Resistance Different Non Linearity [2] Integral Non Linearity [2] Tempo [1] Wiper Resistance [2] Wiper Current T=25ºC, Wiper open ∆RAB/∆T 300 ppm/°C RW 50 Ω VDD=5V, I=VDD/RTotal [7] 80 Ω VDD=2.7V, I=VDD/RTotal [7] IW -1 1 mA N 8 DNL -1 ±0.2 +1 LSB INL -1 ±0.1 +1 LSB Divider Mode Resolution Different Non Linearity Integral Non Linearity [2] [2] Temperature Coefficient [1] ∆W /∆T Bits +20 ppm/°C Wiper at center Full Scale Error VFSE -1 0 LSB Wiper at highest position Zero Scale Error VZSE 0 1 LSB Wiper at lowest position VA, VB, VW VSS VDD V Resistor Terminal Voltage Range Terminal Capacitance Wiper Capacitance [1] CA, CB 30 pF 30 pF BW10K 1.5 MHz VDD=5V, B =VSS BW50K 300 KHz Wiper at center BW100K 200 KHz [1] Dynamic Characteristics [1] Bandwidth –3dB Analog Output (Buffer enables) Amp Output Current IOUT Amp Output Resistance Rout Total Harmonic Distortion [1] THD 3 mA 1 VO=1/2 scale 10 Ω IL = 100uA 0.08 % A =2.5V, VDD=5V, f=1kHz, VIN=1VRMS Digital Inputs/Outputs Input High Voltage VIH 0.7xVDD V Input Low Voltage VIL 0.3xVDD V Output Low Voltage VOL 0.4 V - 12 - IOL=2mA WMS7110 / 7111 TABLE 12 – ELECTRICAL CHARACTERISTICS (Packaged parts) – Cont’d PARAMETERS SYMBOL MIN. Input Leakage Current ILI Output Leakage Current ILo Input Capacitance [1] CIN COUT Output Capacitance [1] TYP. CONDITIONDS [5] MAX. UNITS -1 +1 uA CS =VDD,Vin=Vss ~ VDD -1 +1 uA CS =VDD,Vin=VSS ~ VDD 25 pF VDD=5V, fc = 1Mhz 25 pF VDD=5V, fc = 1Mhz Power Requirements Operating Voltage VDD Operating Current IDDR, IDDW 2.7 5.5 V 1 2 mA ISA [3] 0.5 1 mA ISB [4] 0.1 1 uA 1 LSB/V Standby Current Power Supply Rejection Ratio PSRR All operations Buffer = ON CS = HIGH, no load Buffer = OFF CS = HIGH, no load VDD=5V±10%, Wiper at center Notes: [1] Not subject to production test. [2] LSB = (RA/VA – RB/VB) / (T - 1); DNL = (Vi - Vi+1) / LSB + 1 (if increment) or = (Vi Vi+1) / LSB - 1 (if decrement); INL = (Vi - i*LSB) / LSB; where i = [0, (T -1)] and T = # of taps of the device. [3] WMS7111 only. [4] WMS7110 only. [5] Conditions: VCC = 2.7 to 5.5V, T = 25ºC and timing measured at 50% level, unless stated. [6] Only guarantee by design. [7] Rtotal = end-to-end resistance. - 13 - Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 10.1 TEST CIRCUITS VA VW V+ V+ = VDD 1LSB= V+/127 VB WMS71xx VA VW VA V+ VMS* VB WMS71xx *Assume infinite input impedance VMS* *Assume infinite input impedance Potentiometer divider nonlinearity error test circuit (INL, DNL) Power supply sensitivity test circuit (PSS, PSRR) No Connection VA WMS71xx IW RA VA = VDD V+ = VDD ± 10% PSRR(dB) = 20LOG( ∆VMS ) ∆VDD VMS PSS(%/%) = ∆ ∆VDD WMS71xx VW W RW VB +5V VOUT RB VMS * ~ VIN 2.5V DC Offset *Assume infinite input impedance Resistor position nonlinearity error test circuit (Rheostat Operation: R-INL, R-DNL) Capacitance test circuit VMS* VA VW VB WMS71xx WMS71xx +5V VA IW = VDD /RTotal IW VIN ~ VW VOUT VB RW = VMS /IW OFFSET GND 2.5V DC *Assume infinite input impedance Gain vs. frequency test circuit Wiper resistance test circuit FIGURE 4 – TEST CIRCUITS - 14 - WMS7110 / 7111 11. TYPICAL APPLICATION CIRCUITS RA RB Vin WMS71XX _ OP AMP VOUT + VOUT = - VIN RA = RB RA RAB (128-W) , 128 RB = RAB*W 128 RAB = Total resistance of potentiometer W = Wiper setting for WMS71XX FIGURE 5 – PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7110/7111 VIN + OP _ AMP RA VOUT RB WMS71XX VOUT = VIN (1+ RA = RB ) RA RAB*W RAB (128-W) , RB = 128 128 RAB = Total resistance of potentiometer W = Wiper setting for WMS71XX FIGURE 6 – PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7110/7111 - 15 - Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 V+ WMS71xx VREFH 5V Vout VREF = 5.0v 0V GND FIGURE 7 – WMS7111 TRIMMING VOLTAGE REFERENCE L1 CHOKE C1 0.1uF CS\ U/D\ INC\ CS\ U/D\ INC\ VSS VDD RA/VA RW/VW RB/VB RF OUT Q1 FILTER RF POWER AMP WMS71xx WINPOT C2 RF Input FIGURE 8 – WMS7111 RF AMP CONTROL - 16 - WMS7110 / 7111 11.1. LAYOUT CONSIDERATIONS Use a 0.1µF bypass capacitor as close as possible to the VDD pin. This is recommended for best performance. Often this can be done by placing the surface mount capacitor on the bottom side of the PC board, directly between the VDD and VSS pins. Care should be taken to separate the analog and digital traces. Sensitive traces should not run under the device or close to the bypass capacitors. A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals. DIGITAL CONTROL LINES ANALOG SIGNAL LINE INC V DD U/D CS CAP R B /V B R A /V A V SS R W /V W DIGITAL CONTROL LINE ANALOG SIGNAL LINES FIGURE 9 – WMS7110/7111 LAYOUT - 17 - Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 12. PACKAGE DRAWINGS AND DIMENSIONS 8 5 E 4 1 Control demensions are in milmeters . E θ FIGURE 10: 8L 150MIL SOIC - 18 - WMS7110 / 7111 D 8 5 E1 1 4 B B 1 E S c A1 A A2 L B a s e P la n e S e a t in g P la n e e1 α S ym b o l A A1 A2 B B1 c D E E1 e1 L α e S D im e n s io n in in c h M in Nom D im e n s io n in m m M in Nom 0 .0 1 0 M ax 4 .4 5 0 .1 7 5 0 .2 5 0 .1 2 5 0 .1 3 0 0 .1 3 5 3 .1 8 3 .3 0 3 .4 3 0 .0 1 6 0 .0 1 8 0 .0 2 2 0 .4 1 0 .4 6 0 .5 6 0 .0 5 8 0 .0 6 0 0 .0 6 4 1 .4 7 1 .5 2 1 .6 3 0 .0 0 8 0 .0 1 0 0 .0 1 4 0 .2 0 0 .2 5 0 .3 6 0 .3 6 0 0 .3 8 0 9 .1 4 9 .6 5 0 .2 9 0 0 .3 0 0 0 .3 1 0 7 .3 7 7 .6 2 7 .8 7 0 .2 4 5 0 .2 5 0 0 .2 5 5 6 .2 2 6 .3 5 6 .4 8 0 .0 9 0 0 .1 0 0 0 .1 1 0 2 .2 9 2 .5 4 2 .7 9 0 .1 2 0 0 .1 3 0 0 .1 4 0 3 .0 5 3 .3 0 3 .5 6 15 0 9 .0 2 9 .5 3 0 A M ax 0 .3 3 5 eA 0 .3 5 5 0 .3 7 5 8 .5 1 0 .0 4 5 15 1 .1 4 FIGURE 11: 8L 300MIL PDIP - 19 - Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 FIGURE 12: 8L 3MM MSOP - 20 - WMS7110 / 7111 13. ORDERING INFORMATION Winbond’s WinPot Part Number Description: WMS71 T B RRR P Winbond WinPot Products w/ Up-Down Interface Number Of Taps: 1 = 128 For Up/Down interface: 0 : No buffer 1 : With buffer End-to-end Resistance: 010: 10Kohm 050: 50Kohm 100: 100Kohm Package: S: SOIC P: PDIP M: MSOP Output Buffer End-to-End Resistance SOIC PDIP MSOP NO 10K WMS7110010S WMS7110010P WMS7110010M 50K WMS7110050S WMS7110050P WMS7110050M 100K WMS7110100S WMS7110100P WMS7110100M 10K WMS7111010S WMS7111010P WMS7111010M 50K WMS7111050S WMS7111050P WMS7111050M 100K WMS7111100S WMS7111100P WMS7111100M YES Notes: Part number with white background: Available for sampling and mass production. Part numbers with shaded background: Call factory for availability. For the latest product information, access Winbond’s worldwide website at http://www.winbond-usa.com - 21 - Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 14. VERSION HISTORY VERSION DATE 1.0 July 2003 DESCRIPTION Initial issue The contents of this document are provided only as a guide for the applications of Winbond products. Winbond makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental injury could occur. Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441797 http://www.winbond-usa.com/ 27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No. 480, Pueiguang Rd. Neihu District Taipei, 114 Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 7F Daini-ueno BLDG. 3-7-18 Shinyokohama Kohokuku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. This product incorporates SuperFlash® technology licensed from SST. - 22 -