74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 3 — 12 October 2020
Product data sheet
1. General description
The 74ABT74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP),
set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored
in the flip-flop and appear at the Q output. This device is fully specified for partial power down
applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging
backflow current through the device when it is powered down.
2. Features and benefits
•
•
•
•
•
•
•
•
Supply voltage range from 4.5 V to 5.5 V
BiCMOS high speed and output drive
Direct interface with TTL levels
Power-up 3-state
IOFF circuitry provides partial Power-down mode operation
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74ABT74D
-40 °C to +85 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74ABT74PW
-40 °C to +85 °C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
4. Functional diagram
4
4 10
3
1SD 2SD
SD
2
12
3
11
1D
D
2D
1CP
CP
2CP
2
1Q
Q
2Q
5
9
1Q
6
8
1
10
FF
Q
RD
2Q
11
12
13
1RD 2RD
1 13
Fig. 1.
S
5
C1
1D
6
R
S
9
C1
1D
8
R
mna419
mna418
Logic symbol
Fig. 2.
IEC logic symbol
nSD
nRD
Q
Q
nCP
nD
Fig. 3.
aaa-024200
Logic diagram for one flip-flop
5. Pinning information
5.1. Pinning
74ABT74
1RD
1
14 VCC
1D
2
13 2RD
1CP
3
12 2D
74ABT74
1RD
1
14 VCC
1D
2
13 2RD
3
12 2D
1SD
4
11 2CP
1CP
1Q
5
10 2SD
1SD
4
11 2CP
1Q
5
10 2SD
1Q
6
9
1Q
6
9
2Q
GND
7
8
2Q
GND
7
8
2Q
2Q
aaa-024202
aaa-024201
Fig. 4.
Pin configuration SOT108-1 (SO14)
74ABT74
Product data sheet
Fig. 5.
Pin configuration SOT402-1 (TSSOP14)
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74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
1RD, 2RD
1, 13
asynchronous reset-direct input (active LOW)
1D, 2D
2, 12
data input
1CP, 2CP
3, 11
clock input (LOW-to-HIGH, edge-triggered)
1SD, 2SD
4, 10
asynchronous set-direct input (active LOW)
1Q, 2Q
5, 9
output
1Q, 2Q
6, 8
complement output
GND
7
ground (0 V)
VCC
14
supply voltage
6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one setup time prior to low-to-high clock transition
L = LOW voltage level; l = LOW voltage level one setup time prior to low-to-high clock transition
X = don’t care
↑ = LOW-to-HIGH clock transition
Input
Output
Operating mode
nSD
nRD
nCP
nD
nQ
nQ
L
H
X
X
H
L
Asynchronous set
H
L
X
X
L
H
Asynchronous reset
L
L
X
X
H
H
Undetermined [1]
H
H
↑
h
H
L
Load "1"
H
H
↑
l
L
H
Load "0"
[1]
This setup is unstable and changes when either set or reset returns to the high level.
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
-0.5
+7.0
V
[1]
-1.2
+7.0
V
[1]
-0.5
+5.5
V
VCC
supply voltage
VI
input voltage
VO
output voltage
output in OFF-state or HIGH-state
IIK
input clamping current
VI < 0 V
-18
-
mA
IOK
output clamping current
VO < 0 V
-50
-
mA
IO
output current
output in LOW-state
-
40
mA
Tj
junction temperature
-
150
°C
Tstg
storage temperature
-65
+150
°C
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74ABT74
Product data sheet
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74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
8. Recommended operating conditions
Table 5. Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
4.5
-
5.5
V
0
-
VCC
V
VCC
supply voltage
VI
input voltage
VIH
HIGH-level input voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
IOH
HIGH-level output current
-15
-
-
mA
IOL
LOW-level output current
-
-
20
mA
Δt/ΔV
input transition rise and fall rate
0
-
10
ns/V
Tamb
ambient temperature
-40
-
+85
°C
in free air
9. Static characteristics
Table 6. Static characteristics
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C Unit
Min
Typ
Max
Min
Max
VIK
input clamping voltage
VCC = 4.5 V; IIK = -18 mA
-1.2
-0.9
-
-1.2
-
V
VOH
HIGH-level output
voltage
VCC = 4.5 V; IOH = -15 mA;
VI = VIL or VIH
2.5
2.9
-
2.5
-
V
VOL
LOW-level output
voltage
VCC = 4.5 V; IOL = 20 mA;
VI = VIL or VIH
-
0.35
0.5
-
0.5
V
II
input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
-
±0.01
±1.0
-
±1.0
μA
IOFF
power-off leakage
current
VCC = 0 V; VI or VO ≤ 4.5 V
-
±5.0
±100
-
±100
μA
ICEX
output high leakage
current
HIGH-state; VO = 5.5 V; VCC = 5.5 V;
VI = GND or VCC
-
5.0
50
-
50
μA
IO
output current
VCC = 5.5 V; VO = 2.5 V
-50
-75
-180
-50
-180
mA
ICC
supply current
VCC = 5.5 V; VI = GND or VCC
-
2
50
-
50
μA
ΔICC
additional supply
current
per input pin; VCC = 5.5 V;
one input at 3.4 V;
other inputs at VCC or GND
-
0.25
500
-
500
μA
CI
input capacitance
VI = 0 V or VCC
-
3
-
-
-
pF
[1]
[2]
[1]
[2]
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input at 3.4 V.
74ABT74
Product data sheet
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74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see Fig. 9.
Symbol Parameter
Conditions
25 °C; VCC = 5.0 V
Min
Typ
-40 °C to +85 °C; Unit
VCC = 5.0 V ± 0.5 V
Max
Min
Max
fmax
maximum frequency nCP; see Fig. 6
180
250
-
150
-
tPLH
LOW to HIGH
propagation delay
nCP to nQ, nQ; see Fig. 6
1.0
3.0
4.2
1.0
4.7
ns
tPHL
HIGH to LOW
propagation delay
nCP to nQ, nQ; see Fig. 6
1.0
2.5
3.5
1.0
4.0
ns
tPLH
LOW to HIGH
propagation delay
nSD, nRD to nQ, nQ; see Fig. 7
1.0
3.4
4.9
1.0
6.2
ns
tPHL
HIGH to LOW
propagation delay
nSD, nRD to nQ, nQ; see Fig. 7
1.0
2.9
4.5
1.0
5.2
ns
tsk(o)
output skew time
-
0.5
0.6
-
0.6
ns
tsu
set-up time
nD to nCP HIGH; see Fig. 6
2.6
1.4
-
2.6
-
ns
nD to nCP LOW; see Fig. 6
2.4
1.4
-
2.4
-
ns
0
-1.4
-
0
-
ns
[1]
MHz
th
hold time
nD to nCP HIGH or LOW; see Fig. 6
tW
pulse width
nCP HIGH or LOW; see Fig. 6
1.7
1.0
-
2.1
-
ns
nSD, nRD LOW; see Fig. 7
2.0
1.3
-
2.2
-
ns
nSD, nRD to nCP; see Fig. 8
2.1
1.4
-
2.4
-
ns
trec
[1]
recovery time
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
74ABT74
Product data sheet
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74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
10.1. Waveforms and test circuit
VI
VM
nD input
GND
th
t su
1/fmax
t su
th
VI
VM
nCP input
GND
tW
t PHL
t PLH
VOH
VM
nQ output
VOL
VOH
nQ output
VM
VOL
t PLH
t PHL
mna422
VM = 1.5 V
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6.
Propagation delay clock input (nCP) to output (nQ, nQ), set-up and hold times data input (nD) to clock
input, clock pulse width and maximum clock (nCP) frequency
74ABT74
Product data sheet
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74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
VI
VM
nCP input
GND
t rec
VI
VM
nSD input
GND
tW
tW
VI
VM
nRD input
GND
t PLH
t PHL
VOH
nQ output
VM
VOL
VOH
VM
nQ output
VOL
t PHL
t PLH
mna423
VM = 1.5 V
VOL and VOH are typical output voltage levels that occur with the output load
Fig. 7.
Propagation delay set (nSD) and reset (nSD) input to output (nQ, nQ), and set (nSD) and reset nRD pulse
width.
Vl
VM
nSD, nRD input
GND
Vl
trec
nCP input
VM
GND
aaa-024203
VM = 1.5 V
Fig. 8.
Recovery time set (nSD) and reset (nRD) to nCP
74ABT74
Product data sheet
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74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
VI
negative
pulse
tW
90 %
90 %
VM
10 %
0V
VI
positive
pulse
0V
VM
10 %
tf
tr
tr
tf
90 %
VEXT
VCC
G
90 %
VM
VI
DUT
VM
10 %
RT
10 %
tW
RL
VO
CL
mna616
001aai298
a. Input pulse definition
RL
b. Test circuit
Test data is given in Table 8.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 9.
Test circuit for measuring switching times
Table 8. Test data
Input
Load
VEXT
VI
fi
tW
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
3.0 V
1 MHz
500 ns
≤ 2.5 ns
50 pF
500 Ω
open
open
7.0 V
74ABT74
Product data sheet
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74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
11. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
A2
Q
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig. 10. Package outline SOT108-1 (SO14)
74ABT74
Product data sheet
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74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
D
SOT402-1
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
pin 1 index
(A 3 )
A1
A
θ
Lp
1
L
7
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig. 11. Package outline SOT402-1 (TSSOP14)
74ABT74
Product data sheet
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74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
12. Abbreviations
Table 9. Abbreviations
Acronym
Description
BiCMOS
Bipolar Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 10. Revision history
Document ID
Release date
Data sheet status
Change notice Supersedes
74ABT74A v.3
20201012
Product data sheet
-
Modifications:
•
•
•
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
Section 1 and Section 2 updated.
Type number 74ABT74DB (SOT337-1 / SSOP14) removed.
74ABT74A v.2
20160812
Modifications:
•
•
74ABT74A v.1
74ABT74
Product data sheet
74ABT74A v.2
Product data sheet
-
74ABT74A v.1
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
19950922
Product specification
-
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-
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11 / 13
74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
14. Legal information
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status
[1][2]
Product
status [3]
Definition
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
This document contains data from
the preliminary specification.
Product [short]
data sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or
completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
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with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
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data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
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of an Nexperia product can reasonably be expected to result in personal
74ABT74
Product data sheet
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
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liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
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may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 October 2020
©
Nexperia B.V. 2020. All rights reserved
12 / 13
74ABT74
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................2
5.1. Pinning.........................................................................2
5.2. Pin description............................................................. 3
6. Functional description................................................. 3
7. Limiting values............................................................. 3
8. Recommended operating conditions..........................4
9. Static characteristics....................................................4
10. Dynamic characteristics............................................ 5
10.1. Waveforms and test circuit........................................ 6
11. Package outline.......................................................... 9
12. Abbreviations............................................................ 11
13. Revision history........................................................11
14. Legal information......................................................12
©
Nexperia B.V. 2020. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 12 October 2020
74ABT74
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 October 2020
©
Nexperia B.V. 2020. All rights reserved
13 / 13