W78E365/W78E365A Data Sheet
8-BIT MICROCONTROLLER
Table of Contents1.
GENERAL DESCRIPTION.......................................................................................................... 3
2.
FEATURES ................................................................................................................................. 3
3.
PIN CONFIGURATIONS ............................................................................................................. 4
4.
PIN DESCRIPTION ..................................................................................................................... 5
5.
BLOCK DIAGRAM ...................................................................................................................... 6
6.
FUNCTIONAL DESCRIPTION.................................................................................................... 7
6.1
RAM ................................................................................................................................ 7
6.2
Timers 0, 1, and 2 ........................................................................................................... 8
6.2.1
6.3
6.4
6.5
Clock ............................................................................................................................... 8
6.3.1
Crystal Oscillator .............................................................................................................. 8
6.3.2
External Clock .................................................................................................................. 8
Power Management ........................................................................................................ 8
6.4.1
Idle Mode.......................................................................................................................... 8
6.4.2
Power-down Mode............................................................................................................ 9
6.4.3
Reduce EMI Emission ...................................................................................................... 9
Reset ............................................................................................................................... 9
6.5.1
6.6
W78E365 Special Function Registers (SFRs) and Reset Values .................................... 9
Port 4 ............................................................................................................................ 10
6.6.1
Port Options Register ..................................................................................................... 11
6.6.2
INT2 / INT3 .................................................................................................................. 11
6.6.3
Port 4 Base Address Registers ...................................................................................... 13
6.7
Pulse Width Modulated Outputs (PWM) ....................................................................... 15
6.8
Watchdog Timer ........................................................................................................... 18
6.9
In-System Programming (ISP) Mode ............................................................................ 20
6.9.1
7.
Timer 2 Output ................................................................................................................. 8
In-System Programming Control Register (CHPCON) ................................................... 21
6.10
Software Reset ............................................................................................................. 21
6.11
H/W Reboot Mode (Boot from LDROM) ....................................................................... 22
6.12
Security ......................................................................................................................... 25
ELECTRICAL CHARACTERISTICS ......................................................................................... 27
7.1
Absolute Maximum Ratings .......................................................................................... 27
7.2
D.C. Characteristics ...................................................................................................... 27
7.3
A.C. Characteristics ...................................................................................................... 29
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Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
8.
9.
10.
11.
TIMING WAVEFORMS ............................................................................................................. 30
8.1
Program Fetch Cycle .................................................................................................... 30
8.2
Data Read Cycle ........................................................................................................... 31
8.3
Data Write Cycle ........................................................................................................... 32
8.4
Port Access Cycle ......................................................................................................... 33
TYPICAL APPLICATION CIRCUIT ........................................................................................... 34
9.1
External Program Memory and Crystal ......................................................................... 34
9.2
Expanded External Data Memory and Oscillator .......................................................... 35
PACKAGE DIMENSIONS ......................................................................................................... 36
10.1
40-pin DIP ..................................................................................................................... 36
10.2
44-pin PLCC ................................................................................................................. 36
10.3
44-pin PQFP ................................................................................................................. 37
10.4
48-pin LQFP .................................................................................................................. 38
APPLICATION NOTE ............................................................................................................... 39
11.1
12.
In-system Programming Software Examples................................................................ 39
REVISION HISTORY ................................................................................................................ 44
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Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
1. GENERAL DESCRIPTION
The W78E365 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E365 is fully compatible with the standard 8052. The
W78E365 contains a 64K bytes of main Flash APROM and a 4K bytes of auxiliary Flash LDROM
which allows the contents of the 64KB main APROM to be updated by the loader program located at
the LDROM; 256+1K bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an
additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a
eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside
the W78E365 allows the program memory to be programmed and read electronically. Once the code is
confirmed, the user can protect the code for security.
The W78E365 microcontroller has two power reduction modes, idle mode and power-down mode, both
of which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
Fully static design 8-bit CMOS microcontroller
64K bytes of in-system programmable Flash EPROM for Application Program (APROM)
4K bytes of auxiliary ROM for Loader Program (LDROM)
256+1K bytes of on-chip RAM. (Including 1K bytes of AUX-RAM, software selectable)
Four 8-bit bi-directional ports; Port 0 has internal pull-up resisters enabled by software
One 4-bit multipurpose programmable port (I/O, interrupt, Chip select function)
Three 16-bit timer/counters
One full duplex serial port
Watchdog timer
5 channel PWM
Software Reset
P1.0 T2 programmable clock out
Eight-sources, two-level interrupt capability
Built-in power management
Code protection
Packaged in
Lead Free (RoHS) DIP 40:
Lead Free (RoHS) PLCC 44:
Lead Free (RoHS) PQFP 44:
Lead Free (RoHS) LQFP 48:
W78E365A40DL
W78E365A40PL
W78E365A40FL
W78E365A40LL
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Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
3. PIN CONFIGURATIONS
40-pin DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
T2, P1.0
T2EX, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
44-pin PLCC
T
2
E
X
,
P P P P
1 1 1 1
. . . .
4 3 2 1
VDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
RXD, P3.0
INT2, P4.3
TXD, P3.1
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
44-pin PQFP
P1.1
P1.0
P4.2
VDD
P0.0
P0.1
P0.2
P0.3
45
44
43
42
41
40
39
38
37
8
29
ALE
P3.3
9
28
PSEN
P3.4
10
27
P2.7
P3.5
11
26
P2.6
NC
12
25
P2.5
NC
P4.1
P3.2
P2.4
30
24
7
P2.3
EA
P3.1
23
31
P2.2
6
22
P0.7
P4.3
P2.1
32
21
5
P2.0
P0.6
P3.0
20
33
P4.0
4
19
P0.5
RST
VSS
34
18
3
XTAL1
P0.4
P1.7
17
NC
35
XTAL2
36
2
16
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P1.2
EA
P4.1
ALE
1
P1.6
P3.7
P
2
.
3
,
A
1
1
AD4
AD5
AD6
AD7
P1.5
15
P
2
.
2
,
A
1
0
P0.4,
P0.5,
P0.6,
P0.7,
46
A
D
3
,
P
0
.
3
P3.6
P
2
.
1
,
A
9
P
2
.
4
,
A
1
2
14
X V P P
T S 4 2
A S . .
L
0 0
1
,
A
8
P
2
.
3
,
A
1
1
13
X
T
A
L
2
P
2
.
2
,
A
1
0
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P1.3
A
D
2
,
P
0
.
2
44 43 42 41 40 39 38 37 36 35 34
33
32
31
3
30
4
29
5
28
6
27
7
26
8
9
25
10
24
23
11
12 13 14 15 16 17 18 19 20 21 22
P
3
.
7
,
/
R
D
P
2
.
1
,
A
9
ALE
48-pin LQFP
1
2
P
3
.
6
,
/
W
R
X V P P
T S 4 2
A S . .
L
0 0
1
,
A
8
AD4
AD5
AD6
AD7
EA
P4.1
47
INT1, P3.3
T0, P3.4
T1, P3.5
X
T
A
L
2
P0.4,
P0.5,
P0.6,
P0.7,
48
INT0, P3.2
A
D
3
,
P
0
.
3
A
D
2
,
P
0
.
2
NC
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
T
2
,
P
1
.
0
A
D
1
,
P
0
.
1
P1.4
T
2
E
X
,
P P P P
1 1 1 1
. . . .
4 3 2 1
/
I
A A
N
D D
T
0 1
3
, ,
,
P P
P
V
0 0
4
. D . .
D
0 1
2
A
D
0
,
P
0
.
0
6 5 4 3 2 1 44 43 42 41 40
7
39
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
18 19 20 21 22 23 24 25 26 27 28
P1.5
P1.6
P1.7
RST
EA
ALE
/
I
N
T T
2 3
, ,
P P
1 4 V
. . D
0 2 D
P
2
.
4
,
A
1
2
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Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
4. PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTIONS
EA
I
PSEN
O H
ALE
O H
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RST
I L
RESET: A high on this pin for two machine cycles while the oscillator is running
resets the device.
XTAL1
I
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
XTAL2
O
CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS
I
GROUND: ground potential.
VDD
I
POWER SUPPLY: Supply voltage for operation.
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
the EA pin is high.
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
PORT 0: Function is the same as that of standard 8052.
P0.0 P0.7
I/O D This port also provides a multiplexed low order address/data bus during
accesses to external memory. Port 0 has internal pull-up resisters enabled by
software.
P1.0 P1.7
I/O H PORT 1: Function is the same as that of standard 8052.
P2.0 P2.7
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory. The P2.6
I/O H
and P2.7 also provide the alternate function REBOOT which is H/W reboot
from LD flash.
P3.0 P3.7
I/O H PORT 3: Function is the same as that of the standard 8052.
P4.0 P4.7
I/O H
PORT 4: A bi-directional I/O. The P4.3 also provides the alternate function
REBOOT which is H/W reboot from LD flash.
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
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Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
5. BLOCK DIAGRAM
P1.0
Port
1
Port 1
Latch
P1.7
ACC
B
P0.0
Port 0
Interrupt
T1
Latch
T2
P0.7
Timer
2
Timer
0
Port
0
DPTR
Stack
Pointer
PSW
ALU
Temp Reg.
Timer
1
PC
Incrementor
UART
Addr. Reg.
P3.0
Port
3
Port 3
Latch
P3.7
64KB
SFR RAM
Address
Instruction
Decoder
&
Sequencer
Flash APROM
4KB
Flash LDROM
256+1K bytes
RAM & SFR
P2.0
Port 2
Latch
Bus & Clock
Controller
P4.0
P4.3
Port
4
Port
2
P2.7
Port 4
Latch
Oscillator
XTAL1 XTAL2
Reset Block
ALE
PSEN
RST
-6-
Pow er control
VCC
Vs s
Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
6. FUNCTIONAL DESCRIPTION
The W78E365 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 256+1K bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.
6.1
RAM
The internal data RAM in the W78E365 is 256+1K bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 1K bytes of AUX-RAM. These RAMs are addressed by different ways.
RAM 0H 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
RAM 80H FFH can only be addressed indirectly as the same as in 8051. Address pointers are
R0, R1 of the selected registers bank.
AUX-RAM 0H 3FFH is addressed indirectly as the same way to access external data memory
with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than 3FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is enabled after a reset.
Clearing the bit 4 in CHPCON register will disable the access to AUX-RAM. When executing from
internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD .
Example:
CHPENR
CHPCON
XRAMAH
MOV
MOV
ORL
MOV
MOV
MOV
MOV
MOVX
MOV
MOV
MOVX
MOV
MOV
MOVX
MOV
MOVX
REG
REG
REG
F6H
BFH
A1H
CHPENR , #87H
CHPENR, #59H
CHPCON, #00010000B
CHPENR, #00H
XRAMAH, #01H
R0, #23H
A, #55H
@R0, A
XRAMAH, #02H
R1, #FFH
A, @R1
DPTR, #0134H
A, #78H
@DPTR, A
DPTR, #7FFFH
A, @DPRT
; enable AUX-RAM
; internal high address
; Write 55h data to 0123h AUX-RAM address.
; Read data from 02FFh AUX-RAM address.
; Write 78h data to 0134h AUX-RAM address.
; Read data from the external 7FFFh address SRAM
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Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
6.2
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by
the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or
as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.
6.2.1
Timer 2 Output
If set T2OE (T2MOD.1) bit and clear C/T2 (T2CON.1) bit at auto-reload mode, P1.0 will be toggled
once overflow.
TIMER 2 Mode
Bit:
7
6
5
4
3
2
1
0
T2OE
Mnemonic: T2MOD
Address: C9H
T2OE: Enable this bit to toggle P1.0 pin while Timer2 has been overflowed.
6.3
Clock
The W78E365 is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78E365 relatively insensitive to duty cycle
variations in the clock.
6.3.1
Crystal Oscillator
The W78E365 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground.
6.3.2
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
6.4
6.4.1
Power Management
Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the
processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will
exit idle mode when either an interrupt or a reset occurs.
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Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
6.4.2
Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware
reset or external interrupts INT0 to INT1 when enabled and set to level triggered.
6.4.3
Reduce EMI Emission
The W78E365 allows user to diminish the gain of on-chip oscillator amplifier by using programmer to
clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the
external crystal operating improperly at high frequency. The value of C1 and C2 may need some
adjustment while running at lower gain.
ALE Off Function
Auxiliary Register
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
ALEOFF
Mnemonic: AUXR
Address: 8EH
ALEOFF: Set this bit to disable ALE output.
6.5
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E365 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
6.5.1
W78E365 Special Function Registers (SFRs) and Reset Values
F8
F0
+B
00000000
CHPENR
00000000
E8
E0
D8
D0
C8
C0
+ACC
00000000
+P4
11111111
+PSW
00000000
+T2CON
00000000
+XICON
00000000
PWMP
00000000
PWM0
00000000
PWM1
00000000
PWMCON1
00000000
PWM2
00000000
PWM3
00000000
T2MOD
00000000
RCAP2L
00000000
P4CONA
00000000
RCAP2H
00000000
P4CONB
00000000
TL2
00000000
SFRAL
00000000
TH2
00000000
SFRAH
00000000
PWMCON2
00000000
SFRFD
00000000
-9-
PWM4
00000000
SFRCN
00000000
Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
W78E365 Special Function Registers (SFRs) and Reset Values, continued
+IP
00000000
+P3
11111111
+IE
00000000
+P2
11111111
+SCON
00000000
+P1
11111111
+TCON
00000000
+P0
11111111
B8
B0
A8
A0
98
90
88
80
CHPCON
00x11000
P43AL
00000000
P42AL
00000000
P43AH
00000000
P42AH
00000000
P4CSIN
00000000
P41AL
00000000
TH0
00000000
P40AL
00000000
P41AH
00000000
TH1
00000000
P40AH
00000000
AUXR
00000000
POR
00000000
XRAMAH
00000000
SBUF
xxxxxxxx
TMOD
00000000
SP
00000111
TL0
00000000
DPL
00000000
TL1
00000000
DPH
00000000
WDTC
00000000
PCON
00110000
Notes:
1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable.
2. The text of SFR with bold type characters are extension function registers.
6.6
Port 4
Port 4, address D8H, is a 8-bit multipurpose programmable I/O port. Each bit can be configured
individually by software. The Port 4 has four different operation modes.
Mode 0: P4.0P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as
external interrupt PSEN and INT2 if enabled.
Mode 1: P4.0P4.3 are read strobe signals that are synchronized with RD signal at specified
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 2: P4.0P4.3 are write strobe signals that are synchronized with WR signal at specified
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 3: P4.0P4.3 are read/write strobe signals that are synchronized with RD or WR signal at
specified addresses. These signals can be used as chip-select signals for external
peripherals.
When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH
and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the
control bits to configure the Port 4 operation mode.
- 10 -
Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
6.6.1
Port Options Register
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
P0UP
Mnemonic: POR
Address: 86H
P0UP: Enable Port 0 weak up. The pins of Port 0 can be configured with either the open drain or
standard port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When
the P0UP bit in the POR register is set, the pins of port 0 will perform a bi-directional I/O port with
internal pull-up that is structurally the same Port2.
6.6.2
INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown
by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable
but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the
XICON register, one can use the "SETB ( CLR ) bit" instruction. For example, "SETB 0C2H" sets the
EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
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Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
Eight-source interrupt information:
VECTOR
ADDRESS
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
External Interrupt 0
03H
0 (highest)
IE.0
TCON.0
Timer/Counter 0
0BH
1
IE.1
-
External Interrupt 1
13H
2
IE.2
TCON.2
Timer/Counter 1
1BH
3
IE.3
-
Serial Port
23H
4
IE.4
-
Timer/Counter 2
2BH
5
IE.5
-
External Interrupt 2
33H
6
XICON.2
XICON.0
External Interrupt 3
3BH
7 (lowest)
XICON.6
XICON.3
INTERRUPT SOURCE
P4CONB (C3H)
BIT
NAME
FUNCTION
00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
7, 6
P43FUN1 10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address
P43FUN0
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.
5, 4
3, 2
1, 0
Chip-select signals address comparison:
00: Compare the full address (16 bits length) with the base address register
P43AH, P43AL.
01: Compare the 15 high bits (A15A1) of address bus with the base address
P43CMP1
register P43AH, P43AL.
P43CMP0
10: Compare the 14 high bits (A15A2) of address bus with the base address
register P43AH, P43AL.
11: Compare the 8 high bits (A15A8) of address bus with the base address
register P43AH, P43AL.
P42FUN1 The P4.2 function control bits which are the similar definition as P43FUN1,
P42FUN0 P43FUN0.
P42CMP1 The P4.2 address comparator length control bits which are the similar definition
P42CMP0 as P43CMP1, P43CMP0.
- 12 -
Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
P4CONA (C2H)
BIT
NAME
FUNCTION
7, 6
P41FUN1 The P4.1 function control bits which are the similar definition as P43FUN1,
P41FUN0 P43FUN0.
5, 4
P41CMP1 The P4.1 address comparator length control bits which are the similar definition
P41CMP0 as P43CMP1, P43CMP0.
3, 2
P40FUN1 The P4.0 function control bits which are the similar definition as P43FUN1,
P40FUN0 P43FUN0.
1, 0
P40CMP1 The P4.0 address comparator length control bits which are the similar definition
P40CMP0 as P43CMP1, P43CMP0.
P4CSIN (AEH)
BIT
NAME
FUNCTION
7
The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe
signal.
= 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe
P43CSINV
signal.
= 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe
signal.
6
P42CSINV The similarity definition as P43SINV.
5
P41CSINV The similarity definition as P43SINV.
4
P40CSINV The similarity definition as P43SINV.
3
-
Reserve
2
-
Reserve
1
-
0
0
-
0
6.6.3
Port 4 Base Address Registers
P40AH, P40AL:
The Base address register for comparator of
P40AL contains the low-order byte of address.
P41AH, P41AL:
The Base address register for comparator of
P41AL contains the low-order byte of address.
P42AH, P42AL:
The Base address register for comparator of
P42AL contains the low-order byte of address.
P43AH, P43AL:
The Base address register for comparator of
P43AL contains the low-order byte of address.
P4.0. P40AH contains the high-order byte of address,
P4.1. P41AH contains the high-order byte of address,
P4.2. P42AH contains the high-order byte of address,
P4.3. P43AH contains the high-order byte of address,
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Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
P4 (D8H)
BIT
NAME
FUNCTION
7
P47
I/O pin
6
P46
I/O pin.
5
P45
I/O pin.
4
P44
I/O pin.
3
P43
Port 4 Data bit which outputs to pin P4.3 at mode 0.
2
P42
Port 4 Data bit. which outputs to pin P4.2 at mode 0.
1
P41
Port 4 Data bit. which outputs to pin P4.1at mode 0.
0
P40
Port 4 Data bit which outputs to pin P4.0 at mode 0.
Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H
1237H and positive polarity, and P4.1 P4.3 are used as general I/O ports.
MOV
MOV
MOV
MOV
MOV
P40AH, #12H
P40AL, #34H
P4CONA, #00001010B
P4CONB, #00H
P2ECON, #10H
; Base I/O address 1234H for P4.0
; P4.0 a write strobe signal and address line A0 and A1 are masked.
; P4.1 P4.3 as general I/O port which are the same as PORT1
; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity
; default is negative.
Then any instruction MOVX @DPTR, A (with DPTR = 1234H 1237H) will generate the positive
polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of
data #XX to pin P4.3 P4.1.
P4xCSINV
P4 REGISTER
P4.x
DATA I/O
RD_CS
MUX 4->1
WR_CS
READ
WRITE
RD/WR_CS
PIN
P4.x
ADDRESS BUS
P4xFUN0
P4xFUN1
EQUAL
REGISTER
P4xAL
P4xAH
Bit Length
Selectable
comparator
P4.x INPUT DATA BUS
REGISTER
P4xCMP0
P4xCMP1
- 14 -
Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
6.7
Pulse Width Modulated Outputs (PWM)
There are five pulse width modulated output channels to generate pulses of programmable length and
interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for
the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts
modular 255 (0 ~ 254). The value of the 8-bit counter compared to the contents of five registers:
PWM0, PWM1, PWM2, PWM3 and PWM4. Provided the contents of either these registers is greater
than the counter value, the corresponding PWM0, PWM1, PWM2, PWM3 or PWM4 output is set
HIGH. If the contents of these registers are equal to, or less than the counter value, the output will be
LOW. The pulse-width-ratio is defined by the contents of the registers PWM0, PWM1, PWM2, PWM3
and PWM4. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of
1/255. ENPWM0, ENPWM1, ENPWM2, ENPWM3 and ENPWM4 bit will enable or disable PWM
output.
Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be
proportional to the contents of PWM0/1/2/3/4. The repetition frequency fpwm , at the PWM0/1/2/3/4
output is given by:
fpwm
fosc
2 (1 PWMP ) 255
Prescaler division factor = PWM + 1
PWMn high/low ratio of
PWMn
(PWMn)
255 - (PWMn)
This gives a repetition frequency range of 123 Hz to 31.4K Hz ( fosc = 16M Hz). By loading the PWM
registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level,
respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the
PWM registers when they are loaded with FFH.
When a compare register (PWM0, PWM1, PWM2, PWM3, PWM4) is loaded with a new value, the
associated output updated immediately. It does not have to wait until the end of the current counter
period. There is weakly pulled high on PWM output.
- 15 -
Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
PWM0
Register
ENPWM 0/1/2/3/4/5
PWM0
Counter
X
+
1/2
PWMP
Counter
Y
8-bits Counter
PWM0
(P1.3)
>
PWM0OE
--
Fosc
PWM1
Register
X
PWM1
Counter
+
Y
PWM2
Register
X
PWM2
Counter
Y
PWM3
Register
X
PWM3
Counter
>
PWM1OE
-
+
>
PWM2OE
-
>
PWM3OE
X
PWM4
Counter
PWM2
(P1.5)
+
Y
PWM4
Register
PWM1
(P1.4)
PWM3
(P1.6)
+
>
Y
-
PWM4OE
PWM4
(P1.7)
FIGURE 1 PWM DIAGRAM
Please refer as below code.
mov pwmcon1, #00110011b
mov pwmcon2, #00000101b
mov pwmp, #40h
jb
p1.3, $
mov pwm0, #14h
jb
p1.4, $
mov pwm1, #18h
jb
p1.5, $
mov pwm2, #20h
jb
p1.6, $
mov pwm3, #b0h
jb
p1.7,$
mov pwm4, #40h
mov pwmcon1, #11111111b
; enable pwm3, 2, 1, 0
; enable pwm4
; Fpwm = XT/(2*(1+pwmp)*255)
; duty cycle high/low = pwm0/(255-pmw0)
; output enable pwm3, 2, 1, 0
- 16 -
Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
PWM3 Register
Bit:
7
6
5
4
Mnemonic: PWM3
3
2
1
0
1
0
Address: DEH
PWM2 Register
Bit:
7
6
5
4
Mnemonic: PWM2
3
2
Address: DDH
PWM Control 1 Register
Bit:
7
6
5
4
3
2
1
0
PWM3OE
PWM2OE
ENPWM3
ENPWM2
PWM1OE
PWM0OE
ENPWM1
ENWPM0
Mnemonic: PWMCON1
Address: DCH
PWM3OE: Output enable for PWM3
PWM2OE: Output enable for PWM2
ENPWM3: Enable PWM3
ENPWM2: Enable PWM2
PWM1OE: Output enable for PWM1
PWM0OE: Output enable for PWM0
ENPWM1: Enable PWM1
ENPWM0: Enable PWM0
PWM1 Register
Bit:
7
6
5
4
Mnemonic: PWM1
3
2
1
0
1
0
1
0
Address: DBH
PWM0 Register
Bit:
7
6
5
4
Mnemonic: PWM0
3
2
Address: DAH
PWMP Register
Bit:
7
6
5
4
Mnemonic: PWMP
- 17 -
3
2
Address: D9H
Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
PWM4 Register
Bit:
7
6
5
4
Mnemonic: PWM4
3
2
1
0
Address: CFH
PWM Control 2 Register
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
PWM4OE
-
ENWPM4
Mnemonic: PWMCON2
Address: CEH
PWM4OE: Output enable for PWM4
ENPWM: Enable for PWM4
6.8
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electromagnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values
depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software
should restart the Watchdog timer to put it into a known state. The control bits that support the
Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit:
7
6
5
4
3
2
1
0
ENW
CLRW
WIDL
-
-
PS2
PS1
PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
- 18 -
Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS20 as follows:
PS2 PS1 PS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
PRESCALER SELECT
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
The time-out period is obtained using the following equation:
1
214 PRESCALER 1000 12 mS
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
ENW
WIDL
IDLE
EXTERNAL
RESET
OSC
PRESCALER
1/12
Watchdog Timer Block Diagram
14-BIT TIMER
INTERNAL
RESET
CLEAR
CLRW
Typical Watch-Dog time-out period when OSC = 20 MHz
PS2 PS1 PS0
WATCHDOG TIME-OUT PERIOD
0
0
0
19.66 mS
0
0
1
39.32 mS
0
1
0
78.64 mS
0
1
1
157.28 mS
1
0
0
314.57 mS
1
0
1
629.14 mS
1
1
0
1.25 S
1
1
1
2.50 S
- 19 -
Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
6.9
In-System Programming (ISP) Mode
The W78E365 equips one 64K byte of main ROM bank for application program (called APROM) and
one 4K byte of auxiliary ROM bank for loader program (called LDROM). In the normal operation, the
microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the
W78E365 allows user to activate the In-System Programming (ISP) mode by setting the CHPCON
register. The CHPCON is read-only by default, software must write two specific values 87H, then
59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing
CHPENR register with the values except 87H and 59H will close CHPCON register write
attribute. The W78E365 achieves all in-system programming operations including enter/exit ISP
Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the
device will enter in-system programming mode after a wake-up from idle mode. Because device needs
proper time to complete the ISP operations before awaken from idle mode, software may use timer
interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for
revising contents of APROM, software located at APROM setting the CHPCON register then enter idle
mode, after awaken from idle mode the device executes the corresponding interrupt service routine in
LDROM. Because the device will clear the program counter while switching from APROM to LDROM,
the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The
device offers a software reset for switching back to APROM while the content of APROM has been
updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset
to reset the CPU. The software reset serves as a external reset. This in-system programming feature
makes the job easy and efficient in which the application needs to update firmware frequently. In some
applications, the in-system programming feature make it possible to easily update the system firmware
without opening the chassis.
SFRAH, SFRAL: The objective address of on-chip ROM in the in-system programming mode.
SFRAH contains the high-order byte of address, SFRAL contains the low-order byte of address.
SFRFD: The programming data for on-chip ROM in programming mode.
SFRCN: The control byte of on-chip ROM programming mode.
SFRCN (C7)
BIT
NAME
7
-
FUNCTION
Reserve.
On-chip ROM bank select for in-system programming.
6
WFWIN
= 0: 64K bytes ROM bank is selected as destination for re-programming.
= 1: 4K bytes ROM bank is selected as destination for re-programming.
5
OEN
ROM output enable.
4
CEN
ROM chip enable.
3, 2, 1, 0
CTRL[3:0]
The flash control signals
- 20 -
Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
MODE
WFWIN
CTRL
OEN
CEN
SFRAH, SFRAL
SFRFD
Erase 64KB APROM
0
0010
1
0
X
X
Program 64KB APROM
0
0001
1
0
Address in
Data in
Read 64KB APROM
0
0000
0
0
Address in
Data out
Erase 4KB LDROM
1
0010
1
0
X
X
Program 4KB LDROM
1
0001
1
0
Address in
Data in
Read 4KB LDROM
1
0000
0
0
Address in
Data out
6.9.1
In-System Programming Control Register (CHPCON)
CHPCON (BFH)
BIT
NAME
FUNCTION
7
SWRESET
When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
6
-
5
LD/AP
4
ENAUXRAM
3
1
Must be 1
2
-
Reserve.
1
FBOOTSL
When this bit is set to 1, and both SWRESET and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
0
FPROGEN
When this bit is set to 1, and both SWRESET and FBOOTSL are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
Reserve.
This bit is read only. 1: CPU is running LDROM program. 0: CPU is running
APROM program.
1: Enable on-chip AUX-RAM.
0: Disable the on-chip AUX-RAM
This register is protected by CHPENR register. Please write as below procedures while you would like
to write CHPCON register.
Mov CHPENR, #87h
Mov CHPENR, #59h
Anl CHPCON, #EFh ; Disable AUX-RAM
Mov CHPENR, #0h
6.10 Software Reset
Set CHPCON = 0X83, timer and enter IDLE mode. CPU will reset and restart from APFLASH after
time out.
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Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
6.11 H/W Reboot Mode (Boot from LDROM)
By default, the W78E365 boots from APROM program after a power on reset. On some occasions,
user can force the W78E365 to boot from the LDROM program via following settings. The possible
situation that you need to enter H/W REBOOT mode when the APROM program can not run properly
and device can not jump back to LDROM to execute in-system programming function. Then you can
use this H/W REBOOT mode to force the W78E365 jumps to LDROM and executes in-system
programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to
switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY
and EJECT buttons on the panel. When the APROM program fails to execute the normal application
program. User can press both two buttons at the same time and then turn on the power of the personal
computer to force the W78E365 to enter the H/W REBOOT mode. After power on of personal
computer, you can release both buttons and finish the in-system programming procedure to update the
APROM code. In application system design, user must take care of the P2, P3, ALE, EA and PSEN
pin value at reset to prevent from accidentally activating the programming mode or H/W REBOOT
mode. It is necessary to add 10K resistor on these P2.6, P2.7 and P4.3 pins.
H/W Reboot Mode
P4.3
P2.7
P2.6
MODE
X
L
L
REBOOT
L
X
X
REBOOT
The Reset Timing For Entering
F04KBOOT Mode
P2.7
Hi-Z
P2.6
Hi-Z
RST
30 mS
10 mS
- 22 -
Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
The Algorithm of In-System Programming
Part 1:32KB APROM
procedure of entering
In-System Programming Mode
START
Enter In-System
Programming Mode ?
(conditions depend on
user's application)
No
Yes
Setting control registers
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#03H
Execute the normal application
program
Setting Timer (about 1.5 us)
and enable timer interrupt
END
Start Timer and enter idle Mode.
(CPU will be wakened from idle mode
by timer interrupt, then enter In-System
Programming mode)
CPU w ill be w akened by interrupt and
re-boot f rom 4KB LDROM to execute
the loader program.
Go
- 23 -
Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
Part 2: 4KB LDROM
Go
Procedure of Updating
the 32KB APROM
Timer Interrupt Service Routine:
Stop Timer & disable interrupt
PGM
Yes
Yes
Is F04KBOOT Mode?
(CHPCON.7=1)
End of Programming ?
No
No
Reset the CHPCON Register:
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#03H
Setting Timer and enable Timer
interrupt for w ake-up .
(50us for program operation)
Yes
Is currently in the
F04KBOOT Mode ?
No
Get the parameters of new code
Setting Timer and enable Timer
interrupt for w ake-up .
(15 ms for erasing operation)
Setting erase operation mode:
MOV SFRCN,#22H
(Erase 32KB APROM)
Start Timer and enter IDLE
Mode.
(Erasing...)
(Address and data bytes)
through I/O ports, UART or
other interfaces.
Softw are reset CPU and
re-boot from the 32KB
APROM.
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#83H
Setting control registers for
programming:
MOV
MOV
MOV
MOV
Hardw are Reset
to re-boot from
new 32 KB APROM.
(S/W reset is
invalid in F04KBOOT
M ode)
SFRAH,#ADDRESS_H
SFRAL,#ADDRESS_L
SFRFD,#DATA
SFRCN,#21H
End of erase
operation. CPU w ill
be w akened by Timer
interrupt.
END
Executing new code
from address
00H in the 32KB APROM.
PGM
- 24 -
Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
6.12 Security
During the on-chip ROM programming mode, the ROM can be programmed and verified repeatedly.
Until the code inside the ROM is confirmed OK, the code can be protected. The protection of ROM and
those operations on it are described below.
The W78E365 has a Security Register that can be accessed in programming mode. Those bits of the
Security Registers can not be changed once they have been programmed from high to low. They can
only be reset through erase-all operation. The Security Register is located at the 0FFFFH of the
LDROM space.
B7 Reserved
B2 B1 B0
4KB On-chip ROM
Program Memory
LDROM
Security Bits
0000h
32KB On-chip ROM
Program Memory
0FFFh
B0: Lock bit, logic 0: active
B1: MOVC inhibit,
logic 0: the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1: no restriction.
B2: Encryption
logic 0: the encryption logic enable
logic 1: the encryption logic disable
B07: Osillator Control
logic 0: 1/2 gain
logic 1: Full gain
Default 1 for all security bits.
Reserved bits must be kept in logic 1.
Reserved
Reserved
Security Register
APROM
7FFFh
FFFFh
Special Setting Register
Lock bit
This bit is used to protect the customer's program code in the W78E365. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
ROM data and Security Register can not be accessed again.
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
- 25 -
Publication Release Date: January 12, 2009
Revision A12
W78E365/W78E365A
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
Oscillator Control
W78E365/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to
set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly
affect the external crystal operation at high frequency above 24 MHz. The value of R and C1, C2 may
need some adjustment while running at lower gain.
- 26 -
Publication Release Date: January 12, 2009
Revision A11
W78E365/W78E365A
7. ELECTRICAL CHARACTERISTICS
7.1
Absolute Maximum Ratings
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
VDDVSS
-0.3
+6.0
V
Input Voltage
VIN
VSS -0.3
VDD +0.3
V
Operating Temperature
TA
0
70
C
Storage Temperature
TST
-55
+150
C
DC Power Supply
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
7.2
D.C. Characteristics
(VDD VSS= 5V 10%, TA = 25C, Fosc = 20 MHz, unless otherwise specified.)
SYMBOL
PARAMETER
SPECIFICATION
MIN.
MAX.
UNIT
VDD
Operating Voltage
4.5
5.5
V
IDD
Operating Current
-
20
mA
IIDLE
Idle Current
-
6
mA
IPWDN
Power Down Current
-
IIN1
IIN2
Input Current
P1, P2, P3, P4
Input Current
RST
10
[*4]
ITL
P1, P2, P3, P4
No load
VDD = 5.5V
Idle mode
VDD = 5.5V
Power-down mode
VDD = 5.5V
+10
A
VDD = 5.5V
-10
+300
A
VDD = 5.5V
-10
+10
A
-500
-200
A
VDD = 5.5V
0
0.8
V
VDD = 4.5V
0
0.8
V
VDD = 4.5V
P0, EA
Logic 1 to 0 Transition Current
RST = 1, P0 = VDD
-50
Input Leakage Current
ILK
A
TEST CONDITIONS
VIN = 0V or VDD
0
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