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NUC100LC1DN

NUC100LC1DN

  • 厂商:

    NUVOTON(新唐)

  • 封装:

    LQFP48

  • 描述:

    IC MCU 32BIT 32KB FLASH 48LQFP

  • 数据手册
  • 价格&库存
NUC100LC1DN 数据手册
NUC100/120xxxDN ARM® Cortex® -M 32-bit Microcontroller NuMicro® NUC100 Series NUC100/120xxxDN Datasheet Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com Aug 31, 2015 Page 1 of 107 Rev 1.01 NUC100/120XXXDN DATASHEET The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. NUC100/120xxxDN Table of Contents List of Figures ................................................................................... 6 List of Tables .................................................................................... 7 1 GENERAL DESCRIPTION ............................................................. 8 2 FEATURES ............................................................................... 9 2.1 NuMicro® NUC100 Features – Advanced Line .......................................... 9 2.2 NuMicro® NUC120 Features – USB Line ............................................... 13 3 ABBREVIATIONS ...................................................................... 17 4 PARTS INFORMATION LIST AND PIN CONFIGURATION ..................... 19 NuMicro® NUC100/120xxxDN Selection Guide ........................................ 19 4.1 4.1.1 NuMicro® NUC100 Advanced Line Selection Guide ......................................... 19 4.1.2 NuMicro® NUC120 USB Line Selection Guide ............................................... 19 Pin Configuration ........................................................................... 21 4.2 4.2.1 NuMicro® NUC100 Pin Diagram ................................................................ 21 4.2.2 NuMicro® NUC120 Pin Diagram ................................................................ 24 Pin Description .............................................................................. 27 4.3 4.3.1 NuMicro® NUC100 Pin Description............................................................. 27 4.3.2 NuMicro® NUC120 Pin Description............................................................. 34 BLOCK DIAGRAM ...................................................................... 41 5 NUC100/120XXXDN DATASHEET 5.1 NuMicro® NUC100 Block Diagram ....................................................... 41 5.2 NuMicro® NUC120 Block Diagram ....................................................... 42 FUNCTIONAL DESCRIPTION........................................................ 43 6 6.1 ARM® Cortex® -M0 Core ................................................................... 43 6.2 System Manager ............................................................................ 45 6.2.1 Overview ........................................................................................... 45 6.2.2 System Reset ..................................................................................... 45 6.2.3 Power Modes and Wake-up Sources .......................................................... 51 6.2.4 System Power Distribution ...................................................................... 53 6.2.5 System Memory Map ............................................................................. 56 6.2.6 System Timer (SysTick) ......................................................................... 58 6.2.7 Nested Vectored Interrupt Controller (NVIC) ................................................. 59 6.3 Clock Controller ............................................................................. 60 6.3.1 Overview ........................................................................................... 60 6.3.2 Clock Generator................................................................................... 62 Aug 31, 2015 Page 2 of 107 Rev 1.01 NUC100/120xxxDN 6.3.3 System Clock and SysTick Clock .............................................................. 63 6.3.4 Peripherals Clock ................................................................................. 64 6.3.5 Power-down Mode Clock ........................................................................ 64 6.3.6 Frequency Divider Output ....................................................................... 64 6.4 FLASH MEMORY CONTROLLER (FMC) .............................................. 66 6.4.1 Overview ........................................................................................... 66 6.4.2 Features ............................................................................................ 66 6.5 External Bus Interface (EBI) .............................................................. 67 6.5.1 Overview ........................................................................................... 67 6.5.2 Features ............................................................................................ 67 6.6 General Purpose I/O (GPIO) .............................................................. 68 6.6.1 Overview ........................................................................................... 68 6.6.2 Features ............................................................................................ 68 6.7 PDMA Controller (PDMA) ................................................................. 69 6.7.1 Overview ........................................................................................... 69 6.7.2 Features ............................................................................................ 69 6.8 Timer Controller (TMR) .................................................................... 70 6.8.1 Overview ........................................................................................... 70 6.8.2 Features ............................................................................................ 70 6.9 PWM Generator and Capture Timer (PWM) ............................................ 71 Overview ........................................................................................... 71 6.9.2 Features ............................................................................................ 72 6.10 Watchdog Timer (WDT) ................................................................... 73 6.10.1 Overview ........................................................................................ 73 6.10.2 Features ......................................................................................... 73 6.11 Window Watchdog Timer (WWDT) ...................................................... 74 6.11.1 Overview ........................................................................................ 74 6.11.2 Features ......................................................................................... 74 6.13 Real Time Clock (RTC) .................................................................... 75 6.13.1 Overview ........................................................................................ 75 6.13.2 Features ......................................................................................... 75 6.14 UART Interface Controller (UART) ....................................................... 76 6.14.1 Overview ........................................................................................ 76 6.14.2 Features ......................................................................................... 78 6.15 Smart Card Host Interface (SC) .......................................................... 80 Aug 31, 2015 Page 3 of 107 Rev 1.01 NUC100/120XXXDN DATASHEET 6.9.1 NUC100/120xxxDN 6.15.1 Overview ........................................................................................ 80 6.15.2 Features ......................................................................................... 80 6.16 PS/2 Device Controller (PS2D) ........................................................... 81 6.16.1 Overview ........................................................................................ 81 6.16.2 Features ......................................................................................... 81 6.17 I2C Serial Interface Controller (I2C)....................................................... 82 6.17.1 Overview ........................................................................................ 82 6.17.2 Features ......................................................................................... 83 6.18 Serial Peripheral Interface (SPI) .......................................................... 84 6.18.1 Overview ........................................................................................ 84 6.18.2 Features ......................................................................................... 84 6.19 I2S Controller (I2S) .......................................................................... 85 6.19.1 Overview ........................................................................................ 85 6.19.2 Features ......................................................................................... 85 6.20 USB Device Controller (USB) ............................................................. 86 6.20.1 Overview ........................................................................................ 86 6.20.2 Features ......................................................................................... 86 6.21 Analog-to-Digital Converter (ADC) ....................................................... 87 6.21.1 Overview ........................................................................................ 87 6.21.2 Features ......................................................................................... 87 NUC100/120XXXDN DATASHEET 6.22 Analog Comparator (ACMP) .............................................................. 88 6.22.1 Overview ........................................................................................ 88 6.22.2 Features ......................................................................................... 88 7 APPLICATION CIRCUIT............................................................... 89 8 ELECTRICAL CHARACTERISTICS ................................................. 90 8.1 Absolute Maximum Ratings ............................................................... 90 8.2 DC Electrical Characteristics .............................................................. 91 8.3 AC Electrical Characteristics .............................................................. 95 8.3.1 External 4~24 MHz High Speed Oscillator .................................................... 95 8.3.2 External 4~24 MHz High Speed Crystal ....................................................... 95 8.3.3 External 32.768 kHz Low Speed Crystal Oscillator .......................................... 96 8.3.4 Internal 22.1184 MHz High Speed Oscillator ................................................. 96 8.3.5 Internal 10 kHz Low Speed Oscillator ......................................................... 96 8.4 8.4.1 Analog Characteristics ..................................................................... 97 12-bit SARADC Specification ................................................................... 97 Aug 31, 2015 Page 4 of 107 Rev 1.01 NUC100/120xxxDN 8.4.2 LDO and Power Management Specification .................................................. 97 8.4.3 Low Voltage Reset Specification ............................................................... 98 8.4.4 Brown-out Detector Specification ............................................................... 98 8.4.5 Power-on Reset Specification................................................................... 98 8.4.6 Temperature Sensor Specification ............................................................. 99 8.4.7 Comparator Specification ........................................................................ 99 8.4.8 USB PHY Specification ......................................................................... 100 8.5 Flash DC Electrical Characteristics .................................................... 102 PACKAGE DIMENSIONS ........................................................... 103 9 9.1 100-pin LQFP (14x14x1.4 mm footprint 2.0 mm) .................................... 103 9.2 64-pin LQFP (10x10x1.4 mm footprint 2.0 mm) ...................................... 104 9.3 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ......................................... 105 10 REVISION HISTORY................................................................. 106 NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 5 of 107 Rev 1.01 NUC100/120xxxDN List of Figures Figure 4-1 NuMicro® NUC100 Series Selection Code ................................................................... 20 Figure 4-2 NuMicro® NUC100VxxDN LQFP 100-pin Diagram ...................................................... 21 Figure 4-3 NuMicro® NUC100RxxDN LQFP 64-pin Diagram ........................................................ 22 Figure 4-4 NuMicro® NUC100LxxDN LQFP 48-pin Diagram ......................................................... 23 Figure 4-5 NuMicro® NUC120VxxDN LQFP 100-pin Diagram ...................................................... 24 Figure 4-6 NuMicro® NUC120RxxDN LQFP 64-pin Diagram ........................................................ 25 Figure 4-7 NuMicro® NUC120LxxDN LQFP 48-pin Diagram ......................................................... 26 Figure 5-1 NuMicro® NUC100 Block Diagram ............................................................................... 41 Figure 5-2 NuMicro® NUC120 Block Diagram ............................................................................... 42 Figure 6-1 Functional Controller Diagram ...................................................................................... 43 Figure 6-2 System Reset Resources ............................................................................................. 46 Figure 6-3 nRESET Reset Waveform ............................................................................................ 48 Figure 6-4 Power-on Reset (POR) Waveform ............................................................................... 48 Figure 6-5 Low Voltage Reset (LVR) Waveform............................................................................ 49 Figure 6-6 Brown-Out Detector (BOD) Waveform ......................................................................... 50 Figure 6-7 Power Mode State Machine ......................................................................................... 51 Figure 6-8 NuMicro® NUC100 Power Distribution Diagram ........................................................... 54 Figure 6-9 NuMicro® NUC120 Power Distribution Diagram ........................................................... 55 Figure 6-10 Clock Generator Global View Diagram....................................................................... 61 Figure 6-11 Clock Generator Block Diagram ................................................................................. 62 NUC100/120XXXDN DATASHEET Figure 6-12 System Clock Block Diagram ..................................................................................... 63 Figure 6-13 SysTick Clock Control Block Diagram ........................................................................ 63 Figure 6-14 Clock Source of Frequency Divider ............................................................................ 64 Figure 6-15 Frequency Divider Block Diagram .............................................................................. 65 Figure 6-16 UART nRTS Auto-Flow Control Trigger Level ............................................................ 77 Figure 6-17 I2C Bus Timing ............................................................................................................ 82 Figure 8-1 Typical Crystal Application Circuit ................................................................................ 96 Aug 31, 2015 Page 6 of 107 Rev 1.01 NUC100/120xxxDN List of Tables Table 1-1 NuMicro® NUC100 Series Connectivity Support Table ................................................... 8 Table 3-1 List of Abbreviations....................................................................................................... 18 Table 6-1 Reset Value of Registers ............................................................................................... 47 Table 6-2 Power Mode Difference Table ....................................................................................... 51 Table 6-3 Clocks in Power Modes ................................................................................................. 52 Table 6-4 Condition of Entering Power-down Mode Again ............................................................ 53 Table 6-5 Address Space Assignments for On-Chip Controllers ................................................... 57 Table 6-6 UART Baud Rate Equation ............................................................................................ 76 Table 6-7 UART Baud Rate Setting Table ..................................................................................... 77 NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 7 of 107 Rev 1.01 NUC100/120xxxDN 1 GENERAL DESCRIPTION The NuMicro® NUC100 series 32-bit microcontroller (MCU) is embedded with the ARM® Cortex® M0 core with the cost equivalent to traditional 8-bit MCU. The NUC100 series can be used in consumer electronics, industrial control and applications which requiring rich communication interfaces such as industrial automation, alarm system, energy system and power system. The NuMicro® NUC100 Advanced Line and NUC120 USB Line are embedded with the Cortex® M0 core running up to 50 MHz and features 32/64/128 Kbytes Flash, 4/8/16 Kbytes embedded SRAM and 4 Kbytes loader ROM for the ISP. It operates at a wide voltage range of 2.5V ~ 5.5V and temperature range of -40℃ ~ +85℃. The NUC100 series is also provided with plenty of peripheral devices, such as Timers, Watchdog Timer, Window Watchdog Timer, RTC, PDMA with CRC calculation unit, UART, SPI, I2C, I2S, PWM Timer, GPIO, PS/2, EBI, Smart Card Host, 12-bit ADC, Analog Comparator, Low Voltage Reset Controller and Brown-out Detector. Additionally, the NUC120 USB Line is equipped with a USB 2.0 Full-speed Device. These peripherals have been incorporated into the NUC100 series to reduce component count, board space and system cost. The NUC100 series is equipped with ISP (In-System Programming), IAP (In-ApplicationProgramming) and ICP (In-Circuit Programming) functions, which allows the user to update the program under software control through the on-chip connectivity interface, such as SWD, UART and USB. 2 2 Product Line UART SPI IC USB PS/2 IS SC NUC100xxxDN 3 4 2 - 1 1 3 NUC120xxxDN 3 4 2 1 1 1 3 ® Table 1-1 NuMicro NUC100 Series Connectivity Support Table NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 8 of 107 Rev 1.01 NUC100/120xxxDN 2 FEATURES The equipped features are dependent on the product line and their sub products. 2.1 NuMicro® NUC100 Features – Advanced Line  ARM® Cortex® -M0 core – Runs up to 50 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – Serial Wire Debug supports with 2 watchpoints/4 breakpoints  Built-in LDO for wide operating voltage ranged from 2.5 V to 5.5 V  Flash Memory – – – 32/64/128 Kbytes Flash for program code 4 KB flash for ISP loader Supports In-System-Program (ISP) and In-Application-Program (IAP) application code update – 512 byte page erase for flash – Configurable Data Flash address and size for 128 KB system, fixed 4 KB Data Flash for the 32 KB and 64 KB system – Supports 2-wired ICP update through SWD/ICE interface – Supports fast parallel programming mode by external programmer  SRAM Memory – 4/8/16 Kbytes embedded SRAM – Supports PDMA mode  PDMA (Peripheral DMA) – – – Flexible selection for different applications Built-in 22.1184 MHz high speed oscillator for system operation  Trimmed to ±1 % at +25 ℃ and VDD = 5 V  Trimmed to ±3 % at -40 ℃ ~ +85 ℃ and VDD = 2.5 V ~ 5.5 V – Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation – Supports one PLL, up to 50 MHz, for high performance system operation – External 4~24 MHz high speed crystal input for precise timing operation – External 32.768 kHz low speed crystal input for RTC function and low power system operation  GPIO – Four I/O modes:  Quasi-bidirectional  Push-pull output  Open-drain output  Input only with high impendence – TTL/Schmitt trigger input selectable – I/O pin configured as interrupt source with edge/level setting  Timer Aug 31, 2015 Page 9 of 107 Rev 1.01 NUC100/120XXXDN DATASHEET Supports 9 channels PDMA for automatic data transfer between SRAM and peripherals – Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC16 and CRC-32  Clock Control NUC100/120xxxDN – Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter – Independent clock source for each timer – Provides one-shot, periodic, toggle and continuous counting operation modes – Supports event counting function – Supports input capture function  Watchdog Timer – Multiple clock sources – 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source) – Wake-up from Power-down or Idle mode – Interrupt or reset selectable on watchdog time-out  Window Watchdog Timer – 6-bit down counter with 11-bit prescale for wide range window selected  RTC – – – – – – Supports software compensation by setting frequency compensate register (FCR) Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) Supports Alarm registers (second, minute, hour, day, month, year) Selectable 12-hour or 24-hour mode Automatic leap year recognition Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second – Supports wake-up function  PWM/Capture – NUC100/120XXXDN DATASHEET Up to four built-in 16-bit PWM generators providing eight PWM outputs or four complementary paired PWM outputs – Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one Dead-Zone generator for complementary paired PWM – Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight rising/falling capture inputs – Supports Capture interrupt  UART – – – – – – – –  SPI – – – – – – – – – – Aug 31, 2015 Up to three UART controllers UART ports with flow control (TXD, RXD, CTS and RTS) UART0 with 64-byte FIFO is for high speed UART1/2(optional) with 16-byte FIFO for standard device Supports IrDA (SIR) and LIN function Supports RS-485 9-bit mode and direction control Programmable baud-rate generator up to 1/16 system clock Supports PDMA mode Up to four sets of SPI controllers SPI clock rate of Master can be up to 36 MHz (chip working at 5V); SPI clock rate of Slave can be up to 18 MHz (chip working at 5V) Supports SPI Master/Slave mode Full duplex synchronous serial data transfer Variable length of transfer data from 8 to 32 bits MSB or LSB first data transfer Rx and Tx on both rising or falling edge of serial clock independently Two slave/device select lines in Master mode, and one slave/device select line in Slave mode Supports Byte Suspend mode in 32-bit transmission Supports PDMA mode Page 10 of 107 Rev 1.01 NUC100/120xxxDN  – Supports three wire, no slave select signal, bi-direction interface I2C – – – – – – – – – –  I2S Up to two sets of I2C device Master/Slave mode Bidirectional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer Programmable clocks allowing for versatile rate control Supports multiple address recognition (four slave address with mask option) Supports wake-up function – Interface with external audio CODEC – Operate as either Master or Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Supports mono and stereo audio data – Supports I2S and MSB justified data format – Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving  PS/2 Device NUC100/120XXXDN DATASHEET – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – Software override bus  EBI (External bus interface) – Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode – Supports 8-/16-bit data width – Supports byte write in 16-bit data width mode  ADC – 12-bit SAR ADC with 760 kSPS – Up to 8-ch single-end input or 4-ch differential input – Single scan/single cycle scan/continuous scan – Each channel with individual result register – Scan on enabled channels – Threshold voltage detection – Conversion started by software programming or external input – Supports PDMA mode  Analog Comparator – Up to two analog comparators – External input or internal Band-gap voltage selectable at negative node – Interrupt when compare results change – Supports Power-down wake-up  Smart Card Host (SC) – – Aug 31, 2015 Compliant to ISO-7816-3 T=0, T=1 Supports up to three ISO-7816-3 ports Page 11 of 107 Rev 1.01 NUC100/120xxxDN – – – – – Separate receive / transmit 4 bytes entry FIFO for data payloads Programmable transmission clock frequency Programmable receiver buffer trigger level Programmable guard time selection (11 ETU ~ 266 ETU) One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting times processing – Supports auto inverse convention function – Supports transmitter and receiver error retry and error limit function – Supports hardware activation sequence process – Supports hardware warm reset sequence process – Supports hardware deactivation sequence process – Supports hardware auto deactivation sequence when detecting the card is removal  96-bit unique ID (UID)  One built-in temperature sensor with 1℃ resolution  Brown-out Detector – With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V – Supports Brown-out Interrupt and Reset option  Low Voltage Reset – Threshold voltage level: 2.0 V  Operating Temperature: -40℃ ~ 85℃  Packages: – – – – All Green package (RoHS) LQFP 100-pin LQFP 64-pin LQFP 48-pin NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 12 of 107 Rev 1.01 NUC100/120xxxDN 2.2 NuMicro® NUC120 Features – USB Line  ARM® Cortex® -M0 core – Runs up to 50 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – Serial Wire Debug supports with 2 watchpoints/4 breakpoints  Built-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V  Flash Memory – – – 32/64/128 Kbytes Flash for program code 4 KB flash for ISP loader Supports In-System-Program (ISP) and In-Application-Program (IAP) application code update – 512 byte page erase for flash – Configurable Data Flash address and size for 128 KB system, fixed 4 KB Data Flash for the 32 KB and 64 KB system – Supports 2-wired ICP update through SWD/ICE interface – Supports fast parallel programming mode by external programmer  SRAM Memory – 4/8/16 Kbytes embedded SRAM – Supports PDMA mode  PDMA (Peripheral DMA) – – – Flexible selection for different applications Built-in 22.1184 MHz high speed oscillator for system operation  Trimmed to ±1 % at +25 ℃ and VDD = 5 V  Trimmed to ±3 % at -40 ℃ ~ +85 ℃ and VDD = 2.5 V ~ 5.5 V – Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation – Supports one PLL, up to 50 MHz, for high performance system operation – External 4~24 MHz high speed crystal input for USB and precise timing operation – External 32.768 kHz low speed crystal input for RTC function and low power system operation  GPIO – Four I/O modes:  Quasi-bidirectional  Push-pull output  Open-drain output  Input only with high impendence – TTL/Schmitt trigger input selectable – I/O pin configured as interrupt source with edge/level setting  Timer – – – Aug 31, 2015 Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter Independent clock source for each timer Provides one-shot, periodic, toggle and continuous counting operation modes Page 13 of 107 Rev 1.01 NUC100/120XXXDN DATASHEET Supports 9 channels PDMA for automatic data transfer between SRAM and peripherals – Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC16 and CRC-32  Clock Control NUC100/120xxxDN – Supports event counting function – Supports input capture function  Watchdog Timer – Multiple clock sources – 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source) – Wake-up from Power-down or Idle mode – Interrupt or reset selectable on watchdog time-out  Window Watchdog Timer – 6-bit down counter with 11-bit prescale for wide range window selected  RTC – – – – – – Supports software compensation by setting frequency compensate register (FCR) Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) Supports Alarm registers (second, minute, hour, day, month, year) Selectable 12-hour or 24-hour mode Automatic leap year recognition Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second – Supports wake-up function  PWM/Capture – Up to four built-in 16-bit PWM generators providing eight PWM outputs or four complementary paired PWM outputs – Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one Dead-Zone generator for complementary paired PWM – Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight rising/falling capture inputs – Supports Capture interrupt  UART NUC100/120XXXDN DATASHEET – – – – – – – –  SPI – – – – – – – – – – – –  Up to three UART controllers UART ports with flow control (TXD, RXD, CTS and RTS) UART0 with 64-byte FIFO is for high speed UART1/2(optional) with 16-byte FIFO for standard device Supports IrDA (SIR) and LIN function Supports RS-485 9-bit mode and direction control Programmable baud-rate generator up to 1/16 system clock Supports PDMA mode Up to four sets of SPI controllers The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V) The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V) Supports SPI Master/Slave mode Full duplex synchronous serial data transfer Variable length of transfer data from 8 to 32 bits MSB or LSB first data transfer Rx and Tx on both rising or falling edge of serial clock independently Two slave/device select lines in Master mode, and one slave/device select line in Slave mode Supports Byte Suspend mode in 32-bit transmission Supports PDMA mode Supports three wire, no slave select signal, bi-direction interface I2C Aug 31, 2015 Page 14 of 107 Rev 1.01 NUC100/120xxxDN – – – – – – – – – –  I2S Up to two sets of I2C device Master/Slave mode Bidirectional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer Programmable clocks allowing for versatile rate control Supports multiple address recognition (four slave address with mask option) Supports wake-up function – Interface with external audio CODEC – Operate as either Master or Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Supports mono and stereo audio data – Supports I2S and MSB justified data format – Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving  PS/2 Device – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – Software override bus  EBI (External bus interface) NUC100/120XXXDN DATASHEET – Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode – Supports 8-/16-bit data width – Supports byte write in 16-bit data width mode  USB 2.0 Full-Speed Device – One set of USB 2.0 FS Device 12 Mbps – On-chip USB Transceiver – Provides 1 interrupt source with 4 interrupt events – Supports Control, Bulk In/Out, Interrupt and Isochronous transfers – Auto suspend function when no bus signaling for 3 ms – Provides 6 programmable endpoints – Includes 512 Bytes internal SRAM as USB buffer – Provides remote wake-up capability  ADC – 12-bit SAR ADC with 760 kSPS – Up to 8-ch single-end input or 4-ch differential input – Single scan/single cycle scan/continuous scan – Each channel with individual result register – Scan on enabled channels – Threshold voltage detection – Conversion started by software programming or external input – Supports PDMA mode  Analog Comparator Aug 31, 2015 Page 15 of 107 Rev 1.01 NUC100/120xxxDN – Up to two analog comparators – External input or internal Band-gap voltage selectable at negative node – Interrupt when compare results change – Supports Power-down wake-up  Smart Card Host (SC) – – – – – – – Compliant to ISO-7816-3 T=0, T=1 Supports up to three ISO-7816-3 ports Separate receive / transmit 4 bytes entry FIFO for data payloads Programmable transmission clock frequency Programmable receiver buffer trigger level Programmable guard time selection (11 ETU ~ 266 ETU) One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting times processing – Supports auto inverse convention function – Supports transmitter and receiver error retry and error limit function – Supports hardware activation sequence process – Supports hardware warm reset sequence process – Supports hardware deactivation sequence process – Supports hardware auto deactivation sequence when detecting the card removal  96-bit unique ID (UID)  One built-in temperature sensor with 1℃ resolution  Brown-out Detector – With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V – Supports Brown-out Interrupt and Reset option  Low Voltage Reset  NUC100/120XXXDN DATASHEET  – Threshold voltage level: 2.0 V Operating Temperature: -40℃ ~ 85℃ Packages: – – – – Aug 31, 2015 All Green package (RoHS) LQFP 100-pin LQFP 64-pin LQFP48-pin Page 16 of 107 Rev 1.01 NUC100/120xxxDN 3 ABBREVIATIONS Description ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AES Advanced Encryption Standard APB Advanced Peripheral Bus AHB Advanced High-Performance Bus BOD Brown-out Detection CAN Controller Area Network DAP Debug Access Port DES Data Encryption Standard EBI External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO First In, First Out FMC Flash Memory Controller FPU Floating-point Unit GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC 22.1184 MHz Internal High Speed RC Oscillator HXT 4~24 MHz External High Speed Crystal Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIN Local Interconnect Network LIRC 10 kHz internal low speed RC oscillator (LIRC) MPU Memory Protection Unit NVIC Nested Vectored Interrupt Controller PCLK The Clock of Advanced Peripheral Bus PDMA Peripheral Direct Memory Access PLL Phase-Locked Loop PWM Pulse Width Modulation QEI Quadrature Encoder Interface SDIO Secure Digital Input/Output SPI Serial Peripheral Interface Aug 31, 2015 Page 17 of 107 NUC100/120XXXDN DATASHEET Acronym Rev 1.01 NUC100/120xxxDN SPS Samples per Second TDES Triple Data Encryption Standard TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 3-1 List of Abbreviations NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 18 of 107 Rev 1.01 NUC100/120xxxDN 4 PARTS INFORMATION LIST AND PIN CONFIGURATION 4.1 NuMicro® NUC100/120xxxDN Selection Guide 4.1.1 NuMicro® NUC100 Advanced Line Selection Guide Part Number APROM RAM ISP Data Loader Flash ROM Connectivity I2S SC I/O Timer UART SPI I2C USB LIN CAN Co ISP PWM ADC RTC EBI Package mp. ICP NUC100LC1DN 32 KB 4 KB 4 KB 4 KB up to 4x3237 bit 2 1 2 - - - 1 3 1 6 8x12bit v - v LQFP48 NUC100LD1DN 64 KB 4 KB 4 KB 4 KB up to 4x3237 bit 2 1 2 - - - 1 3 1 6 8x12bit v - v LQFP48 NUC100LD2DN 64 KB 8 KB 4 KB 4 KB up to 4x3237 bit 2 1 2 - - - 1 3 1 6 8x12bit v - v LQFP48 NUC100LD3DN 64 KB 16 KB 4 KB 4 KB up to 4x3237 bit 2 1 2 - - - 1 3 1 6 8x12bit v - v LQFP48 Defin able 4 KB up to 4x3237 bit 2 1 2 - - - 1 3 1 6 8x12bit v - v LQFP48 NUC100LE3DN 128 KB 16 KB NUC100RC1DN 32 KB 4 KB 4 KB 4 KB up to 4x3251 bit 3 2 2 - - - 1 3 2 6 8x12bit v v v LQFP64 NUC100RD1DN 64 KB 4 KB 4 KB 4 KB up to 4x3251 bit 3 2 2 - - - 1 3 2 6 8x12bit v v v LQFP64 NUC100RD2DN 64 KB 8 KB 4 KB 4 KB up to 4x3251 bit 3 2 2 - - - 1 3 2 6 8x12bit v v v LQFP64 NUC100RD3DN 64 KB 16 KB 4 KB 4 KB up to 4x3251 bit 3 2 2 - - - 1 3 2 6 8x12bit v v v LQFP64 Defin able 4 KB up to 4x3251 bit 3 2 2 - - - 1 3 2 6 8x12bit v v v LQFP64 NUC100RE3DN 128 KB 16 KB 64 KB 8 KB 4 KB 4 KB up to 4x3284 bit 3 4 2 - - - 1 3 2 8 8x12bit v v v LQFP100 NUC100VD3DN 64 KB 16 KB 4 KB 4 KB up to 4x3284 bit 3 4 2 - - - 1 3 2 8 8x12bit v v v LQFP100 Defin able 4 KB up to 4x3284 bit 3 4 2 - - - 1 3 2 8 8x12bit v v v LQFP100 NUC100VE3DN 128 KB 16 KB 4.1.2 NuMicro® NUC120 USB Line Selection Guide Part Number APROM RAM ISP Data Loader Flash ROM Connectivity I2S SC I/O Timer 2 UART SPI I C USB LIN CAN Co ISP PWM ADC RTC EBI Package mp. ICP NUC120LC1DN 32 KB 4 KB 4 KB 4 KB up to 4x3233 bit 2 1 2 1 - - 1 3 1 4 8x12bit v - v LQFP48 NUC120LD1DN 64 KB 4 KB 4 KB 4 KB up to 4x3233 bit 2 1 2 1 - - 1 3 1 4 8x12bit v - v LQFP48 NUC120LD2DN 64 KB 8 KB 4 KB 4 KB up to 4x3233 bit 2 1 2 1 - - 1 3 1 4 8x12bit v - v LQFP48 NUC120LD3DN 64 KB 16 KB 4 KB 4 KB up to 4x3233 bit 2 1 2 1 - - 1 3 1 4 8x12bit v - v LQFP48 Defin able 4 KB up to 4x3233 bit 2 1 2 1 - - 1 3 1 4 8x12bit v - v LQFP48 NUC120LE3DN 128 KB 16 KB Aug 31, 2015 Page 19 of 107 Rev 1.01 NUC100/120XXXDN DATASHEET NUC100VD2DN NUC100/120xxxDN NUC120RC1DN 32 KB 4 KB 4 KB 4 KB up to 4x3247 bit 2 2 2 1 - - 1 3 2 6 8x12bit v v v LQFP64 NUC120RD1DN 64 KB 4 KB 4 KB 4 KB up to 4x3247 bit 2 2 2 1 - - 1 3 2 6 8x12bit v v v LQFP64 NUC120RD2DN 64 KB 8 KB 4 KB 4 KB up to 4x3247 bit 2 2 2 1 - - 1 3 2 6 8x12bit v v v LQFP64 NUC120RD3DN 64 KB 16 KB 4 KB 4 KB up to 4x3247 bit 2 2 2 1 - - 1 3 2 6 8x12bit v v v LQFP64 Defin able 4 KB up to 4x3247 bit 2 2 2 1 - - 1 3 2 6 8x12bit v v v LQFP64 NUC120RE3DN 128 KB 16 KB NUC120VD2DN 64 KB 8 KB 4 KB 4 KB up to 4x3280 bit 3 4 2 1 - - 1 3 2 8 8x12bit v v v LQFP100 NUC120VD3DN 64 KB 16 KB 4 KB 4 KB up to 4x3280 bit 3 4 2 1 - - 1 3 2 8 8x12bit v v v LQFP100 Defin able 4 KB up to 4x3280 bit 3 4 2 1 - - 1 3 2 8 8x12bit v v v LQFP100 NUC120VE3DN 128 KB 16 KB NUC 1 0 0 - X X X X X ARM-Based 32-bit Microcontroller Temperature CPU core N: -40℃ ~ +85℃ E: -40℃ ~ +105℃ C: -40℃ ~ +125℃ NUC100/120XXXDN DATASHEET 1/2: Cortex-M0 5/7: ARM7 9: ARM9 Reserve Function RAM Size 1: 4 KB 2: 8 KB 3: 16 KB 0: Advanced Line 2: USB Line 3: Automotive Line 4: Connectivity Line APROM Size A: 8 KB B: 16 KB C: 32 KB D: 64 KB E: 128 KB Package Type Y: QFN 36 L: LQFP 48 R: LQFP 64 V: LQFP 100 Figure 4-1 NuMicro® NUC100 Series Selection Code Aug 31, 2015 Page 20 of 107 Rev 1.01 NUC100/120xxxDN 4.2 Pin Configuration PA.4/ADC4/AD9/SC1PWR PA.3/ADC3/AD10/SC0DAT PA.2/ADC2/AD11/SC0CLK PA.1/ADC1/AD12/SC0RST PA.0/ADC0/SC0PWR AVSS VSS VDD ICE_CK ICE_DAT PA.12/PWM0/AD13/SC2DAT PA.13/PWM1/AD14/SC2CLK PA.14/PWM2/AD15/SC2RST PA.15/PWM3/I2SMCLK/SC2PWR PC.8/SPISS10/MCLK PC.9/SPICLK1 PC.10/MISO10 PC.11/MOSI10 PC.12/MISO11 PC.13/MOSI11 PE.0/PWM6 PE.1/PWM7 PE.2 PE.3 PE.4 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NuMicro® NUC100VxxDN LQFP 100 pin 74 4.2.1.1 NuMicro® NUC100 Pin Diagram 75 4.2.1 76 50 PB.9/TM0/SPISS11 SC1CLK/AD7/ADC6/PA.6 77 49 PB.10/TM1/SPISS01 SC1DAT/AD6/ADC7/SPISS21/PA.7 78 48 PB.11/TM2/PWM4 VREF 79 47 PE.5/T1EX/PWM5 AVDD 80 46 PE.6 SPISS20/PD.0 81 45 PC.0/SPISS00/I2SLRCLK SPICLK2/PD.1 82 44 PC.1/SPICLK0/I2SBCLK MISO20/PD.2 83 43 PC.2/MISO00/I2SDI MOSI20/PD.3 84 42 PC.3/MOSI00/I2SDO MISO21/PD.4 85 41 PC.4/MISO01 MOSI21/PD.5 86 40 PC.5/MOSI01 SC1CD/AD5/CPN0/PC.7 87 39 PD.15/TXD2 SC0CD/AD4/CPP0/PC.6 88 38 PD.14/RXD2 AD3/CPN1/PC.15 89 37 PD.7 AD2/CPP1/PC.14 90 36 PD.6 T0EX/INT1/PB.15 91 35 PB.3/CTS0/T3EX/nWRH/SC2CD XT1_OUT/PF.0 92 34 PB.2/RTS0/T2EX/nWRL XT1_IN/PF.1 93 33 PB.1/TXD0 /RESET 94 32 PB.0/RXD0 VSS 95 31 PE.7 VDD 96 30 PE.8 PS2DAT/PF.2 97 29 PE.9 PS2CLK/PF.3 98 28 PE.10 PVSS 99 27 PE.11 100 26 PE.12 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I2C0SCL/PA.9 I2C0SDA/PA.8 SPISS30/PD.8 SPICLK3/PD.9 MISO30/PD.10 MOSI30/PD.11 MISO31/PD.12 MOSI31/PD.13 RXD1/PB.4 TXD1/PB.5 ALE/RTS1/PB.6 nCS/CTS1/PB.7 LDO VDD VSS 7 X32O 10 6 AD0/CLKO/CPO0/PB.12 nWR/I2C1SDA/PA.10 5 AD1/CPO1/PB.13 9 4 SPISS31/INT0/PB.14 nRD/I2C1SCL/PA.11 3 PE.13 8 2 PE.14 X32I 1 PE.15 TM0/STADC/PB.8 NUC100VxxDN LQFP 100-pin NUC100/120XXXDN DATASHEET SC1RST/AD8/ADC5/PA.5 Figure 4-2 NuMicro® NUC100VxxDN LQFP 100-pin Diagram Aug 31, 2015 Page 21 of 107 Rev 1.01 NUC100/120xxxDN PA.4/ADC4/AD9/SC1PWR PA.3/ADC3/AD10/SC0DAT PA.2/ADC2/AD11/SC0CLK PA.1/ADC1/AD12/SC0RST PA.0/ADC0/SC0PWR AVSS ICE_CK ICE_DAT PA.12/PWM0/AD13/SC2DAT PA.13/PWM1/AD14/SC2CLK PA.14/PWM2/AD15/SC2RST PA.15/PWM3/I2SMCLK/SC2PWR PC.8/SPISS10/MCLK PC.9/SPICLK1 PC.10/MISO10 PC.11/MOSI10 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro® NUC100RxxDN LQFP 64 pin 48 4.2.1.2 SC1RST/AD8/ADC5/PA.5 49 32 PB.9/TM1 SC1CLK/AD7/ADC6/PA.6 50 31 PB.10/TM2 SC1DAT/AD6/ADC7/PA.7 51 30 PB.11/TM3/PWM4 AVDD 52 29 PE.5/T1EX/PWM5 SC1CD/AD5/CPN0/PC.7 53 28 PC.0/SPISS00/I2SLRCLK SC0CD/AD4/CPP0/PC.6 54 27 PC.1/SPICLK0/I2SBCLK AD3/CPN1/PC.15 55 26 PC.2/MISO00/I2SDI AD2/CPP1/PC.14 56 25 PC.3/MOSI00/I2SDO T0EX/INT1/PB.15 57 24 PD.15/TXD2 XT1_OUT/PF.0 58 23 PD.14/RXD2 XT1_IN/PF.1 59 22 PD.7 /RESET 60 21 PD.6 VSS 61 20 PB.3/CTS0/T3EX/nWRH/SC2CD VDD 62 19 PB.2/RTS0/T2EX/nWRL PVSS 63 18 PB.1/TXD0 TM0/STADC/PB.8 64 17 PB.0/RXD0 10 11 12 13 14 15 16 TXD1/PB.5 ALE/RTS1/PB.6 nCS/CTS1/PB.7 LDO VDD VSS 9 I2C0SDA/PA.8 RXD1/PB.4 8 I2C0SCL/PA.9 5 X32I 7 4 X32O nWR/I2C1SDA/PA.10 3 AD0/CLKO/CPO0/PB.12 6 2 nRD/I2C1SCL/PA.11 1 INT0/PB.14 NUC100/120XXXDN DATASHEET AD1/CPO1/PB.13 NUC100RxxDN LQFP 64-pin Figure 4-3 NuMicro® NUC100RxxDN LQFP 64-pin Diagram Aug 31, 2015 Page 22 of 107 Rev 1.01 NUC100/120xxxDN PA.4/ADC4/SC1PWR PA.3/ADC3/SC0DAT PA.2/ADC2/SC0CLK PA.1/ADC1/SC0RST PA.0/ADC0/SC0PWR AVSS ICE_CK ICE_DAT PA.12/PWM0/SC2DAT PA.13/PWM1/SC2CLK PA.14/PWM2/SC2RST PA.15/PWM3/I2SMCLK/SC2PWR 36 35 34 33 32 31 30 29 28 27 26 25 NuMicro® NUC100LxxDN LQFP 48 pin SC1RST/ADC5/PA.5 37 24 PB.9/TM1 SC1CLK/ADC6/PA.6 38 23 PB.10/TM2 SC1DAT/ADC7/PA.7 39 22 PB.11/TM3/PWM4 AVDD 40 21 PE.5/T1EX/PWM5 SC1CD/CPN0/PC.7 41 20 PC.0/SPISS00/I2SLRCLK SC0CD/CPP0/PC.6 42 19 PC.1/SPICLK0/I2SBCLK T0EX/INT1/PB.15 43 18 PC.2/MISO00/I2SDI XT1_OUT/PF.0 44 17 PC.3/MOSI00/I2SDO XT1_IN/PF.1 45 16 PB.3/CTS0/T3EX/SC2CD /RESET 46 15 PB.2/RTS0/T2EX PVSS 47 14 PB.1/TXD0 TM0/STADC/PB.8 48 13 PB.0/RXD0 8 9 RXD1/PB.4 TXD1/PB.5 12 7 I2C0SDA/PA.8 VSS 6 I2C0SCL/PA.9 11 5 I2C1SDA/PA.10 10 4 VDD 3 X32I I2C1SCL/PA.11 LDO 2 X32O NUC100/120XXXDN DATASHEET 1 NUC100LxxDN LQFP 48-pin CLKO/CPO0/PB.12 4.2.1.3 Figure 4-4 NuMicro® NUC100LxxDN LQFP 48-pin Diagram Aug 31, 2015 Page 23 of 107 Rev 1.01 NUC100/120xxxDN PA.4/ADC4/AD9/SC1PWR PA.3/ADC3/AD10/SC0DAT PA.2/ADC2/AD11/SC0CLK PA.1/ADC1/AD12/SC0RST PA.0/ADC0/SC0PWR AVSS VSS VDD ICE_CK ICE_DAT PA.12/PWM0/AD13/SC2DAT PA.13/PWM1/AD14/SC2CLK PA.14/PWM2/AD15/SC2RST PA.15/PWM3/I2SMCLK/SC2PWR PC.8/SPISS10/MCLK PC.9/SPICLK1 PC.10/MISO10 PC.11/MOSI10 PC.12/MISO11 PC.13/MOSI11 PE.0/PWM6 PE.1/PWM7 PE.2 PE.3 PE.4 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NuMicro® NUC120VxxDN LQFP 100 pin 74 4.2.2.1 NuMicro® NUC120 Pin Diagram 75 4.2.2 SC1RST/AD8/ADC5/PA.5 76 50 PB.9/TM1/SPISS11 SC1CLK/AD7/ADC6/PA.6 77 49 PB.10/TM2/SPISS01 SC1DAT/AD6/ADC7/SPISS21/PA.7 78 48 PB.11/TM3/PWM4 VREF 79 47 PE.5/T1EX/PWM5 AVDD 80 46 PE.6 SPISS20/PD.0 81 45 PC.0/SPISS00/I2SLRCLK SPICLK2/PD.1 82 44 PC.1/SPICLK0/I2SBCLK MISO20/PD.2 83 43 PC.2/MISO00/I2SDI MOSI20/PD.3 84 42 PC.3/MOSI00/I2SDO MISO21/PD.4 85 41 PC.4/MISO01 MOSI21/PD.5 86 40 PC.5/MOSI01 SC1CD/AD5/CPN0/PC.7 87 39 PD.15/TXD2 SC0CD/AD4/CPP0/PC.6 88 38 PD.14/RXD2 AD3/CPN1/PC.15 89 37 PD.7 AD2/CPP1/PC.14 90 36 PD.6 T0EX/INT1/PB.15 91 35 PB.3/CTS0/T3EX/nWRH/SC2CD XT1_OUT/PF.0 92 34 PB.2/RTS0/T2EX/nWRL XT1_IN/PF.1 93 33 PB.1/TXD0 /RESET 94 32 PB.0/RXD0 VSS 95 31 D+ VDD 96 30 D- PS2DAT/PF.2 97 29 VDD33 PS2CLK/PF.3 98 28 VBUS PVSS 99 27 PE.7 100 26 PE.8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I2C0SCL/PA.9 I2C0SDA/PA.8 SPISS30/PD.8 SPICLK3/PD.9 MISO30/PD.10 MOSI30/PD.11 MISO31/PD.12 MOSI31/PD.13 RXD1/PB.4 TXD1/PB.5 ALE/RTS1/PB.6 nCS/CTS1/PB.7 LDO VDD VSS 7 X32O 10 6 AD0/CLKO/CPO0/PB.12 nWR/I2C1SDA/PA.10 5 AD1/CPO1/PB.13 9 4 SPISS31/INT0/PB.14 nRD/I2C1SCL/PA.11 3 PE.13 8 2 X32I 1 PE.14 NUC100/120XXXDN DATASHEET PE.15 TM0/STADC/PB.8 NUC120VxxDN LQFP 100-pin Figure 4-5 NuMicro® NUC120VxxDN LQFP 100-pin Diagram Aug 31, 2015 Page 24 of 107 Rev 1.01 NUC100/120xxxDN PA.4/ADC4/AD9/SC1PWR PA.3/ADC3/AD10/SC0DAT PA.2/ADC2/AD11/SC0CLK PA.1/ADC1/AD12/SC0RST PA.0/ADC0/SC0PWR AVSS ICE_CK ICE_DAT PA.12/PWM0/AD13/SC2DAT PA.13/PWM1/AD14/SC2CLK PA.14/PWM2/AD15/SC2RST PA.15/PWM3/I2SMCLK/SC2PWR PC.8/SPISS10/MCLK PC.9/SPICLK1 PC.10/MISO10 PC.11/MOSI10 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro® NUC120RxxDN LQFP 64 pin 48 4.2.2.2 SC1RST/AD8/ADC5/PA.5 49 32 PB.9/TM1 SC1CLK/AD7/ADC6/PA.6 50 31 PB.10/TM2 SC1DAT/AD6/ADC7/PA.7 51 30 PB.11/TM3/PWM4 AVDD 52 29 PE.5/T1EX/PWM5 SC1CD/AD5/CPN0/PC.7 53 28 PC.0/SPISS00/I2SLRCLK SC0CD/AD4/CPP0/PC.6 54 27 PC.1/SPICLK0/I2SBCLK AD3/CPN1/PC.15 55 26 PC.2/MISO00/I2SDI AD2/CPP1/PC.14 56 25 PC.3/MOSI00/I2SDO T0EX/INT1/PB.15 57 24 PB.3/CTS0/T3EX/nWRH/SC2CD XT1_OUT/PF.0 58 23 PB.2/RTS0/T2EX/nWRL XT1_IN/PF.1 59 22 PB.1/TXD0 /RESET 60 21 PB.0/RXD0 VSS 61 20 D+ VDD 62 19 D- PVSS 63 18 VDD33 TM0/STADC/PB.8 64 17 VBUS 10 11 12 13 14 15 16 TXD1/PB.5 ALE/RTS1/PB.6 nCS/CTS1/PB.7 LDO VDD VSS 9 I2C0SDA/PA.8 RXD1/PB.4 8 I2C0SCL/PA.9 5 X32I 7 4 X32O nWR/I2C1SDA/PA.10 3 AD0/CLKO/CPO0/PB.12 6 2 nRD/I2C1SCL/PA.11 1 INT0/PB.14 NUC100/120XXXDN DATASHEET AD1/CPO1/PB.13 NUC120RxxDN LQFP 64-pin Figure 4-6 NuMicro® NUC120RxxDN LQFP 64-pin Diagram Aug 31, 2015 Page 25 of 107 Rev 1.01 NUC100/120xxxDN PA.4/ADC4/SC1PWR PA.3/ADC3/SC0DAT PA.2/ADC2/SC0CLK PA.1/ADC1/SC0RST PA.0/ADC0/SC0PWR AVSS ICE_CK ICE_DAT PA.12/PWM0/SC2DAT PA.13/PWM1/SC2CLK PA.14/PWM2/SC2RST PA.15/PWM3/I2SMCLK/SC2PWR 36 35 34 33 32 31 30 29 28 27 26 25 NuMicro® NUC120LxxDN LQFP 48 pin SC1RST/ADC5/PA.5 37 24 PC.0/SPISS00/I2SLRCLK SC1CLK/ADC6/PA.6 38 23 PC.1/SPICLK0/I2SBCLK SC1DAT/ADC7/PA.7 39 22 PC.2/MISO00/I2SDI AVDD 40 21 PC.3/MOSI00/I2SDO SC1CD/CPN0/PC.7 41 20 PB.3/CTS0/T3EX/SC2CD SC0CD/CPP0/PC.6 42 19 PB.2/RTS0/T2EX T0EX/INT1/PB.15 43 18 PB.1/TXD0 XT1_OUT/PF.0 44 17 PB.0/RXD0 XT1_IN/PF.1 45 16 D+ /RESET 46 15 D- PVSS 47 14 VDD33 TM0/STADC/PB.8 48 13 VBUS 8 9 RXD1/PB.4 TXD1/PB.5 12 7 I2C0SDA/PA.8 VSS 6 I2C0SCL/PA.9 11 5 I2C1SDA/PA.10 10 4 VDD 3 X32I I2C1SCL/PA.11 LDO 2 X32O NUC100/120XXXDN DATASHEET 1 NUC120LxxDN LQFP 48-pin CLKO/CPO0/PB.12 4.2.2.3 Figure 4-7 NuMicro® NUC120LxxDN LQFP 48-pin Diagram Aug 31, 2015 Page 26 of 107 Rev 1.01 NUC100/120xxxDN 4.3 Pin Description 4.3.1 NuMicro® NUC100 Pin Description Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description 1 PE.15 I/O General purpose digital I/O pin. 2 PE.14 I/O General purpose digital I/O pin. 3 PE.13 I/O General purpose digital I/O pin. PB.14 I/O General purpose digital I/O pin. /INT0 I 1 4 5 2 1 6 External interrupt0 input pin. nd SPISS31 I/O 2 SPI3 slave select pin. PB.13 I/O General purpose digital I/O pin. CPO1 O Comparator1 output pin. AD1 I/O EBI Address/Data bus bit1 PB.12 I/O General purpose digital I/O pin. CPO0 O Comparator0 output pin CLKO O Frequency Divider output pin AD0 I/O EBI Address/Data bus bit0 3 7 4 2 X32O O External 32.768 kHz low speed crystal output pin 8 5 3 X32I I External 32.768 kHz low speed crystal input pin I/O General purpose digital I/O pin. 9 6 I2C1SCL I/O I C1 clock pin. nRD O EBI read enable output pin PA.10 I/O General purpose digital I/O pin. I2C1SDA I/O I C1 data input/output pin. nWR O EBI write enable output pin PA.9 I/O General purpose digital I/O pin. I2C0SCL I/O I C0 clock pin. PA.8 I/O General purpose digital I/O pin. I2C0SDA I/O I C0 data input/output pin. PD.8 I/O General purpose digital I/O pin. SPISS30 I/O 1 SPI3 slave select pin. PD.9 I/O General purpose digital I/O pin. SPICLK3 I/O SPI3 serial clock pin. PD.10 I/O General purpose digital I/O pin. 5 10 11 12 7 8 9 6 7 13 NUC100/120XXXDN DATASHEET PA.11 4 2 2 2 2 st 14 15 Aug 31, 2015 Page 27 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description I/O 1 SPI3 MISO (Master In, Slave Out) pin. PD.11 I/O General purpose digital I/O pin. MOSI30 I/O 1 SPI3 MOSI (Master Out, Slave In) pin. PD.12 I/O General purpose digital I/O pin. MISO31 I/O 2 SPI3 MISO (Master In, Slave Out) pin. PD.13 I/O General purpose digital I/O pin. MOSI31 I/O 2 SPI3 MOSI (Master Out, Slave In) pin. PB.4 I/O General purpose digital I/O pin. RXD1 I PB.5 I/O General purpose digital I/O pin. TXD1 O Data transmitter output pin for UART1. PB.6 I/O General purpose digital I/O pin. RTS1 O Request to Send output pin for UART1. ALE O EBI address latch enable output pin PB.7 I/O General purpose digital I/O pin. CTS1 I Clear to Send input pin for UART1. nCS O EBI chip select enable output pin 16 17 18 19 20 21 22 10 11 st MISO30 st nd nd 8 Data receiver input pin for UART1. 9 12 13 NUC100/120XXXDN DATASHEET 23 14 10 LDO P LDO output pin 24 15 11 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. 25 16 12 VSS P Ground pin for digital circuit. 26 PE.12 I/O General purpose digital I/O pin. 27 PE.11 I/O General purpose digital I/O pin. 28 PE.10 I/O General purpose digital I/O pin. 29 PE.9 I/O General purpose digital I/O pin. 30 PE.8 I/O General purpose digital I/O pin. 31 PE.7 I/O General purpose digital I/O pin. PB.0 I/O General purpose digital I/O pin. RXD0 I PB.1 I/O General purpose digital I/O pin. TXD0 O Data transmitter output pin for UART0. PB.2 I/O General purpose digital I/O pin. RTS0 O Request to Send output pin for UART0. 32 33 34 17 18 19 Aug 31, 2015 13 Data receiver input pin for UART0. 14 15 Page 28 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description T2EX I Timer2 external capture input pin. nWRL O EBI low byte write enable output pin PB.3 I/O General purpose digital I/O pin. CTS0 I Clear to Send input pin for UART0. T3EX I Timer3 external capture input pin. SC2CD I SmartCard2 card detect pin. nWRH O EBI high byte write enable output pin 16 35 20 36 21 PD.6 I/O General purpose digital I/O pin. 37 22 PD.7 I/O General purpose digital I/O pin. PD.14 I/O General purpose digital I/O pin. 38 23 RXD2 I PD.15 I/O General purpose digital I/O pin. TXD2 O Data transmitter output pin for UART2. PC.5 I/O General purpose digital I/O pin. MOSI01 I/O 2 SPI0 MOSI (Master Out, Slave In) pin. PC.4 I/O General purpose digital I/O pin. MISO01 I/O 2 SPI0 MISO (Master In, Slave Out) pin. PC.3 I/O General purpose digital I/O pin. MOSI00 I/O 1 SPI0 MOSI (Master Out, Slave In) pin. I2SDO O I S data output. PC.2 I/O General purpose digital I/O pin. MISO00 I/O 1 SPI0 MISO (Master In, Slave Out) pin. 39 Data receiver input pin for UART2. 24 40 41 43 44 45 25 26 27 28 17 18 19 20 46 47 29 Aug 31, 2015 nd NUC100/120XXXDN DATASHEET 42 nd st 2 st 2 I2SDI I I S data input. PC.1 I/O General purpose digital I/O pin. SPICLK0 I/O SPI0 serial clock pin. I2SBCLK I/O I S bit clock pin. PC.0 I/O General purpose digital I/O pin. SPISS00 I/O 1 SPI0 slave select pin. I2SLRCLK I/O I S left right channel clock. PE.6 I/O General purpose digital I/O pin. PE.5 I/O General purpose digital I/O pin. PWM5 I/O PWM5 output/Capture input. 2 st 2 21 Page 29 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description T1EX I PB.11 I/O General purpose digital I/O pin. TM3 I/O Timer3 event counter input / toggle output. PWM4 I/O PWM4 output/Capture input. PB.10 I/O General purpose digital I/O pin. TM2 I/O Timer2 event counter input / toggle output. SPISS01 I/O 2 SPI0 slave select pin. PB.9 I/O General purpose digital I/O pin. TM1 I/O Timer1 event counter input / toggle output. SPISS11 I/O 2 SPI1 slave select pin. 51 PE.4 I/O General purpose digital I/O pin. 52 PE.3 I/O General purpose digital I/O pin. 53 PE.2 I/O General purpose digital I/O pin. PE.1 I/O General purpose digital I/O pin. PWM7 I/O PWM7 output/Capture input. PE.0 I/O General purpose digital I/O pin. PWM6 I/O PWM6 output/Capture input. PC.13 I/O General purpose digital I/O pin. MOSI11 I/O 2 SPI1 MOSI (Master Out, Slave In) pin. PC.12 I/O General purpose digital I/O pin. MISO11 I/O 2 SPI1 MISO (Master In, Slave Out) pin. PC.11 I/O General purpose digital I/O pin. MOSI10 I/O 1 SPI1 MOSI (Master Out, Slave In) pin. PC.10 I/O General purpose digital I/O pin. MISO10 I/O 1 SPI1 MISO (Master In, Slave Out) pin. PC.9 I/O General purpose digital I/O pin. SPICLK1 I/O SPI1 serial clock pin. PC.8 I/O General purpose digital I/O pin. SPISS10 I/O 1 SPI1 slave select pin. MCLK O EBI external clock output pin PA.15 I/O General purpose digital I/O pin. PWM3 I/O PWM output/Capture input. 48 30 31 22 23 49 32 Timer1 external capture input pin. nd 24 50 nd 54 55 NUC100/120XXXDN DATASHEET 56 57 58 59 60 61 62 33 34 nd nd st st 35 36 37 Aug 31, 2015 st 25 Page 30 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin 26 63 2 I2SMCLK O I S master clock output pin. SC2PWR O SmartCard2 power pin. PA.14 I/O General purpose digital I/O pin. PWM2 I/O PWM2 output/Capture input. SC2RST O SmartCard2 reset pin. AD15 I/O EBI Address/Data bus bit15 PA.13 I/O General purpose digital I/O pin. PWM1 I/O PWM1 output/Capture input. SC2CLK O SmartCard2 clock pin. AD14 I/O EBI Address/Data bus bit14 PA.12 I/O General purpose digital I/O pin. PWM0 I/O PWM0 output/Capture input. SC2DAT O SmartCard2 data pin. AD13 I/O EBI Address/Data bus bit13 39 28 65 Pin Type Description 38 27 64 Pin Name 40 41 29 ICE_DAT I/O Serial Wire Debugger Data pin 67 42 30 ICE_CLK I Serial Wire Debugger Clock pin 68 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. 69 VSS P Ground pin for digital circuit. AVSS AP Ground pin for analog circuit. PA.0 I/O General purpose digital I/O pin. ADC0 AI ADC0 analog input. SC0PWR O SmartCard0 power pin. PA.1 I/O General purpose digital I/O pin. ADC1 AI ADC1 analog input. SC0RST O SmartCard0 reset pin. AD12 I/O EBI Address/Data bus bit12 PA.2 I/O General purpose digital I/O pin. ADC2 AI ADC2 analog input. SC0CLK O SmartCard0 clock pin. AD11 I/O EBI Address/Data bus bit11 PA.3 I/O General purpose digital I/O pin. ADC3 AI ADC3 analog input. 70 71 43 44 31 32 33 72 45 34 73 74 NUC100/120XXXDN DATASHEET 66 46 47 Aug 31, 2015 35 Page 31 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin 36 75 SC0DAT O SmartCard0 data pin. AD10 I/O EBI Address/Data bus bit10 PA.4 I/O General purpose digital I/O pin. ADC4 AI ADC4 analog input. SC1PWR O SmartCard1 power pin. AD9 I/O EBI Address/Data bus bit9 PA.5 I/O General purpose digital I/O pin. ADC5 AI ADC5 analog input. SC1RST O SmartCard1 reset pin. AD8 I/O EBI Address/Data bus bit8 PA.6 I/O General purpose digital I/O pin. ADC6 AI ADC6 analog input. SC1CLK I/O SmartCard1 clock pin. AD7 I/O EBI Address/Data bus bit7 PA.7 I/O General purpose digital I/O pin. ADC7 AI ADC7 analog input. SC1DAT O SmartCard1 data pin. SPISS21 I/O 2 SPI2 slave select pin. AD6 I/O EBI Address/Data bus bit6 VREF AP Voltage reference input for ADC. AVDD AP Power supply for internal analog circuit. PD.0 I/O General purpose digital I/O pin. SPISS20 I/O 1 SPI2 slave select pin. PD.1 I/O General purpose digital I/O pin. SPICLK2 I/O SPI2 serial clock pin. PD.2 I/O General purpose digital I/O pin. MISO20 I/O 1 SPI2 MISO (Master In, Slave Out) pin. PD.3 I/O General purpose digital I/O pin. MOSI20 I/O 1 SPI2 MOSI (Master Out, Slave In) pin. PD.4 I/O General purpose digital I/O pin. MISO21 I/O 2 SPI2 MISO (Master In, Slave Out) pin. PD.5 I/O General purpose digital I/O pin. MOSI21 I/O 2 SPI2 MOSI (Master Out, Slave In) pin. 49 38 77 Pin Type Description 48 37 76 Pin Name 50 39 78 51 NUC100/120XXXDN DATASHEET 79 80 52 40 81 nd st 82 83 84 85 86 Aug 31, 2015 st st nd nd Page 32 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin 41 87 Pin Name PC.7 I/O General purpose digital I/O pin. CPN0 AI Comparator0 negative input pin. 53 SC1CD 42 88 90 91 93 SmartCard1 card detect pin. I/O EBI Address/Data bus bit5 PC.6 I/O General purpose digital I/O pin. CPP0 AI Comparator0 positive input pin. 54 55 56 57 58 59 43 I SmartCard0 card detect pin. AD4 I/O EBI Address/Data bus bit4 PC.15 I/O General purpose digital I/O pin. CPN1 AI Comparator1 negative input pin. AD3 I/O EBI Address/Data bus bit3 PC.14 I/O General purpose digital I/O pin. CPP1 AI Comparator1 positive input pin. AD2 I/O EBI Address/Data bus bit2 PB.15 I/O General purpose digital I/O pin. /INT1 I External interrupt1 input pin. T0EX I Timer0 external capture input pin. PF.0 I/O General purpose digital I/O pin. XT1_OUT O External 4~24 MHz (high speed) crystal output pin. PF.1 I/O General purpose digital I/O pin. 44 45 46 XT1_IN I External 4~24 MHz (high speed) crystal input pin. /RESET I External reset input: active LOW, with an internal pull-up. Set this pin low reset chip to initial state. Ground pin for digital circuit. 94 60 95 61 VSS P 96 62 VDD P PF.2 I/O Power supply for I/O ports and LDO source for internal PLL and digital circuit. General purpose digital I/O pin. PS2DAT I/O PS/2 data pin. PF.3 I/O General purpose digital I/O pin. PS2CLK I/O PS/2 clock pin. 97 98 99 100 63 64 47 48 PVSS P PB.8 I/O STADC TM0 PLL ground. I General purpose digital I/O pin. ADC external trigger input. I/O Timer0 event counter input / toggle output. Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power Aug 31, 2015 Page 33 of 107 Rev 1.01 NUC100/120XXXDN DATASHEET 92 I AD5 SC0CD 89 Pin Type Description NUC100/120xxxDN 4.3.2 NuMicro® NUC120 Pin Description Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description 1 PE.15 I/O General purpose digital I/O pin. 2 PE.14 I/O General purpose digital I/O pin. 3 PE.13 I/O General purpose digital I/O pin. PB.14 I/O General purpose digital I/O pin. /INT0 I 1 4 5 2 1 6 External interrupt0 input pin. nd SPISS31 I/O 2 SPI3 slave select pin. PB.13 I/O General purpose digital I/O pin. CPO1 O Comparator1 output pin. AD1 I/O EBI Address/Data bus bit1 PB.12 I/O General purpose digital I/O pin. CPO0 O Comparator0 output pin CLKO O Frequency Divider output pin AD0 I/O EBI Address/Data bus bit0 3 7 4 2 X32O O External 32.768 kHz low speed crystal output pin 8 5 3 X32I I External 32.768 kHz low speed crystal input pin PA.11 I/O General purpose digital I/O pin. I2C1SCL I/O I C1 clock pin. nRD O EBI read enable output pin PA.10 I/O General purpose digital I/O pin. I2C1SDA I/O I C1 data input/output pin. nWR O EBI write enable output pin PA.9 I/O General purpose digital I/O pin. I2C0SCL I/O I C0 clock pin. PA.8 I/O General purpose digital I/O pin. I2C0SDA I/O I C0 data input/output pin. PD.8 I/O General purpose digital I/O pin. SPISS30 I/O 1 SPI3 slave select pin. PD.9 I/O General purpose digital I/O pin. SPICLK3 I/O SPI3 serial clock pin. PD.10 I/O General purpose digital I/O pin. MISO30 I/O 1 SPI3 MISO (Master In, Slave Out) pin. PD.11 I/O General purpose digital I/O pin. 4 NUC100/120XXXDN DATASHEET 9 6 5 10 11 12 7 8 9 6 7 13 2 2 2 2 st 14 15 16 Aug 31, 2015 st Page 34 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description I/O 1 SPI3 MOSI (Master Out, Slave In) pin. PD.12 I/O General purpose digital I/O pin. MISO31 I/O 2 SPI3 MISO (Master In, Slave Out) pin. PD.13 I/O General purpose digital I/O pin. MOSI31 I/O 2 SPI3 MOSI (Master Out, Slave In) pin. PB.4 I/O General purpose digital I/O pin. RXD1 I PB.5 I/O General purpose digital I/O pin. TXD1 O Data transmitter output pin for UART1. PB.6 I/O General purpose digital I/O pin. RTS1 O Request to Send output pin for UART1. ALE O EBI address latch enable output pin PB.7 I/O General purpose digital I/O pin. CTS1 I Clear to Send input pin for UART1. nCS O EBI chip select enable output pin 17 18 19 20 21 22 10 11 st MOSI30 nd nd 8 Data receiver input pin for UART1. 9 12 13 14 10 LDO P LDO output pin 24 15 11 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. 25 16 12 VSS P Ground pin for digital circuit. 26 PE.8 I/O General purpose digital I/O pin. 27 PE.7 I/O General purpose digital I/O pin. 28 17 13 VBUS USB Power supply from USB host or HUB. 29 18 14 VDD33 USB Internal power regulator output 3.3V decoupling pin. 30 19 15 D- USB USB differential signal D-. 31 20 16 D+ USB USB differential signal D+. 32 21 17 33 22 I/O General purpose digital I/O pin. RXD0 I PB.1 I/O General purpose digital I/O pin. TXD0 O Data transmitter output pin for UART0. PB.2 I/O General purpose digital I/O pin. RTS0 O Request to Send output pin for UART0. T2EX I Timer2 external capture input pin. nWRL O EBI low byte write enable output pin Data receiver input pin for UART0. 18 29 34 PB.0 NUC100/120XXXDN DATASHEET 23 23 Aug 31, 2015 Page 35 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description PB.3 I/O General purpose digital I/O pin. CTS0 I Clear to Send input pin for UART0. T3EX I Timer3 external capture input pin. SC2CD I SmartCard2 card detect pin. nWRH O EBI high byte write enable output pin 36 PD.6 I/O General purpose digital I/O pin. 37 PD.7 I/O General purpose digital I/O pin. PD.14 I/O General purpose digital I/O pin. RXD2 I PD.15 I/O General purpose digital I/O pin. TXD2 O Data transmitter output pin for UART2. PC.5 I/O General purpose digital I/O pin. MOSI01 I/O 2 SPI0 MOSI (Master Out, Slave In) pin. PC.4 I/O General purpose digital I/O pin. MISO01 I/O 2 SPI0 MISO (Master In, Slave Out) pin. PC.3 I/O General purpose digital I/O pin. MOSI00 I/O 1 SPI0 MOSI (Master Out, Slave In) pin. I2SDO O I S data output. PC.2 I/O General purpose digital I/O pin. MISO00 I/O 1 SPI0 MISO (Master In, Slave Out) pin. 20 35 24 38 Data receiver input pin for UART2. 39 40 41 NUC100/120XXXDN DATASHEET 42 43 44 45 25 26 27 28 46 47 48 29 30 Aug 31, 2015 21 22 23 24 nd nd st 2 st 2 I2SDI I I S data input. PC.1 I/O General purpose digital I/O pin. SPICLK0 I/O SPI0 serial clock pin. I2SBCLK I/O I S bit clock pin. PC.0 I/O General purpose digital I/O pin. SPISS00 I/O 1 SPI0 slave select pin. I2SLRCLK I/O I S left right channel clock. PE.6 I/O General purpose digital I/O pin. PE.5 I/O General purpose digital I/O pin. PWM5 I/O PWM5 output/Capture input. T1EX I PB.11 I/O 2 st 2 Timer1 external capture input pin. General purpose digital I/O pin. Page 36 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Type Description TM3 I/O Timer3 event counter input / toggle output. PWM4 I/O PWM4 output/Capture input. PB.10 I/O General purpose digital I/O pin. TM2 I/O Timer2 event counter input / toggle output. SPISS01 I/O 2 SPI0 slave select pin. PB.9 I/O General purpose digital I/O pin. TM1 I/O Timer1 event counter input / toggle output. SPISS11 I/O 2 SPI1 slave select pin. 51 PE.4 I/O General purpose digital I/O pin. 52 PE.3 I/O General purpose digital I/O pin. 53 PE.2 I/O General purpose digital I/O pin. PE.1 I/O General purpose digital I/O pin. PWM7 I/O PWM7 output/Capture input. PE.0 I/O General purpose digital I/O pin. PWM6 I/O PWM6 output/Capture input. PC.13 I/O General purpose digital I/O pin. MOSI11 I/O 2 SPI1 MOSI (Master Out, Slave In) pin. PC.12 I/O General purpose digital I/O pin. MISO11 I/O 2 SPI1 MISO (Master In, Slave Out) pin. PC.11 I/O General purpose digital I/O pin. MOSI10 I/O 1 SPI1 MOSI (Master Out, Slave In) pin. PC.10 I/O General purpose digital I/O pin. MISO10 I/O 1 SPI1 MISO (Master In, Slave Out) pin. PC.9 I/O General purpose digital I/O pin. SPICLK1 I/O SPI1 serial clock pin. PC.8 I/O General purpose digital I/O pin. SPISS10 I/O 1 SPI1 slave select pin. MCLK O EBI external clock output pin PA.15 I/O General purpose digital I/O pin. PWM3 I/O PWM output/Capture input. I2SMCLK O I S master clock output pin. SC2PWR O SmartCard2 power pin. 31 49 nd 32 50 nd 54 55 56 58 59 60 61 62 33 34 NUC100/120XXXDN DATASHEET 57 nd nd st st 35 36 37 Aug 31, 2015 25 st 2 Page 37 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin 26 63 PA.14 I/O General purpose digital I/O pin. PWM2 I/O PWM2 output/Capture input. SC2RST O SmartCard2 reset pin. AD15 I/O EBI Address/Data bus bit15 PA.13 I/O General purpose digital I/O pin. PWM1 I/O PWM1 output/Capture input. SC2CLK O SmartCard2 clock pin. AD14 I/O EBI Address/Data bus bit14 PA.12 I/O General purpose digital I/O pin. PWM0 I/O PWM0 output/Capture input. SC2DAT O SmartCard2 data pin. AD13 I/O EBI Address/Data bus bit13 39 28 65 Pin Type Description 38 27 64 Pin Name 40 66 41 29 ICE_DAT I/O Serial Wire Debugger Data pin 67 42 30 ICE_CLK I Serial Wire Debugger Clock pin 68 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. 69 VSS P Ground pin for digital circuit. AVSS AP Ground pin for analog circuit. PA.0 I/O General purpose digital I/O pin. ADC0 AI ADC0 analog input. SC0PWR O SmartCard0 power pin. PA.1 I/O General purpose digital I/O pin. ADC1 AI ADC1 analog input. SC0RST O SmartCard0 reset pin. AD12 I/O EBI Address/Data bus bit12 PA.2 I/O General purpose digital I/O pin. ADC2 AI ADC2 analog input. SC0CLK O SmartCard0 clock pin. AD11 I/O EBI Address/Data bus bit11 PA.3 I/O General purpose digital I/O pin. ADC3 AI ADC3 analog input. SC0DAT O SmartCard0 data pin. AD10 I/O EBI Address/Data bus bit10 70 NUC100/120XXXDN DATASHEET 71 43 44 31 32 33 72 45 34 73 46 35 74 47 Aug 31, 2015 Page 38 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin 36 75 PA.4 I/O General purpose digital I/O pin. ADC4 AI ADC4 analog input. SC1PWR O SmartCard1 power pin. AD9 I/O EBI Address/Data bus bit9 PA.5 I/O General purpose digital I/O pin. ADC5 AI ADC5 analog input. SC1RST O SmartCard1 reset pin. AD8 I/O EBI Address/Data bus bit8 PA.6 I/O General purpose digital I/O pin. ADC6 AI ADC6 analog input. SC1CLK I/O SmartCard1 clock pin. AD7 I/O EBI Address/Data bus bit7 PA.7 I/O General purpose digital I/O pin. ADC7 AI ADC7 analog input. SC1DAT O SmartCard1 data pin. SPISS21 I/O 2 SPI2 slave select pin. AD6 I/O EBI Address/Data bus bit6 VREF AP Voltage reference input for ADC. AVDD AP Power supply for internal analog circuit. PD.0 I/O General purpose digital I/O pin. SPISS20 I/O 1 SPI2 slave select pin. PD.1 I/O General purpose digital I/O pin. SPICLK2 I/O SPI2 serial clock pin. PD.2 I/O General purpose digital I/O pin. MISO20 I/O 1 SPI2 MISO (Master In, Slave Out) pin. PD.3 I/O General purpose digital I/O pin. MOSI20 I/O 1 SPI2 MOSI (Master Out, Slave In) pin. PD.4 I/O General purpose digital I/O pin. MISO21 I/O 2 SPI2 MISO (Master In, Slave Out) pin. PD.5 I/O General purpose digital I/O pin. MOSI21 I/O 2 SPI2 MOSI (Master Out, Slave In) pin. PC.7 I/O General purpose digital I/O pin. CPN0 AI Comparator0 negative input pin. 49 38 77 Pin Type Description 48 37 76 Pin Name 50 39 78 51 80 52 40 81 NUC100/120XXXDN DATASHEET 79 nd st 82 83 84 85 86 87 53 Aug 31, 2015 st st nd nd 41 Page 39 of 107 Rev 1.01 NUC100/120xxxDN Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name SC1CD 42 88 90 91 92 NUC100/120XXXDN DATASHEET 93 I SmartCard1 card detect pin. AD5 I/O EBI Address/Data bus bit5 PC.6 I/O General purpose digital I/O pin. CPP0 AI Comparator0 positive input pin. 54 SC0CD 89 Pin Type Description 55 56 57 58 59 43 I SmartCard0 card detect pin. AD4 I/O EBI Address/Data bus bit4 PC.15 I/O General purpose digital I/O pin. CPN1 AI Comparator1 negative input pin. AD3 I/O EBI Address/Data bus bit3 PC.14 I/O General purpose digital I/O pin. CPP1 AI Comparator1 positive input pin. AD2 I/O EBI Address/Data bus bit2 PB.15 I/O General purpose digital I/O pin. /INT1 I External interrupt1 input pin. T0EX I Timer0 external capture input pin. PF.0 I/O General purpose digital I/O pin. XT1_OUT O External 4~24 MHz (high speed) crystal output pin. PF.1 I/O General purpose digital I/O pin. 44 45 46 XT1_IN I External 4~24 MHz (high speed) crystal input pin. /RESET I External reset input: active LOW, with an internal pull-up. Set this pin low reset chip to initial state. 94 60 95 61 VSS P Ground pin for digital circuit. 96 62 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. PF.2 I/O General purpose digital I/O pin. PS2DAT I/O PS/2 data pin. PF.3 I/O General purpose digital I/O pin. PS2CLK I/O PS/2 clock pin. 97 98 99 100 63 64 47 48 PVSS P PB.8 I/O STADC TM0 PLL ground. I General purpose digital I/O pin. ADC external trigger input. I/O Timer0 event counter input / toggle output. Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power Aug 31, 2015 Page 40 of 107 Rev 1.01 NUC100/120xxxDN 5 BLOCK DIAGRAM 5.1 NuMicro® NUC100 Block Diagram Memory Timer/PWM Analog Interface 32-bit Timer x 4 APROM 128/64/32 KB ARM LDROM 4 KB PDM A Cortex-M0 50MHz DataFlash 4 KB 12-bit ADC x 8 RTC EBI Watchdog Timer SRAM 16/8/4 KB Analog Comparator x2 PWM/Capture Timer x 8 Bridge AHB Bus Power Control Clock Control LDO PLL APB Bus Connectivity I/O Ports UART x 3 General Purpose I/O SPI x 4 Power On Reset LVR Brownout Detection High Speed Oscillator 22.1184 MHz Low Speed Oscillator 10 kHz High Speed Crystal Osc. 4 ~ 24 MHz Low Speed Crystal Osc. 32.768 KHz I2C x 2 External Interrupt I2S Reset Pin PS/2 SC x3 NUC100/120XXXDN DATASHEET Figure 5-1 NuMicro® NUC100 Block Diagram Aug 31, 2015 Page 41 of 107 Rev 1.01 NUC100/120xxxDN 5.2 NuMicro® NUC120 Block Diagram Memory ARM APROM 128/64/32 KB LDROM 4 KB DataFlash 4 KB SRAM 16/8/4 KB PDM A Cortex-M0 50MHz Timer/PWM Analog Interface 32-bit Timer x 4 12-bit ADC x 8 RTC EBI USB PHY Watchdog Timer PWM/Capture Timer x 8 Bridge AHB Bus Power Control Clock Control LDO PLL APB Bus Connectivity I/O Ports UART x 3 General Purpose I/O SPI x 4 I2 C x 2 Power On Reset LVR Brownout Detection High Speed Oscillator 22.1184 MHz High Speed Crystal Osc. 4 ~ 24 MHz Low Speed Crystal Osc. 32.768 KHz External Interrupt I2S PS/2 Low Speed Oscillator 10 kHz Analog Comparator x2 Reset Pin SC x3 USB NUC100/120XXXDN DATASHEET Figure 5-2 NuMicro® NUC120 Block Diagram Aug 31, 2015 Page 42 of 107 Rev 1.01 NUC100/120xxxDN 6 FUNCTIONAL DESCRIPTION 6.1 ARM® Cortex® -M0 Core The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex® -M profile processor. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. Figure 6-1 shows the functional controller of processor. ® Cortex -M0 Components ® Cortex -M0 processor Nested ® Vectored Cortex -M0 Interrupt Processor Controller Core (NVIC) Interrupts Wakeup Interrupt Controller (WIC) Bus Matrix Debug Breakpoint and Watchpoint Unit Debugger Interface AHB-Lite Interface Debug Access Port (DAP) Serial Wire or JTAG Debug Port Figure 6-1 Functional Controller Diagram NUC100/120XXXDN DATASHEET The implemented device provides the following components and features:   Aug 31, 2015 A low gate count processor: – ARMv6-M Thumb® instruction set – Thumb-2 technology – ARMv6-M compliant 24-bit SysTick timer – A 32-bit hardware multiplier – System interface supported with little-endian data accesses – Ability to have deterministic, fixed-latency, interrupt handling – Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling – C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers – Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature NVIC: Page 43 of 107 Rev 1.01 NUC100/120xxxDN   – 32 external interrupt inputs, each with four levels of priority – Dedicated Non-maskable Interrupt (NMI) input – Supports for both level-sensitive and pulse-sensitive interrupt lines – Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep mode Debug support – Four hardware breakpoints – Two watchpoints – Program Counter Sampling Register (PCSR) for non-intrusive code profiling – Single step and vector catch capabilities Bus interfaces: – Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory – Single 32-bit slave port that supports the DAP (Debug Access Port) NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 44 of 107 Rev 1.01 NUC100/120xxxDN 6.2 System Manager 6.2.1 Overview The system manager provides the functions of system control, power modes, wake-up sources, reset sources, system memory map, product ID and multi-function pin control. The following sections describe the functions for 6.2.2  System Reset  System Power Architecture  System Memory Map  System management registers for Part Number ID, chip reset and on-chip controllers reset, and multi-functional pin control  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System Control registers System Reset The system reset can be issued by one of the events listed below. These reset event flags can be read from RSTSRC register to determine the reset source. Hardware reset can reset chip through peripheral reset signals. Software reset can trigger reset through control registers.  – Power-on Reset (POR) – Low level on the nRESET pin – Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset) – Low Voltage Reset (LVR) – Brown-out Detector Reset (BOD Reset) Software Reset Sources – CHIP Reset will reset whole chip by writing 1 to CHIP_RST (IPRSTC1[0]) – MCU Reset to reboot but keeping the booting setting from APROM or LDROM by writing 1 to SYSRESETREQ (AIRCR[2]) – CPU Reset for Cortex® -M0 core Only by writing 1 to CPU_RST (IPRSTC1[1]) Power-on Reset or CHIP_RST (IPRSTC1[0]) reset the whole chip including all peripherals, external crystal circuit and BS (ISPCON[1]) bit. SYSRESETREQ (AIRCR[2]) reset the whole chip including all peripherals, but does not reset external crystal circuit and BS (ISPCON[1]) bit. Aug 31, 2015 Page 45 of 107 Rev 1.01 NUC100/120XXXDN DATASHEET  Hardware Reset Sources NUC100/120xxxDN Glitch Filter 36 us nRESET ~50k ohm @5v POR_DIS_CODE(PORCR[15:0]) Power-on Reset VDD LVR_EN(BODCR[7]) AVDD Reset Pulse Width 3.2ms Low Voltage Reset BOD_RSTEN(BODCR[3]) Brown-out Reset WDT/WWDT Reset System Reset Reset Pulse Width 64 WDT clocks CHIP Reset CHIP_RST(IPRSTC1[0]) MCU Reset SYSRESETREQ(AIRCR[2]) Software Reset Reset Pulse Width 2 system clocks CPU Reset CPU_RST(IPRSTC1[1]) Figure 6-2 System Reset Resources There are a total of 8 reset sources in the NuMicro® family. In general, CPU reset is used to reset Cortex® -M0 only; the other reset sources will reset Cortex® -M0 and all peripherals. However, there are small differences between each reset source and they are listed in Table 6-1. NUC100/120XXXDN DATASHEET Reset Sources POR nRESET WDT LVR BOD CHIP MCU CPU Register RSTSRC Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 0 = 1 Bit 5 = 1 Bit 7 = 1 CHIP_RST 0x0 - - - - - - - Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - Reload from CONFIG0 Reload from CONFIG0 - Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - (PWRCON[0]) Reload from CONFIG0 WDT_EN 0x1 - 0x1 - - 0x1 - - Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - (CLKSEL0[2:0]) Reload from CONFIG0 WDT_S 0x3 0x3 - - - - - - (IPRSTC1[0]) BOD_EN (BODCR[0]) BOD_VL (BODCR[2:1]) BOD_RSTEN (BODCR[3]) XTL12M_EN (APBCLK[0]) HCLK_S Aug 31, 2015 Page 46 of 107 Rev 1.01 NUC100/120xxxDN (CLKSEL1[1:0]) XTL12M_STB 0x0 - - - - - - - 0x0 - - - - - - - 0x0 - - - - - - - 0x0 - - - - - - - 0x0 - - - - - - - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - - (WTCR[7]) WTCR 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 - - WTCRALT 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTRLD 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTCR 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 - - WWDTSR 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTCVR 0x3F 0x3F 0x3F 0x3F 0x3F 0x3F - - BS Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - - DFBADR Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 - - CBS (ISPSTA[2:1)) Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - - VECMAP (ISPSTA[20:9]) Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 - - Other Peripheral Registers Reset Value FMC Registers Reset Value (CLKSTATUS[0]) XTL32K_STB (CLKSTATUS[1]) PLL_STB (CLKSTATUS[2]) OSC10K_STB (CLKSTATUS[3]) OSC22M_STB (CLKSTATUS[4]) CLK_SW_FAIL (CLKSTATUS[7]) WTE (ISPCON[1]) Note: ‘-‘ means that the value of register keeps original setting. Table 6-1 Reset Value of Registers Aug 31, 2015 Page 47 of 107 Rev 1.01 NUC100/120XXXDN DATASHEET - NUC100/120xxxDN 6.2.2.1 nRESET Reset The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage is lower than 0.2 VDD and the state keeps longer than 36 us (glitch filter), chip will be reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the state keeps longer than 36 us (glitch filter). The RSTS_RESET (RSTSRC[1]) will be set to 1 if the previous reset source is nRESET reset. Figure 6-3 shows the nRESET reset waveform. nRESET 0.7 VDD 36 us 0.2 VDD SS 36 us nRESET Reset SS Figure 6-3 nRESET Reset Waveform 6.2.2.2 Power-On Reset (POR) NUC100/120XXXDN DATASHEET The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the POR module will detect the rising voltage and generate reset signal to system until the voltage is ready for MCU operation. At POR reset, the RSTS_POR (RSTSRC[0]) will be set to 1 to indicate there is a POR reset event. The RSTS_POR (RSTSRC[0]) bit can be cleared by writing 1 to it. Figure 6-4 shows the waveform of Power-On reset. VPOR 0.1V VDD Power On Reset Figure 6-4 Power-on Reset (POR) Waveform 6.2.2.3 Low Voltage Reset (LVR) If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVR_EN (BODCR[7]) to 1, after 100us delay, LVR detection circuit will be stable and the LVR function will be active. Then LVR function will detect AVDD during system operation. When the Aug 31, 2015 Page 48 of 107 Rev 1.01 NUC100/120xxxDN AVDD voltage is lower than VLVR and the state keeps longer than De-glitch time (16*HCLK cycles), chip will be reset. The LVR reset will control the chip in reset state until the AVDD voltage rises above VLVR and the state keeps longer than De-glitch time. The RSTS_RESET (RSTSRC[1]) will be set to 1 if the previous reset source is nRESET reset. Figure 6-5 shows the Low Voltage Reset waveform. AVDD VLVR T1 (= 8 2 1 1 Don’t care A UART_CLK / (A+2), A must >=3 Table 6-6 UART Baud Rate Equation System Clock = Internal 22.1184 MHz High Speed Oscillator Mode 0 Mode 1 Mode 2 Baud Rate 921600 Aug 31, 2015 Parameter Register Parameter Register Parameter Register x x A=0,B=11 0x2B00_0000 A=22 0x3000_0016 Page 76 of 107 Rev 1.01 NUC100/120xxxDN 0x2F00_0001 460800 A=1 0x0000_0001 A=1,B=15 A=2,B=11 230400 A=4 0x0000_0004 A=4,B=15 A=6,B=11 0x2B00_0006 115200 A=10 0x0000_000A A=10,B=15 A=14,B=11 0x2B00_000E 57600 A=22 0x0000_0016 A=22,B=15 A=30,B=11 38400 A=34 0x0000_0022 19200 A=70 9600 A=142 4800 A=286 A=46 0x3000_002E A=94 0x3000_005E A=190 0x3000_00BE 0x2F00_0016 0x2B00_001E A=382 0x3000_017E A=62,B=8 A=46,B=11 A=34,B=15 0x2800_003E 0x2B00_002E 0x2F00_0022 A=574 0x3000_023E 0x0000_0046 A=126,B=8 A=94,B=11 A=70,B=15 0x2800_007E 0x2B00_005E 0x2F00_0046 A=1150 0x3000_047E 0x0000_008E A=254,B=8 A=190,B=11 A=142,B=15 0x2B00_00BE A=2302 0x3000_08FE A=4606 0x3000_11FE 0x0000_011E A=510,B=8 A=382,B=11 A=286,B=15 0x2B00_0002 0x2F00_0004 0x2F00_000A 0x2800_00FE 0x2F00_008E 0x2800_01FE 0x2B00_017E 0x2F00_011E Table 6-7 UART Baud Rate Setting Table UART Mode : MCR[LEV_RTS] = 1 MCR [RTS] MCR [RTS_ST] UART Mode : MCR[LEV_RTS] = 0 MCR [RTS] MCR [RTS_ST] Figure 6-16 UART nRTS Auto-Flow Control Trigger Level The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set IrDA_EN (UA_FUN_SEL [1]) to enable IrDA function). The SIR specification defines a short-range infrared asynchronous serial transmission mode with 1 start bit, 8 data bits, and 1 stop bit. The maximum data rate supports up to 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA Aug 31, 2015 Page 77 of 107 Rev 1.01 NUC100/120XXXDN DATASHEET The UART0 and UART1 controllers support the auto-flow control function that uses two low-level signals, /CTS (clear-to-send) and /RTS (request-to-send), to control the flow of data transfer between the chip and external devices (e.g. Modem). When auto-flow is enabled, the UART is not allowed to receive data until the UART asserts /RTS to external device. When the number of bytes in the RX FIFO equals the value of RTS_TRI_LEV (UA_FCR [19:16]), the /RTS is deasserted. The UART sends data out when UART controller detects /CTS is asserted from external device. If a valid asserted /CTS is not detected the UART controller will not send data out. NUC100/120xxxDN SIR Protocol encoder/decoder. The IrDA SIR Protocol encoder/decoder is half-duplex only. So it cannot transmit and receive data at the same time. The IrDA SIR physical layer specifies a minimum 10ms transfer delay between transmission and reception, and this delay feature must be implemented by software. The alternate function of UART controllers is LIN (Local Interconnect Network) function. The LIN mode is selected by setting the UA_FUN_SEL[1:0] to ’01’. In LIN mode, 1 start bit and 8 data bits format with 1 stop bit are required in accordance with the LIN standard. For NuMicro® NUC100 series, another alternate function of UART controllers is RS-485 9-bit mode, and direction control provided by /RTS pin or can program GPIO (PB.2 for UART0_nRTS and PB.6 for UART1_nRTS) to implement the function by software. The RS-485 mode is selected by setting the UA_FUN_SEL register to select RS-485 function. The RS-485 transceiver control is implemented using the /RTS control signal from an asynchronous serial port to enable the RS485 transceiver. In RS-485 mode, many characteristics of the receiving and transmitting are same as UART. 6.14.2 Features NUC100/120XXXDN DATASHEET  Full duplex, asynchronous communications  Separates receive / transmit 64/16/16 bytes (UART0/UART1/UART2) entry FIFO for data payloads  Supports hardware auto flow control/flow control function (CTS, RTS) and programmable RTS flow control trigger level (UART0 and UART1 support)  Programmable receiver buffer trigger level  Supports programmable baud-rate generator for each channel individually  Supports CTS wake-up function (UART0 and UART1 support)  Supports 7-bit receiver buffer time-out detection function  UART0/UART1 can through DMA channels to receive/transmit data  Programmable transmitting data delay time between the last stop and the next start bit by setting UA_TOR [DLY] register  Supports break error, frame error, parity error and receive / transmit buffer overflow detect function  Fully programmable serial-interface characteristics  – Programmable data bit length, 5-, 6-, 7-, 8-bit character – Programmable parity bit, even, odd, no parity or stick parity bit generation and detection – Programmable stop bit length, 1, 1.5, or 2 stop bit generation IrDA SIR function mode –   Supports 3-/16-bit duration for normal mode LIN function mode – Supports LIN master/slave mode – Supports programmable break generation function for transmitter – Supports break detect function for receiver RS-485 function mode. Aug 31, 2015 Page 78 of 107 Rev 1.01 NUC100/120xxxDN – Supports RS-485 9-bit mode – Supports hardware or software direct enable control provided by RTS pin NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 79 of 107 Rev 1.01 NUC100/120xxxDN 6.15 Smart Card Host Interface (SC) 6.15.1 Overview The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully compliant with PC/SC Specifications. It also provides status of card insertion/removal. 6.15.2 Features  ISO7816-3 T=0, T=1 compliant  EMV2000 compliant  Supports up to three ISO7816-3 ports  Separates receive/ transmit 4 byte entry buffer for data payloads  Programmable transmission clock frequency  Programmable receiver buffer trigger level  Programmable guard time selection (11 ETU ~ 266 ETU)  One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting times processing  Supports auto inverse convention function  Supports transmitter and receiver error retry and error retry number limitation function  Supports hardware activation sequence process  Supports hardware warm reset sequence process  Supports hardware deactivation sequence process  Supports hardware auto deactivation sequence when detecting the card removal NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 80 of 107 Rev 1.01 NUC100/120xxxDN 6.16 PS/2 Device Controller (PS2D) 6.16.1 Overview The PS/2 device controller provides a basic timing control for PS/2 communication. All communication between the device and the host is managed through the CLK and DATA pins. Unlike PS/2 keyboard or mouse device controller, the receive/transmit code needs to be translated as meaningful code by firmware. The device controller generates the CLK signal after receiving a “Request to Send” state, but host has ultimate control over communication. Data of DATA line sent from the host to the device is read on the rising edge and sent from the device to the host is change after rising edge. A 16 bytes FIFO is used to reduce CPU intervention. Software can select 1 to 16 bytes for a continuous transmission. 6.16.2 Features  Host communication inhibit and Request to Send state detection  Reception frame error detection  Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention  Double buffer for data reception  Software override bus NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 81 of 107 Rev 1.01 NUC100/120xxxDN 6.17 I2C Serial Interface Controller (I2C) 6.17.1 Overview 2 I C is a two-wire, bidirectional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to Figure 6-17 for more detailed I2C BUS Timing. STOP Repeated START START STOP SDA tBUF tLOW SCL tr tHIGH tHD;STA tHD;DAT tf tSU;DAT tSU;STA tSU;STO Figure 6-17 I2C Bus Timing NUC100/120XXXDN DATASHEET The device’s on-chip I2C logic provides a serial interface that meets the I2C bus standard mode specification. The I2C port handles byte transfers autonomously. To enable this port, the bit ENS1 in I2CON should be set to '1'. The I2C hardware interfaces to the I2C bus via two pins: SDA and SCL. Pull-up resistor is needed for I2C operation as the SDA and SCL are open drain pins. When I/O pins are used as I2C ports, user must set the pins function to I2C in advance. Aug 31, 2015 Page 82 of 107 Rev 1.01 NUC100/120xxxDN 6.17.2 Features The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus include:  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus  Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer  A built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows  External pull-up resistors needed for high output  Programmable clocks allowing for versatile rate control  Supports 7-bit addressing mode  Supports multiple address recognition (four slave addresses with mask option) NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 83 of 107 Rev 1.01 NUC100/120xxxDN 6.18 Serial Peripheral Interface (SPI) 6.18.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bidirection interface. The NuMicro® NUC100 series contains up to four sets of SPI controllers performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller can be configured as a master or a slave device. The SPI controller supports the variable serial clock function for special applications and 2-bit Transfer mode to connect 2 off-chip slave devices at the same time. This controller also supports the PDMA function to access the data buffer and also supports Dual I/O Transfer mode. 6.18.2 Features NUC100/120XXXDN DATASHEET  Up to four sets of SPI controllers  Supports Master or Slave mode operation  Supports 2-bit Transfer mode  Supports Dual I/O Transfer mode  Configurable bit length of a transfer word from 8 to 32-bit  Provides separate 8-layer depth transmit and receive FIFO buffers  Supports MSB first or LSB first transfer sequence  Two slave select lines in Master mode  Supports the byte reorder function  Supports Byte or Word Suspend mode  Variable output serial clock frequency in Master mode  Supports PDMA transfer  Supports 3-wire, no slave select signal, bi-direction interface Aug 31, 2015 Page 84 of 107 Rev 1.01 NUC100/120xxxDN 6.19 I2S Controller (I2S) 6.19.1 Overview The I2S controller consists of I2S protocol to interface with external audio CODEC. Two 8-word deep FIFO for read path and write path respectively and is capable of handling 8-, 16-, 24- and 32-bit word sizes. PDMA controller handles the data movement between FIFO and memory. 6.19.2 Features  Operated as either Master or Slave  Capable of handling 8-, 16-, 24- and 32-bit word sizes  Supports Mono and stereo audio data  Supports I2S and MSB justified data format  Provides two 8-word FIFO data buffers, one for transmitting and the other for receiving  Generates interrupt requests when buffer levels cross a programmable boundary  Two PDMA requests, one for transmitting and the other for receiving NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 85 of 107 Rev 1.01 NUC100/120xxxDN 6.20 USB Device Controller (USB) 6.20.1 Overview There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/ isochronous transfer types. In this device controller, there are two main interfaces: the APB bus and USB bus which comes from the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set the effective starting address of SRAM for each endpoint buffer through “buffer segmentation register (USB_BUFSEGx)”. There are 6 endpoints in this controller. Each of the endpoint can be configured as IN or OUT endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are implemented in this block. The block of ENDPOINT CONTROL is also used to manage the data sequential synchronization, endpoint states, current start address, transaction status, and data buffer status for each endpoint. There are four different interrupt events in this controller. They are the wake-up function, device plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend and resume, etc. Any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of interrupt occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to acknowledge what kind of event occurring in this endpoint. A software-disable function is also supported for this USB controller. It is used to simulate the disconnection of this device from the host. If user enables DRVSE0 bit (USB_DRVSE0), the USB controller will force the output of USB_DP and USB_DM to level low and its function is disabled. After disable the DRVSE0 bit, host will enumerate the USB device again. Please refer to Universal Serial Bus Specification Revision 1.1 NUC100/120XXXDN DATASHEET 6.20.2 Features This Universal Serial Bus (USB) performs a serial interface with a single connector type for attaching all USB peripherals to the host system. Following is the feature list of this USB.  Compliant with USB 2.0 Full-Speed specification  Provides 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB and BUS)  Supports Control/Bulk/Interrupt/Isochronous transfer type  Supports suspend function when no bus activity existing for 3 ms  Provides 6 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and maximum 512 bytes buffer size  Provides remote wake-up capability Aug 31, 2015 Page 86 of 107 Rev 1.01 NUC100/120xxxDN 6.21 Analog-to-Digital Converter (ADC) 6.21.1 Overview The NuMicro® NUC100 series contains one 12-bit successive approximation analog-to-digital converters (SAR A/D converter) with 8 input channels. The A/D converter supports three operation modes: single, single-cycle scan and continuous scan mode. The A/D converter can be started by software, PWM Center-aligned trigger and external STADC pin. 6.21.2 Features  Analog input voltage range: 0~VREF  12-bit resolution and 10-bit accuracy is guaranteed  Up to 8 single-end analog input channels or 4 differential analog input channels  Up to 760 kSPS conversion rate as ADC clock frequency is 16 MHz (chip working at 5V)  Three operating modes –Single mode: A/D conversion is performed one time on a specified channel –Single-cycle scan mode: A/D conversion is performed one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel –Continuous scan mode: A/D converter continuously performs Single-cycle scan mode until software stops A/D conversion  An A/D conversion can be started by: –Writing 1 to ADST bit through software –PWM Center-aligned trigger –External pin STADC Conversion results are held in data registers for each channel with valid and overrun indicators  Conversion result can be compared with specify value and user can select whether to generate an interrupt when conversion result matches the compare register setting  Channel 7 supports 3 input sources: external analog voltage, internal Band-gap voltage, and internal temperature sensor output Aug 31, 2015 Page 87 of 107 Rev 1.01 NUC100/120XXXDN DATASHEET  NUC100/120xxxDN 6.22 Analog Comparator (ACMP) 6.22.1 Overview The NuMicro® NUC100 series contains two comparators which can be used in a number of different configurations. The comparator output is logic 1 when positive input voltage is greater than negative input voltage; otherwise the output is logic 0. Each comparator can be configured to cause an interrupt when the comparator output value changes. 6.22.2 Features  Analog input voltage range: 0~ VDDA  Supports Hysteresis function  Supports optional internal reference voltage input at negative end for each comparator NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 88 of 107 Rev 1.01 NUC100/120xxxDN 7 APPLICATION CIRCUIT DVCC [1] AVCC SPISS00 SPICLK0 MISO00 AVDD DVCC Power FB VDD CS CLK MISO MOSI MOSI00 VDD SPI Device VSS 0.1uF 0.1uF VSS DVCC FB DVCC AVSS 4.7K 4.7K CLK I2C0SCL VDD ICE_CLK ICE_DAT /RESET VSS SWD Interface I2C0SDA I2C Device VSS Smart Card VCC 20p XT1_IN VDD DIO NUC1xx Series USB PORT VBUS 33 D+ Crystal 33 4~24 MHz crystal 20p D- XT1_OUT VSS DVCC Reset Circuit 10K /RESET 10uF/25V RS232 Transceiver ROUT TXD TIN NUC100/120XXXDN DATASHEET LDO RXD PC COM Port RIN TOUT UART 1uF LDO Aug 31, 2015 Note: For the SPI device, the chip supply voltage must be equal to SPI device working voltage. For example, when the SPI Flash working voltage is 3.3 V, the NUC1xx chip supply voltage must also be 3.3V. Page 89 of 107 Rev 1.01 NUC100/120xxxDN 8 8.1 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings SYMBOL PARAMETER MIN. MAX UNIT VDDVSS -0.3 +7.0 V VIN VSS-0.3 VDD+0.3 V 1/tCLCL 4 24 MHz TA -40 +85 C TST -55 +150 C - 120 mA Maximum Current out of VSS 120 mA Maximum Current sunk by a I/O pin 35 mA Maximum Current sourced by a I/O pin 35 mA Maximum Current sunk by total I/O pins 100 mA Maximum Current sourced by total I/O pins 100 mA DC Power Supply Input Voltage Oscillator Frequency Operating Temperature Storage Temperature Maximum Current into VDD Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device. NUC100/120XXXDN DATASHEET Aug 31, 2015 Page 90 of 107 Rev 1.01 NUC100/120xxxDN 8.2 DC Electrical Characteristics (VDD-VSS=5.5 V, TA = 25C, FOSC = 50 MHz unless otherwise specified.) SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. Operation Voltage Power Ground LDO Output Voltage Analog Operating Voltage VDD VSS AVSS VLDO TYP. 2.5 MAX. UNIT 5.5 V -0.3 1.62 VDD = 2.5V ~ 5.5V up to 50 MHz V 1.8 1.98 V VDD > 2.5V When system used analog function, please refer to chapter 8.4 for corresponding analog operating voltage AVDD VDD V IDD1 34 mA Operating Current VDD XTAL PLL All IP 5.5V 12 MHz V V Normal Run Mode IDD2 15 mA 5.5V 12 MHz V X at 50 MHz IDD3 32 mA 3.3V 12 MHz V V IDD4 14 mA 3.3V 12 MHz V X VDD XTAL PLL All IP IDD5 8.5 mA 5.5V 12 MHz X V Operating Current IDD6 3.6 mA 5.5V 12 MHz X X at 12 MHz IDD7 7.5 mA 3.3V 12 MHz X V IDD8 2.6 mA 3.3V 12 MHz X X VDD XTAL PLL All IP IDD9 3.6 mA 5.5V 4 MHz X V Operating Current Normal Run Mode IDD10 2 mA 5.5V 4 MHz X X at 4 MHz IDD11 2.8 mA 3.3V 4 MHz X V IDD12 1.2 mA 3.3V 4 MHz X X VDD XTAL PLL All IP 5.5V 32.768 kHz X V IDD13 141 A Operating Current Normal Run Mode at 32.768 kHz Aug 31, 2015 IDD14 129 A 5.5V 32.768 kHz X X IDD15 138 A 3.3V 32.768 kHz X V Page 91 of 107 Rev 1.01 NUC100/120XXXDN DATASHEET Normal Run Mode NUC100/120xxxDN SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IDD16 125 A IDD17 125 A Operating Current 3.3V 32.768 kHz X X VDD LIRC PLL All IP 5.5V 10 kHz X V Normal Run Mode IDD18 120 A 5.5V 10 kHz X X at 10 kHz IDD19 125 A 3.3V 10 kHz X V IDD20 120 A 3.3V 10 kHz X X VDD XTAL PLL All IP IIDLE1 28 mA 5.5V 12 MHz V V Operating Current Idle Mode IIDLE2 10 mA 5.5V 12 MHz V X at 50 MHz IIDLE3 27 mA 3.3V 12 MHz V V IIDLE4 9 mA 3.3V 12 MHz V X VDD XTAL PLL All IP IIDLE5 7.5 mA 5.5V 12 MHz X V Operating Current NUC100/120XXXDN DATASHEET Idle Mode IIDLE6 2.4 mA 5.5V 12 MHz X X at 12 MHz IIDLE7 6.5 mA 3.3V 12 MHz X V IIDLE8 1.5 mA 3.3V 12 MHz X X VDD XTAL PLL All IP IIDLE9 3.3 mA 5.5V 4 MHz X V Operating Current Idle Mode IIDLE10 1.7 mA 5.5V 4 MHz X X at 4 MHz IIDLE11 2.4 mA 3.3V 4 MHz X V IIDLE12 0.8 mA 3.3V 4 MHz X X VDD XTAL PLL All IP 5.5V 32.768 kHz X V IIDLE13 133 A Operating Current Idle Mode at 32.768 kHz Operating Current Aug 31, 2015 IIDLE14 120 A 5.5V 32.768 kHz X X IIDLE15 133 A 3.3V 32.768 kHz X V IIDLE16 120 A 3.3V 32.768 kHz X X IIDLE13 122 A VDD LIRC PLL All IP Page 92 of 107 Rev 1.01 NUC100/120xxxDN SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Idle Mode at 10 kHz 5.5V 10 kHz X V IIDLE14 118 A 5.5V 10 kHz X X IIDLE15 122 A 3.3V 10 kHz X V IIDLE16 118 A 3.3V 10 kHz X X VDD BOD function 15 A RTC IPWD1 5.5V X X Standby Current IPWD2 15 A 5.5V X X IPWD3 17 A 3.3V X X IPWD4 17 A 3.3V X X Input Current PA, PB, PC, PD, PE, PF (Quasibidirectional mode) IIN1 -50 -60 A VDD = 5.5V, VIN = 0V or VIN=VDD Input Current at /RESET[1] IIN2 -55 -45 -30 A VDD = 3.3V, VIN = 0.45V Input Leakage Current PA, PB, PC, PD, PE, PF ILK -2 - +2 A VDD = 5.5V, 0
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