0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
NUC240VE3AE

NUC240VE3AE

  • 厂商:

    NUVOTON(新唐)

  • 封装:

    LQFP100

  • 描述:

    IC MCU 32BIT 128KB FLASH 100LQFP

  • 数据手册
  • 价格&库存
NUC240VE3AE 数据手册
NuMicro NUC230/240 Datasheet NuMicro™ NUC230/240 Series DataSheet Nuvoton is providing this document only for reference purposes of NuMicroTM microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com Dec. 30, 2014 Page 1 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. NuMicro NUC230/240 Datasheet TABLE OF CONTENTS LIST OF FIGURES ..................................................................................................... 6 LIST OF TABLES ....................................................................................................... 7 1 GENERAL DESCRIPTION ..................................................................................... 8 2 FEATURES ............................................................................................................ 9 2.1 NuMicro NUC230 Features – Automotive Line ............................................ 9 2.2 NuMicro NUC240 Features – Connectivity Line .......................................... 13 3 ABBREVIATIONS ................................................................................................ 17 4 PARTS INFORMATION LIST AND PIN CONFIGURATION ................................ 19 4.1 NuMicro NUC230/240xxxAE Selection Guide ............................................ 19 4.1.1 NuMicro NUC230 Automotive Line Selection Guide ......................................... 19 4.1.2 NuMicro NUC240 Connectivity Line Selection Guide ........................................ 19 4.2 Pin Configuration ................................................................................ 21 4.2.1 NuMicro NUC230 Pin Diagram .................................................................. 21 4.2.2 NuMicro NUC240 Pin Diagram .................................................................. 24 4.3 Pin Description .................................................................................. 27 4.3.1 NuMicro NUC230 Pin Description............................................................... 27 NUMICRO™ NUC230/240 DATASHEET 4.3.2 NuMicro NUC240 Pin Description............................................................... 35 5 BLOCK DIAGRAM ............................................................................................... 43 5.1 NuMicro NUC230 Block Diagram ........................................................... 43 5.2 NuMicro NUC240 Block Diagram ........................................................... 44 6 FUNCTIONAL DESCRIPTION ............................................................................. 45 6.1 ARM® Cortex™-M0 Core ...................................................................... 45 6.2 System Manager ................................................................................ 47 6.2.1 Overview .............................................................................................. 47 6.2.2 System Reset ........................................................................................ 47 6.2.3 System Power Distribution ......................................................................... 48 6.2.4 System Memory Map ............................................................................... 50 6.2.5 System Timer (SysTick) ............................................................................ 52 6.2.6 Nested Vectored Interrupt Controller (NVIC) .................................................... 53 6.2.7 System Control ....................................................................................... 56 6.3 Clock Controller ................................................................................. 57 6.3.1 Overview .............................................................................................. 57 6.3.2 System Clock and SysTick Clock ................................................................. 60 Dec. 30, 2014 Page 2 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.3.3 Power-down Mode Clock ........................................................................... 61 6.3.4 Frequency Divider Output .......................................................................... 62 6.4 Flash Memory Controller (FMC) .............................................................. 63 6.4.1 Overview .............................................................................................. 63 6.4.2 Features .............................................................................................. 63 6.5 External Bus Interface (EBI) ................................................................... 64 6.5.1 Overview .............................................................................................. 64 6.5.2 Features .............................................................................................. 64 6.6 General Purpose I/O (GPIO) .................................................................. 65 6.6.1 Overview .............................................................................................. 65 6.6.2 Features .............................................................................................. 65 6.7 PDMA Controller (PDMA) ...................................................................... 65 6.7.1 Overview .............................................................................................. 65 6.7.2 Features .............................................................................................. 66 6.8 Timer Controller (TIMER) ...................................................................... 66 6.8.1 Overview .............................................................................................. 66 6.8.2 Features .............................................................................................. 67 6.9 PWM Generator and Capture Timer (PWM) ................................................ 68 6.9.2 Features .............................................................................................. 69 6.10 Watchdog Timer (WDT) ........................................................................ 70 6.10.1 Overview .............................................................................................. 70 6.10.2 Features .............................................................................................. 70 6.11 Window Watchdog Timer (WWDT) ........................................................... 71 6.11.1 Overview .............................................................................................. 71 6.11.2 Features .............................................................................................. 71 6.12 Real Time Clock (RTC) ........................................................................ 71 6.12.1 Overview .............................................................................................. 71 6.12.2 Features .............................................................................................. 71 6.13 UART Interface Controller (UART) ........................................................... 72 6.13.1 Overview .............................................................................................. 72 6.13.2 Features .............................................................................................. 72 6.14 Smart Card Host Interface (SC) ............................................................... 73 6.14.1 Overview .............................................................................................. 73 6.14.2 Features .............................................................................................. 73 Dec. 30, 2014 Page 3 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET 6.9.1 Overview .............................................................................................. 68 NuMicro NUC230/240 Datasheet 6.15 PS/2 Device Controller (PS2D) ............................................................... 74 6.15.1 Overview .............................................................................................. 74 6.15.2 Features .............................................................................................. 74 6.16 I2C Serial Interface Controller (I2C) ........................................................... 75 6.16.1 Overview .............................................................................................. 75 6.16.2 Features .............................................................................................. 75 6.17 Serial Peripheral Interface (SPI) .............................................................. 75 6.17.1 Overview .............................................................................................. 75 6.17.2 Features .............................................................................................. 76 6.18 I2S Controller (I2S) .............................................................................. 76 6.18.1 Overview .............................................................................................. 76 6.18.2 Features .............................................................................................. 76 6.19 USB Device Controller (USBD) ............................................................... 77 6.19.1 Overview .............................................................................................. 77 6.19.2 Features .............................................................................................. 77 6.20 Controller Area Network (CAN) ............................................................... 78 6.20.1 Overview .............................................................................................. 78 6.20.2 Features .............................................................................................. 78 NUMICRO™ NUC230/240 DATASHEET 6.21 Analog-to-Digital Converter (ADC) ........................................................... 78 6.21.1 Overview .............................................................................................. 78 6.21.2 Features .............................................................................................. 78 6.22 Analog Comparator (ACMP)................................................................... 79 6.22.1 Overview .............................................................................................. 79 6.22.2 Features .............................................................................................. 79 7 APPLICATION CIRCUIT ...................................................................................... 80 8 ELECTRICAL CHARACTERISTICS .................................................................... 81 8.1 Absolute Maximum Ratings ................................................................... 81 8.2 DC Electrical Characteristics .................................................................. 82 8.3 AC Electrical Characteristics .................................................................. 87 8.3.1 External 4~24 MHz High Speed Oscillator ....................................................... 87 8.3.2 External 4~24 MHz High Speed Crystal .......................................................... 87 8.3.3 External 32.768 kHz Low Speed Crystal Oscillator ............................................. 88 8.3.4 Internal 22.1184 MHz High Speed Oscillator .................................................... 88 8.3.5 Internal 10 kHz Low Speed Oscillator ............................................................ 88 8.4 Analog Characteristics ......................................................................... 89 Dec. 30, 2014 Page 4 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 8.4.1 12-bit SARADC Specification ...................................................................... 89 8.4.2 LDO and Power Management Specification ..................................................... 89 8.4.3 Low Voltage Reset Specification .................................................................. 90 8.4.4 Brown-out Detector Specification ................................................................. 90 8.4.5 Power-on Reset Specification ..................................................................... 90 8.4.6 Temperature Sensor Specification ................................................................ 91 8.4.7 Comparator Specification........................................................................... 91 8.4.8 USB PHY Specification ............................................................................. 92 8.5 Flash DC Electrical Characteristics ........................................................... 93 9 PACKAGE DIMENSIONS .................................................................................... 94 9.1 100-pin LQFP (14x14x1.4 mm footprint 2.0 mm) ........................................... 94 9.2 64-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ............................................... 95 9.3 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ............................................... 96 10 REVISION HISTORY ............................................................................................ 97 NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 5 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet LIST OF FIGURES Figure 4-1 NuMicro NUC230/240 Series Selection Code ........................................................... 20 Figure 4-2 NuMicro NUC230VxxAE LQFP 100-pin Diagram...................................................... 21 Figure 4-3 NuMicro NUC230SxxAE LQFP 64-pin Diagram ........................................................ 22 Figure 4-4 NuMicro NUC230LxxAE LQFP 48-pin Diagram ........................................................ 23 Figure 4-5 NuMicro NUC240VxxAE LQFP 100-pin Diagram...................................................... 24 Figure 4-6 NuMicro NUC240SxxAE LQFP 64-pin Diagram ........................................................ 25 Figure 4-7 NuMicro NUC240LxxAE LQFP 48-pin Diagram ........................................................ 26 Figure 5-1 NuMicro NUC230 Block Diagram .............................................................................. 43 Figure 5-2 NuMicro NUC240 Block Diagram .............................................................................. 44 Figure 6-1 Functional Controller Diagram ...................................................................................... 45 Figure 6-2 NuMicro NUC230 Power Distribution Diagram .......................................................... 48 Figure 6-3 NuMicro NUC240 Power Distribution Diagram .......................................................... 49 Figure 6-4 Clock Generator Block Diagram ................................................................................... 58 Figure 6-5 Clock Generator Global View Diagram......................................................................... 59 Figure 6-6 System Clock Block Diagram ....................................................................................... 60 Figure 6-7 SysTick Clock Control Block Diagram .......................................................................... 60 Figure 6-8 Clock Source of Frequency Divider .............................................................................. 62 Figure 6-9 Frequency Divider Block Diagram ................................................................................ 62 NUMICRO™ NUC230/240 DATASHEET Figure 8-1 Typical Crystal Application Circuit ................................................................................ 88 Dec. 30, 2014 Page 6 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet LIST OF TABLES Table 1-1 NuMicro NUC230/240 Series Connectivity Support Table ........................................... 8 Table 3-1 List of Abbreviations....................................................................................................... 18 Table 6-1 Address Space Assignments for On-Chip Controllers ................................................... 51 Table 6-2 Exception Model ............................................................................................................ 54 Table 6-3 System Interrupt Map..................................................................................................... 55 Table 6-4 Vector Table Format ...................................................................................................... 56 NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 7 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 1 GENERAL DESCRIPTION The NuMicro NUC230/240 series 32-bit microcontrollers are embedded with the ARM® Cortex™-M0 core with a cost equivalent to traditional 8-bit MCU for industrial control and applications requiring rich communication interfaces. The NuMicro NUC230/240 series includes NUC230 and NUC240 product lines. The NuMicro NUC230 CAN Line is embedded with the Cortex™-M0 core running up to 72 MHz and features 32K/64K/128K bytes flash, 8K/16K bytes embedded SRAM, and 8 Kbytes loader ROM for the ISP. It is also equipped with plenty of peripheral devices, such as Timers, Watchdog Timer, Window Watchdog Timer, RTC, PDMA with CRC calculation unit, UART, SPI, I2C, I2S, PWM Timer, GPIO, LIN, CAN, PS/2, Smart Card Host, 12-bit ADC, Analog Comparator, Low Voltage Reset Controller and Brown-out Detector. The NuMicro NUC240 Connectivity Line with USB 2.0 full-speed and CAN functions is embedded with the Cortex™-M0 core running up to 72 MHz and features 32K/64K/128K bytes flash, 8K/16K bytes embedded SRAM, and 8 Kbytes loader ROM for the ISP. It is also equipped with plenty of peripheral devices, such as Timers, Watchdog Timer, Window Watchdog Timer, RTC, PDMA with CRC calculation unit, UART, SPI, I2C, I2S, PWM Timer, GPIO, LIN, CAN, PS/2, USB 2.0 FS Device, Smart Card Host, 12-bit ADC, Analog Comparator, Low Voltage Reset Controller and Brown-out Detector. 2 Product Line UART SPI IC NUC230 ● ● ● NUC240 ● ● ● USB ● 2 LIN CAN PS/2 IS SC ● ● ● ● ● ● ● ● ● ● Table 1-1 NuMicro NUC230/240 Series Connectivity Support Table NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 8 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 2 FEATURES The equipped features are dependent on the product line and their sub products. 2.1 NuMicro NUC230 Features – Automotive Line Dec. 30, 2014 Page 9 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET  ARM® Cortex™-M0 core – Runs up to 72 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – Serial Wire Debug supports with 2 watchpoints/4 breakpoints  Built-in LDO for wide operating voltage ranged from 2.5 V to 5.5 V  Flash Memory – 32K/64K/128K bytes Flash for program code – 8 KB flash for ISP loader – Supports In-System-Program (ISP) and In-Application-Program (IAP) application code update – 512 byte page erase for flash – Configurable Data Flash address and size for 128 KB system, fixed 4 KB Data Flash for the 32 KB and 64 KB system – Supports 2-wired ICP update through SWD/ICE interface – Supports fast parallel programming mode by external programmer  SRAM Memory – 8K/16K bytes embedded SRAM – Supports PDMA mode  PDMA (Peripheral DMA) – Supports 9 channels PDMA for automatic data transfer between SRAM and peripherals – Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC-16 and CRC-32  Clock Control – Flexible selection for different applications – Built-in 22.1184 MHz high speed oscillator for system operation  Trimmed to ±1 % at +25 ℃ and VDD = 5 V  Trimmed to ±3 % at -40 ℃ ~ +105 ℃ and VDD = 2.5 V ~ 5.5 V – Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation – Supports one PLL, up to 72 MHz, for high performance system operation – External 4~24 MHz high speed crystal input for precise timing operation – External 32.768 kHz low speed crystal input for RTC function and low power system operation  GPIO – Four I/O modes:  Quasi-bidirectional  Push-pull output  Open-drain output  Input only with high impendence – TTL/Schmitt trigger input selectable – I/O pin configured as interrupt source with edge/level setting  Timer – Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter – Independent clock source for each timer – Provides one-shot, periodic, toggle and continuous counting operation modes – Supports event counting function – Supports input capture function  Watchdog Timer – Multiple clock sources NuMicro NUC230/240 Datasheet     NUMICRO™ NUC230/240 DATASHEET  – 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source) – Wake-up from Power-down or Idle mode – Interrupt or reset selectable on watchdog time-out – Supports 4 selectable Watchdog Timer reset delay period(1026, 130, 18 or 3 WDT_CLK) Window Watchdog Timer – 6-bit down counter with 11-bit prescale for wide range window selected RTC – Supports software compensation by setting frequency compensate register (FCR) – Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) – Supports Alarm registers (second, minute, hour, day, month, year) – Selectable 12-hour or 24-hour mode – Automatic leap year recognition – Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second – Supports battery power pin (VBAT) – Supports wake-up function PWM/Capture – Up to four built-in 16-bit PWM generators providing eight PWM outputs or four complementary paired PWM outputs – Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one Dead-Zone generator for complementary paired PWM – Supports One-shot or Auto-reload mode – Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight rising/falling capture inputs – Supports Capture interrupt UART – Up to six UART controllers (three UART controllers are shared with SC) – UART ports with flow control (TXD, RXD, nCTS and nRTS) – UART0 with 64-byte FIFO is for high speed – UART1/2(optional) with 16-byte FIFO for standard device – Supports IrDA (SIR) and LIN function – Supports RS-485 9-bit mode and direction control – Programmable baud-rate generator up to 1/16 system clock – Supports CTS wake-up function (UART0 and UART1 support) – Supports PDMA mode Smart Card Host (SC) – Supports up to three ISO-7816-3 ports  Compliant to ISO-7816-3 T=0, T=1  Separate receive / transmit 4 bytes entry FIFO for data payloads  Programmable transmission clock frequency  Programmable receiver buffer trigger level  Programmable guard time selection (11 ETU ~ 266 ETU)  One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting times processing  Supports auto inverse convention function  Supports transmitter and receiver error retry and error limit function  Supports hardware activation sequence process  Supports hardware warm reset sequence process  Supports hardware deactivation sequence process  Supports hardware auto deactivation sequence when detecting the card is removal – Supports up to three UART ports  Full duplex, asynchronous communications  Supports receiving / transmitting 4-bytes FIFO  Supports programmable baud rate generator for each channel  Programmable even, odd or no parity bit generation and detection  Programmable stop bit, 1 or 2 stop bit generation Dec. 30, 2014 Page 10 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Dec. 30, 2014 Page 11 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET  SPI – Up to four sets of SPI controllers – The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V) – The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V) – Supports SPI Master/Slave mode – Full duplex synchronous serial data transfer – Variable length of transfer data from 8 to 32 bits – MSB or LSB first data transfer – Rx and Tx on both rising or falling edge of serial clock independently – Two slave/device select lines in Master mode, and one slave/device select line in Slave mode – Supports Byte Suspend mode in 32-bit transmission – Supports PDMA mode – Supports three wire, no slave select signal, bi-direction interface  I2C – Up to two sets of I2C devices – Master/Slave mode – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Arbitration between simultaneously transmitting masters without corruption of serial data on the bus – Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus – Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer – Programmable clocks allowing for versatile rate control – Supports multiple address recognition (four slave address with mask option) – Supports wake-up function  I2S – Interface with external audio CODEC – Operate as either Master or Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Supports mono and stereo audio data – Supports I2S and MSB justified data format – Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving  PS/2 Device – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – Software override bus  CAN 2.0 – Supports CAN protocol version 2.0 part A and B – Bit rates up to 1M bit/s – 32 Message Objects – Each Message Object has its own identifier mask – Programmable FIFO mode (concatenation of Message Object) – Maskable interrupt – Disabled Automatic Re-transmission mode for Time Triggered CAN applications – Support wake-up function  ADC – 12-bit SAR ADC with 1 MSPS (chip working at 5V) – Up to 8-ch single-end input or 4-ch differential input – Single scan/single cycle scan/continuous scan NuMicro NUC230/240 Datasheet          – Each channel with individual result register – Scan on enabled channels – Threshold voltage detection – Conversion started by software programming, external input or PWM Center-aligned trigger – Supports PDMA mode Analog Comparator – Up to two analog comparators – External input or internal Band-gap voltage selectable at negative node – Interrupt when compare result change – Supports Power-down wake-up EBI (External bus interface) – Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode – Supports 8-/16-bit data width – Supports byte write in 16-bit data width mode 96-bit unique ID (UID) 128-bit unique customer ID(UCID) One built-in temperature sensor with 1℃ resolution Brown-out Detector – With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V – Supports Brown-out Interrupt and Reset option Low Voltage Reset – Threshold voltage level: 2.0 V Operating Temperature: -40℃ ~ 105℃ Packages: – All Green package (RoHS) – LQFP 100-pin / 64-pin / 48-pin NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 12 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 2.2 NuMicro NUC240 Features – Connectivity Line Dec. 30, 2014 Page 13 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET  ARM® Cortex™-M0 core – Runs up to 72 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – Serial Wire Debug supports with 2 watchpoints/4 breakpoints  Built-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V  Flash Memory – 32K/64K/128K bytes Flash for program code – 8 KB flash for ISP loader – Supports In-System-Program (ISP) and In-Application-Program (IAP) application code update – 512 byte page erase for flash – Configurable Data Flash address and size for 128 KB system, fixed 4 KB Data Flash for the 32 KB and 64 KB system – Supports 2-wired ICP update through SWD/ICE interface  SRAM Memory – 8K/16K bytes embedded SRAM – Supports PDMA mode  PDMA (Peripheral DMA) – Supports 9 channels PDMA for automatic data transfer between SRAM and peripherals – Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC-16 and CRC-32  Clock Control – Flexible selection for different applications – Built-in 22.1184 MHz high speed oscillator for system operation  Trimmed to ±1 % at +25 ℃ and VDD = 5 V  Trimmed to ±3 % at -40 ℃ ~ +105 ℃ and VDD = 2.5 V ~ 5.5 V – Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation – Supports one PLL, up to 72 MHz, for high performance system operation – External 4~24 MHz high speed crystal input for USB and precise timing operation – External 32.768 kHz low speed crystal input for RTC function and low power system operation  GPIO – Four I/O modes:  Quasi-bidirectional  Push-pull output  Open-drain output  Input only with high impendence – TTL/Schmitt trigger input selectable – I/O pin configured as interrupt source with edge/level setting  Timer – Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter – Independent clock source for each timer – Provides one-shot, periodic, toggle and continuous counting operation modes – Supports event counting function – Supports input capture function  Watchdog Timer – Multiple clock sources – 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source) – Wake-up from Power-down or Idle mode – Interrupt or reset selectable on watchdog time-out – Supports 4 selectable Watchdog Timer reset delay period(1026, 130, 18 or 3 WDT_CLK) NuMicro NUC230/240 Datasheet NUMICRO™ NUC230/240 DATASHEET  Window Watchdog Timer – 6-bit down counter with 11-bit prescale for wide range window selected  RTC – Supports software compensation by setting frequency compensate register (FCR) – Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) – Supports Alarm registers (second, minute, hour, day, month, year) – Selectable 12-hour or 24-hour mode – Automatic leap year recognition – Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second – Supports battery power pin (VBAT) – Supports wake-up function  PWM/Capture – Up to four built-in 16-bit PWM generators providing eight PWM outputs or four complementary paired PWM outputs – Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one Dead-Zone generator for complementary paired PWM – Supports One-shot or Auto-reload mode – Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight rising/falling capture inputs – Supports Capture interrupt  UART – Up to six UART controllers (three UART controllers are shared with SC) – UART ports with flow control (TXD, RXD, nCTS and nRTS) – UART0 with 64-byte FIFO is for high speed – UART1/2(optional) with 16-byte FIFO for standard device – Supports IrDA (SIR) and LIN function – Supports RS-485 9-bit mode and direction control – Programmable baud-rate generator up to 1/16 system clock – Supports CTS wake-up function (UART0 and UART1 support) – Supports PDMA mode  Smart Card Host (SC) – Supports up to three ISO-7816-3 ports  Compliant to ISO-7816-3 T=0, T=1  Separate receive / transmit 4 bytes entry FIFO for data payloads  Programmable transmission clock frequency  Programmable receiver buffer trigger level  Programmable guard time selection (11 ETU ~ 266 ETU)  One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting times processing  Supports auto inverse convention function  Supports transmitter and receiver error retry and error limit function  Supports hardware activation sequence process  Supports hardware warm reset sequence process  Supports hardware deactivation sequence process  Supports hardware auto deactivation sequence when detecting the card is removal – Supports up to three UART ports  Full duplex, asynchronous communications  Supports receiving / transmitting 4-bytes FIFO  Supports programmable baud rate generator for each channel  Programmable even, odd or no parity bit generation and detection  Programmable stop bit, 1 or 2 stop bit generation  SPI – Up to four sets of SPI controllers – The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V) – The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V) Dec. 30, 2014 Page 14 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet – – – – – –     Dec. 30, 2014 Page 15 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET  Supports SPI Master/Slave mode Full duplex synchronous serial data transfer Variable length of transfer data from 8 to 32 bits MSB or LSB first data transfer Rx and Tx on both rising or falling edge of serial clock independently Two slave/device select lines in Master mode, and one slave/device select line in Slave mode – Supports Byte Suspend mode in 32-bit transmission – Supports PDMA mode – Supports three wire, no slave select signal, bi-direction interface I2C – Up to two sets of I2C devices – Master/Slave mode – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Arbitration between simultaneously transmitting masters without corruption of serial data on the bus – Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus – Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer – Programmable clocks allowing for versatile rate control – Supports multiple address recognition (four slave address with mask option) – Supports wake-up function I2S – Interface with external audio CODEC – Operate as either Master or Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Supports mono and stereo audio data – Supports I2S and MSB justified data format – Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving PS/2 Device – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – Software override bus CAN 2.0 – Supports CAN protocol version 2.0 part A and B – Bit rates up to 1M bit/s – 32 Message Objects – Each Message Object has its own identifier mask – Programmable FIFO mode (concatenation of Message Object) – Maskable interrupt – Disabled Automatic Re-transmission mode for Time Triggered CAN applications – Supports Power-down wake-up function USB 2.0 Full-Speed Device – One set of USB 2.0 FS Device 12 Mbps – On-chip USB Transceiver – Provides 1 interrupt source with 4 interrupt events – Supports Control, Bulk In/Out, Interrupt and Isochronous transfers – Auto suspend function when no bus signaling for 3 ms – Provides 8 programmable endpoints – Includes 512 Bytes internal SRAM as USB buffer NuMicro NUC230/240 Datasheet NUMICRO™ NUC230/240 DATASHEET – Provides remote wake-up capability  ADC – 12-bit SAR ADC with 1 MSPS(chip working at 5V) – Up to 8-ch single-end input or 4-ch differential input – Single scan/single cycle scan/continuous scan – Each channel with individual result register – Scan on enabled channels – Threshold voltage detection – Conversion started by software programming, external input or PWM Center-aligned trigger – Supports PDMA mode  Analog Comparator – Up to two analog comparators – External input or internal Band-gap voltage selectable at negative node – Interrupt when compare result change – Supports Power-down wake-up  EBI (External bus interface) – Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode – Supports 8-/16-bit data width – Supports byte write in 16-bit data width mode  96-bit unique ID (UID)  128-bit unique customer ID(UCID)  One built-in temperature sensor with 1℃ resolution  Brown-out Detector – With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V – Supports Brown-out Interrupt and Reset option  Low Voltage Reset – Threshold voltage level: 2.0 V  Operating Temperature: -40℃ ~ 105℃  Packages: – All Green package (RoHS) – LQFP 100-pin / 64-pin / 48-pin Dec. 30, 2014 Page 16 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 3 ABBREVIATIONS Description ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AES Advanced Encryption Standard APB Advanced Peripheral Bus AHB Advanced High-Performance Bus BOD Brown-out Detection CAN Controller Area Network DAP Debug Access Port DES Data Encryption Standard EBI External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO First In, First Out FMC Flash Memory Controller FPU Floating-point Unit GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC 22.1184 MHz Internal High Speed RC Oscillator HXT 4~24 MHz External High Speed Crystal Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIN Local Interconnect Network LIRC 10 kHz internal low speed RC oscillator (LIRC) MPU Memory Protection Unit NVIC Nested Vectored Interrupt Controller PCLK The Clock of Advanced Peripheral Bus PDMA Peripheral Direct Memory Access PLL Phase-Locked Loop PWM Pulse Width Modulation QEI Quadrature Encoder Interface SDIO Secure Digital Input/Output SPI Serial Peripheral Interface Dec. 30, 2014 Page 17 of 97 NUMICRO™ NUC230/240 DATASHEET Acronym Revision 1.01 NuMicro NUC230/240 Datasheet SPS Samples per Second TDES Triple Data Encryption Standard TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 3-1 List of Abbreviations NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 18 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 4 PARTS INFORMATION LIST AND PIN CONFIGURATION 4.1 NuMicro NUC230/240xxxAE Selection Guide 4.1.1 NuMicro NUC230 Automotive Line Selection Guide RAM (KB) Data Flash (KB) ISP ROM (KB) I/O Timer (32-bit) UART SPI IC USB LIN CAN IS SC Comp. PWM ADC (12-bit) RTC EBI ISP/ICP/IAP Package 32 8 4 8 35 4 5 1 2 - 3 2 1 2 1 4 7 v - v LQFP48 NUC230LD2AE 64 8 4 8 35 4 5 1 2 - 3 2 1 2 1 4 7 v - v LQFP48 2 APROM (KB) NUC230LC2AE 2 Part Number Connectivity NUC230LE3AE 128 16 Config. 8 35 4 5 1 2 - 3 2 1 2 1 4 7 v - v LQFP48 NUC230SC2AE 32 8 4 8 49 4 5 2 2 - 3 2 1 2 2 6 7 v v v LQFP64 NUC230SD2AE 64 8 4 8 49 4 5 2 2 - 3 2 1 2 2 6 7 v v v LQFP64 NUC230SE3AE 128 16 Config. 8 49 4 5 2 2 - 3 2 1 2 2 6 7 v v v LQFP64 NUC230VE3AE 128 16 Config. 8 83 4 6 4 2 - 3 2 1 3 2 8 8 v v v LQFP100 4.1.2 NuMicro NUC240 Connectivity Line Selection Guide RAM (KB) Data Flash (KB) ISP ROM (KB) I/O Timer (32-bit) UART SPI IC USB LIN CAN IS SC Comp. PWM ADC (12-bit) RTC EBI ISP/ICP/IAP Package 8 4 8 31 4 4 1 2 1 2 2 1 1 1 4 7 v - v LQFP48 NUC240LD2AE 64 8 4 8 31 4 4 1 2 1 2 2 1 1 1 4 7 v - v LQFP48 NUC240LE3AE 128 16 Config. 8 31 4 4 1 2 1 2 2 1 1 1 4 7 v - v LQFP48 NUC240SC2AE 32 8 4 8 45 4 5 2 2 1 3 2 1 2 2 4 7 v v v LQFP64 NUC240SD2AE 64 8 4 8 45 4 5 2 2 1 3 2 1 2 2 4 7 v v v LQFP64 NUC240SE3AE 128 16 Config. 8 45 4 5 2 2 1 3 2 1 2 2 4 7 v v v LQFP64 NUC240VE3AE 128 16 Config. 8 79 4 6 4 2 1 3 2 1 3 2 8 8 v v v LQFP100 Dec. 30, 2014 Page 19 of 97 2 APROM (KB) 32 2 Part Number NUC240LC2AE Revision 1.01 NUMICRO™ NUC230/240 DATASHEET Connectivity NuMicro NUC230/240 Datasheet NUC 2 X 0 - X X X X X ARM-Based 32-bit Microcontroller Temperature CPU core N: -40℃ ~ +85℃ E: -40℃ ~ +105℃ C: -40℃ ~ +125℃ 1/2: Cortex-M0 5/7: ARM7 9: ARM9 Reserve Function RAM Size 2: 8 KB 3: 16 KB 3: Automotive Line 4: Connectivity Line APROM Size C: 32 KB D: 64 KB E: 128 KB Package Type L: LQFP 48 S: LQFP 64 V: LQFP 100 Figure 4-1 NuMicro NUC230/240 Series Selection Code NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 20 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 4.2 Pin Configuration 4.2.1 NuMicro NUC230 Pin Diagram PA.4/ADC4/SC1_PWR/AD9 PA.3/ADC3/SC0_DAT/UART3_RXD/AD10 PA.2/ADC2/SC0_CLK/UART3_TXD/AD11 PA.1/ADC1/SC0_RST/AD12 PA.0/ADC0/SC0_PWR AVSS VSS VDD ICE_CLK ICE_DAT PA.12/PWM0/SC2_DAT/UART5_RXD/AD13 PA.13/PWM1/SC2_CLK/UART5_TXD/AD14 PA.14/PWM2/SC2_RST/AD15 PA.15/PWM3/I2S_MCLK/SC2_PWR PC.8/SPI1_SS0/MCLK PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1 PC.13/SPI1_MOSI1 PE.0/PWM6 PE.1/PWM7 PE.2 PE.3 PE.4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 4.2.1.1 NuMicro NUC230VxxAE LQFP 100 pin 76 50 PB.9/TM1/SPI1_SS1 77 49 PB.10/TM2/SPI0_SS1 UART4_RXD/SC1_DAT/AD6/ADC7/SPI2_SS1/PA.7 78 48 PB.11/TM3/PWM4 VREF 79 47 PE.5/TM1_EXT/PWM5/TM1 AVDD 80 46 PE.6 SPI2_SS0/PD.0 81 45 PC.0/SPI0_SS0/I2S_LRCLK SPI2_CLK/PD.1 82 44 PC.1/SPI0_CLK/I2S_BCLK SPI2_MISO0/PD.2 83 43 PC.2/SPI0_MISO0/I2S_DI SPI2_MOSI0/PD.3 84 42 PC.3/SPI0_MOSI0/I2S_DO SPI2_MISO1/PD.4 85 41 PC.4/SPI0_MISO1 SPI2_MOSI1/PD.5 86 40 PC.5/SPI0_MOSI1 SC1_CD/AD5/ACMP0_N/PC.7 87 39 PD.15/UART2_TXD/CAN1_TXD SC0_CD/AD4/ACMP0_P/PC.6 88 38 PD.14/UART2_RXD/CAN1_RXD AD3/ACMP1_N/PC.15 89 37 PD.7/CAN0_TXD AD2/ACMP1_P/PC.14 90 36 PD.6/CAN0_RXD TM0/TM0_EXT/INT1/PB.15 91 35 PB.3/UART0_nCTS/TM3_EXT/SC2_CD/TM3/nWRH XT1_OUT/PF.0 92 34 PB.2/UART0_nRTS/TM2_EXT/ACMP0_O/TM2/nWRL XT1_IN/PF.1 93 33 PB.1/UART0_TXD nRESET 94 32 PB.0/UART0_RXD VSS 95 31 PE.7 VDD 96 30 PE.8 PS2_DAT/PF.2 97 29 PE.9 PS2_CLK/PF.3 98 28 PE.10 PVSS 99 27 PE.11 100 26 PE.12 22 23 24 25 nCS/UART1_nCTS/PB.7 LDO_CAP VDD VSS 19 UART1_RXD/PB.4 21 18 SPI3_MOSI1/PD.13 20 17 SPI3_MISO1/PD.12 UART1_TXD/PB.5 16 SPI3_MOSI0/PD.11 ALE/UART1_nRTS/PB.6 15 10 nWR/CAN1_TXD/I2C1_SDA/PA.10 SPI3_MISO0/PD.10 9 nRD/CAN1_RXD/I2C1_SCL/PA.11 14 8 X32_IN SPI3_CLK/PD.9 7 X32_OUT 13 6 VBAT SPI3_SS0/PD.8 5 AD1/ACMP1_O/PB.13 12 4 AD0/SPI3_SS1/INT0/PB.14 11 3 PE.13 I2C0_SCL/PA.9 2 PE.14 I2C0_SDA/PA.8 1 PE.15 CLKO/TM0/STADC/PB.8 NUC230VxxAE LQFP 100-pin NUMICRO™ NUC230/240 DATASHEET SC1_RST/AD8/ADC5/PA.5 UART4_TXD/SC1_CLK/AD7/ADC6/PA.6 Figure 4-2 NuMicro NUC230VxxAE LQFP 100-pin Diagram Dec. 30, 2014 Page 21 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet PA.4/ADC4/AD9 PA.3/ADC3/SC0_DAT/UART3_RXD/AD10 PA.2/ADC2/SC0_CLK/UART3_TXD/AD11 PA.1/ADC1/SC0_RST/AD12 PA.0/ADC0/SC0_PWR AVSS ICE_CLK ICE_DAT PA.12/PWM0/SC2_DAT/UART5_RXD/AD13 PA.13/PWM1/SC2_CLK/UART5_TXD/AD14 PA.14/PWM2/SC2_RST/AD15 PA.15/PWM3/I2S_MCLK/SC2_PWR PC.8/SPI1_SS0/MCLK PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 4.2.1.2 NuMicro NUC230SxxAE LQFP 64 pin AD8/ADC5/PA.5 49 32 PB.9/TM1 AD7/ADC6/PA.6 50 31 PB.10/TM2 VREF 51 30 PB.11/TM3/PWM4 AVDD 52 29 PE.5/TM1_EXT/PWM5/TM1 AD5/ACMP0_N/PC.7 53 28 PC.0/SPI0_SS0/I2S_LRCLK SC0_CD/AD4/ACMP0_P/PC.6 54 27 PC.1/SPI0_CLK/I2S_BCLK AD3/ACMP1_N/PC.15 55 26 PC.2/SPI0_MISO0/I2S_DI AD2/ACMP1_P/PC.14 56 25 PC.3/SPI0_MOSI0/I2S_DO AD6/TM0/TM0_EXT/INT1/PB.15 57 24 PD.15/UART2_TXD/CAN1_TXD XT1_OUT/PF.0 58 23 PD.14/UART2_RXD/CAN1_RXD XT1_IN/PF.1 59 22 PD.7/CAN0_TXD nRESET 60 21 PD.6/CAN0_RXD VSS 61 20 PB.3/UART0_nCTS/TM3_EXT/SC2_CD/TM3/nWRH VDD 62 19 PB.2/UART0_nRTS/TM2_EXT/ACMP0_O/TM2/nWRL PVSS 63 18 PB.1/UART0_TXD CLKO/TM0/STADC/PB.8 64 17 PB.0/UART0_RXD 14 15 16 LDO_CAP VDD VSS 9 I2C0_SDA/PA.8 13 8 I2C0_SCL/PA.9 nCS/UART1_nCTS/PB.7 7 nWR/CAN1_TXD/I2C1_SDA/PA.10 12 6 nRD/CAN1_RXD/I2C1_SCL/PA.11 ALE/UART1_nRTS/PB.6 5 X32_IN 11 4 X32_OUT UART1_TXD/PB.5 3 VBAT 10 2 UART1_RXD/PB.4 1 AD0/INT0/PB.14 NUMICRO™ NUC230/240 DATASHEET AD1/ACMP1_O/PB.13 NUC230SxxAE LQFP 64-pin Figure 4-3 NuMicro NUC230SxxAE LQFP 64-pin Diagram Dec. 30, 2014 Page 22 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet PA.4/ADC4 PA.3/ADC3/SC0_DAT/UART3_RXD PA.2/ADC2/SC0_CLK/UART3_TXD PA.1/ADC1/SC0_RST PA.0/ADC0/SC0_PWR AVSS ICE_CLK ICE_DAT PA.12/PWM0/SC2_DAT/UART5_RXD PA.13/PWM1/SC2_CLK/UART5_TXD PA.14/PWM2/SC2_RST PA.15/PWM3/I2S_MCLK/SC2_PWR 36 35 34 33 32 31 30 29 28 27 26 25 4.2.1.3 NuMicro NUC230LxxAE LQFP 48 pin ADC5/PA.5 37 24 PC.0/SPI0_SS0/I2S_LRCLK ADC6/PA.6 38 23 PC.1/SPI0_CLK/I2S_BCLK VREF 39 22 PC.2/SPI0_MISO0/I2S_DI AVDD 40 21 PC.3/SPI0_MOSI0/I2S_DO ACMP0_N/PC.7 41 20 PD.15/UART2_TXD/CAN1_TXD SC0_CD/ACMP0_P/PC.6 42 19 PD.14/UART2_RXD/CAN1_RXD TM0/TM0_EXT/INT1/PB.15 43 18 PD.7/CAN0_TXD XT1_OUT/PF.0 44 17 PD.6/CAN0_RXD XT1_IN/PF.1 45 16 PB.3/UART0_nCTS/TM3_EXT/SC2_CD/TM3 nRESET 46 15 PB.2/UART0_nRTS/TM2_EXT/ACMP0_O/TM2 PVSS 47 14 PB.1/UART0_TXD CLKO/TM0/STADC/PB.8 48 13 PB.0/UART0_RXD 9 UART1_TXD/PB.5 12 8 UART1_RXD/PB.4 VSS 7 I2C0_SDA/PA.8 11 6 I2C0_SCL/PA.9 VDD 5 CAN1_TXD/I2C1_SDA/PA.10 10 4 CAN1_RXD/I2C1_SCL/PA.11 LDO_CAP 3 2 X32_IN 1 VBAT NUMICRO™ NUC230/240 DATASHEET X32_OUT NUC230LxxAE LQFP 48-pin Figure 4-4 NuMicro NUC230LxxAE LQFP 48-pin Diagram Dec. 30, 2014 Page 23 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 4.2.2 NuMicro NUC240 Pin Diagram PA.4/ADC4/SC1_PWR/AD9 PA.3/ADC3/SC0_DAT/UART3_RXD/AD10 PA.2/ADC2/SC0_CLK/UART3_TXD/AD11 PA.1/ADC1/SC0_RST/AD12 PA.0/ADC0/SC0_PWR AVSS VSS VDD ICE_CLK ICE_DAT PA.12/PWM0/SC2_DAT/UART5_RXD/AD13 PA.13/PWM1/SC2_CLK/UART5_TXD/AD14 PA.14/PWM2/SC2_RST/AD15 PA.15/PWM3/I2S_MCLK/SC2_PWR PC.8/SPI1_SS0/MCLK PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1 PC.13/SPI1_MOSI1 PE.0/PWM6 PE.1/PWM7 PE.2 PE.3 PE.4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 4.2.2.1 NuMicro NUC240VxxAE LQFP 100 pin SC1_RST/AD8/ADC5/PA.5 76 50 PB.9/TM1/SPI1_SS1 UART4_TXD/SC1_CLK/AD7/ADC6/PA.6 77 49 PB.10/TM2/SPI0_SS1 UART4_RXD/SC1_DAT/AD6/ADC7/SPI2_SS1/PA.7 78 48 PB.11/TM3/PWM4 VREF 79 47 PE.5/TM1_EXT/PWM5/TM1 AVDD 80 46 PE.6 SPI2_SS0/PD.0 81 45 PC.0/SPI0_SS0/I2S_LRCLK SPI2_CLK/PD.1 82 44 PC.1/SPI0_CLK/I2S_BCLK SPI2_MISO0/PD.2 83 43 PC.2/SPI0_MISO0/I2S_DI SPI2_MOSI0/PD.3 84 42 PC.3/SPI0_MOSI0/I2S_DO SPI2_MISO1/PD.4 85 41 PC.4/SPI0_MISO1 86 40 PC.5/SPI0_MOSI1 87 39 PD.15/UART2_TXD/CAN1_TXD SC0_CD/AD4/ACMP0_P/PC.6 88 38 PD.14/UART2_RXD/CAN1_RXD AD3/ACMP1_N/PC.15 89 37 PD.7/CAN0_TXD AD2/ACMP1_P/PC.14 90 36 PD.6/CAN0_RXD TM0/TM0_EXT/INT1/PB.15 91 35 PB.3/UART0_nCTS/TM3_EXT/SC2_CD/TM3/nWRH XT1_OUT/PF.0 92 34 PB.2/UART0_nRTS/TM2_EXT/ACMP0_O/TM2/nWRL XT1_IN/PF.1 93 33 PB.1/UART0_TXD nRESET 94 32 PB.0/UART0_RXD VSS 95 31 USB_D+ VDD 96 30 USB_D- PS2_DAT/PF.2 97 29 USB_VDD33_CAP PS2_CLK/PF.3 98 28 USB_VBUS PVSS 99 27 PE.7 100 26 PE.8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I2C0_SCL/PA.9 I2C0_SDA/PA.8 SPI3_SS0/PD.8 SPI3_CLK/PD.9 SPI3_MISO0/PD.10 SPI3_MOSI0/PD.11 SPI3_MISO1/PD.12 SPI3_MOSI1/PD.13 UART1_RXD/PB.4 UART1_TXD/PB.5 ALE/UART1_nRTS/PB.6 nCS/UART1_nCTS/PB.7 LDO_CAP VDD VSS 7 X32_OUT 10 6 VBAT nWR/CAN1_TXD/I2C1_SDA/PA.10 5 AD1/ACMP1_O/PB.13 9 4 AD0/SPI3_SS1/INT0/PB.14 nRD/CAN1_RXD/I2C1_SCL/PA.11 3 PE.13 8 2 X32_IN 1 PE.14 CLKO/TM0/STADC/PB.8 NUC240VxxAE LQFP 100-pin PE.15 NUMICRO™ NUC230/240 DATASHEET SPI2_MOSI1/PD.5 SC1_CD/AD5/ACMP0_N/PC.7 Figure 4-5 NuMicro NUC240VxxAE LQFP 100-pin Diagram Dec. 30, 2014 Page 24 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet PA.4/ADC4/AD9 PA.3/ADC3/SC0_DAT/UART3_RXD/AD10 PA.2/ADC2/SC0_CLK/UART3_TXD/AD11 PA.1/ADC1/SC0_RST/AD12 PA.0/ADC0/SC0_PWR AVSS ICE_CLK ICE_DAT PA.12/PWM0/SC2_DAT/UART5_RXD/AD13 PA.13/PWM1/SC2_CLK/UART5_TXD/AD14 PA.14/PWM2/SC2_RST/AD15 PA.15/PWM3/I2S_MCLK/SC2_PWR PC.8/SPI1_SS0/MCLK PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 4.2.2.2 NuMicro NUC240SxxAE LQFP 64 pin AD8/ADC5/PA.5 49 32 PC.0/SPI0_SS0/I2S_LRCLK AD7/ADC6/PA.6 50 31 PC.1/SPI0_CLK/I2S_BCLK VREF 51 30 PC.2/SPI0_MISO0/I2S_DI AVDD 52 29 PC.3/SPI0_MOSI0/I2S_DO AD5/ACMP0_N/PC.7 53 28 PD.15/UART2_TXD/CAN1_TXD SC0_CD/AD4/ACMP0_P/PC.6 54 27 PD.14/UART2_RXD/CAN1_RXD AD3/ACMP1_N/PC.15 55 26 PD.7/CAN0_TXD AD2/ACMP1_P/PC.14 56 25 PD.6/CAN0_RXD AD6/TM0/TM0_EXT/INT1/PB.15 57 24 PB.3/UART0_nCTS/TM3_EXT/SC2_CD/TM3/nWRH XT1_OUT/PF.0 58 23 PB.2/UART0_nRTS/TM2_EXT/ACMP0_O/TM2/nWRL XT1_IN/PF.1 59 22 PB.1/UART0_TXD nRESET 60 21 PB.0/UART0_RXD VSS 61 20 USB_D+ VDD 62 19 USB_D- PVSS 63 18 USB_VDD33_CAP CLKO/TM0/STADC/PB.8 64 17 USB_VBUS 14 15 16 LDO_CAP VDD VSS 9 I2C0_SDA/PA.8 13 8 I2C0_SCL/PA.9 nCS/UART1_nCTS/PB.7 7 nWR/CAN1_TXD/I2C1_SDA/PA.10 12 6 nRD/CAN1_RXD/I2C1_SCL/PA.11 ALE/UART1_nRTS/PB.6 5 X32_IN 11 4 X32_OUT UART1_TXD/PB.5 3 VBAT 10 2 UART1_RXD/PB.4 1 AD0/INT0/PB.14 NUMICRO™ NUC230/240 DATASHEET AD1/ACMP1_O/PB.13 NUC240SxxAE LQFP 64-pin Figure 4-6 NuMicro NUC240SxxAE LQFP 64-pin Diagram Dec. 30, 2014 Page 25 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet PA.4/ADC4 PA.3/ADC3/SC0_DAT/UART3_RXD PA.2/ADC2/SC0_CLK/UART3_TXD PA.1/ADC1/SC0_RST PA.0/ADC0/SC0_PWR AVSS ICE_CLK ICE_DAT PA.12/PWM0/UART5_RXD PA.13/PWM1/UART5_TXD PA.14/PWM2 PA.15/PWM3/I2S_MCLK 36 35 34 33 32 31 30 29 28 27 26 25 4.2.2.3 NuMicro NUC240LxxAE LQFP 48 pin ADC5/PA.5 37 24 PC.0/SPI0_SS0/I2S_LRCLK ADC6/PA.6 38 23 PC.1/SPI0_CLK/I2S_BCLK VREF 39 22 PC.2/SPI0_MISO0/I2S_DI AVDD 40 21 PC.3/SPI0_MOSI0/I2S_DO ACMP0_N/PC.7 41 20 PD.7/CAN0_TXD SC0_CD/ACMP0_P/PC.6 42 19 PD.6/CAN0_RXD TM0/TM0_EXT/INT1/PB.15 43 18 PB.1/UART0_TXD XT1_OUT/PF.0 44 17 PB.0/UART0_RXD XT1_IN/PF.1 45 16 USB_D+ nRESET 46 15 USB_D- PVSS 47 14 USB_VDD33_CAP CLKO/TM0/STADC/PB.8 48 13 USB_VBUS 9 UART1_TXD/PB.5 12 8 UART1_RXD/PB.4 VSS 7 I2C0_SDA/PA.8 11 6 I2C0_SCL/PA.9 VDD 5 CAN1_TXD/I2C1_SDA/PA.10 10 4 CAN1_RXD/I2C1_SCL/PA.11 LDO_CAP 3 2 X32_IN 1 VBAT NUMICRO™ NUC230/240 DATASHEET X32_OUT NUC240LxxAE LQFP 48-pin Figure 4-7 NuMicro NUC240LxxAE LQFP 48-pin Diagram Dec. 30, 2014 Page 26 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 4.3 Pin Description 4.3.1 NuMicro NUC230 Pin Description Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Description Type 1 PE.15 I/O General purpose digital I/O pin. 2 PE.14 I/O General purpose digital I/O pin. 3 PE.13 I/O General purpose digital I/O pin. PB.14 I/O General purpose digital I/O pin. AD0 I/O EBI Address/Data bus bit0 INT0 I 1 4 5 2 External interrupt0 input pin. nd SPI3_SS1 I/O 2 SPI3 slave select pin. PB.13 I/O General purpose digital I/O pin. AD1 I/O EBI Address/Data bus bit1 ACMP1_O O Comparator1 output pin. 6 3 1 VBAT P Power supply by batteries for RTC. 7 4 2 X32_OUT O External 32.768 kHz (low speed) crystal output pin. 8 5 3 X32_IN I External 32.768 kHz (low speed) crystal input pin. 9 11 12 General purpose digital I/O pin. I2C1_SCL I/O I C1 clock pin. 2 6 5 10 I/O NUMICRO™ NUC230/240 DATASHEET 4 PA.11 CAN1_RXD I Data receiver input pin for CAN1. nRD O EBI read enable output pin PA.10 I/O General purpose digital I/O pin. I2C1_SDA I/O I C1 data input/output pin. CAN1_TXD O Data transmitter output pin for CAN1. nWR O EBI write enable output pin PA.9 I/O General purpose digital I/O pin. I2C0_SCL I/O I C0 clock pin. PA.8 I/O General purpose digital I/O pin. I2C0_SDA I/O I C0 data input/output pin. PD.8 I/O General purpose digital I/O pin. SPI3_SS0 I/O 1 SPI3 slave select pin. PD.9 I/O General purpose digital I/O pin. SPI3_CLK I/O SPI3 serial clock pin. PD.10 I/O General purpose digital I/O pin. 2 7 8 9 6 7 13 2 2 st 14 15 Dec. 30, 2014 Page 27 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Description Type I/O 1 SPI3 MISO (Master In, Slave Out) pin. PD.11 I/O General purpose digital I/O pin. SPI3_MOSI0 I/O 1 SPI3 MOSI (Master Out, Slave In) pin. PD.12 I/O General purpose digital I/O pin. SPI3_MISO1 I/O 2 SPI3 MISO (Master In, Slave Out) pin. PD.13 I/O General purpose digital I/O pin. SPI3_MOSI1 I/O 2 SPI3 MOSI (Master Out, Slave In) pin. PB.4 I/O General purpose digital I/O pin. 16 17 18 19 10 21 22 11 st nd nd 8 UART1_RXD 20 st SPI3_MISO0 I Data receiver input pin for UART1. NUMICRO™ NUC230/240 DATASHEET PB.5 I/O General purpose digital I/O pin. UART1_TXD O Data transmitter output pin for UART1. PB.6 I/O General purpose digital I/O pin. ALE O EBI address latch enable output pin UART1_nRTS O Request to Send output pin for UART1. PB.7 I/O General purpose digital I/O pin. nCS O EBI chip select enable output pin UART1_nCTS I Clear to Send input pin for UART1. 9 12 13 23 14 10 LDO_CAP P LDO output pin. 24 15 11 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. 25 16 12 VSS P Ground pin for digital circuit. 26 PE.12 I/O General purpose digital I/O pin. 27 PE.11 I/O General purpose digital I/O pin. 28 PE.10 I/O General purpose digital I/O pin. 29 PE.9 I/O General purpose digital I/O pin. 30 PE.8 I/O General purpose digital I/O pin. 31 PE.7 I/O General purpose digital I/O pin. PB.0 I/O General purpose digital I/O pin. 32 17 13 UART0_RXD 33 34 Dec. 30, 2014 18 19 I Data receiver input pin for UART0. PB.1 I/O General purpose digital I/O pin. UART0_TXD O Data transmitter output pin for UART0. PB.2 I/O General purpose digital I/O pin. UART0_nRTS O Request to Send output pin for UART0. 14 15 Page 28 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Description Type TM2_EXT I Timer2 external capture input pin. ACMP0_O O Comparator0 output pin. nWRL O EBI low byte write enable output pin PB.3 I/O General purpose digital I/O pin. UART0_nCTS I Clear to Send input pin for UART0. TM3_EXT I Timer3 external capture input pin. SC2_CD I SmartCard2 card detect pin. nWRH O EBI high byte write enable output pin PD.6 I/O General purpose digital I/O pin. 16 35 36 20 21 17 CAN0_RXD 37 38 23 24 PD.7 I/O General purpose digital I/O pin. CAN0_TXD O Data transmitter output pin for CAN0. PD.14 I/O General purpose digital I/O pin. 18 19 20 UART2_RXD I Data receiver input pin for UART2. CAN1_RXD I Data receiver input pin for CAN1. PD.15 I/O General purpose digital I/O pin. UART2_TXD O Data transmitter output pin for UART2. CAN1_TXD O Data transmitter output pin for CAN1. PC.5 I/O General purpose digital I/O pin. SPI0_MOSI1 I/O 2 SPI0 MOSI (Master Out, Slave In) pin. PC.4 I/O General purpose digital I/O pin. SPI0_MISO1 I/O 2 SPI0 MISO (Master In, Slave Out) pin. PC.3 I/O General purpose digital I/O pin. SPI0_MOSI0 I/O 1 SPI0 MOSI (Master Out, Slave In) pin. I2S_DO O I S data output. PC.2 I/O General purpose digital I/O pin. SPI0_MISO0 I/O 1 SPI0 MISO (Master In, Slave Out) pin. 40 41 42 43 25 26 21 22 I2S_DI 44 45 Dec. 30, 2014 27 28 Data receiver input pin for CAN0. 23 24 I NUMICRO™ NUC230/240 DATASHEET 39 22 I nd nd st 2 st 2 I S data input. PC.1 I/O General purpose digital I/O pin. SPI0_CLK I/O SPI0 serial clock pin. I2S_BCLK I/O I S bit clock pin. PC.0 I/O General purpose digital I/O pin. 2 Page 29 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin LQFP 64-pin 46 47 LQFP 48-pin Pin Name Pin Description Type st SPI0_SS0 I/O 1 SPI0 slave select pin. I2S_LRCLK I/O I S left right channel clock. PE.6 I/O General purpose digital I/O pin. PE.5 I/O General purpose digital I/O pin. PWM5 I/O PWM5 output/Capture input. 2 29 TM1_EXT I Timer1 external capture input pin. TM1 O Timer1 toggle output pin. PB.11 I/O General purpose digital I/O pin. TM3 I/O Timer3 event counter input / toggle output. PWM4 I/O PWM4 output/Capture input. PB.10 I/O General purpose digital I/O pin. TM2 I/O Timer2 event counter input / toggle output. SPI0_SS1 I/O 2 SPI0 slave select pin. PB.9 I/O General purpose digital I/O pin. TM1 I/O Timer1 event counter input / toggle output. SPI1_SS1 I/O 2 SPI1 slave select pin. 51 PE.4 I/O General purpose digital I/O pin. 52 PE.3 I/O General purpose digital I/O pin. 53 PE.2 I/O General purpose digital I/O pin. PE.1 I/O General purpose digital I/O pin. PWM7 I/O PWM7 output/Capture input. PE.0 I/O General purpose digital I/O pin. PWM6 I/O PWM6 output/Capture input. PC.13 I/O General purpose digital I/O pin. SPI1_MOSI1 I/O 2 SPI1 MOSI (Master Out, Slave In) pin. PC.12 I/O General purpose digital I/O pin. SPI1_MISO1 I/O 2 SPI1 MISO (Master In, Slave Out) pin. PC.11 I/O General purpose digital I/O pin. SPI1_MOSI0 I/O 1 SPI1 MOSI (Master Out, Slave In) pin. PC.10 I/O General purpose digital I/O pin. SPI1_MISO0 I/O 1 SPI1 MISO (Master In, Slave Out) pin. PC.9 I/O General purpose digital I/O pin. 48 30 31 49 nd 32 50 nd NUMICRO™ NUC230/240 DATASHEET 54 55 56 57 58 59 60 Dec. 30, 2014 33 34 35 nd nd st st Page 30 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin 61 62 LQFP 64-pin LQFP 48-pin 36 37 Pin Description Type SPI1_CLK I/O SPI1 serial clock pin. PC.8 I/O General purpose digital I/O pin. MCLK O EBI clock output SPI1_SS0 I/O 1 SPI1 slave select pin. PA.15 I/O General purpose digital I/O pin. PWM3 I/O PWM output/Capture input. I2S_MCLK O I S master clock output pin. SC2_PWR O SmartCard2 power pin. PA.14 I/O General purpose digital I/O pin. PWM2 I/O PWM2 output/Capture input. SC2_RST O SmartCard2 reset pin. AD15 I/O EBI Address/Data bus bit15 PA.13 I/O General purpose digital I/O pin. PWM1 I/O PWM1 output/Capture input. SC2_CLK O SmartCard2 clock pin. UART5_TXD O Data transmitter output pin for UART5. AD14 I/O EBI Address/Data bus bit14 PA.12 I/O General purpose digital I/O pin. PWM0 I/O PWM0 output/Capture input. SC2_DAT O SmartCard2 data pin. UART5_RXD I Data receiver input pin for UART5. 25 26 63 Pin Name st 2 38 27 64 39 65 40 AD13 I/O EBI Address/Data bus bit13 66 41 29 ICE_DAT I/O Serial wire debugger data pin. 67 42 30 ICE_CLK I Serial wire debugger clock pin. 68 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. 69 VSS P Ground pin for digital circuit. AVSS AP Ground pin for analog circuit. PA.0 I/O General purpose digital I/O pin. ADC0 AI ADC0 analog input. SC0_PWR O SmartCard0 power pin. PA.1 I/O General purpose digital I/O pin. ADC1 AI ADC1 analog input. 70 71 72 Dec. 30, 2014 43 44 45 31 32 33 Page 31 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET 28 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Description Type SC0_RST O SmartCard0 reset pin. AD12 I/O EBI Address/Data bus bit12 PA.2 I/O General purpose digital I/O pin. ADC2 AI ADC2 analog input. SC0_CLK O SmartCard0 clock pin. UART3_TXD O Data transmitter output pin for UART3. AD11 I/O EBI Address/Data bus bit11 PA.3 I/O General purpose digital I/O pin. ADC3 AI ADC3 analog input. SC0_DAT O SmartCard0 data pin. UART3_RXD I Data receiver input pin for UART3. 34 73 46 35 74 47 AD10 I/O EBI Address/Data bus bit10 PA.4 I/O General purpose digital I/O pin. ADC4 AI ADC4 analog input. AD9 I/O EBI Address/Data bus bit9 SC1_PWR O SmartCard1 power pin. PA.5 I/O General purpose digital I/O pin. ADC5 AI ADC5 analog input. AD8 I/O EBI Address/Data bus bit8 SC1_RST O SmartCard1 reset pin. PA.6 I/O General purpose digital I/O pin. ADC6 AI ADC6 analog input. AD7 I/O EBI Address/Data bus bit7 SC1_CLK I/O SmartCard1 clock pin. UART4_TXD O Data transmitter output pin for UART4. PA.7 I/O General purpose digital I/O pin. ADC7 AI ADC7 analog input. AD6 I/O EBI Address/Data bus bit6 SC1_DAT O SmartCard1 data pin. UART4_RXD I Data receiver input pin for UART4. 36 48 75 NUMICRO™ NUC230/240 DATASHEET 37 49 76 38 50 77 78 nd SPI2_SS1 I/O 2 SPI2 slave select pin. 79 51 39 VREF AP Voltage reference input for ADC. 80 52 40 AVDD AP Power supply for internal analog circuit. Dec. 30, 2014 Page 32 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Description Type PD.0 I/O General purpose digital I/O pin. SPI2_SS0 I/O 1 SPI2 slave select pin. PD.1 I/O General purpose digital I/O pin. SPI2_CLK I/O SPI2 serial clock pin. PD.2 I/O General purpose digital I/O pin. SPI2_MISO0 I/O 1 SPI2 MISO (Master In, Slave Out) pin. PD.3 I/O General purpose digital I/O pin. SPI2_MOSI0 I/O 1 SPI2 MOSI (Master Out, Slave In) pin. PD.4 I/O General purpose digital I/O pin. SPI2_MISO1 I/O 2 SPI2 MISO (Master In, Slave Out) pin. PD.5 I/O General purpose digital I/O pin. SPI2_MOSI1 I/O 2 SPI2 MOSI (Master Out, Slave In) pin. PC.7 I/O General purpose digital I/O pin. CMP0_N AI Comparator0 negative input pin. AD5 I/O EBI Address/Data bus bit5 81 st 82 83 84 85 86 st st nd nd 41 53 87 SC1_CD PC.6 I/O General purpose digital I/O pin. ACMP0_P AI Comparator0 positive input pin. 54 SC0_CD 89 90 SmartCard1 card detect pin. NUMICRO™ NUC230/240 DATASHEET 42 88 I 55 56 I SmartCard0 card detect pin. AD4 I/O EBI Address/Data bus bit4 PC.15 I/O General purpose digital I/O pin. AD3 I/O EBI Address/Data bus bit3 ACMP1_N AI Comparator1 negative input pin. PC.14 I/O General purpose digital I/O pin. AD2 I/O EBI Address/Data bus bit2 ACMP1_P AI Comparator1 positive input pin. PB.15 I/O General purpose digital I/O pin. INT1 I External interrupt1 input pin. TM0_EXT I Timer0 external capture input pin. TM0 O Timer0 toggle output pin. AD6 I/O EBI Address/Data bus bit6 PF.0 I/O General purpose digital I/O pin. XT1_OUT O External 4~24 MHz (high speed) crystal output pin. 43 91 92 Dec. 30, 2014 57 58 44 Page 33 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin 93 59 45 Pin Name PF.1 46 Pin Description Type I/O General purpose digital I/O pin. XT1_IN I External 4~24 MHz (high speed) crystal input pin. nRESET I External reset input: active LOW, with an internal pull-up. Set this pin low reset chip to initial state. 94 60 95 61 VSS P Ground pin for digital circuit. 96 62 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. PF.2 I/O General purpose digital I/O pin. PS2_DAT I/O PS2 data pin. PF.3 I/O General purpose digital I/O pin. PS2_CLK I/O PS2 clock pin. 97 98 99 63 47 PVSS P PB.8 I/O STADC 100 64 I PLL ground. General purpose digital I/O pin. ADC external trigger input. 48 TM0 I/O Timer0 event counter input / toggle output. CLKO O Frequency divider clock output pin. Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 34 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 4.3.2 NuMicro NUC240 Pin Description Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Description Type 1 PE.15 I/O General purpose digital I/O pin. 2 PE.14 I/O General purpose digital I/O pin. 3 PE.13 I/O General purpose digital I/O pin. PB.14 I/O General purpose digital I/O pin. AD0 I/O EBI Address/Data bus bit0 INT0 I 1 4 5 2 External interrupt0 input pin. nd SPI3_SS1 I/O 2 SPI3 slave select pin. PB.13 I/O General purpose digital I/O pin. AD1 I/O EBI Address/Data bus bit1 ACMP1_O O Comparator1 output pin. 6 3 1 VBAT P Power supply by batteries for RTC. 7 4 2 X32_OUT O External 32.768 kHz (low speed) crystal output pin. 8 5 3 X32_IN I External 32.768 kHz (low speed) crystal input pin. 9 11 12 General purpose digital I/O pin. I2C1_SCL I/O I C1 clock pin. 2 6 5 10 I/O NUMICRO™ NUC230/240 DATASHEET 4 PA.11 CAN1_RXD I Data receiver input pin for CAN1. nRD O EBI read enable output pin PA.10 I/O General purpose digital I/O pin. I2C1_SDA I/O I C1 data input/output pin. CAN1_TXD O Data transmitter output pin for CAN1. nWR O EBI write enable output pin PA.9 I/O General purpose digital I/O pin. I2C0_SCL I/O I C0 clock pin. PA.8 I/O General purpose digital I/O pin. I2C0_SDA I/O I C0 data input/output pin. PD.8 I/O General purpose digital I/O pin. SPI3_SS0 I/O 1 SPI3 slave select pin. PD.9 I/O General purpose digital I/O pin. SPI3_CLK I/O SPI3 serial clock pin. PD.10 I/O General purpose digital I/O pin. SPI3_MISO0 I/O 1 SPI3 MISO (Master In, Slave Out) pin. 2 7 8 9 6 7 13 2 2 st 14 15 Dec. 30, 2014 st Page 35 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Description Type PD.11 I/O General purpose digital I/O pin. SPI3_MOSI0 I/O 1 SPI3 MOSI (Master Out, Slave In) pin. PD.12 I/O General purpose digital I/O pin. SPI3_MISO1 I/O 2 SPI3 MISO (Master In, Slave Out) pin. PD.13 I/O General purpose digital I/O pin. SPI3_MOSI1 I/O 2 SPI3 MOSI (Master Out, Slave In) pin. PB.4 I/O General purpose digital I/O pin. 16 17 18 19 10 21 22 11 nd nd 8 UART1_RXD 20 st I Data receiver input pin for UART1. NUMICRO™ NUC230/240 DATASHEET PB.5 I/O General purpose digital I/O pin. UART1_TXD O Data transmitter output pin for UART1. PB.6 I/O General purpose digital I/O pin. ALE O EBI address latch enable output pin UART1_nRTS O Request to Send output pin for UART1. PB.7 I/O General purpose digital I/O pin. nCS O EBI chip select enable output pin UART1_nCTS I Clear to Send input pin for UART1. 9 12 13 23 14 10 LDO_CAP P LDO output pin. 24 15 11 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. 25 16 12 VSS P Ground pin for digital circuit. 26 PE.8 I/O General purpose digital I/O pin. 27 PE.7 I/O General purpose digital I/O pin. 28 17 13 USB_VBUS USB Power supply from USB host or HUB. 29 18 14 USB_VDD33_CAP USB Internal power regulator output 3.3V decoupling pin. 30 19 15 USB_D- USB USB differential signal D-. 31 20 16 USB_D+ USB USB differential signal D+. 32 21 17 PB.0 UART0_RXD 33 34 22 23 Dec. 30, 2014 I/O I General purpose digital I/O pin. Data receiver input pin for UART0. PB.1 I/O General purpose digital I/O pin. UART0_TXD O Data transmitter output pin for UART0. PB.2 I/O General purpose digital I/O pin. nWRL O EBI low byte write enable output pin UART0_nRTS O Request to Send output pin for UART0. 18 Page 36 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin 35 LQFP 64-pin LQFP 48-pin Pin Name TM2_EXT I Timer2 external capture input pin. TM2 O Timer2 toggle output pin. ACMP0_O O Comparator0 output pin. PB.3 I/O General purpose digital I/O pin. UART0_nCTS I Clear to Send input pin for UART0. nWRH O EBI high byte write enable output pin TM3_EXT I Timer3 external capture input pin. TM3 O Timer3 toggle output pin. SC2_CD I SmartCard2 card detect pin. 24 PD.6 36 25 38 I Data receiver input pin for CAN0. PD.7 I/O General purpose digital I/O pin. CAN0_TXD O Data transmitter output pin for CAN0. PD.14 I/O General purpose digital I/O pin. 20 27 28 UART2_RXD I Data receiver input pin for UART2. CAN1_RXD I Data receiver input pin for CAN1. PD.15 I/O General purpose digital I/O pin. UART2_TXD O Data transmitter output pin for UART2. CAN1_TXD O Data transmitter output pin for CAN1. PC.5 I/O General purpose digital I/O pin. SPI0_MOSI1 I/O 2 SPI0 MOSI (Master Out, Slave In) pin. PC.4 I/O General purpose digital I/O pin. SPI0_MISO1 I/O 2 SPI0 MISO (Master In, Slave Out) pin. PC.3 I/O General purpose digital I/O pin. SPI0_MOSI0 I/O 1 SPI0 MOSI (Master Out, Slave In) pin. I2S_DO O I S data output. PC.2 I/O General purpose digital I/O pin. SPI0_MISO0 I/O 1 SPI0 MISO (Master In, Slave Out) pin. 40 41 42 43 29 30 21 22 I2S_DI 44 31 Dec. 30, 2014 General purpose digital I/O pin. 23 NUMICRO™ NUC230/240 DATASHEET 39 26 I/O 19 CAN0_RXD 37 Pin Description Type nd nd st 2 st 2 I I S data input. PC.1 I/O General purpose digital I/O pin. SPI0_CLK I/O SPI0 serial clock pin. I2S_BCLK I/O I S bit clock pin. 2 Page 37 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin 45 LQFP 64-pin 32 46 47 LQFP 48-pin 24 Pin Name Pin Description Type PC.0 I/O General purpose digital I/O pin. SPI0_SS0 I/O 1 SPI0 slave select pin. I2S_LRCLK I/O I S left right channel clock. PE.6 I/O General purpose digital I/O pin. PE.5 I/O General purpose digital I/O pin. PWM5 I/O PWM5 output/Capture input. st 2 TM1_EXT I Timer1 external capture input pin. TM1 O Timer1 toggle output pin. PB.11 I/O General purpose digital I/O pin. TM3 I/O Timer3 event counter input / toggle output. PWM4 I/O PWM4 output/Capture input. PB.10 I/O General purpose digital I/O pin. TM2 I/O Timer2 event counter input / toggle output. SPI0_SS1 I/O 2 SPI0 slave select pin. PB.9 I/O General purpose digital I/O pin. TM1 I/O Timer1 event counter input / toggle output. SPI1_SS1 I/O 2 SPI1 slave select pin. 51 PE.4 I/O General purpose digital I/O pin. 52 PE.3 I/O General purpose digital I/O pin. 53 PE.2 I/O General purpose digital I/O pin. PE.1 I/O General purpose digital I/O pin. PWM7 I/O PWM7 output/Capture input. PE.0 I/O General purpose digital I/O pin. PWM6 I/O PWM6 output/Capture input. PC.13 I/O General purpose digital I/O pin. SPI1_MOSI1 I/O 2 SPI1MOSI (Master Out, Slave In) pin. PC.12 I/O General purpose digital I/O pin. SPI1_MISO1 I/O 2 SPI1 MISO (Master In, Slave Out) pin. PC.11 I/O General purpose digital I/O pin. SPI1_MOSI0 I/O 1 SPI1 MOSI (Master Out, Slave In) pin. PC.10 I/O General purpose digital I/O pin. SPI1_MISO0 I/O 1 SPI1 MISO (Master In, Slave Out) pin. 48 49 NUMICRO™ NUC230/240 DATASHEET 50 nd nd 54 55 56 57 58 59 33 34 Dec. 30, 2014 nd nd st st Page 38 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin LQFP 64-pin 60 35 61 LQFP 48-pin Pin Description Type PC.9 I/O General purpose digital I/O pin. SPI1_CLK I/O SPI1 serial clock pin. PC.8 I/O General purpose digital I/O pin. MCLK O EBI clock output SPI1_SS0 I/O 1 SPI1 slave select pin. PA.15 I/O General purpose digital I/O pin. PWM3 I/O PWM3 output/Capture input. I2S_MCLK O I S master clock output pin. SC2_PWR O SmartCard2 power pin. PA.14 I/O General purpose digital I/O pin. PWM2 I/O PWM2 output/Capture input. AD15 I/O EBI Address/Data bus bit15 SC2_RST O SmartCard2 reset pin. PA.13 I/O General purpose digital I/O pin. PWM1 I/O PWM1 output/Capture input. AD14 I/O EBI Address/Data bus bit14 SC2_CLK O SmartCard2 clock pin. UART5_TXD O Data transmitter output pin for UART5. PA.12 I/O General purpose digital I/O pin. PWM0 I/O PWM0 output/Capture input. AD13 I/O EBI Address/Data bus bit13 SC2_DAT O SmartCard2 data pin. 28 UART5_RXD I Data receiver input pin for UART5. 36 25 62 Pin Name 37 st 2 26 63 38 27 39 27 28 65 40 66 41 29 ICE_DAT I/O Serial wire debugger data pin. 67 42 30 ICE_CLK I Serial wire debugger clock pin. 68 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. 69 VSS P Ground pin for digital circuit. AVSS AP Ground pin for analog circuit. PA.0 I/O General purpose digital I/O pin. ADC0 AI ADC0 analog input. SC0_PWR O SmartCard0 power pin. PA.1 I/O General purpose digital I/O pin. 70 71 72 43 44 45 Dec. 30, 2014 31 32 33 Page 39 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET 64 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin Pin Name Pin Description Type ADC1 AI ADC1 analog input. SC0_RST O SmartCard0 reset pin. AD12 I/O EBI Address/Data bus bit12 PA.2 I/O General purpose digital I/O pin. ADC2 AI ADC2 analog input. SC0_CLK O SmartCard0 clock pin. UART3_TXD O Data transmitter output pin for UART3. AD11 I/O EBI Address/Data bus bit11 PA.3 I/O General purpose digital I/O pin. ADC3 AI ADC3 analog input. SC0_DAT O SmartCard0 data pin. UART3_RXD I Data receiver input pin for UART3. 34 73 46 35 74 47 AD10 I/O EBI Address/Data bus bit10 PA.4 I/O General purpose digital I/O pin. ADC4 AI ADC4 analog input. AD9 I/O EBI Address/Data bus bit9 SC1_PWR O SmartCard1 power pin. PA.5 I/O General purpose digital I/O pin. ADC5 AI ADC5 analog input. AD8 I/O EBI Address/Data bus bit8 SC1_RST O SmartCard1 reset pin. PA.6 I/O General purpose digital I/O pin. ADC6 AI ADC6 analog input. AD7 I/O EBI Address/Data bus bit7 SC1_CLK I/O SmartCard1 clock pin. UART4_TXD O Data transmitter output pin for UART4. PA.7 I/O General purpose digital I/O pin. ADC7 AI ADC7 analog input. AD6 I/O EBI Address/Data bus bit6 SC1_DAT O SmartCard1 data pin. UART4_RXD I Data receiver input pin for UART4. 36 48 75 NUMICRO™ NUC230/240 DATASHEET 37 49 76 38 50 77 78 SPI2_SS1 Dec. 30, 2014 I/O nd 2 SPI2 slave select pin. Page 40 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. Pin Name Pin Description Type LQFP 100-pin LQFP 64-pin LQFP 48-pin 79 51 39 VREF AP Voltage reference input for ADC. 80 52 40 AVDD AP Power supply for internal analog circuit. PD.0 I/O General purpose digital I/O pin. SPI2_SS0 I/O 1 SPI2 slave select pin. PD.1 I/O General purpose digital I/O pin. SPI2_CLK I/O SPI2 serial clock pin. PD.2 I/O General purpose digital I/O pin. SPI2_MISO0 I/O 1 SPI2 MISO (Master In, Slave Out) pin. PD.3 I/O General purpose digital I/O pin. SPI2_MOSI0 I/O 1 SPI2 MOSI (Master Out, Slave In) pin. PD.4 I/O General purpose digital I/O pin. SPI2_MISO1 I/O 2 SPI2 MISO (Master In, Slave Out) pin. PD.5 I/O General purpose digital I/O pin. SPI2_MOSI1 I/O 2nd SPI2 MOSI (Master Out, Slave In) pin. PC.7 I/O General purpose digital I/O pin. ACMP0_N AI Comparator0 negative input pin. AD5 I/O EBI Address/Data bus bit5 81 st 82 83 84 85 st st nd 86 41 SC1_CD 42 88 90 SmartCard1 card detect pin. PC.6 I/O General purpose digital I/O pin. ACMP0_P AI Comparator0 positive input pin. 54 SC0_CD 89 I NUMICRO™ NUC230/240 DATASHEET 53 87 55 56 I SmartCard0 card detect pin. AD4 I/O EBI Address/Data bus bit4 PC.15 I/O General purpose digital I/O pin. AD3 I/O EBI Address/Data bus bit3 ACMP1_N AI Comparator1 negative input pin. PC.14 I/O General purpose digital I/O pin. AD2 I/O EBI Address/Data bus bit2 ACMP1_P AI Comparator1 positive input pin. PB.15 I/O General purpose digital I/O pin. INT1 I External interrupt1 input pin. TM0_EXT I Timer 0 external capture input pin. TM0 O Timer0 toggle output pin. AD6 I/O EBI Address/Data bus bit6 43 91 57 Dec. 30, 2014 Page 41 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet Pin No. LQFP 100-pin LQFP 64-pin LQFP 48-pin 92 58 44 93 59 Pin Name Pin Description Type PF.0 I/O General purpose digital I/O pin. XT1_OUT O External 4~24 MHz (high speed) crystal output pin. PF.1 I/O General purpose digital I/O pin. 45 46 XT1_IN I External 4~24 MHz (high speed) crystal input pin. nRESET I External reset input: active LOW, with an internal pull-up. Set this pin low reset chip to initial state. 94 60 95 61 VSS P Ground pin for digital circuit. 96 62 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. PF.2 I/O General purpose digital I/O pin. PS2_DAT I/O PS/2 data pin. PF.3 I/O General purpose digital I/O pin. PS2_CLK I/O PS/2 clock pin. 97 98 99 63 47 PVSS P PB.8 I/O STADC 100 64 I PLL ground. General purpose digital I/O pin. ADC external trigger input. 48 NUMICRO™ NUC230/240 DATASHEET TM0 I/O Timer0 event counter input / toggle output. CLKO O Frequency divider clock output pin. Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power Dec. 30, 2014 Page 42 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 5 BLOCK DIAGRAM 5.1 NuMicro NUC230 Block Diagram Memory Timer/PWM Analog Interface 32-bit Timer x 4 APROM 128/64/32 KB ARM LDROM 8 KB PDMA Cortex-M0 72MHz Watchdog Timer DataFlash Configurable/ 4 KB SRAM 16/8 KB Bridge Power Control Clock Control LDO PLL APB Bus Connectivity I/O Ports UART x 3 General Purpose I/O SPI x 4 LVR High Speed Oscillator 22.1184 MHz High Speed Crystal Osc. 4 ~ 24 MHz Low Speed Oscillator 10 kHz Low Speed Crystal Osc. 32.768 KHz I2C x 2 External Interrupt I2S x 1 PS/2 x 1 Reset Pin SC (UART) x 3 NUMICRO™ NUC230/240 DATASHEET Brownout Detection Analog Comparator x2 PWM/Capture Timer x 8 AHB Bus Power On Reset 12-bit ADC x 8 RTC CAN x 2 Figure 5-1 NuMicro NUC230 Block Diagram Dec. 30, 2014 Page 43 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 5.2 NuMicro NUC240 Block Diagram Memory APROM 128/64/32 KB ARM LDROM 8 KB Analog Interface 32-bit Timer x 4 12-bit ADC x 8 RTC PDMA Cortex-M0 72MHz Timer/PWM USB PHY Watchdog Timer DataFlash Configurable/ 4 KB SRAM 16/8 KB PWM/Capture Timer x 8 Bridge AHB Bus Power Control Clock Control LDO PLL LVR NUMICRO™ NUC230/240 DATASHEET Brownout Detection APB Bus Connectivity I/O Ports UART x 3 General Purpose I/O SPI x 4 I2 C x 2 Power On Reset High Speed Oscillator 22.1184 MHz High Speed Crystal Osc. 4 ~ 24 MHz I2S x 1 Low Speed Crystal Osc. 32.768 KHz External Interrupt PS/2 x 1 SC (UART) x 3 Low Speed Oscillator 10 kHz Analog Comparator x2 Reset Pin USB CAN x 2 Figure 5-2 NuMicro NUC240 Block Diagram Dec. 30, 2014 Page 44 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6 FUNCTIONAL DESCRIPTION 6.1 ARM® Cortex™-M0 Core The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex™-M profile processor. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. Figure 6-1 shows the functional controller of processor. CortexTM-M0 Components CortexTM-M0 processor Nested Vectored Interrupt Controller (NVIC) Interrupts Wakeup Interrupt Controller (WIC) Debug CortexTM-M0 Processor Core Bus Matrix Breakpoint and Watchpoint Unit Debugger Interface Serial Wire or JTAG Debug Port Figure 6-1 Functional Controller Diagram The implemented device provides the following components and features:  Dec. 30, 2014 A low gate count processor: - ARMv6-M Thumb® instruction set - Thumb-2 technology - ARMv6-M compliant 24-bit SysTick timer - A 32-bit hardware multiplier - System interface supported with little-endian data accesses - Ability to have deterministic, fixed-latency, interrupt handling - Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling - C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers - Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature Page 45 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET AHB-Lite Interface Debug Access Port (DAP) NuMicro NUC230/240 Datasheet    NVIC: - 32 external interrupt inputs, each with four levels of priority - Dedicated Non-maskable Interrupt (NMI) input - Supports for both level-sensitive and pulse-sensitive interrupt lines - Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep mode Debug support - Four hardware breakpoints - Two watchpoints - Program Counter Sampling Register (PCSR) for non-intrusive code profiling - Single step and vector catch capabilities Bus interfaces: - Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory - Single 32-bit slave port that supports the DAP (Debug Access Port) NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 46 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.2 System Manager 6.2.1 Overview System management includes the following sections:  System Resets  System Memory Map  System management registers for Part Number ID, chip reset and on-chip controllers reset , multi-functional pin control  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System Control registers 6.2.2 System Reset The system reset can be issued by one of the following listed events. For these reset event flags can be read by RSTSRC register. Power-on Reset  Low level on the nRESET pin  Watchdog Time-out Reset  Low Voltage Reset  Brown-out Detector Reset  CPU Reset  System Reset System Reset and Power-on Reset all reset the whole chip including all peripherals. The difference between System Reset and Power-on Reset is external crystal circuit and BS(ISPCON[1]) bit. System Reset does not reset external crystal circuit and BS(ISPCON[1]) bit, but Power-on Reset does. Dec. 30, 2014 Page 47 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET  NuMicro NUC230/240 Datasheet 6.2.3 System Power Distribution In this chip, the power distribution is divided into three segments.  Analog power from AVDD and AVSS provides the power for analog components operation.  Digital power from VDD and VSS supplies the power to the internal regulator which provides a fixed 1.8 V power for digital operation and I/O pins.  USB transceiver power from VBUS offers the power for operating the USB transceiver.  Battery power from VBAT supplies the RTC and external 32.768 kHz crystal. The outputs of internal voltage regulators, LDO and VDD33, require an external capacitor which should be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level with the digital power (VDD). 錯誤! 找不到參照來源。Figure 6-2 shows the NuMicro NUC230 power distribution, and Figure 6-3 shows the NuMicro NUC240 power distribution. NUC230 Power Distribution AVDD 12-bit SAR-ADC AVSS Temperature Seneor Analog Comparator FLASH Digital Logic Brownout Detector Low Voltage Reset Internal 22.1184 MHz & 10 kHz Oscillator 1.8V 1.8V POR18 RTC LDO PLL IO cell GPIO VSS POR50 PVSS X32_IN External 32.768 kHz Crystal X32_UTO VBAT ULDO 1uF VDD NUMICRO™ NUC230/240 DATASHEET LDO_CAP Figure 6-2 NuMicro NUC230 Power Distribution Diagram Dec. 30, 2014 Page 48 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet AVDD 12-bit SAR-ADC AVSS NUC240 Power Distribution Analog Comparator Low Voltage Reset USB_DUSB_VDD33_CAP 3.3V Brownout Detector Temperature Seneor USB_D+ USB 1.1 Tranceiver 1uF 5V to 3.3V LDO FLASH USB_VBUS Internal 22.1184 MHz & 10 kHz Oscillator Digital Logic LDO_CAP 1.8V 1.8V LDO PLL IO cell GPIO VSS POR50 VDD RTC PVSS X32_IN External 32.768 kHz Crystal NUMICRO™ NUC230/240 DATASHEET X32_OUT VBAT ULDO 1uF POR18 Figure 6-3 NuMicro NUC240 Power Distribution Diagram Dec. 30, 2014 Page 49 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.2.4 System Memory Map The NuMicro NUC230/240 series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in the following table. The detailed register definition, memory space, and programming detailed will be described in the following sections for each on-chip peripheral. The NuMicro NUC230/240 series only supports little-endian data format. Address Space Token Controllers 0x0000_0000 – 0x0001_FFFF FLASH_BA FLASH Memory Space (128 KB) 0x2000_0000 – 0x2000_3FFF SRAM_BA SRAM Memory Space (16 KB) Flash and SRAM Memory Space AHB Controllers Space (0x5000_0000 – 0x501F_FFFF) 0x5000_0000 – 0x5000_01FF GCR_BA System Global Control Registers 0x5000_0200 – 0x5000_02FF CLK_BA Clock Control Registers 0x5000_0300 – 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers 0x5000_4000 – 0x5000_7FFF GPIO_BA GPIO Control Registers 0x5000_8000 – 0x5000_BFFF PDMA_BA Peripheral DMA Control Registers 0x5000_C000 – 0x5000_FFFF FMC_BA Flash Memory Control Registers 0x5001_0000 – 0x5001_03FF EBI_BA External Bus Interface Control Registers APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF) NUMICRO™ NUC230/240 DATASHEET 0x4000_4000 – 0x4000_7FFF WDT_BA Watchdog Timer Control Registers 0x4000_8000 – 0x4000_BFFF RTC_BA Real Time Clock (RTC) Control Register 0x4001_0000 – 0x4001_3FFF TMR01_BA Timer0/Timer1 Control Registers 0x4002_0000 – 0x4002_3FFF I2C0_BA I C0 Interface Control Registers 0x4003_0000 – 0x4003_3FFF SPI0_BA SPI0 with master/slave function Control Registers 0x4003_4000 – 0x4003_7FFF SPI1_BA SPI1 with master/slave function Control Registers 0x4004_0000 – 0x4004_3FFF PWMA_BA PWM0/1/2/3 Control Registers 0x4005_0000 – 0x4005_3FFF UART0_BA UART0 Control Registers 0x4006_0000 – 0x4006_3FFF USBD_BA USB 2.0 FS device Controller Registers 0x400D_0000 – 0x400D_3FFF ACMP_BA Analog Comparator Control Registers 0x400E_0000 – 0x400E_FFFF ADC_BA Analog-Digital-Converter (ADC) Control Registers 2 APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF) 0x4010_0000 – 0x4010_3FFF PS2_BA PS/2 Interface Control Registers 0x4011_0000 – 0x4011_3FFF TMR23_BA Timer2/Timer3 Control Registers 0x4012_0000 – 0x4012_3FFF I2C1_BA I C1 Interface Control Registers 0x4013_0000 – 0x4013_3FFF SPI2_BA SPI2 with master/slave function Control Registers 0x4013_4000 – 0x4013_7FFF SPI3_BA SPI3 with master/slave function Control Registers Dec. 30, 2014 2 Page 50 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 0x4014_0000 – 0x4014_3FFF PWMB_BA PWM4/5/6/7 Control Registers 0x4015_0000 – 0x4015_3FFF UART1_BA UART1 Control Registers 0x4015_4000 – 0x4015_7FFF UART2_BA UART2 Control Registers 0x4018_0000 – 0x4018_3FFF CAN0_BA CAN0 Bus Control Registers 0x4018_4000 – 0x4018_7FFF CAN1_BA CAN1 Bus Control Registers 0x4019_0000 – 0x4019_3FFF SC0_BA SC0 Control Registers 0x4019_4000 – 0x4019_7FFF SC1_BA SC1 Control Registers 0x4019_8000 – 0x4019_BFFF SC2_BA SC2 Control Registers 0x401A_0000 – 0x401A_3FFF I2S_BA I S Interface Control Registers 2 System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers Table 6-1 Address Space Assignments for On-Chip Controllers NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 51 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.2.5 System Timer (SysTick) The Cortex™-M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0 before enabling the feature. This ensures the timer will count from the SYST_RVR value rather than an arbitrary value when it is enabled. If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit. For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”. NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 52 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.2.6 Nested Vectored Interrupt Controller (NVIC) The Cortex™-M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor kernel and provides following features:  Nested and Vectored interrupt support  Automatic processor state saving and restoration  Reduced and deterministic interrupt latency The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Thus it will take less and deterministic time to process the interrupt request. For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”. Dec. 30, 2014 Page 53 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one without delay penalty. Thus it advances the real-time capability. NuMicro NUC230/240 Datasheet 6.2.6.1 Exception Model and System Interrupt Map The following table lists the exception model supported by NuMicro NUC230/240 series. Software can set four levels of priority on some of these exceptions as well as on all interrupts. The highest user-configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”. Exception Name Vector Number Priority Reset 1 -3 NMI 2 -2 Hard Fault 3 -1 Reserved 4 ~ 10 Reserved SVCall 11 Configurable Reserved 12 ~ 13 Reserved PendSV 14 Configurable SysTick 15 Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 6-2 Exception Model NUMICRO™ NUC230/240 DATASHEET Vector Number Interrupt Number (Bit In Interrupt Registers) Interrupt Name Source Module 1 ~ 15 - - - 16 0 BOD_INT Brown-out 17 1 WDT_INT WDT Watchdog Timer interrupt 18 2 EINT0 GPIO External signal interrupt from PB.14 pin 19 3 EINT1 GPIO External signal interrupt from PB.15 pin 20 4 GPAB_INT GPIO External signal interrupt from PA[15:0]/PB[13:0] 21 5 GPCDEF_INT GPIO External interrupt from PC[15:0]/PD[15:0]/PE[15:0]/PF[3:0] 22 6 PWMA_INT PWM0~3 PWM0, PWM1, PWM2 and PWM3 interrupt 23 7 PWMB_INT PWM4~7 PWM4, PWM5, PWM6 and PWM7 interrupt 24 8 TMR0_INT TMR0 Timer 0 interrupt 25 9 TMR1_INT TMR1 Timer 1 interrupt 26 10 TMR2_INT TMR2 Timer 2 interrupt 27 11 TMR3_INT TMR3 Timer 3 interrupt 28 12 UART02_INT UART0/2 29 13 UART1_INT UART1 30 14 SPI0_INT SPI0 Dec. 30, 2014 Interrupt Description System exceptions Brown-out low voltage detected interrupt UART0 and UART2 interrupt UART1 interrupt SPI0 interrupt Page 54 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 31 15 SPI1_INT SPI1 SPI1 interrupt 32 16 SPI2_INT SPI2 SPI2 interrupt 33 17 SPI3_INT SPI3 SPI3 interrupt 34 18 I2C0_INT I C0 35 19 I2C1_INT I C1 36 20 - - Reserved 37 21 - - Reserved 38 22 SC012_INT SC0/1/2 SC0, SC1 and SC2 interrupt 39 23 USB_INT USBD USB 2.0 FS Device interrupt 40 24 PS2_INT PS/2 41 25 ACMP_INT ACMP Analog Comparator interrupt 42 26 PDMA_INT PDMA PDMA interrupt 43 27 I2S_INT IS 44 28 PWRWU_INT CLKC Clock controller interrupt for chip wake-up from Powerdown state 45 29 ADC_INT ADC ADC interrupt 46 30 IRC_INT IRC IRC TRIM interrupt 47 31 RTC_INT RTC Real Time Clock interrupt 2 I C0 interrupt 2 I C1 interrupt 2 2 2 PS/2 interrupt 2 I S interrupt Table 6-3 System Interrupt Map NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 55 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.2.6.2 Vector Table When an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. Vector Table Word Offset 0 Vector Number Description SP_main – The Main stack pointer Exception Entry Pointer using that Vector Number Table 6-4 Vector Table Format 6.2.6.3 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt SetEnable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt. NUMICRO™ NUC230/240 DATASHEET NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution status of an Active interrupt. NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting four interrupts). The general registers associated with the NVIC are all accessible from a block of memory in the System Control Space and will be described in next section. 6.2.7 System Control The Cortex™-M0 status and operating mode control are managed by System Control Registers. Including CPUID, Cortex™-M0 interrupt priority and Cortex™-M0 power management can be controlled through these system control registers. For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”. Dec. 30, 2014 Page 56 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.3 Clock Controller 6.3.1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and clock divider. The chip enters Power-down mode when Cortex™-M0 core executes the WFI instruction only if the PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1. After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave Power-down mode. In the Power-down mode, the clock controller turns off the 4~24 MHz external high speed crystal oscillator and 22.1184 MHz internal high speed RC oscillator to reduce the overall system power consumption. The following figures show the clock generator and the overview of the clock source control. The clock generator consists of 5 clock sources as listed below:  32.768 kHz external low speed crystal oscillator (LXT)  4~24 MHz external high speed crystal oscillator (HXT)  Programmable PLL output clock frequency (PLL source can be selected from external 4~24 MHz external high speed crystal oscillator (HXT) or 22.1184 MHz internal high speed RC oscillator (HIRC)) (PLL FOUT)  22.1184 MHz internal high speed RC oscillator (HIRC)  10 kHz internal low speed RC oscillator (LIRC) NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 57 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet XTL32K_EN (PWRCON[1]) X32_OUT LXT 32.768 kHz LXT X32_IN XTL12M_EN (PWRCON[0]) XT1_OUT HXT 4~24 MHz HXT PLL_SRC (PLLCON[19]) XT1_IN 0 OSC22M_EN (PWRCON[2]) PLL PLL FOUT 1 22.1184 MHz HIRC HIRC OSC10K_EN(PWRCON[3]) LIRC 10 kHz LIRC NUMICRO™ NUC230/240 DATASHEET Legend: LXT = 32.768 kHz external low speed crystal oscillator HXT = 4~24 MHz external high speed crystal oscillator HIRC = 22.1184 MHz internal high speed RC oscillator LIRC = 10 kHz internal low speed RC oscillator Figure 6-4 Clock Generator Block Diagram Dec. 30, 2014 Page 58 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 22.1184 MHz 22.1184 MHz 111 10 kHz 4~24 MHz PLLFOUT 010 32.768 kHz 32.768 kHz 1/(HCLK_N+1) 000 22.1184 MHz HCLK HCLK 4~24 MHz PLLFOUT 32.768 kHz 4~24 MHz 1/2 111 1/2 011 1/2 010 001 4~24 MHz 000 10 kHz 22.1184 MHz HCLK 4~24 MHz PLLFOUT 4~24 MHz 4~24 MHz 10 00 HCLK PLLFOUT 4~24 MHz PLLFOUT 4~24 MHz CLKSEL3[5:4] CLKSEL3[3:2] CLKSEL3[1:0] 011 PWM 6-7 PWM 4-5 PWM 2-3 PWM 0-1 010 001 000 CLKSEL2[17:16] 10 kHz 11 WWDT CLKSEL2[11:4] CLKSEL1[31:28] 10 10 kHz HCLK 1/2048 11 10 01 WDT 22.1184 MHz PS2 CLKSEL1[1:0] 11 I2S 01 HCLK 00 PLLFOUT 1 SPI0-3 0 CLK_SEL1[7:4] 1/(UART_N+1) UART 0-2 1/(ADC_N+1) ADC 11 10 01 22.1184 MHz 00 HCLK 32.768 kHz 4~24 MHz HCLK SYST_CSR[2] 111 32.768 kHz CLKSEL1[3:2] 22.1184 MHz 1 SysTick 01 CLKSEL1[25:24] 22.1184 MHz CPUCLK FMC 10 kHz 11 BOD 10 FDIV 01 10 kHz 00 32.768 kHz 11 CLKSEL2[3:2] 1 RTC 0 CLKSEL2[18] 10 1/(SC2_N+1) SC 2 1/(SC1_N+1) SC 1 1/(SC0_N+1) SC 0 1/(USB_N+1) USB 01 00 PLLFOUT Figure 6-5 Clock Generator Global View Diagram Dec. 30, 2014 Page 59 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET PLLFOUT 22.1184 MHz 11 CLKSEL2[1:0] 22.1184 MHz 000 0 CLKSEL0[5:3] HCLK TMR 3 TMR 2 TMR 1 TMR 0 011 CLKSEL1[22:20] CLKSEL1[18:16] CLKSEL1[14:12] CLKSEL1[10:8] 32.768 kHz 22.1184 MHz ACMP I2C 0~1 CAN 0~1 001 0 32.768 kHz PCLK 010 1 PLLCON[19] 22.1184 MHz PDMA 101 External trigger 4~24 MHz HCLK 111 10 kHz CLKSEL0[2:0] 22.1184 MHz CPU 001 4~24 MHz 10 kHz CPUCLK 011 NuMicro NUC230/240 Datasheet 6.3.2 System Clock and SysTick Clock The system clock has 5 clock sources which were generated from clock generator block. The clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is shown in Figure 6-6. HCLK_S (CLKSEL0[2:0]) 22.1184 MHz 10 kHz PLLFOUT 32.768 kHz 4~24 MHz 111 011 CPUCLK 010 HCLK CPU 1/(HCLK_N+1) 001 HCLK_N (CLKDIV[3:0]) AHB PCLK APB 000 CPU in Power Down Mode Figure 6-6 System Clock Block Diagram The clock source of SysTick in Cortex™-M0 core can use CPU clock or external clock (SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block diagram is shown in Figure 6-7. STCLK_S (CLKSEL0[5:3]) NUMICRO™ NUC230/240 DATASHEET 22.1184 MHz HCLK 4~24 MHz 32.768 kHz 4~24 MHz 1/2 111 1/2 011 1/2 010 STCLK 001 000 Figure 6-7 SysTick Clock Control Block Diagram Dec. 30, 2014 Page 60 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.3.3 Power-down Mode Clock When chip enters Power-down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down mode. The clocks still kept active are listed below:   Clock Generator - 10 kHz internal low speed RC oscillator clock - 32.768 kHz external low speed crystal oscillator clock RTC/WDT/Timer/PWM Peripherals Clock (when 32.768 kHz external low speed crystal oscillator or 10 kHz intertnal low speed RC oscillator is adopted as clock source) NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 61 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.3.4 Frequency Divider Output This device is equipped with a power-of-2 frequency divider which is composed by16 chained divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider. The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]). When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0 to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low state and stay in low state. If DIVIDER1(FRQDIV[5]) is set to 1, the frequency divider clock (FRQDIV_CLK) will bypass power-of-2 frequency divider. The frequency divider clock will be output to CLKO pin directly. FRQDIV_S (CLKSEL2[3:2]) FDIV_EN(APBCLK[6]) 22.1184 MHz HCLK 11 FRQDIV_CLK 10 32.768 kHz 4~24 MHz 01 00 NUMICRO™ NUC230/240 DATASHEET Figure 6-8 Clock Source of Frequency Divider DIVIDER_EN (FRQDIV[4]) Enable divide-by-2 counter FRQDIV_CLK 1/2 1/22 FSEL (FRQDIV[3:0]) 16 chained divide-by-2 counter 1/23 …... 1/215 DIVIDER1 (FRQDIV[5]) 1/216 0000 0001 : : 1110 1111 16 to 1 MUX 0 CLKO 1 Figure 6-9 Frequency Divider Block Diagram Dec. 30, 2014 Page 62 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.4 Flash Memory Controller (FMC) 6.4.1 Overview The NuMicro NUC230/240 series has 128/64/32K bytes on-chip embedded Flash for application program memory (APROM) that can be updated through ISP procedure. The In-SystemProgramming (ISP) function enables user to update program memory when chip is soldered on PCB. After chip is powered on, Cortex™-M0 CPU fetches code from APROM or LDROM decided by boot select (CBS) in CONFIG0. By the way, the NuMicro NUC230/240 series also provides additional Data Flash for user to store some application dependent data. For 128K bytes APROM device, the Data Flash is shared with original 128K program memory and its start address is configurable in CONFIG1. For 64K/32K bytes APROM device, the Data Flash is fixed at 4KB. 6.4.2 Features Runs up to 50 MHz with zero wait cycle for continuous address read access and runs up to 72MHz with one wait cycle for continuous address read.  All embedded flash memory supports 512 bytes page erase  128/64/32 KB application program memory (APROM)  8KB In-System-Programming (ISP) loader program memory (LDROM)  4KB Data Flash for 64/32 KB APROM device  Configurable Data Flash size for 128KB APROM device  Configurable or fixed 4 KB Data Flash with 512 bytes page erase unit  Supports In-Application-Programming (IAP) to switch code between APROM and LDROM without reset  In-System-Programming (ISP) to update on-chip Flash Dec. 30, 2014 Page 63 of 97 NUMICRO™ NUC230/240 DATASHEET  Revision 1.01 NuMicro NUC230/240 Datasheet 6.5 External Bus Interface (EBI) 6.5.1 Overview The NuMicro NUC100 series LQFP-64 and LQFP-100 package equips an external bus interface (EBI) for access external device. To save the connections between external device and this chip, EBI supports address bus and data bus multiplex mode. And, address latch enable (ALE) signal is used to differentiate the address and data cycle. 6.5.2 Features External Bus Interface has the following functions:  Supports external devices with max. 64 KB size (8-bit data width)/128 KB (16-bit data width)  Supports variable external bus base clock (MCLK) which based on HCLK  Supports 8-bit or 16-bit data width  Supports variable data access time (tACC), address latch enable time (tALE) and address hold time (tAHD)  Supports address bus and data bus multiplex mode to save the address pins  Supports configurable idle cycle for different access condition: Write command finish (W2X), Read-to-Read (R2R) NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 64 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.6 General Purpose I/O (GPIO) 6.6.1 Overview The NuMicro NUC230/240 series has up to 84 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 84 pins are arranged in 6 ports named as GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. The GPIOA/B/C/D/E port has the maximum of 16 pins and GPIOF port has the maximum of 4 pins. Each of the 84 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each of I/O pins can be configured by software individually as input, output, opendrain or Quasi-bidirectional mode. After reset, the I/O mode of all pins are depending on Config0[10] setting. In Quasi-bidirectional mode, I/O pin has a very weak individual pull-up resistor which is about 110~300 K for VDD is from 5.0 V to 2.5 V. 6.6.2 Features  Four I/O modes: - Quasi-bidirectional - Push-Pull output - Open-Drain output - Input only with high impendence  TTL/Schmitt trigger input selectable by GPx_TYPE[15:0] in GPx_MFP[31:16]  I/O pin configured as interrupt source with edge/level setting  Configurable default I/O mode of all pins after reset by Config0[10] setting If Config[10] is 0, all GPIO pins in input tri-state mode after chip reset - If Config[10] is 1, all GPIO pins in Quasi-bidirectional mode after chip reset  I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode  Enabling the pin interrupt function will also enable the pin wake-up function. 6.7 PDMA Controller (PDMA) 6.7.1 Overview The NuMicro NUC230/240 series DMA contains nine-channel peripheral direct memory access (PDMA) controller and a cyclic redundancy check (CRC) generator. The PDMA that transfers data to and from memory or transfer data to and from APB devices. For PDMA channel (PDMA CH0~CH8), there is one-word buffer as transfer buffer between the Peripherals APB devices and Memory. Software can stop the PDMA operation by disable PDMA PDMACEN (PDMA_CSRx[0]). The CPU can recognize the completion of a PDMA operation by software polling or when it receives an internal PDMA interrupt. The PDMA controller can increase source or destination address or fixed them as well. The DMA controller contains a cyclic redundancy check (CRC) generator that can perform CRC calculation with programmable polynomial settings. The CRC engine supports CPU PIO mode and DMA transfer mode. Dec. 30, 2014 Page 65 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET - NuMicro NUC230/240 Datasheet 6.7.2 Features  Supports nine PDMA channels and one CRC channel. Each PDMA channel can support a unidirectional transfer  AMBA AHB master/slave interface compatible, for data transfer and register read/write  Hardware round robin priority scheme. DMA channel 0 has the highest priority and channel 8 has the lowest priority  PDMA operation  - Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer - Supports word/half-word/byte transfer data width from/to peripheral - Supports address direction: increment, fixed. Cyclic Redundancy Check (CRC) - Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32  CRC-CCITT: X16 + X12 + X5 + 1  CRC-8: X8 + X2 + X + 1  CRC-16: X16 + X15 + X2 + 1  CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 NUMICRO™ NUC230/240 DATASHEET - Supports programmable CRC seed value. - Supports programmable order reverse setting for input data and CRC checksum. - Supports programmable 1’s complement setting for input data and CRC checksum. - Supports CPU PIO mode or DMA transfer mode. - Supports the follows write data length in CPU PIO mode -  8-bit write mode (byte): 1-AHB clock cycle operation.  16-bit write mode (half-word): 2-AHB clock cycle operation.  32-bit write mode (word): 4-AHB clock cycle operation. Supports byte alignment transfer data length and word alignment transfer source address in CRC DMA mode. 6.8 Timer Controller (TIMER) 6.8.1 Overview The timer controller includes four 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. Dec. 30, 2014 Page 66 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.8.2 Features  Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter  Independent clock source for each timer  Provides four timer counting modes: one-shot, periodic, toggle and continuous counting  Time-out period = (Period of timer clock input) * (8-bit prescale counter + 1) * (24-bit TCMP)  Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock  24-bit up counter value is readable through TDR (Timer Data Register)  Supports event counting function to count the event from external counter pin (TM0~TM3)  Supports external pin capture (TM0_EXT~TM3_EXT) for interval measurement  Supports external pin capture (TM0_EXT~TM3_EXT) for reset 24-bit up counter  Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 67 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.9 PWM Generator and Capture Timer (PWM) 6.9.1 Overview The NuMicro NUC230/240 series has 2 sets of PWM group supporting a total of 4 sets of PWM generators that can be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4 complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6, PWM7) with 4 programmable Dead-zone generators. Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM counters for PWM period control, two 16-bit comparators for PWM duty control and one Dead-zone generator. The 4 sets of PWM generators provide eight independent PWM interrupt flags set by hardware when the corresponding PWM period down counter reaches 0. Each PWM interrupt source with its corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators can be configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode to output PWM waveform continuously. When DZEN01 (PCR[4]) is set, PWM0 and PWM1 perform complementary PWM paired function; the paired PWM period, duty and Dead-time are determined by PWM0 timer and Dead-zone generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and (PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2, 4 and 6, respectively. Refer to 錯誤! 找不到參照來源。 and 錯誤! 找不到參照來源。 for the architecture of PWM Timers. To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and 16-bit comparator are implemented with double buffer. When user writes data to counter/comparator buffer registers the updated value will be load into the 16-bit down counter/ comparator at the time down counter reaching 0. The double buffering feature avoids glitch at PWM outputs. NUMICRO™ NUC230/240 DATASHEET When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM-timer is set as auto-reload mode, when the down counter reaches 0, it is reloaded with PWM Counter Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set as oneshot mode, the down counter will stop and generate one interrupt request when it reaches 0. The value of PWM counter comparator is used for pulse high width modulation. The counter control logic changes the output to high level when down-counter value matches the value of compare register. The alternate feature of the PWM-timer is digital input Capture function. If Capture function is enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc. Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR) when input channel has a rising transition and latched PWM-counter to Capture Falling Latch Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is programmable by setting CRL_IE0 (CCR0[1]) (Rising latch Interrupt enable) and CFL_IE0 (CCR0[2]) (Falling latch Interrupt enable) to decide the condition of interrupt occur. Capture channel 1 has the same feature by setting CRL_IE1 (CCR0[17]) and CFL_IE1 (CCR0[18]). And capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3, the PWM counter 0/1/2/3 will be reload at this moment. The maximum captured frequency that PWM can capture is confined by the capture interrupt latency. When capture interrupt occurred, software will do at least three steps, including: Read PIIR to get interrupt source and Read CRLRx/CFLRx(x=0~3) to get capture value and finally write 1 to clear PIIR to 0. If interrupt latency will take time T0 to finish, the capture signal mustn’t transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For Dec. 30, 2014 Page 68 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet example: HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns So the maximum capture frequency will be 1/900ns ≈ 1000 kHz 6.9.2 Features 6.9.2.1 PWM Function:  Up to 2 PWM groups (PWMA/PWMB) to support 8 PWM channels or 4 complementary PWM paired channels  Each PWM group has two PWM generators with each PWM generator supporting one 8-bit prescaler, two clock divider, two PWM-timers, one Dead-zone generator and two PWM outputs.  Up to 16-bit resolution  PWM Interrupt request synchronized with PWM period  One-shot or Auto-reload mode  Edge-aligned type or Center-aligned type option  PWM trigger ADC start-to-conversion 6.9.2.2 Capture Function: Timing control logic shared with PWM Generators  Supports 8 Capture input channels shared with 8 PWM output channels  Each channel supports one rising latch register (CRLR), one falling latch register (CFLR) and Capture interrupt flag (CAPIFx) Dec. 30, 2014 Page 69 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET  NuMicro NUC230/240 Datasheet 6.10 Watchdog Timer (WDT) 6.10.1 Overview The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up system from Idle/Power-down mode. 6.10.2 Features  18-bit free running up counter for Watchdog Timer time-out interval.  Selectable time-out interval (24 ~ 218) WDT_CLK cycle and the time-out interval period is 104 ms ~ 26.3168 s if WDT_CLK = 10 kHz.  System kept in reset state for a period of (1 / WDT_CLK) * 63  Supports Watchdog Timer reset delay period - Selectable it includes (1026、130、18 or 3) * WDT_CLK reset delay period.  Supports to force Watchdog Timer enabled after chip powered on or reset while CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0.  Supports Watchdog Timer time-out wake-up function only if WDT clock source is selected as 10 kHz NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 70 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.11 Window Watchdog Timer (WWDT) 6.11.1 Overview The Window Watchdog Timer is used is to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.11.2 Features  6-bit down counter value (WWDTVAL[5:0]) and 6-bit compare window value (WWDTCR[21:16]) to make the WWDT time-out window period flexible  Supports 4-bit value to programmable maximum 11-bit prescale counter period of WWDT counter 6.12 Real Time Clock (RTC) 6.12.1 Overview The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers programmable time tick and alarm match interrupts. The data format of time and calendar messages are expressed in BCD format. A digital frequency compensation feature is available to compensate external crystal oscillator frequency accuracy. The RTC controller also offers 80 bytes spare registers to store user’s important information.  Supports real time counter in Time Loading Register (TLR) (hour, minute, second) and calendar counter in Calendar Loading Register (CLR) (year, month, day) for RTC time and calendar check  Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in Time Alarm Register (TAR) and Calendar Alarm Register (CAR) register  Selectable 12-hour or 24-hour time scale in Time Scale Selection Register (TSSR) register  Supports Leap Year indication in Leap Year Indicator Register (LIR) register  Supports Day of the Week counter in Day of the Week Register (DWR) register  Frequency of RTC clock source compensate by RTC Frequency Compensation Register (FCR) register  All time and calendar message expressed in BCD format  Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second  Supports RTC Time Tick and Alarm Match interrupt  Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is generated  Supports 80 bytes spare registers Dec. 30, 2014 Page 71 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET 6.12.2 Features NuMicro NUC230/240 Datasheet 6.13 UART Interface Controller (UART) 6.13.1 Overview The NuMicro NUC230/240 series provides up to three channels of Universal Asynchronous Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform Normal Speed UART. Besides, only UART0 and UART1 support the flow control function. The UART Controller performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU. The UART controller also supports IrDA SIR Function, LIN master/slave function and RS-485 function mode. Each UART Controller channel supports seven types of interrupts. 6.13.2 Features NUMICRO™ NUC230/240 DATASHEET  Full duplex, asynchronous communications  Separates receive / transmit 64/16/16 bytes (UART0/UART1/UART2) entry FIFO for data payloads  Supports hardware auto flow control/flow control function (CTS, RTS) and programmable RTS flow control trigger level (UART0 and UART1 support)  Programmable receiver buffer trigger level  Supports programmable baud-rate generator for each channel individually  Supports CTS wake-up function (UART0 and UART1 support)  Supports 7-bit receiver buffer time-out detection function  UART0/UART1 can through DMA channels to receive/transmit data  Programmable transmitting data delay time between the last stop and the next start bit by setting UA_TOR [DLY] register  Supports break error, frame error, parity error and receive / transmit buffer overflow detect function  Fully programmable serial-interface characteristics  - Programmable data bit length, 5-, 6-, 7-, 8-bit character - Programmable parity bit, even, odd, no parity or stick parity bit generation and detection - Programmable stop bit length, 1, 1.5, or 2 stop bit generation IrDA SIR function mode -   Dec. 30, 2014 Supports 3-/16-bit duration for normal mode LIN function mode - Supports LIN master/slave mode - Supports programmable break generation function for transmitter - Supports break detect function for receiver RS-485 function mode. - Supports RS-485 9-bit mode - Supports hardware or software direct enable control provided by RTS pin (UART0 and UART1 support) Page 72 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.14 Smart Card Host Interface (SC) 6.14.1 Overview The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully compliant with PC/SC Specifications. It also provides status of card insertion/removal. It also support UART mode for full duplex asynchronous communications. 6.14.2 Features  Dec. 30, 2014 - ISO7816-3 T=0, T=1 compliant - EMV2000 compliant - Separates receive/ transmit 4 byte entry FIFO for data payloads. - Programmable transmission clock frequency. - Programmable receiver buffer trigger level. - Programmable guard time selection (11 ETU ~ 267 ETU). - A 24-bit and two 8-bit times for Answer to Request (ATR) and waiting times processing. - Supports auto inverse convention function. - Supports transmitter and receiver error retry and error number limiting function. - Supports hardware activation sequence, hardware warm reset sequence and hardware deactivation sequence process. - Supports hardware auto deactivation sequence when detecting the card removal. Supports up to three UART ports (UART3, UART4, UART5) - Full duplex, asynchronous communications. - Programmable data bit length, 5-, 6-, 7-, 8-bit character. - Separates receiving / transmitting 4 bytes entry FIFO for data payloads. - Supports programmable baud rate generator for each channel. - Supports programmable receiver buffer trigger level. - Programmable transmitting data delay time between the last stop bit leaving the TX-FIFO and the de-assertion by setting SCx_EGTR [EGT] register. - Programmable even, odd or no parity bit generation and detection. - Programmable stop bit, 1 or 2 stop bit generation. Page 73 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET  Supports up to three ISO7816-3 ports (SC0, SC1 and SC2) NuMicro NUC230/240 Datasheet 6.15 PS/2 Device Controller (PS2D) 6.15.1 Overview PS/2 device controller provides a basic timing control for PS/2 communication. All communication between the device and the host is managed through the PS2_CLK and PS2_DATA pins. Unlike PS/2 keyboard or mouse device controller, the receive/transmit code needs to be translated as meaningful code by firmware. The device controller generates the PS2_CLK signal after receiving a “Request to Send” state, but host has ultimate control over communication. Data of PS2_DATA line sent from the host to the device is read on the rising edge and sent from the device to the host is change after rising edge. A 16 bytes FIFO is used to reduce CPU intervention. Software can select 1 to 16 bytes for a continuous transmission. 6.15.2 Features  Host communication inhibit and "Request-to-Send" state detection  Reception frame error detection  Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention  Double buffer for data reception  Software override bus NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 74 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.16 I2C Serial Interface Controller (I2C) 6.16.1 Overview I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. 6.16.2 Features The I2C bus uses two wires (I2Cn_SDA and I2Cn_SCL) to transfer information between devices connected to the bus. The main features of the I2C bus include: Supports up to two I2C serial interface controller  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allow devices with different bit rates to communicate via one serial bus  Built-in a 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows.  Programmable clocks allow for versatile rate control  Supports 7-bit addressing mode  Supports multiple address recognition ( four slave address with mask option)  Supports Power-down wake-up function 6.17 Serial Peripheral Interface (SPI) 6.17.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bidirection interface. The NuMicro NUC230/240 series contains up to four sets of SPI controllers performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller can be configured as a master or a slave device. The SPI controller supports the variable bus clock function for special applications and 2-bit Transfer mode to connect 2 off-chip slave devices at the same time. This controller also supports the PDMA function to access the data buffer and also supports Dual I/O Transfer mode. Dec. 30, 2014 Page 75 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET  NuMicro NUC230/240 Datasheet 6.17.2 Features  Up to four sets of SPI controllers  Supports Master or Slave mode operation  Supports 2-bit Transfer mode  Supports Dual I/O Transfer mode  Configurable bit length of a transaction word from 8 to 32 bits  Provides separate 8-layer depth transmit and receive FIFO buffers  Supports MSB first or LSB first transfer sequence  Two slave select lines in Master mode  Supports the Byte Reorder function  Supports Byte or Word Suspend mode  Variable output bus clock frequency in Master mode  Supports PDMA transfer  Supports 3-wire, no slave select signal, bi-direction interface 6.18 I2S Controller (I2S) 6.18.1 Overview NUMICRO™ NUC230/240 DATASHEET The I2S controller consists of I2S protocol to interface with external audio CODEC. Two 8-word depth FIFO for reading path and writing path respectively and is capable of handling 8-, 16-, 24and 32-bit word sizes. PDMA controller handles the data movement between FIFO and memory. 6.18.2 Features  Supports Master mode and Slave mode  Capable of handling 8-, 16-, 24- and 32-bit word sizes  Supports monaural and stereo audio data  Supports I2S and MSB justified data format  Provides two 8-word FIFO data buffers, one for transmitting and the other for receiving  Supports PDMA transfer Dec. 30, 2014 Page 76 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 6.19 USB Device Controller (USBD) 6.19.1 Overview There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/ isochronous transfer types. In this device controller, there are two main interfaces: the APB bus and USB bus which comes from the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set the effective starting address of SRAM for each endpoint buffer through “buffer segmentation register (USB_BUFSEGx)”. There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are implemented in this block. The block of “Endpoint Control” is also used to manage the data sequential synchronization, endpoint states, current start address, transaction status, and data buffer status for each endpoint. There are four different interrupt events in this controller. They are the wake-up function, device plug-in or plug-out event, USB events, and BUS events. Any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of interrupt occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to acknowledge what kind of event occurring in this endpoint. Please refer to Universal Serial Bus Specification Revision 1.1 for details. 6.19.2 Features  Compliant with USB 2.0 Full-Speed specification  Provides 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB and BUS)  Supports Control/Bulk/Interrupt/Isochronous transfer type  Supports suspend function when no bus activity existing for 3 ms  Provides 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and maximum 512 bytes buffer size  Provides remote wake-up capability Dec. 30, 2014 Page 77 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET A software-disconnect function is also supported for this USB controller. It is used to simulate the disconnection of this device from the host. If DRVSE0 (USB_DRVSE0[0]) is set to 1, the USB controller will force the output of USB_D+ and USB_D- to level low. After DRVSE0 bit is cleared to 0, host will enumerate the USB device again. NuMicro NUC230/240 Datasheet 6.20 Controller Area Network (CAN) 6.20.1 Overview The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and Module Interface (Refer 錯誤! 找不到參照來源。). The CAN Core performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the physical layer, additional transceiver hardware is required. For communication on a CAN network, individual Message Objects are configured. The Message Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message RAM. All functions concerning the handling of messages are implemented in the Message Handler. These functions include acceptance filtering, the transfer of messages between the CAN Core and the Message RAM, and the handling of transmission requests as well as the generation of the module interrupt. The register set of the C_CAN can be accessed directly by the software through the module interface. These registers are used to control/configure the CAN Core and the Message Handler and to access the Message RAM. 6.20.2 Features NUMICRO™ NUC230/240 DATASHEET  Supports CAN protocol version 2.0 part A and B.  Bit rates up to 1 MBit/s.  32 Message Objects.  Each Message Object has its own identifier mask.  Programmable FIFO mode (concatenation of Message Objects).  Maskable interrupt.  Disabled Automatic Re-transmission mode for Time Triggered CAN applications.  Programmable loop-back mode for self-test operation.  16-bit module interfaces to the AMBA APB bus.  Supports wake-up function 6.21 Analog-to-Digital Converter (ADC) 6.21.1 Overview The NuMicro NUC230/240 series contains one 12-bit successive approximation analog-todigital converters (SAR A/D converter) with 8 input channels. The A/D converter supports three operation modes: single, single-cycle scan and continuous scan mode. The A/D converter can be started by software, PWM Center-aligned trigger and external STADC pin. 6.21.2 Features  Analog input voltage range: 0~VREF  12-bit resolution and 10-bit accuracy is guaranteed  Up to 8 single-end analog input channels or 4 differential analog input channels Dec. 30, 2014 Page 78 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet  Up to 1 MSPS conversion rate (chip working at 5V)  Three operating modes  - Single mode: A/D conversion is performed one time on a specified channel - Single-cycle scan mode: A/D conversion is performed one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel - Continuous scan mode: A/D converter continuously performs Single-cycle scan mode until software stops A/D conversion An A/D conversion can be started by: - Writing 1 to ADST bit (ADCR[11])through software - PWM Center-aligned trigger - External pin STADC  Conversion results are held in data registers for each channel with valid and overrun indicators  Supports two set digital comparators. The conversion result can be compared with specify value and user can select whether to generate an interrupt when conversion result matches the compare register setting  Channel 7 supports 3 input sources: external analog voltage, internal Band-gap voltage, and internal temperature sensor output 6.22 Analog Comparator (ACMP) The NuMicro NUC230/240 series contains two comparators which can be used in a number of different configurations. The comparator output is logic 1 when positive input voltage is greater than negative input voltage; otherwise the output is logic 0. Each comparator can be configured to generate interrupt request when the comparator output value changes. The block diagram is shown in 錯誤! 找不到參照來源。. 6.22.2 Features  Analog input voltage range: 0~ VDDA (Voltage of AVDD pin)  Supports Hysteresis function  Optional internal reference voltage source for each comparator negative input Dec. 30, 2014 Page 79 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET 6.22.1 Overview NuMicro NUC230/240 Datasheet 7 APPLICATION CIRCUIT DVCC [1] AVCC SPISS0 SPICLK0 MISO_0 AVDD DVCC Power FB VDD CS CLK MISO MOSI MOSI_0 VDD SPI Device VSS 0.1uF 0.1uF VSS DVCC FB DVCC AVSS 4.7K 4.7K CLK SCL0 VDD ICE_CLK ICE_DAT nRST VSS SWD Interface SDA0 DIO Crystal I2C Device VSS Smart Card VCC 20p XTAL1 VDD NUC2xx Series SC_PWR 4~24 MHz crystal 20p XTAL2 Smart Card Slot SC_RST SC_CLK SC_DAT SC_Detect DVCC CAN Transceiver Reset Circuit 10K nRST CAN_TX D CAN_H CAN_RX R CAN_L ODB Port CAN NUMICRO™ NUC230/240 DATASHEET 10uF/25V RS232 Transceiver LDO_CAP RXD ROUT TXD TIN PC COM Port RIN TOUT UART 1uF LDO Dec. 30, 2014 Note: For the SPI device, the chip supply voltage must be equal to SPI device working voltage. For example, when the SPI Flash working voltage is 3.3 V, the M05xx chip supply voltage must also be 3.3V. Page 80 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 8 ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings SYMBOL PARAMETER MIN. MAX UNIT VDDVSS -0.3 +7.0 V Battery Power Supply VBAT +2.4 +5.0 V Input Voltage VIN VSS-0.3 VDD+0.3 V 1/tCLCL 4 24 MHz Operating Temperature TA -40 +105 C Storage Temperature TST -55 +150 C - 120 mA Maximum Current out of VSS 120 mA Maximum Current sunk by a I/O pin 35 mA Maximum Current sourced by a I/O pin 35 mA Maximum Current sunk by total I/O pins 100 mA Maximum Current sourced by total I/O pins 100 mA DC Power Supply Oscillator Frequency Maximum Current into VDD Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device. NUMICRO™ NUC230/240 DATASHEET Dec. 30, 2014 Page 81 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet 8.2 DC Electrical Characteristics (VDD-VSS=5.5 V, TA = 25C, FOSC = 50 MHz unless otherwise specified.) SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. Operation Voltage Power Ground VDD VSS AVSS TYP. 2.5 MAX. UNIT 5.5 V -0.3 VDD = 2.5V ~ 5.5V up to 72 MHz V LDO Output Voltage VLDO 1.62 1.8 1.98 V VDD > 2.5V Band-gap Voltage VBG 1.22 1.25 1.28 V VDD = 2.5 V ~ 5.5 V, TA = 25C Analog Operating Voltage AVDD V When system used analog function, please refer to NUC230/240 Series Technical Reference Manual chapter 6.5 for corresponding analog operating voltage RTC Operating Voltage VBAT Operating Current IDD1 VDD 2.5 5.5 50 V HXT HIRC PLL All digital module 5.5V 12 MHz X V V mA Normal Run Mode NUMICRO™ NUC230/240 DATASHEET VDD at 72 MHz IDD2 20 mA 5.5V 12 MHz X V X IDD3 48 mA 3.3V 12 MHz X V V IDD4 18 mA 3.3V 12 MHz X V X IDD5 34 mA 5.5V 12 MHz X V V IDD6 15 mA 5.5V 12 MHz X V X while(1){} executed from flash IDD7 32 mA 3.3V 12 MHz X V V VLDO =1.8 V IDD8 14 mA 3.3V 12 MHz X V X Operating Current IDD9 8.5 mA 5.5V 12 MHz X X V IDD10 3.6 mA 5.5V 12 MHz X X X while(1){} executed from flash IDD11 7.5 mA 3.3V 12 MHz X X V VLDO =1.8 V IDD12 2.6 mA 3.3V 12 MHz X X X Operating Current IDD13 3.6 mA 5.5V 4 MHz X X V IDD14 2 mA 5.5V 4 MHz X X X while(1){} executed from flash IDD15 2.8 mA 3.3V 4 MHz X X V VLDO =1.8 V IDD16 1.2 mA 3.3V 4 MHz X X X while(1){} executed from flash VLDO =1.8 V Operating Current Normal Run Mode at 50 MHz Normal Run Mode at 12 MHz Normal Run Mode at 4 MHz Dec. 30, 2014 Page 82 of 97 Revision 1.01 NuMicro NUC230/240 Datasheet SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. Operating Current IDD17 TYP. 141 MAX. UNIT A Normal Run Mode at 32.768 kHz while(1){} executed from flash VDD LXT (kHz) HIRC PLL All digital module 5.5V 32.768 X X V IDD18 129 A 5.5V 32.768 X X X IDD19 138 A 3.3V 32.768 X X V IDD20 125 A 3.3V 32.768 X X X 125 A PLL IDD21 All digital module VLDO =1.8 V Operating Current Normal Run Mode at 10 kHz while(1){} executed from flash VDD HXT/LXT LIRC (kHz) 5.5V X 10 X V IDD22 120 A 5.5V X 10 X X IDD23 125 A 3.3V X 10 X V IDD24 120 A 3.3V X 10 X X VDD HXT HIRC PLL All digital module 5.5V 12 MHz X V V VLDO =1.8 V Operating Current IIDLE1 42 mA Idle Mode IIDLE2 11 mA 5.5V 12 MHz X V X VLDO =1.8 V IIDLE3 41 mA 3.3V 12 MHz X V V IIDLE4 9 mA 3.3V 12 MHz X V X IIDLE5 28 mA 5.5V 12 MHz X V V Idle Mode IIDLE6 10 mA 5.5V 12 MHz X V X at 50 MHz IIDLE7 27 mA 3.3V 12 MHz X V V IIDLE8 9 mA 3.3V 12 MHz X V X IIDLE9 7.5 mA 5.5V 12 MHz X X V IIDLE10 2.4 mA 5.5V 12 MHz X X X IIDLE11 6.5 mA 3.3V 12 MHz X X V IIDLE12 1.5 mA 3.3V 12 MHz X X X IIDLE13 3.3 mA 5.5V 4 MHz X X V IIDLE14 1.7 mA 5.5V 4 MHz X X X IIDLE15 2.4 mA 3.3V 4 MHz X X V IIDLE16 0.8 mA 3.3V 4 MHz X X X VDD LXT (kHz) HIRC PLL All digital module 5.5V 32.768 X X V 5.5V 32.768 X X X Operating Current VLDO =1.8 V Operating Current Idle Mode at 12 MHz VLDO =1.8 V Operating Current Idle Mode at 4 MHz VLDO =1.8 V Operating Current Idle Mode IIDLE17 133 A at 32.768 kHz VLDO =1.8 V Dec. 30, 2014 IIDLE18 120 A Page 83 of 97 Revision 1.01 NUMICRO™ NUC230/240 DATASHEET at 72 MHz NuMicro NUC230/240 Datasheet SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IIDLE19 133 A 3.3V 32.768 X X V IIDLE20 120 A 3.3V 32.768 X X X 122 A PLL IIDLE21 All digital module Operating Current Idle Mode VDD HXT/LXT LIRC (kHz) 5.5V X 10 X V IIDLE22 118 A 5.5V X 10 X X IIDLE23 122 A 3.3V X 10 X V IIDLE24 118 A 3.3V X 10 X X LXT (kHz) RTC RAM retension at 10 kHz IPWD1 A 15 Standby Current Power-down Mode VDD HXT/HIRC PLL 5.5V X X X V IPWD2 15 A 5.5V X X X V IPWD3 17 A 3.3V X 32.768 V V IPWD4 17 A 3.3V X 32.768 V V IVBAT 1.6 A VBAT= 3.0V, RTC enabled Input Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional mode) IIN1 -50 -60 A VDD = 5.5V, VIN = 0V or VIN=VDD Input Current at [1] /RESET IIN2 -55 -45 -30 A VDD = 3.3V, VIN = 0.45V Input Leakage Current PA, PB, PC, PD, PE, PF ILK -2 - +2 A VDD = 5.5V, 0
NUC240VE3AE 价格&库存

很抱歉,暂时无法提供与“NUC240VE3AE”相匹配的价格&库存,您可以联系我们找货

免费人工找货