XEF232-1024-FB374-I40

PRELIMINARY XEF232-1024-FB374 Datasheet 2015/08/27 XMOS © 2015, All Rights Reserved Document Number: X009587, PRELIMINARY XEF232-1024-FB374 Datasheet 1 Table of Contents 1 xCORE Multicore Microcontrollers . . . . . 2 XEF232-1024-FB374 Features . . . . . . . 3 Pin Configuration . . . . . . . . . . . . . . 4 Signal Description . . . . . . . . . . . . . . 5 Example Application Diagram . . . . . . . 6 Product Overview . . . . . . . . . . . . . . 7 PLL . . . . . . . . . . . . . . . . . . . . . . . 8 Boot Procedure . . . . . . . . . . . . . . . . 9 Memory . . . . . . . . . . . . . . . . . . . . 10 USB PHY . . . . . . . . . . . . . . . . . . . . 11 RGMII . . . . . . . . . . . . . . . . . . . . . 12 JTAG . . . . . . . . . . . . . . . . . . . . . . 13 Board Integration . . . . . . . . . . . . . . 14 DC and Switching Characteristics . . . . . 15 Package Information . . . . . . . . . . . . 16 Ordering Information . . . . . . . . . . . . Appendices . . . . . . . . . . . . . . . . . . . . . A Configuration of the XEF232-1024-FB374 B Processor Status Configuration . . . . . . C Tile Configuration . . . . . . . . . . . . . . D Node Configuration . . . . . . . . . . . . . E USB Node Configuration . . . . . . . . . . F USB PHY Configuration . . . . . . . . . . . G Device Errata . . . . . . . . . . . . . . . . . H JTAG, xSCOPE and Debugging . . . . . . . I Schematics Design Check List . . . . . . . J PCB Layout Design Check List . . . . . . . K Associated Design Documentation . . . . L Related Documentation . . . . . . . . . . . M Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 5 6 12 13 16 17 18 19 20 22 23 27 31 32 33 33 36 47 55 63 65 72 72 74 77 78 78 79 TO OUR VALUED CUSTOMERS It is our intention to provide you with accurate and comprehensive documentation for the hardware and software components used in this product. To subscribe to receive updates, visit http://www.xmos.com/. XMOS Ltd. is the owner or licensee of the information in this document and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes no representation that the information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. XMOS and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries, and may not be used without written permission. Company and product names mentioned in this document are the trademarks or registered trademarks of their respective owners. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet I/O pins xTIME scheduler Hardware response ports 1 PLL JTAG xTIME scheduler 2 I/O pins Hardware response ports xCORE logical Microcontrollers core xCORE logical core xCORE Multicore xCORE logical core xCORE logical core xCONNECT Switch ThexCORE xCORE-200 of 32-bit multicore microconlogical core Series is a comprehensive xCORE logical core range FLASH trollers that brings the low latency and timing determinism of the xCORE architeclogical core xCORE logical coreUnlike conventional microcontrollers, turexCORE to mainstream embedded applications. xCORE multicore microcontrollers execute multiple real-time tasks simultaneously xCORE logical core xCORE logical core and communicate between tasks using a high speed network. Because xCORE xCORE logical core xCORE logical core multicore microcontrollers are completely deterministic, you can write software to implement functions that traditionally require USB RGMII dedicated hardware. USB SRAM OTP OTP SRAM SRAM OTP OTP SRAM xCORE logical core Figure 1: XEF232-1024FB374 block diagram RGMII xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core I/O pins xTIME scheduler Hardware response ports FLASH xCORE logical core PLL JTAG xTIME scheduler I/O pins Hardware response ports Key features of the XEF232-1024-FB374 include: · Tiles: Devices consist of one or more xCORE tiles. Each tile contains between five and eight 32-bit xCOREs with highly integrated I/O and on-chip memory. · Logical cores Each logical core can execute tasks such as computational code, DSP code, control software (including logic decisions and executing a state machine) or software that handles I/O. Section 6.1 · xTIME scheduler The xTIME scheduler performs functions similar to an RTOS, in hardware. It services and synchronizes events in a core, so there is no requirement for interrupt handler routines. The xTIME scheduler triggers cores on events generated by hardware resources such as the I/O pins, communication channels and timers. Once triggered, a core runs independently and concurrently to other cores, until it pauses to wait for more events. Section 6.2 · Channels and channel ends Tasks running on logical cores communicate using channels formed between two channel ends. Data can be passed synchronously or asynchronously between the channel ends assigned to the communicating tasks. Section 6.5 · xCONNECT Switch and Links Between tiles, channel communications are implemented over a high performance network of xCONNECT Links and routed through a hardware xCONNECT Switch. Section 6.6 X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 3 · Ports The I/O pins are connected to the processing cores by Hardware Response ports. The port logic can drive its pins high and low, or it can sample the value on its pins optionally waiting for a particular condition. Section 6.3 · Clock blocks xCORE devices include a set of programmable clock blocks that can be used to govern the rate at which ports execute. Section 6.4 · Memory Each xCORE Tile integrates a bank of SRAM for instructions and data, and a block of one-time programmable (OTP) memory that can be configured for system wide security features. Section 9 · PLL The PLL is used to create a high-speed processor clock given a low speed external oscillator. Section 7 · USB The USB PHY provides High-Speed and Full-Speed, device, host, and on-thego functionality. Data is communicated through ports on the digital node. A library is provided to implement USB device functionality. Section 10 · RGMII The device has a set of pins that can be dedicated to communicate with an RGMII, including Gbit Ethernet PHYs, according to the RGMII v1.3 specification. Section 11 · Flash The device has a built-in 4MBflash. Section 8 · JTAG The JTAG module can be used for loading programs, boundary scan testing, in-circuit source-level debugging and programming the OTP memory. Section 12 1.1 Software Devices are programmed using C, C++ or xC (C with multicore extensions). XMOS provides tested and proven software libraries, which allow you to quickly add interface and processor functionality such as USB, Ethernet, PWM, graphics driver, and audio EQ to your applications. 1.2 xTIMEcomposer Studio The xTIMEcomposer Studio development environment provides all the tools you need to write and debug your programs, profile your application, and write images into flash memory or OTP memory on the device. Because xCORE devices operate deterministically, they can be simulated like hardware within xTIMEcomposer: uniquely in the embedded world, xTIMEcomposer Studio therefore includes a static timing analyzer, cycle-accurate simulator, and high-speed in-circuit instrumentation. xTIMEcomposer can be driven from either a graphical development environment, or the command line. The tools are supported on Windows, Linux and MacOS X and available at no cost from xmos.com/downloads. Information on using the tools is provided in the xTIMEcomposer User Guide, X3766. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 2 4 XEF232-1024-FB374 Features · Multicore Microcontroller with Advanced Multi-Core RISC Architecture • 32 real-time logical cores on 4 xCORE tiles • Cores share up to 2000 MIPS — Up to 4000 MIPS in dual issue mode • Each logical core has: — Guaranteed throughput of between 1/5 and 1/6 of tile MIPS — 16x32bit dedicated registers • 167 high-density 16/32-bit instructions — All have single clock-cycle execution (except for divide) — 32x32→64-bit MAC instructions for DSP, arithmetic and user-definable cryptographic functions · USB PHY, fully compliant with USB 2.0 specification · RGMII support, compliant with RGMII v1.3 specification · Programmable I/O • 176 general-purpose I/O pins, configurable as input or output — Up to 59 x 1bit port, 22 x 4bit port, 15 x 8bit port, 8 x 16bit port, 4 x 32bit port — 10 xCONNECT links • Port sampling rates of up to 60 MHz with respect to an external clock • 64 channel ends for communication with other cores, on or off-chip · Memory • 1024KB internal single-cycle SRAM (max 256KB per tile) for code and data storage • 32KB internal OTP (max 8KB per tile) for application boot code • 4MB internal flash for application code and overlays · Hardware resources • 24 clock blocks (6 per tile) • 40 timers (10 per tile) • 16 locks (4 per tile) · JTAG Module for On-Chip Debug · Security Features • Programming lock disables debug and prevents read-back of memory contents • AES bootloader ensures secrecy of IP held on external flash memory · Ambient Temperature Range • Commercial qualification: 0 °C to 70 °C • Industrial qualification: -40 °C to 85 °C · Speed Grade • 40: 2000 MIPS · Power Consumption • 1140 mA (typical) · 374-pin FBGA package 0.8 mm pitch X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 3 5 Pin Configuration A B D E F 5 2 3 1D 4E 4E GND VDDIO X1D11 X1D32 X1D26 rx2 tx_clk 8 9 6 7 VDDIOT _0 8D 4F 4F X1D41 X0D31 X0D29 H J K L 12 13 14 4E 4F TDI VDDIO CLK TDO X3D32 X3D30 rx2 rx0 tx2 1M 1C 4E 4E 8D 8D 4F 4F 1M X0D36 X1D10 X1D33 X1D27 X1D42 X1D40 X0D30 X0D28 X2D36 rx3 tx_ctl tx1 tx3 1P 1O X0D38 XLi20 XLi30 VDD 4F 4F 8D X1D30 X1D28 X1D43 rx0 rx_clk tx0 8D 8D 1K 4F 4F X0D41 X0D40 X1D34 X1D31 X1D29 XLi00 XLi10 XLo2 0 rx1 rx_ctl VDD VDD 8D 8D 1L X0D43 X0D42 X1D35 XLo1 0 XLo0 0 XLo3 0 VDDIO GND 32A 32A 32A X1D49 X1D50 X1D51 XLi41 XLi31 XLi21 GND GND GND VDDIO VDDIO 4E 4E X0D33 X0D32 NC VDD GLOBAL _DEBUG 1M X1D36 VDD VDD NC NC MODE1 GND OTP_ VCC MODE0 RST_N TRST VDD VDD VDD VDD 1O 1N 1K NC NC XLi30 XLi40 TCK TMS PLL_ AVDD VDDIOT _1 4F 4F 4E X2D31 X2D29 X2D32 N P R T V VDDIO GND 4F 4E 4F 4F 4E 4E 1L X3D31 X3D27 X2D30 X2D28 X2D27 X2D26 X2D35 rx1 tx_ctl XLo4 7 XLo3 7 XLo2 7 8D 8D 4E 1J 1K GND X3D43 X3D41 X2D33 VDD X2D25 X2D34 tx0 tx2 XLo0 7 XLo1 7 1C 4F X3D29 1D 4F 4E 8D 8D 32A 1A 1B 1I X3D11 X3D28 X3D26 X3D42 X3D40 X2D70 X3D00 X3D01 X2D24 rx_clk tx_clk tx1 tx3 XLo4 6 XLi27 XLi17 XLi07 32A 4A 4A VDD VDDIO GND VDD VDD X2D69 X3D08 X3D09 XLo3 6 XLi47 XLi37 GND VDDIO X2D68 32A 32A 32A X2D67 X2D66 X2D65 XLo1 6 XLo0 6 XLi06 32A 32A VDD X2D63 X2D64 32A VDD VDD VDD VDD VDD 8D 8D 8D 8D 1P NC NC NC NC NC NC XLo2 0 XLo1 0 XLo0 0 XLi00 XLi10 XLi20 VDD VDD XLo2 6 NC NC 32A 32A X1D52 XLi01 XLi11 XLi26 XLi16 32A 32A 32A 32A X1D54 X1D55 X2D62 X2D61 XLo0 1 XLo1 1 XLi36 XLi46 VDD VDD GND GND GND GND GND GND GND GND GND GND VDD 32A 32A 32A 32A 32A 32A X1D58 X1D57 X1D56 X2D56 X2D57 X2D58 XLo4 1 XLo3 1 XLo2 1 XLo2 5 XLo3 5 XLo4 5 32A 32A GND VDDIO VDDIO GND GND X1D61 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND X2D55 XLo1 5 32A 32A 32A X1D64 X1D63 X1D62 XLi12 XLi22 XLi32 32A 32A X1D65 X1D66 XLi02 XLo0 2 32A 32A 4B 4B X1D68 X1D67 X3D06 X3D07 XLo2 2 XLo1 2 XLo3 4 XLo4 4 32A 32A 1N X1D69 X1D70 X1D37 XLo3 2 XLo4 2 XLi43 GND VDD GND GND GND NC NC NC VDDIO GND 4D 4D 1P X1D17 X1D16 X1D39 XLi03 XLi13 XLi23 4D 4D 1B 4A 4A 1D X1D19 X1D18 X0D01 X0D02 X0D08 X0D11 XLo1 3 XLo0 3 XLo2 3 VDD VDD VDD VDD 1C 1G 4A X0D03 X0D09 XLo4 3 USB_ VDD33_ 0 4A X1D22 XLo3 3 Y 1H 1A 4B 4B 1E X1D23 X0D00 X0D04 X0D06 X1D12 AA 4B 4B 1F GND VDDIO X0D05 X0D07 X1D13 X009587, GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 32A 32A 32A X2D54 X2D53 X2D52 XLo0 5 XLi05 XLi15 32A 32A X2D50 X2D51 XLi35 XLi25 VDD VDD 1O X1D38 GND VDD X0D10 W 21 X1D53 VDD XLi33 U 20 rx3 XLi42 M 19 17 4E X3D10 VDD PLL_ AGND 18 16 X3D33 rx_ctl VDD XLo4 0 G 11 1N X0D39 15 10 X0D37 XLi40 C 4 1 GND USB_ RTUNE_ 0 NC USB_ VDD_0 VDDIO 4D 1B 1G 1C NC NC NC NC XLo1 3 XLo2 3 XLo4 3 XLo3 3 VDD NC VDD VDD VDD GND VDD VDDIO VDD VDD VDD VDD USB_ ID_0 4C 1J 4C X1D14 X1D25 X0D21 4C 4C 1E 1H 1A 4B 4B GND X1D15 X0D14 X0D12 X0D23 X2D00 X2D04 1D GND X2D11 1E 4A 4A VDDIO X3D12 X2D03 X2D09 USB_ VBUS_0 1I 4C 4C 1F X1D24 X1D20 X0D15 X0D13 USB_ DM_0 USB_ DP_0 4C 4C 1G X1D21 X0D20 X0D22 NC 1H 4B 4B X3D23 X2D05 X2D07 NC USB_ VDD_1 VDDIO NC NC NC 32A 4B 4B X2D49 X3D04 X3D05 XLi45 XLo1 4 XLo2 4 GND VDDIO X3D03 4A VDD VDD VDD XLo0 4 GND USB_ ID_1 NC X2D06 GND USB_ RTUNE_ 1 4A 4A 1F X2D02 X2D08 VDD VDD NC 4D 4A X2D19 X3D02 XLi14 XLi04 4C 4C 1E 4D 4D X3D15 X3D21 X2D12 X2D17 X2D18 XLi34 XLi24 4C 4C 4D X3D20 USB_ VDD33_ 1 1H X3D14 X2D23 X2D16 XLi44 4C 4C 1I 1F 1G X3D13 VUSB_ BUS_1 X2D14 X2D20 X3D24 X2D13 X2D22 USB_ DM_1 USB_ DP_1 4C 4C 1J X2D15 X2D21 X3D25 VDDIO GND XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 4 6 Signal Description This section lists the signals and I/O pins available on the XEF232-1024-FB374. The device provides a combination of 1bit, 4bit, 8bit and 16bit ports, as well as wider ports that are fully or partially (gray) bonded out. All pins of a port provide either output or input, but signals in different directions cannot be mapped onto the same port. Pins may have one or more of the following properties: · PD/PU: The IO pin a weak pull-down or pull-up resistor. On GPIO pins this resistor can be enabled. · ST: The IO pin has a Schmitt Trigger on its input. Power pins (12) Signal Function Type GND Digital ground GND OTP_VCC OTP power supply PWR PLL_AGND Analog ground for PLL PWR PLL_AVDD Analog PLL power PWR USB_VDD33_0 PWR USB_VDD33_1 PWR USB_VDD_0 PWR USB_VDD_1 Properties PWR VDD Digital tile power PWR VDDIO Digital I/O power PWR VDDIOT_0 PWR VDDIOT_1 PWR JTAG pins (6) Signal Function Type Properties RST_N Global reset input Input IOL, PU, ST TCK Test clock Input IOL, PD, ST TDI Test data input Input IOL, PU TDO Test data output Output IOL, PD TMS Test mode select Input IOL, PU Input IOL, PU, ST TRST I/O pins (176) Signal Function X0D00 X0D01 XL32 out Type Properties 1A0 I/O IOL, PD 1B0 I/O— IOL, PD (continued) X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Signal Type Properties X0D02 4A0 8A0 16A0 32A20 I/O IOL, PD X0D03 4A1 8A1 16A1 32A21 I/O IOL, PD X0D04 4B0 8A2 16A2 32A22 I/O— IOL, PD X0D05 4B1 8A3 16A3 32A23 I/O— IOL, PD X0D06 4B2 8A4 16A4 32A24 I/O— IOL, PD X0D07 4B3 8A5 16A5 32A25 I/O— IOL, PD X0D08 4A2 8A6 16A6 32A26 I/O IOL, PD X0D09 4A3 8A7 16A7 32A27 I/O IOL, PD 1C0 I/O— IOL, PD X0D11 1D0 I/O IOL, PD X0D12 1E0 I/O IOR, PD X0D13 1F0 I/O IOR, PD X0D10 Function XL33 out X0D14 4C0 8B0 16A8 32A28 I/O IOR, PD X0D15 4C1 8B1 16A9 32A29 I/O IOR, PD X0D20 4C2 8B6 16A14 32A30 I/O IOR, PD X0D21 4C3 8B7 16A15 32A31 I/O IOR, PD X0D22 1G0 I/O IOR, PD X0D23 1H0 I/O IOR, PD X0D28 4F0 8C2 16B2 I/O IOR, PD X0D29 4F1 8C3 16B3 I/O IOR, PD X0D30 4F2 8C4 16B4 I/O IOR, PD X0D31 4F3 8C5 16B5 I/O IOR, PD X0D32 4E2 8C6 16B6 I/O IOR, PD X0D33 4E3 8C7 16B7 I/O IOR, PD 1M0 8D0 16B8 I/O IOL, PD X0D36 X0D37 XL04 in 1N0 8D1 16B9 I/O IOL, PD X0D38 XL03 in 1O0 8D2 16B10 I/O IOL, PD X0D39 XL02 in 1P0 8D3 16B11 I/O IOL, PD X0D40 XL01 in 8D4 16B12 I/O IOL, PD X0D41 XL00 in 8D5 16B13 I/O IOL, PD X0D42 XL00 out 8D6 16B14 I/O IOL, PD X0D43 XL01 out 8D7 16B15 I/O IOL, PD X1D10 1C0 I/O IOT, PD X1D11 1D0 I/O IOT, PD X1D12 1E0 I/O IOL, PD X1D13 1F0 I/O IOL, PD X1D14 4C0 8B0 16A8 32A28 I/O IOR, PD X1D15 4C1 8B1 16A9 32A29 I/O IOR, PD X1D16 XL31 in 4D0 8B2 16A10 I/O IOL, PD X1D17 XL30 in 4D1 8B3 16A11 I/O IOL, PD X1D18 XL30 out 4D2 8B4 16A12 I/O IOL, PD X1D19 XL31 out 4D3 8B5 16A13 I/O IOL, PD 4C2 8B6 16A14 I/O IOR, PD X1D20 32A30 7 (continued) X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Signal Function Type Properties I/O IOR, PD 1G0 I/O IOL, PD X1D23 1H0 I/O IOL, PD X1D24 1I0 I/O IOR, PD X1D25 1J0 I/O IOR, PD 4C3 X1D21 X1D22 XL34 out 8B7 16A15 32A31 X1D26 tx_clk (rgmii) 4E0 8C0 16B0 I/O IOT, PD X1D27 tx_ctl (rgmii) 4E1 8C1 16B1 I/O IOT, PD X1D28 rx_clk (rgmii) 4F0 8C2 16B2 I/O IOT, PD X1D29 rx_ctl (rgmii) 4F1 8C3 16B3 I/O IOT, PD X1D30 rx0 (rgmii) 4F2 8C4 16B4 I/O IOT, PD X1D31 rx1 (rgmii) 4F3 8C5 16B5 I/O IOT, PD X1D32 rx2 (rgmii) 4E2 8C6 16B6 I/O IOT, PD X1D33 rx3 (rgmii) 4E3 8C7 16B7 I/O IOT, PD X1D34 XL02 out 1K0 I/O IOL, PD X1D35 XL03 out 1L0 I/O IOL, PD X1D36 XL04 out 1M0 8D0 16B8 I/O IOL, PD X1D37 XL34 in 1N0 8D1 16B9 I/O IOL, PD X1D38 XL33 in 1O0 8D2 16B10 I/O IOL, PD X1D39 XL32 in 1P0 8D3 16B11 I/O IOL, PD X1D40 tx3 (rgmii) 8D4 16B12 I/O IOT, PD X1D41 tx2 (rgmii) 8D5 16B13 I/O IOT, PD X1D42 tx1 (rgmii) 8D6 16B14 I/O IOT, PD X1D43 tx0 (rgmii) 8D7 16B15 I/O IOT, PD X1D49 XL14 in 32A0 I/O IOL, PD X1D50 XL13 in 32A1 I/O IOL, PD X1D51 XL12 in 32A2 I/O IOL, PD X1D52 XL11 in 32A3 I/O IOL, PD X1D53 XL10 in 32A4 I/O IOL, PD X1D54 XL10 out 32A5 I/O IOL, PD X1D55 XL11 out 32A6 I/O IOL, PD X1D56 XL12 out 32A7 I/O IOL, PD X1D57 XL13 out 32A8 I/O IOL, PD X1D58 XL14 out 32A9 I/O IOL, PD X1D61 XL24 in 32A10 I/O IOL, PD X1D62 XL23 in 32A11 I/O IOL, PD X1D63 XL22 in 32A12 I/O IOL, PD X1D64 XL21 in 32A13 I/O IOL, PD X1D65 XL20 in 32A14 I/O IOL, PD X1D66 XL20 out 32A15 I/O IOL, PD X1D67 XL21 out 32A16 I/O IOL, PD X1D68 XL22 out 32A17 I/O IOL, PD X1D69 XL23 out 32A18 I/O IOL, PD X1D70 XL24 out 32A19 I/O IOL, PD 8 (continued) X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Signal Function 1A0 X2D00 Type Properties I/O IOL, PD X2D02 4A0 8A0 16A0 32A20 I/O IOL, PD X2D03 4A1 8A1 16A1 32A21 I/O IOL, PD X2D04 4B0 8A2 16A2 32A22 I/O IOL, PD X2D05 4B1 8A3 16A3 32A23 I/O IOL, PD X2D06 4B2 8A4 16A4 32A24 I/O IOL, PD X2D07 4B3 8A5 16A5 32A25 I/O IOL, PD X2D08 4A2 8A6 16A6 32A26 I/O IOL, PD X2D09 4A3 8A7 16A7 32A27 I/O IOL, PD X2D11 1D0 I/O IOL, PD X2D12 1E0 I/O IOR, PD X2D13 1F0 I/O IOR, PD X2D14 4C0 8B0 16A8 32A28 I/O IOR, PD X2D15 4C1 8B1 16A9 32A29 I/O IOR, PD X2D16 XL44 in 4D0 8B2 16A10 I/O IOR, PD X2D17 XL43 in 4D1 8B3 16A11 I/O IOR, PD X2D18 XL42 in 4D2 8B4 16A12 I/O IOR, PD X2D19 XL41 in 4D3 8B5 16A13 I/O IOR, PD X2D20 4C2 8B6 16A14 32A30 I/O IOR, PD X2D21 4C3 8B7 16A15 32A31 I/O IOR, PD X2D22 1G0 I/O IOR, PD X2D23 1H0 I/O IOR, PD X2D24 XL70 in 1I0 I/O IOR, PD X2D25 XL70 out 1J0 I/O IOR, PD X2D26 XL73 out 4E0 8C0 16B0 I/O IOR, PD X2D27 XL74 out 4E1 8C1 16B1 I/O IOR, PD X2D28 4F0 8C2 16B2 I/O IOR, PD X2D29 4F1 8C3 16B3 I/O IOR, PD X2D30 4F2 8C4 16B4 I/O IOR, PD X2D31 4F3 8C5 16B5 I/O IOR, PD X2D32 4E2 8C6 16B6 I/O IOR, PD X2D33 4E3 8C7 16B7 I/O IOR, PD X2D34 XL71 out 1K0 I/O IOR, PD X2D35 XL72 out 1L0 I/O IOR, PD I/O IOL, PD 1M0 X2D36 8D0 16B8 X2D49 XL54 in 32A0 I/O IOR, PD X2D50 XL53 in 32A1 I/O IOR, PD X2D51 XL52 in 32A2 I/O IOR, PD X2D52 XL51 in 32A3 I/O IOR, PD X2D53 XL50 in 32A4 I/O IOR, PD X2D54 XL50 out 32A5 I/O IOR, PD X2D55 XL51 out 32A6 I/O IOR, PD X2D56 XL52 out 32A7 I/O IOR, PD 9 (continued) X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Signal Function Type Properties X2D57 XL53 out 32A8 I/O IOR, PD X2D58 XL54 out 32A9 I/O IOR, PD X2D61 XL64 in 32A10 I/O IOR, PD X2D62 XL63 in 32A11 I/O IOR, PD X2D63 XL62 in 32A12 I/O IOR, PD X2D64 XL61 in 32A13 I/O IOR, PD X2D65 XL60 in 32A14 I/O IOR, PD X2D66 XL60 out 32A15 I/O IOR, PD X2D67 XL61 out 32A16 I/O IOR, PD X2D68 XL62 out 32A17 I/O IOR, PD X2D69 XL63 out 32A18 I/O IOR, PD X2D70 XL64 out 32A19 I/O IOR, PD X3D00 XL72 in 1A0 I/O IOR, PD X3D01 XL71 in 1B0 I/O IOR, PD X3D02 XL40 in 4A0 8A0 16A0 32A20 I/O IOR, PD X3D03 XL40 out 4A1 8A1 16A1 32A21 I/O IOR, PD X3D04 XL41 out 4B0 8A2 16A2 32A22 I/O IOR, PD X3D05 XL42 out 4B1 8A3 16A3 32A23 I/O IOR, PD X3D06 XL43 out 4B2 8A4 16A4 32A24 I/O IOR, PD X3D07 XL44 out 4B3 8A5 16A5 32A25 I/O IOR, PD X3D08 XL74 in 4A2 8A6 16A6 32A26 I/O IOR, PD X3D09 XL73 in 4A3 8A7 16A7 32A27 I/O IOR, PD X3D10 1C0 I/O IOT, PD X3D11 1D0 I/O IOT, PD X3D12 1E0 I/O IOL, PD X3D13 1F0 I/O IOL, PD X3D14 4C0 8B0 16A8 32A28 I/O IOR, PD X3D15 4C1 8B1 16A9 32A29 I/O IOR, PD X3D20 4C2 8B6 16A14 32A30 I/O IOR, PD X3D21 4C3 8B7 16A15 32A31 I/O IOR, PD X3D23 1H0 I/O IOL, PD X3D24 1I0 I/O IOR, PD X3D25 1J0 I/O IOR, PD X3D26 tx_clk (rgmii) 4E0 8C0 16B0 I/O IOT, PD X3D27 tx_ctl (rgmii) 4E1 8C1 16B1 I/O IOT, PD X3D28 rx_clk (rgmii) 4F0 8C2 16B2 I/O IOT, PD X3D29 rx_ctl (rgmii) 4F1 8C3 16B3 I/O IOT, PD X3D30 rx0 (rgmii) 4F2 8C4 16B4 I/O IOT, PD X3D31 rx1 (rgmii) 4F3 8C5 16B5 I/O IOT, PD X3D32 rx2 (rgmii) 4E2 8C6 16B6 I/O IOT, PD X3D33 rx3 (rgmii) 4E3 8C7 16B7 I/O IOT, PD X3D40 tx3 (rgmii) 8D4 16B12 I/O IOT, PD X3D41 tx2 (rgmii) 8D5 16B13 I/O IOT, PD 10 (continued) X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Signal Function Type Properties X3D42 tx1 (rgmii) 8D6 16B14 I/O IOT, PD X3D43 tx0 (rgmii) 8D7 16B15 I/O IOT, PD Signal Function Type Properties CLK PLL reference clock Input IOL, PD, ST GLOBAL_DEBUG Multi-chip debug I/O IOL, PU MODE0 Boot mode select Input PU MODE1 Boot mode select Input PU Signal Function Type Properties 11 System pins (4) usb pins (10) X009587, USB_DM_0 I/O USB_DM_1 I/O USB_DP_0 I/O USB_DP_1 I/O USB_ID_0 I/O USB_ID_1 I/O USB_RTUNE_0 I/O USB_RTUNE_1 I/O USB_VBUS_0 I/O VUSB_BUS_1 I/O XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 5 12 Example Application Diagram JACK / MAGNETIC IN IN EN RGMII PHY VDDIOT X1D11 X1D10 X1D33 X1D32 X1D31 X1D30 X1D29 X1D28 X1D27 X1D26 X1D43 X1D42 X1D41 X1D40 RESET SUPERVISOR PLL_AGND PG OUT USB_VDD OUT 1V0 VDD 3V3 OUT PLL_AVDD IN 2V5 RST_N OSCILLATOR 25 MHz 24 CLK OTP_VCC XnDnn GPIO xCORE200 X0D01 X009587, GND USB_VDDV33 Figure 2: Simplified Reference Schematic USB_RTUNE VDDIOR USB_VBUS USB_DP USB_DM USB_ID VDDIOL USB XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 6 13 Product Overview The XEF232-1024-FB374 is a powerful device that consists of four xCORE Tiles, each comprising a flexible logical processing cores with tightly integrated I/O and on-chip memory. 6.1 Logical cores Each tile has 6 active logical cores, which issue instructions down a shared fivestage pipeline. Instructions from the active cores are issued round-robin. If up to five logical cores are active, each core is allocated a fifth of the processing cycles. If more than five logical cores are active, each core is allocated at least 1/n cycles (for n cores). Figure 3 shows the guaranteed core performance depending on the number of cores used. Figure 3: Logical core performance Speed MIPS Frequency grade Minimum MIPS per core (for n cores) 1 2 3 4 5 6 7 8 There is no way that the performance of a logical core can be reduced below these predicted levels (unless priority threads are used: in this case the guaranteed minimum performance is computed based on the number of priority threads as defined in the architecture manual). Because cores may be delayed on I/O, however, their unused processing cycles can be taken by other cores. This means that for more than five logical cores, the performance of each core is often higher than the predicted minimum but cannot be guaranteed. The logical cores are triggered by events instead of interrupts and run to completion. A logical core can be paused to wait for an event. 6.2 xTIME scheduler The xTIME scheduler handles the events generated by xCORE Tile resources, such as channel ends, timers and I/O pins. It ensures that all events are serviced and synchronized, without the need for an RTOS. Events that occur at the I/O pins are handled by the Hardware-Response ports and fed directly to the appropriate xCORE Tile. An xCORE Tile can also choose to wait for a specified time to elapse, or for data to become available on a channel. Tasks do not need to be prioritised as each of them runs on their own logical xCORE. It is possible to share a set of low priority tasks on a single core using cooperative multitasking. 6.3 Hardware Response Ports Hardware Response ports connect an xCORE tile to one or more physical pins and as such define the interface between hardware attached to the XEF232-1024-FB374, and the software running on it. A combination of 1bit, 4bit, 8bit, 16bit and 32bit X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 14 ports are available. All pins of a port provide either output or input. Signals in different directions cannot be mapped onto the same port. reference clock readyOut conditional value clock port clock block readyIn port port counter port logic stamp/time PORT FIFO PINS Figure 4: Port block diagram port value output (drive) SERDES transfer register CORE input (sample) The port logic can drive its pins high or low, or it can sample the value on its pins, optionally waiting for a particular condition. Ports are accessed using dedicated instructions that are executed in a single processor cycle. xCORE-200 IO pins can be used as open collector outputs, where signals are driven low if a zero is output, but left high impedance if a one is output. This option is set on a per-port basis. Data is transferred between the pins and core using a FIFO that comprises a SERDES and transfer register, providing options for serialization and buffered data. Each port has a 16-bit counter that can be used to control the time at which data is transferred between the port value and transfer register. The counter values can be obtained at any time to find out when data was obtained, or used to delay I/O until some time in the future. The port counter value is automatically saved as a timestamp, that can be used to provide precise control of response times. The ports and xCONNECT links are multiplexed onto the physical pins. If an xConnect Link is enabled, the pins of the underlying ports are disabled. If a port is enabled, it overrules ports with higher widths that share the same pins. The pins on the wider port that are not shared remain available for use when the narrower port is enabled. Ports always operate at their specified width, even if they share pins with another port. 6.4 Clock blocks xCORE devices include a set of programmable clocks called clock blocks that can be used to govern the rate at which ports execute. Each xCORE tile has six clock blocks: the first clock block provides the tile reference clock and runs at a default frequency of 100MHz; the remaining clock blocks can be set to run at different frequencies. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 100MHz reference clock 15 1-bit port ... ... divider readyIn clock block Figure 5: Clock block diagram port counter A clock block can use a 1-bit port as its clock source allowing external application clocks to be used to drive the input and output interfaces. xCORE-200 clock blocks optionally divide the clock input from a 1-bit port. In many cases I/O signals are accompanied by strobing signals. The xCORE ports can input and interpret strobe (known as readyIn and readyOut) signals generated by external sources, and ports can generate strobe signals to accompany output data. On reset, each port is connected to clock block 0, which runs from the xCORE Tile reference clock. 6.5 Channels and Channel Ends Logical cores communicate using point-to-point connections, formed between two channel ends. A channel-end is a resource on an xCORE tile, that is allocated by the program. Each channel-end has a unique system-wide identifier that comprises a unique number and their tile identifier. Data is transmitted to a channel-end by an output-instruction; and the other side executes an input-instruction. Data can be passed synchronously or asynchronously between the channel ends. 6.6 xCONNECT Switch and Links XMOS devices provide a scalable architecture, where multiple xCORE devices can be connected together to form one system. Each xCORE device has an xCONNECT interconnect that provides a communication infrastructure for all tasks that run on the various xCORE tiles on the system. The interconnect relies on a collection of switches and XMOS links. Each xCORE device has an on-chip switch that can set up circuits or route data. The switches are connected by xConnect Links. An XMOS link provides a physical connection between two switches. The switch has a routing algorithm that supports many different topologies, including lines, meshes, trees, and hypercubes. The links operate in either 2 wires per direction or 5 wires per direction mode, depending on the amount of bandwidth required. Circuit switched, streaming X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 16 xCONNECT Link to another device switch CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE xCONNECT switch CORE CORE Figure 6: Switch, links and channel ends CORE CORE CORE CORE xCORE Tile xCORE Tile and packet switched data can both be supported efficiently. Streams provide the fastest possible data rates between xCORE Tiles (up to 250 MBit/s), but each stream requires a single link to be reserved between switches on two tiles. All packet communications can be multiplexed onto a single link. Information on the supported routing topologies that can be used to connect multiple devices together can be found in the XS1-UEF Link Performance and Design Guide, X2999. 7 PLL The PLL creates a high-speed clock that is used for the switch, tile, and reference clock. The PLL multiplication value is selected through the two MODE pins, and can be changed by software to speed up the tile or use less power. The MODE pins are set as shown in Figure 7: Figure 7: PLL multiplier values and MODE pins X009587, Oscillator Frequency 3.25-10 MHz 9-25 MHz 25-50 MHz 50-100 MHz MODE 1 0 0 0 1 1 1 0 0 1 Tile Frequency 130-400 MHz 144-400 MHz 167-400 MHz 196-400 MHz PLL Ratio 40 16 8 4 PLL settings OD F R 1 159 0 1 63 0 1 31 0 1 15 0 XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 17 Figure 7 also lists the values of OD, F and R, which are the registers that define the ratio of the tile frequency to the oscillator frequency: Fcor e = Fosc × 1 1 F +1 × × 2 R+1 OD + 1 OD, F and R must be chosen so that 0 ≤ R ≤ 63, 0 ≤ F ≤ 4095, 0 ≤ OD ≤ 7, and 1 260MHz ≤ Fosc × F +1 × R+1 ≤ 1.3GHz. The OD, F , and R values can be modified 2 by writing to the digital node PLL configuration register. The MODE pins must be held at a static value during and after deassertion of the system reset. If the USB PHY is used, then either a 24 MHz or 12 MHz oscillator must be used. If a different tile frequency is required (eg, 500 MHz), then the PLL must be reprogrammed after boot to provide the required tile frequency. The XMOS tools perform this operation by default. Further details on configuring the clock can be found in the xCORE-200 Clock Frequency Control document. 8 Boot Procedure The device is kept in reset by driving RST_N low. When in reset, all GPIO pins have a pull-down enabled. The processor must be held in reset until VDDIOL is in spec for at least 1 ms. When the device is taken out of reset by releasing RST_N the processor starts its internal reset process. After 15-150 µs (depending on the input clock) the processor boots. The device boots from a QSPI flash that is embedded in the device. The QSPI flash is connected to the ports on Tile 0 as shown in Figure 8. An external 1K resistor must connect X0D01 to VDDIOL. X0D10 should ideally not be connected. If X0D10 is connected, then a 150 ohm series resistor close to the device is recommended. X0D04..X0D07 should be not connected. VDDIOL Figure 8: QSPI port connectivity X0D04..7 X0D01 X0D10 PORT_4B PORT_1B PORT_1C CS_N CLK D[0..3] 1K xCORE QSPI Flash The xCORE Tile boot procedure is illustrated in Figure 9. If bit 5 of the security register (see §9.1) is set, the device boots from OTP. Otherwise, the device boots from the internal flash. The boot image has the following format: X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 18 Start Boot ROM Primary boot Security Register Bit [5] set No Yes OTP Figure 9: Boot procedure Copy OTP contents to base of SRAM Copy flash contents to base of SRAM Execute program Execute program · A 32-bit program size s in words. · Program consisting of s × 4 bytes. · A 32-bit CRC, or the value 0x0D15AB1E to indicate that no CRC check should be performed. The program size and CRC are stored least significant byte first. The program is loaded into the lowest memory address of RAM, and the program is started from that address. The CRC is calculated over the byte stream represented by the program size and the program itself. The polynomial used is 0xEDB88320 (IEEE 802.3); the CRC register is initialized with 0xFFFFFFFF and the residue is inverted to produce the CRC. 8.1 Security register The security register enables security features on the xCORE tile. The features shown in Figure 10 provide a strong level of protection and are sufficient for providing strong IP security. 9 Memory 9.1 OTP Each xCORE Tile integrates 8 KB one-time programmable (OTP) memory along with a security register that configures system wide security features. The OTP holds data in four sectors each containing 512 rows of 32 bits which can be used to implement secure bootloaders and store encryption keys. Data for the security register is loaded from the OTP on power up. All additional data in OTP is copied from the OTP to SRAM and executed first on the processor. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 19 Feature Bit Description Disable JTAG 0 The JTAG interface is disabled, making it impossible for the tile state or memory content to be accessed via the JTAG interface. Disable Link access 1 Other tiles are forbidden access to the processor state via the system switch. Disabling both JTAG and Link access transforms an xCORE Tile into a “secure island” with other tiles free for non-secure user application code. Secure Boot 5 The xCORE Tile is forced to boot from address 0 of the OTP, allowing the xCORE Tile boot ROM to be bypassed (see §8). Redundant rows 7 Enables redundant rows in OTP. Sector Lock 0 8 Disable programming of OTP sector 0. Sector Lock 1 9 Disable programming of OTP sector 1. Sector Lock 2 10 Disable programming of OTP sector 2. Sector Lock 3 11 Disable programming of OTP sector 3. OTP Master Lock 12 Disable OTP programming completely: disables updates to all sectors and security register. Disable JTAG-OTP 13 Disable all (read & write) access from the JTAG interface to this OTP. 21..15 General purpose software accessable security register available to end-users. 31..22 General purpose user programmable JTAG UserID code extension. Figure 10: Security register features The OTP memory is programmed using three special I/O ports: the OTP address port is a 16-bit port with resource ID 0x100200, the OTP data is written via a 32-bit port with resource ID 0x200100, and the OTP control is on a 16-bit port with ID 0x100300. Programming is performed through libotp and xburn. 9.2 SRAM Each xCORE Tile integrates a single 256KB SRAM bank for both instructions and data. All internal memory is 32 bits wide, and instructions are either 16-bit or 32-bit. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one tile clock cycle. There is no dedicated external memory interface, although data memory can be expanded through appropriate use of the ports. 10 USB PHY The USB PHY provides High-Speed and Full-Speed, device, host, and on-the-go functionality. The PHY is configured through a set of peripheral registers (Appendix F), X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 20 and data is communicated through ports on the digital node. A library, libxud_s.a, is provided to implement USB device functionality. The USB PHY is connected to the ports on Tile 0 and Tile 1 as shown in Figure 11. When the USB PHY is enabled on Tile 0, the ports shown can on Tile 0 only be used with the USB PHY. When the USB PHY is enabled on Tile 1, then the ports shown can on Tile 1 only be used with the USB PHY. All other IO pins and ports are unaffected. The USB PHY should not be enabled on both tiles. An external resistor of 43.2 ohm (1% tolerance) should connect USB_TUNE to ground, as close as possible to the device. 3V3 1V0 USB connector DP DM ID VBUS USB_VDD USB_VDD33 USB_DP USB_DM USB_ID USB_VBUS USB_RTUNE 43R2 Figure 11: USB port functions Please note: ID connection is optional DM may be marked as DN USB PHY xCORE TXD[0..7] TXRDYOUT TXRDYIN PORT_8A PORT_1K PORT_1H CLK PORT_1J RXRDY RXD[0..7] FLAG0 FLAG1 FLAG2 PORT_1I PORT_8B PORT_1E PORT_1F PORT_1G TXDATA CLKBLK CLKBLK RXDATA FLAG0 FLAG1 FLAG2 Figure 11 shows how two clock blocks can be used to clock the USB ports. One clock block for the TXDATA path, and one clock block for the RXDATA path. Details on how to connect those ports are documented in an application note on USB for xCORE-200. 10.1 Logical Core Requirements The XMOS XUD software component runs in a single logical core with endpoint and application cores communicating with it via a combination of channel communication and shared memory variables. Each IN (host requests data from device) or OUT (data transferred from host to device) endpoint requires one logical core. 11 RGMII The device has a series of pins that are dedicated to communicate with an RGMII PHY, as per the RGMII v1.3 spec. This can be used to communicate with GBit Ethernet PHYs. The pins and functions are listed in Figure 12. When RGMII mode is enabled (using processor status register 2) these pins can no longer be used as GPIO pins, and will instead be driven directly from an RGMII block that provides DDR to SDR conversion, which in turn is interfaced to a set of ports on Tile 1. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Figure 12: RGMII block pin functions Pin X1D40 X1D41 X1D42 X1D43 X1D26 X1D27 X1D28 X1D29 X1D30 X1D31 X1D32 X1D33 21 RGMII Function TX3 Transmit bit 3 TX2 Transmit bit 2 TX1 Transmit bit 1 TX0 Transmit bit 0 TX_CLK Receive clock (125 MHz) TX_CTL Transmit data valid/error RX_CLK Receive clock (125 MHz) RX_CTL Receive data valid/error RX0 Receive bit 0 RX1 Receive bit 1 RX2 Receive bit 2 RX3 Receive bit 3 The RGMII block is connected to the ports on Tile 1 as shown in Figure 13. When the RGMII block is enabled, the ports shown can only be used with the RGMII block, and IO pins X1D26..X1D33/X1D40..X1D43 can only be used with the RGMII block. Other IO pins and ports are unaffected. The RGMII block generates a clock (configured using processor status register 2), and has the facility to delay the outgoing clock edge, putting it out of phase with the data. The RGMII block translates the double data-rate 4-wire data signals and 1-wire control signal into single-data rate 8-wire TX and DX signals and two control signals. Figure 13 shows how four clock blocks can be used to clock the RGMII ports. One clock block for the TXDATA path, one clock block for the RXDATA path, one clock block to delay the TX_CLK, and one clock block clocked on a negative valid signal to enable mode switching between 10/100/1000 speeds. Details on how to connect those ports are documented in an application note on RGMII for xCORE-200. The XMOS RGMII software component runs a MAC layer on tile 1. Figure 13: RGMII port functions X009587, External RGMII PHY SMC SMIO TX3 TX2 TX1 TX0 TX_CLK TX_CTL RX_CLK RX_CTL RX0 RX1 RX2 RX3 X1D11 X1D10 X1D40 X1D41 X1D42 X1D43 X1D26 X1D27 X1D28 X1D29 X1D30 X1D31 X1D32 X1D33 xCore TIle 1 RGMII Block TXD0..7 TXDV CLK TXCLK TXERR RXERR RXCLK RXDV RXD0..7 PORT_1D PORT_1C SMC SMIO PORT_8B PORT_1F PORT_1P PORT_1G PORT_1E PORT_1A PORT_1O PORT_1B PORT_8A PORT_1K PORT_4E TXDATA CLKBLK CLKBLK TXERROR RXERROR CLKBLK RXDATA CLKBLK MODE XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 22 The SMI interface should be connected to two one-bit ports that are configured as open-drain IOs, using external pull-ups to 2.5V. Ports 1C and 1D on Tile 1 are notionally allocated for this, but any GPIO can be used for this purpose. The bundles of RX and TX pins should be wired using matched trace-lengths over an uninterrupted ground-plane. The RGMII pins are supplied through the VDDIOT supply pins, which should be provided with 2.5V. Decouplers should be placed with a short path to VDDIOT and ground. If the PHY supports a 3.3V IO voltage, then a 3.3V supply can be used for VDDIOT. The RGMII PHY should be configured so that RX_CLK is low during reset of the xCORE. This can be achieved by putting a pull-down resistor on the reset of the PHY, keeping the PHY in reset until the RGMII layer on the xCORE takes the PHY out of reset. 12 JTAG The JTAG module can be used for loading programs, boundary scan testing, incircuit source-level debugging and programming the OTP memory. BS TAP TDI TDI CHIP TAP TDO TDI TDO TDO TCK TMS Figure 14: JTAG chain structure The JTAG chain structure is illustrated in Figure 14. Directly after reset, two TAP controllers are present in the JTAG chain for each xCORE Tile: the boundary scan TAP and the chip TAP. The boundary scan TAP is a standard 1149.1 compliant TAP that can be used for boundary scan of the I/O pins. The chip TAP provides access into the xCORE Tile, switch and OTP for loading code and debugging. The JTAG module can be reset by holding TMS high for five clock cycles. The JTAG device identification register can be read by using the IDCODE instruction. Its contents are specified in Figure 15. Figure 15: IDCODE return value X009587, Bit31 Device Identification Register Version 0 0 0 0 Bit0 Part Number 0 0 0 0 0 0 0 0 0 0 0 0 Manufacturer Identity 0 0 0 0 0 1 1 6 0 0 1 1 6 0 0 0 1 3 1 1 0 0 1 1 3 XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 23 The JTAG usercode register can be read by using the USERCODE instruction. Its contents are specified in Figure 16. The OTP User ID field is read from bits [22:31] of the security register on xCORE Tile 0, see §9.1 (all zero on unprogrammed devices). Figure 16: USERCODE return value 13 Bit31 Usercode Register OTP User ID 0 0 0 0 0 0 0 0 0 Bit0 Unused 0 0 0 0 0 0 0 Silicon Revision 0 1 0 2 1 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Board Integration The device has the following power supply pins: · VDD pins for the xCORE Tile · VDDIO pins for the I/O lines · PLL_AVDD pins for the PLL · OTP_VCC pins for the OTP Several pins of each type are provided to minimize the effect of inductance within the package, all of which must be connected. The power supplies must be brought up monotonically and input voltages must not exceed specification at any time. The VDD supply must ramp from 0 V to its final value within 10 ms to ensure correct startup. The VDDIO and OTP_VCC supply must ramp to its final value before VDD reaches 0.4 V. The PLLVDD supply should be separated from the other noisier supplies on the board. The PLL requires a very clean power supply, and a low pass filter (for example, a 4.7 Ω resistor and multi-layer ceramic capacitor) is recommended on this pin. The following ground pins are provided: · PLL_AGND for PLL_AVDD · GND for all other supplies All ground pins must be connected directly to the board ground. The VDD and VDDIO supplies should be decoupled close to the chip by several 100 nF low inductance multi-layer ceramic capacitors between the supplies and GND (for example, 4x100nF 0402 low inductance MLCCs per supply rail). The ground side of the decoupling capacitors should have as short a path back to the GND pins as possible. A bulk decoupling capacitor of at least 10 uF should be placed on each of these supplies. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 24 RST_N is an active-low asynchronous-assertion global reset signal. Following a reset, the PLL re-establishes lock after which the device boots up according to the boot mode (see §8). RST_N and must be asserted low during and after power up for 100 ns. 13.1 USB connections USB_VBUS should be connected to the VBUS pin of the USB connector. A 2.2 uF capacitor to ground is required on the VBUS pin. A ferrite bead may be used to reduce HF noise. For self-powered systems, a bleeder resistor may be required to stop VBUS from floating when no USB cable is attached. USB_DP and USB_DN should be connected to the USB connector. USB_ID does not need to be connected. 13.2 USB signal routing and placement The USB_DP and USB_DN lines are the positive and negative data polarities of a high speed USB signal respectively. Their high-speed differential nature implies that they must be coupled and properly isolated. The board design must ensure that the board traces for USB_DP and USB_DN are tightly matched. In addition, according to the USB 2.0 specification, the USB_DP and USB_DN differential impedance must be 90 Ω. Figure 17: USB trace separation showing a low speed signal, two differential pairs and a high-speed clock Low-speed non-periodic signal 20 mils (0.51mm) 13.2.1 USB_DP0 USB_DN0 3.9 mils (0.10mm) USB_DP1 20 mils (0.51mm) High-speed periodic signal USB_DN1 3.9 mils (0.10mm - calculated on the stack up) 50 mils (1.27mm) General routing and placement guidelines The following guidelines will help to avoid signal quality and EMI problems on high speed USB designs. They relate to a four-layer (Signal, GND, Power, Signal) PCB. For best results, most of the routing should be done on the top layer (assuming the USB connector and XS2-UEF32A-1024-FB374 are on the top layer) closest to GND. Reference planes should be below the transmission lines in order to maintain control of the trace impedance. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0.12 mm 0.10 mm USB_DP 25 0.12 mm USB_DN 0.1 mm GND 1.0 mm FR4 Dielectric Power Figure 18: Example USB board stack 0.1 mm We recommend that the high-speed clock and high-speed USB differential pairs are routed first before any other routing. When routing high speed USB signals, the following guidelines should be followed: · High speed differential pairs should be routed together. · High-speed USB signal pair traces should be trace-length matched. Maximum trace-length mismatch should be no greater than 4mm. · Ensure that high speed signals (clocks, USB differential pairs) are routed as far away from off-board connectors as possible. · High-speed clock and periodic signal traces that run parallel should be at least 1.27mm away from USB_DP/USB_DN (see Figure 17). · Low-speed and non-periodic signal traces that run parallel should be at least 0.5mm away from USB_DP/USB_DN (see Figure 17). · Route high speed USB signals on the top of the PCB wherever possible. · Route high speed USB traces over continuous power planes, with no breaks. If a trade-off must be made, changing signal layers is preferable to crossing plane splits. · Follow the 20 × h rule; keep traces 20 × h (the height above the power plane) away from the edge of the power plane. · Use a minimum of vias in high speed USB traces. · Avoid corners in the trace. Where necessary, rather than turning through a 90 degree angle, use two 45 degree turns or an arc. · DO NOT route USB traces near clock sources, clocked circuits or magnetic devices. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 26 · Avoid stubs on high speed USB signals. 13.3 Land patterns and solder stencils The land pattern recommendations in this document are based on a RoHS compliant process and derived, where possible, from the nominal Generic Requirements for Surface Mount Design and Land Pattern Standards IPC-7351B specifications. This standard aims to achieve desired targets of heel, toe and side fillets for solderjoints. Solder paste and ground via recommendations are based on our engineering and development kit board production. They have been found to work and optimized as appropriate to achieve a high yield. The size, type and number of vias used in the center pad affects how much solder wicks down the vias during reflow. This in turn, along with solder paster coverage, affects the final assembled package height. These factors should be taken into account during design and manufacturing of the PCB. The following land patterns and solder paste contains recommendations. Final land pattern and solder paste decisions are the responsibility of the customer. These should be tuned during manufacture to suit the manufacturing process. 13.4 Moisture Sensitivity XMOS devices are, like all semiconductor devices, susceptible to moisture absorption. When removed from the sealed packaging, the devices slowly absorb moisture from the surrounding environment. If the level of moisture present in the device is too high during reflow, damage can occur due to the increased internal vapour pressure of moisture. Example damage can include bond wire damage, die lifting, internal or external package cracks and/or delamination. All XMOS devices are Moisture Sensitivity Level (MSL) 3 - devices have a shelf life of 168 hours between removal from the packaging and reflow, provided they are stored below 30C and 60% RH. If devices have exceeded these values or an included moisture indicator card shows excessive levels of moisture, then the parts should be baked as appropriate before use. This is based on information from Joint IPC/JEDEC Standard For Moisture/Reflow Sensitivity Classification For Nonhermetic Solid State Surface-Mount Devices J-STD-020 Revision D. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 14 27 DC and Switching Characteristics 14.1 Operating Conditions Symbol Parameter MIN TYP MAX UNITS VDD Tile DC supply voltage 0.95 1.00 1.05 V VDDIO I/O supply voltage 2.30 3.30 3.60 V VDDIOT 3v3 I/O supply voltage 3.135 3.30 3.465 V VDDIOT 2v5 I/O supply voltage 2.375 2.50 2.625 V VDD33 Peripheral supply 3.135 3.30 3.465 V PLL_AVDD PLL analog supply 0.95 1.00 1.05 V Cl xCORE Tile I/O load capacitance Ambient operating temperature (Commercial) Ta Ambient operating temperature (Industrial) Figure 19: Operating conditions Tj Junction temperature Tstg Storage temperature 14.2 Figure 20: DC characteristics A B C D X009587, pF 0 70 °C -40 85 °C 125 °C -65 150 °C DC Characteristics Symbol Parameter MIN MAX UNITS Notes V(IH) Input high voltage 2.00 3.60 V A V(IL) Input low voltage -0.30 0.70 V A V(OH) Output high voltage V B, C V(OL) Output low voltage V B, C R(PU) Pull-up resistance 35K Ω D R(PD) Pull-down resistance 35K Ω TYP D 2.20 0.40 All pins except power supply pins. All general-purpose I/Os are nominal 4 mA. Measured with 4 mA drivers sourcing 4 mA, 8 mA drivers sourcing 8 mA. Used to guarantee logic state for an I/O when high impedance. The internal pull-ups/pull-downs should not be used to pull external circuitry. 14.3 Figure 21: ESD stress voltage 25 Notes ESD Stress Voltage Symbol Parameter HBM Human body model CDM Charged Device Model MAX UNITS -2.00 MIN TYP 2.00 KV -500 500 Notes V XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 14.4 Figure 22: Reset timing 28 Reset Timing Symbol Parameters MIN T(RST) Reset pulse width 5 T(INIT) Initialization time TYP MAX UNITS Notes µs 150 µs A A Shows the time taken to start booting after RST_N has gone high. 14.5 Power Consumption Symbol Parameter UNITS Notes I(DDCQ) Quiescent VDD current PD Tile power dissipation 45 mA A, B, C 325 µW/MIPS Active VDD current () TBC A, D, E, F mA Active VDD current () A, G 1140 1400 mA I(ADDPLL) A, H PLL_AVDD current 5 mA I I(VDD33) VDD33 current 53.4 mA J I(USB_VDD) USB_VDD current 16.6 mA K IDD Figure 23: xCORE Tile currents MIN TYP MAX TBC 7 A B C D E F G Use for budgetary purposes only. Assumes typical tile and I/O voltages with no switching activity. Includes PLL current. Assumes typical tile and I/O voltages with nominal switching activity. Assumes 1 MHz = 1 MIPS. PD(TYP) value is the usage power consumption under typical operating conditions. Measurement conditions: VDD = 1.0 V, VDDIO = 3.3 V, 25 °C, 400 MHz, average device resource usage. H Measurement conditions: VDD = 1.0 V, VDDIO = 3.3 V, 25 °C, 500 MHz, average device resource usage. I PLL_AVDD = 1.0 V J HS mode transmitting while driving all 0’s data (constant JKJK on DP/DM). Loading of 10 pF. Transfers do not include any interpacket delay. K HS receive mode; no traffic. The tile power consumption of the device is highly application dependent and should be used for budgetary purposes only. More detailed power analysis can be found in the XS1-UEF Power Consumption document, X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 14.6 Figure 24: Clock 29 Clock Symbol Parameter MIN TYP MAX UNITS f Frequency 3.25 24 100 MHz SR Slew rate 0.10 TJ(LT) Long term jitter (pk-pk) 2 % A Processor clock frequency () 400 MHz B Processor clock frequency 500 MHz B f(MAX) Notes V/ns A Percentage of CLK period. B Assumes typical tile and I/O voltages with nominal activity. Further details can be found in the XS1-UEF Clock Frequency Control document, 14.7 Figure 25: I/O AC characteristics xCORE Tile I/O AC Characteristics Symbol Parameter MIN TYP MAX UNITS T(XOVALID) Input data valid window 8 T(XOINVALID) Output data invalid window 9 T(XIFMAX) Rate at which data can be sampled with respect to an external clock Notes ns ns 60 MHz The input valid window parameter relates to the capability of the device to capture data input to the chip with respect to an external clock source. It is calculated as the sum of the input setup time and input hold time with respect to the external clock as measured at the pins. The output invalid window specifies the time for which an output is invalid with respect to the external clock. Note that these parameters are specified as a window rather than absolute numbers since the device provides functionality to delay the incoming clock with respect to the incoming data. Information on interfacing to high-speed synchronous interfaces can be found in the XS1 Port I/O Timing document, X5821. 14.8 Figure 26: Link performance xConnect Link Performance Symbol Parameter MAX UNITS Notes B(2blinkP) 2b link bandwidth (packetized) MIN TYP 87 MBit/s A, B B(5blinkP) 5b link bandwidth (packetized) 217 MBit/s A, B B(2blinkS) 2b link bandwidth (streaming) 100 MBit/s B B(5blinkS) 5b link bandwidth (streaming) 250 MBit/s B A Assumes 32-byte packet in 3-byte header mode. Actual performance depends on size of the header and payload. B 7.5 ns symbol time. The asynchronous nature of links means that the relative phasing of CLK clocks is not important in a multi-clock system, providing each meets the required stability criteria. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 14.9 Figure 27: JTAG timing 30 JTAG Timing Symbol Parameter f(TCK_D) TCK frequency (debug) MIN TYP MAX UNITS 18 MHz 10 MHz f(TCK_B) TCK frequency (boundary scan) T(SETUP) TDO to TCK setup time 5 ns A T(HOLD) TDO to TCK hold time 5 ns A T(DELAY) TCK to output delay ns B 15 Notes A Timing applies to TMS and TDI inputs. B Timing applies to TDO output from negative edge of TCK. All JTAG operations are synchronous to TCK. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 15 31 Package Information X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 15.1 Part Marking FXCCRNTM MCYYWWXX Figure 28: Part marking scheme 16 32 LLLLLL.LL F - Product family X - Reserved CC - Number of logical cores R - RAM (in log-2) N - Flash size T - Temperature grade M - Speed grade MC - Manufacturer YYWW - Date XX - Reserved Wafer lot code Ordering Information Figure 29: Orderable part numbers X009587, Product Code XEF232-1024-FB374-C40 XEF232-1024-FB374-I40 Marking E032A2C40 E032A2I40 Qualification Commercial Industrial Speed Grade 2000 MIPS 2000 MIPS XS2-UEF32A-1024-FB374 PRELIMINARY xTIME scheduler Hardware response ports XEF232-1024-FB374 Datasheet xCORE logical core A 33 xCORE logical core Processor status xCORE logical core I/O pins Hardware response ports Tile configuration xCORE logical core JTAG xTIME scheduler xCORE logical core Tile configuration Processor status xCORE logical core Appendices PLL Node configuration xCONNECT Switch I/O pins xCORE logical core FLASH xCORE logical core xCORE logical core XEF232-1024-FB374 xCORE logical core Configuration of the xCORE logical core xCORE logical core TheUSB device is configured through banks of registers, as shown in Figure 30. USB RGMII config OTP OTP SRAM SRAM OTP OTP SRAM xCORE logical core xCORE logical core Figure 30: Registers I/O pins xTIME scheduler Hardware response ports PLL JTAG Tile configuration xCORE logical core Node configuration Processor status xCORE logical core xCORE logical core Tile configuration xCORE logical core xCORE logical core RGMII xCORE logical core xCORE logical core Processor status USB USB config SRAM xCORE logical core FLASH xCORE logical core xCORE logical core xTIME scheduler I/O pins Hardware response ports The following communication sequences specify how to access those registers. Any messages transmitted contain the most significant 24 bits of the channel-end to which a response is to be sent. This comprises the node-identifier and the channel number within the node. if no response is required on a write operation, supply 24-bits with the last 8-bits set, which suppresses the reply message. Any multi-byte data is sent most significant byte first. A.1 Accessing a processor status register The processor status registers are accessed directly from the processor instruction set. The instructions GETPS and SETPS read and write a word. The register number should be translated into a processor-status resource identifier by shifting the register number left 8 places, and ORing it with 0x0C. Alternatively, the functions getps(reg) and setps(reg,value) can be used from XC. A.2 Accessing an xCORE Tile configuration register xCORE Tile configuration registers can be accessed through the interconnect using the functions write_tile_config_reg(tileref, ...) and read_tile_config_reg(tile > ref, ...), where tileref is the name of the xCORE Tile, e.g. tile[1]. These functions implement the protocols described below. Instead of using the functions above, a channel-end can be allocated to communicate with the xCORE tile configuration registers. The destination of the channel-end should be set to 0xnnnnC20C where nnnnnn is the tile-identifier. A write message comprises the following: X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet control-token 24-bit response 16-bit 32-bit control-token 192 channel-end identifier register number data 1 34 The response to a write message comprises either control tokens 3 and 1 (for success), or control tokens 4 and 1 (for failure). A read message comprises the following: control-token 24-bit response 16-bit control-token 193 channel-end identifier register number 1 The response to the read message comprises either control token 3, 32-bit of data, and control-token 1 (for success), or control tokens 4 and 1 (for failure). A.3 Accessing node configuration Node configuration registers can be accessed through the interconnect using the functions write_node_config_reg(device, ...) and read_node_config_reg(device, > ...), where device is the name of the node. These functions implement the protocols described below. Instead of using the functions above, a channel-end can be allocated to communicate with the node configuration registers. The destination of the channel-end should be set to 0xnnnnC30C where nnnn is the node-identifier. A write message comprises the following: control-token 24-bit response 16-bit 32-bit control-token 192 channel-end identifier register number data 1 The response to a write message comprises either control tokens 3 and 1 (for success), or control tokens 4 and 1 (for failure). A read message comprises the following: control-token 24-bit response 16-bit control-token 193 channel-end identifier register number 1 The response to a read message comprises either control token 3, 32-bit of data, and control-token 1 (for success), or control tokens 4 and 1 (for failure). A.4 Accessing a register of an analogue peripheral Peripheral registers can be accessed through the interconnect using the functions write_periph_32(device, peripheral, ...), read_periph_32(device, peripheral, ...) > , write_periph_8(device, peripheral, ...), and read_periph_8(device, peripheral > , ...); where device is the name of the analogue device, and peripheral is the number of the peripheral. These functions implement the protocols described below. A channel-end should be allocated to communicate with the configuration registers. The destination of the channel-end should be set to 0xnnnnpp02 where nnnn is the node-identifier and pp is the peripheral identifier. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 35 A write message comprises the following: control-token 24-bit response 8-bit 8-bit 36 channel-end identifier register number size data control-token 1 The response to a write message comprises either control tokens 3 and 1 (for success), or control tokens 4 and 1 (for failure). A read message comprises the following: control-token 24-bit response 8-bit 8-bit control-token 37 channel-end identifier register number size 1 The response to the read message comprises either control token 3, data, and control-token 1 (for success), or control tokens 4 and 1 (for failure). X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet B 36 Processor Status Configuration The processor status control registers can be accessed directly by the processor using processor status reads and writes (use getps(reg) and setps(reg,value) for reads and writes). Number Figure 31: Summary X009587, Perm Description 0x00 RW RAM base address 0x01 RW Vector base address 0x02 RW xCORE Tile control 0x03 RO xCORE Tile boot status 0x05 RW Security configuration 0x06 RW Ring Oscillator Control 0x07 RO Ring Oscillator Value 0x08 RO Ring Oscillator Value 0x09 RO Ring Oscillator Value 0x0A RO Ring Oscillator Value 0x0C RO RAM size 0x10 DRW Debug SSR 0x11 DRW Debug SPC 0x12 DRW Debug SSP 0x13 DRW DGETREG operand 1 0x14 DRW DGETREG operand 2 0x15 DRW Debug interrupt type 0x16 DRW Debug interrupt data 0x18 DRW Debug core control 0x20 .. 0x27 DRW Debug scratch 0x30 .. 0x33 DRW Instruction breakpoint address 0x40 .. 0x43 DRW Instruction breakpoint control 0x50 .. 0x53 DRW Data watchpoint address 1 0x60 .. 0x63 DRW Data watchpoint address 2 0x70 .. 0x73 DRW Data breakpoint control register 0x80 .. 0x83 DRW Resources breakpoint mask 0x90 .. 0x93 DRW Resources breakpoint value 0x9C .. 0x9F DRW Resources breakpoint control register XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet B.1 37 RAM base address: 0x00 This register contains the base address of the RAM. It is initialized to 0x00040000. 0x00: RAM base address Bits Perm 31:2 RW 1:0 RO B.2 Init Description Most significant 16 bits of all addresses. - Reserved Vector base address: 0x01 Base address of event vectors in each resource. On an interrupt or event, the 16 most significant bits of the destination address are provided by this register; the least significant 16 bits come from the event vector. 0x01: Vector base address Bits Perm 31:18 RW 17:0 RO B.3 Init Description The event and interrupt vectors. - Reserved xCORE Tile control: 0x02 Register to control features in the xCORE tile X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Bits Perm Init 38 Description 31:26 RO - 25:18 RW 0 RGMII TX data delay value (in PLL output cycle increments) 17:9 RW 0 RGMII TX clock divider value. TX clk rises when counter (clocked by PLL output) reaches this value and falls when counter reaches (value»1). Value programmed into this field should be actual divide value required minus 1 8 RW 0 Enable RGMII interface periph ports 0x02: xCORE Tile control B.4 Reserved 7:6 RO - 5 RW 0 Reserved Select the dynamic mode (1) for the clock divider when the clock divider is enabled. In dynamic mode the clock divider is only activated when all active threads are paused. In static mode the clock divider is always enabled. 4 RW 0 Enable the clock divider. This divides the output of the PLL to facilitate one of the low power modes. 3 RO - Reserved 2 RW Select between UTMI (1) and ULPI (0) mode. 1 RW Enable the ULPI Hardware support module 0 RO - Reserved xCORE Tile boot status: 0x03 This read-only register describes the boot status of the xCORE tile. Bits 0x03: xCORE Tile boot status X009587, Perm 31:24 RO 23:16 RO 15:9 RO Init - Description Reserved Processor number. - Reserved 8 RO 7:6 RO Overwrite BOOT_MODE. 5 RO Indicates if core1 has been powered off 4 RO Cause the ROM to not poll the OTP for correct read levels 3 RO Boot ROM boots from RAM 2 RO Boot ROM boots from JTAG 1:0 RO The boot PLL mode pin value. - Reserved XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet B.5 39 Security configuration: 0x05 Copy of the security register as read from OTP. Bits Perm Init Description 31 RW 30:15 RO 14 RW 13 RO 12 RW lock all OTP sectors 11:8 RW lock bit for each OTP sector 7 RW Enable OTP reduanacy 6 RO 5 RW Override boot mode and read boot image from OTP 4 RW Disable JTAG access to the PLL/BOOT configuration registers 0x05: Security configuration 3:1 RO 0 RW B.6 Disables write permission on this register - Reserved Disable access to XCore’s global debug - - - Reserved Reserved Reserved Disable access to XCore’s JTAG debug TAP Ring Oscillator Control: 0x06 There are four free-running oscillators that clock four counters. The oscillators can be started and stopped using this register. The counters should only be read when the ring oscillator has been stopped for at least 10 core clock cycles (this can be achieved by inserting two nop instructions between the SETPS and GETPS). The counter values can be read using four subsequent registers. The ring oscillators are asynchronous to the xCORE tile clock and can be used as a source of random bits. Bits 0x06: Ring Oscillator Control Perm Init Description 31:2 RO - 1 RW 0 Core ring oscillator enable. 0 RW 0 Peripheral ring oscillator enable. B.7 Reserved Ring Oscillator Value: 0x07 This register contains the current count of the xCORE Tile Cell ring oscillator. This value is not reset on a system reset. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0x07: Ring Oscillator Value Bits Perm Init 31:16 RO - 15:0 RO 0 B.8 40 Description Reserved Ring oscillator Counter data. Ring Oscillator Value: 0x08 This register contains the current count of the xCORE Tile Wire ring oscillator. This value is not reset on a system reset. 0x08: Ring Oscillator Value Bits Perm Init 31:16 RO - 15:0 RO 0 B.9 Description Reserved Ring oscillator Counter data. Ring Oscillator Value: 0x09 This register contains the current count of the Peripheral Cell ring oscillator. This value is not reset on a system reset. 0x09: Ring Oscillator Value Bits Perm Init 31:16 RO - 15:0 RO 0 B.10 Description Reserved Ring oscillator Counter data. Ring Oscillator Value: 0x0A This register contains the current count of the Peripheral Wire ring oscillator. This value is not reset on a system reset. 0x0A: Ring Oscillator Value Bits Perm Init 31:16 RO - 15:0 RO 0 B.11 Description Reserved Ring oscillator Counter data. RAM size: 0x0C The size of the RAM in bytes X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0x0C: RAM size Bits Perm 31:2 RO 1:0 RO B.12 Init 41 Description Most significant 16 bits of all addresses. - Reserved Debug SSR: 0x10 This register contains the value of the SSR register when the debugger was called. Bits 31:11 Perm Init RO - Description Reserved 10 DRW Address space indentifier 9 DRW Determines the issue mode (DI bit) upon Kernel Entry after Exception or Interrupt. 0x10: Debug SSR 8 RO 7 DRW When 1 the thread is in fast mode and will continually issue. 6 DRW When 1 the thread is paused waiting for events, a lock or another resource. 5 RO 4 DRW 1 when in kernel mode. 3 DRW 1 when in an interrupt handler. 2 DRW 1 when in an event enabling sequence. 1 DRW When 1 interrupts are enabled for the thread. 0 DRW When 1 events are enabled for the thread. B.13 Determines the issue mode (DI bit). - Reserved Debug SPC: 0x11 This register contains the value of the SPC register when the debugger was called. 0x11: Debug SPC Bits Perm 31:0 DRW B.14 Init Description Value. Debug SSP: 0x12 This register contains the value of the SSP register when the debugger was called. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0x12: Debug SSP Bits Perm 31:0 DRW B.15 Init 42 Description Value. DGETREG operand 1: 0x13 The resource ID of the logical core whose state is to be read. 0x13: DGETREG operand 1 Bits 31:8 7:0 B.16 Perm RO Init Description - Reserved DRW Thread number to be read DGETREG operand 2: 0x14 Register number to be read by DGETREG 0x14: DGETREG operand 2 Bits Perm 31:5 RO 4:0 B.17 Init Description - Reserved DRW Register number to be read Debug interrupt type: 0x15 Register that specifies what activated the debug interrupt. Bits 0x15: Debug interrupt type X009587, Perm Init - Description 31:18 RO 17:16 DRW Number of the hardware breakpoint/watchpoint which caused the interrupt (always 0 for =HOST= and =DCALL=). If multiple breakpoints/watchpoints trigger at once, the lowest number is taken. 15:8 DRW Number of thread which caused the debug interrupt (always 0 in the case of =HOST=). 7:3 RO - 2:0 DRW 0 Reserved Reserved Indicates the cause of the debug interrupt 1: Host initiated a debug interrupt through JTAG 2: Program executed a DCALL instruction 3: Instruction breakpoint 4: Data watch point 5: Resource watch point XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet B.18 43 Debug interrupt data: 0x16 On a data watchpoint, this register contains the effective address of the memory operation that triggered the debugger. On a resource watchpoint, it countains the resource identifier. 0x16: Debug interrupt data Bits Perm 31:0 DRW B.19 Init Description Value. Debug core control: 0x18 This register enables the debugger to temporarily disable logical cores. When returning from the debug interrupts, the cores set in this register will not execute. This enables single stepping to be implemented. 0x18: Debug core control Bits Perm 31:8 RO 7:0 B.20 Init - DRW Description Reserved 1-hot vector defining which threads are stopped when not in debug mode. Every bit which is set prevents the respective thread from running. Debug scratch: 0x20 .. 0x27 A set of registers used by the debug ROM to communicate with an external debugger, for example over JTAG. This is the same set of registers as the Debug Scratch registers in the xCORE tile configuration. 0x20 .. 0x27: Debug scratch Bits Perm 31:0 DRW B.21 Init Description Value. Instruction breakpoint address: 0x30 .. 0x33 This register contains the address of the instruction breakpoint. If the PC matches this address, then a debug interrupt will be taken. There are four instruction breakpoints that are controlled individually. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0x30 .. 0x33: Instruction breakpoint address Bits Perm 31:0 DRW B.22 Init 44 Description Value. Instruction breakpoint control: 0x40 .. 0x43 This register controls which logical cores may take an instruction breakpoint, and under which condition. Bits 0x40 .. 0x43: Instruction breakpoint control Perm Init Description 31:24 RO - 23:16 DRW 0 RO - 1 DRW 0 When 0 break when PC == IBREAK_ADDR. When 1 = break when PC != IBREAK_ADDR. 0 DRW 0 When 1 the instruction breakpoint is enabled. 15:2 B.23 Reserved A bit for each thread in the machine allowing the breakpoint to be enabled individually for each thread. Reserved Data watchpoint address 1: 0x50 .. 0x53 This set of registers contains the first address for the four data watchpoints. 0x50 .. 0x53: Data watchpoint address 1 Bits Perm 31:0 DRW B.24 Init Description Value. Data watchpoint address 2: 0x60 .. 0x63 This set of registers contains the second address for the four data watchpoints. 0x60 .. 0x63: Data watchpoint address 2 X009587, Bits Perm 31:0 DRW Init Description Value. XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet B.25 45 Data breakpoint control register: 0x70 .. 0x73 This set of registers controls each of the four data watchpoints. Bits 0x70 .. 0x73: Data breakpoint control register Perm Init 31:24 RO - 23:16 DRW 0 RO - 15:3 Description Reserved A bit for each thread in the machine allowing the breakpoint to be enabled individually for each thread. Reserved 2 DRW 0 When 1 the breakpoints will be be triggered on loads. 1 DRW 0 Determines the break condition: 0 = A AND B, 1 = A OR B. 0 DRW 0 When 1 the instruction breakpoint is enabled. B.26 Resources breakpoint mask: 0x80 .. 0x83 This set of registers contains the mask for the four resource watchpoints. 0x80 .. 0x83: Resources breakpoint mask Bits Perm 31:0 DRW B.27 Init Description Value. Resources breakpoint value: 0x90 .. 0x93 This set of registers contains the value for the four resource watchpoints. 0x90 .. 0x93: Resources breakpoint value Bits Perm 31:0 DRW B.28 Init Description Value. Resources breakpoint control register: 0x9C .. 0x9F This set of registers controls each of the four resource watchpoints. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Bits 0x9C .. 0x9F: Resources breakpoint control register X009587, Perm Init 31:24 RO - 23:16 DRW 0 15:2 46 Description Reserved A bit for each thread in the machine allowing the breakpoint to be enabled individually for each thread. RO - 1 DRW 0 Reserved When 0 break when condition A is met. When 1 = break when condition B is met. 0 DRW 0 When 1 the instruction breakpoint is enabled. XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet C 47 Tile Configuration The xCORE Tile control registers can be accessed using configuration reads and writes (use write_tile_config_reg(tileref, ...) and read_tile_config_reg(tileref, > ...) for reads and writes). Number Perm Description 0x00 CRO Device identification 0x01 CRO xCORE Tile description 1 0x02 CRO xCORE Tile description 2 0x04 CRW Control PSwitch permissions to debug registers 0x05 CRW Cause debug interrupts 0x06 CRW xCORE Tile clock divider 0x07 CRO Security configuration 0x20 .. 0x27 CRW Debug scratch 0x40 CRO PC of logical core 0 0x41 CRO PC of logical core 1 Figure 32: Summary C.1 0x42 CRO PC of logical core 2 0x43 CRO PC of logical core 3 0x44 CRO PC of logical core 4 0x45 CRO PC of logical core 5 0x46 CRO PC of logical core 6 0x47 CRO PC of logical core 7 0x60 CRO SR of logical core 0 0x61 CRO SR of logical core 1 0x62 CRO SR of logical core 2 0x63 CRO SR of logical core 3 0x64 CRO SR of logical core 4 0x65 CRO SR of logical core 5 0x66 CRO SR of logical core 6 0x67 CRO SR of logical core 7 Device identification: 0x00 This register identifies the xCORE Tile X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0x00: Device identification Bits Perm 31:24 CRO Processor ID of this XCore. 23:16 CRO Number of the node in which this XCore is located. 15:8 CRO XCore revision. 7:0 CRO XCore version. C.2 Init 48 Description xCORE Tile description 1: 0x01 This register describes the number of logical cores, synchronisers, locks and channel ends available on this xCORE tile. 0x01: xCORE Tile description 1 Bits Perm 31:24 CRO Number of channel ends. 23:16 CRO Number of the locks. 15:8 CRO Number of synchronisers. 7:0 C.3 RO Init - Description Reserved xCORE Tile description 2: 0x02 This register describes the number of timers and clock blocks available on this xCORE tile. Bits 0x02: xCORE Tile description 2 31:16 Perm RO Init - Description Reserved 15:8 CRO Number of clock blocks. 7:0 CRO Number of timers. C.4 Control PSwitch permissions to debug registers: 0x04 This register can be used to control whether the debug registers (marked with permission CRW) are accessible through the tile configuration registers. When this bit is set, write -access to those registers is disabled, preventing debugging of the xCORE tile over the interconnect. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0x04: Control PSwitch permissions to debug registers Bits Perm Init 31 CRW 0 RO - CRW 0 30:1 0 C.5 49 Description When 1 the PSwitch is restricted to RO access to all CRW registers from SSwitch, XCore(PS_DBG_Scratch) and JTAG Reserved When 1 the PSwitch is restricted to RO access to all CRW registers from SSwitch Cause debug interrupts: 0x05 This register can be used to raise a debug interrupt in this xCORE tile. Bits 0x05: Cause debug interrupts Perm 31:2 C.6 Init Description RO - 1 CRW 0 Reserved 1 when the processor is in debug mode. 0 CRW 0 Request a debug interrupt on the processor. xCORE Tile clock divider: 0x06 This register contains the value used to divide the PLL clock to create the xCORE tile clock. The divider is enabled under control of the tile control register 0x06: xCORE Tile clock divider Bits Perm Init 31 CRW 0 30:16 15:0 C.7 RO - CRW 0 Description Clock disable. Writing ’1’ will remove the clock to the tile. Reserved Clock divider. Security configuration: 0x07 Copy of the security register as read from OTP. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Bits Perm 31 CRO 30:15 Init CRO 13 RO Description Disables write permission on this register RO 14 - Reserved Disable access to XCore’s global debug - Reserved 12 CRO lock all OTP sectors 11:8 CRO lock bit for each OTP sector 7 CRO Enable OTP reduanacy 0x07: Security configuration 6 RO 5 CRO Override boot mode and read boot image from OTP 4 CRO Disable JTAG access to the PLL/BOOT configuration registers 3:1 0 C.8 50 - RO - CRO Reserved Reserved Disable access to XCore’s JTAG debug TAP Debug scratch: 0x20 .. 0x27 A set of registers used by the debug ROM to communicate with an external debugger, for example over the switch. This is the same set of registers as the Debug Scratch registers in the processor status. 0x20 .. 0x27: Debug scratch Bits Perm 31:0 CRW C.9 Init Description Value. PC of logical core 0: 0x40 Value of the PC of logical core 0. 0x40: PC of logical core 0 Bits Perm 31:0 CRO C.10 Init Description Value. PC of logical core 1: 0x41 Value of the PC of logical core 1. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0x41: PC of logical core 1 Bits Perm 31:0 CRO C.11 Init 51 Description Value. PC of logical core 2: 0x42 Value of the PC of logical core 2. 0x42: PC of logical core 2 Bits Perm 31:0 CRO C.12 Init Description Value. PC of logical core 3: 0x43 Value of the PC of logical core 3. 0x43: PC of logical core 3 Bits Perm 31:0 CRO C.13 Init Description Value. PC of logical core 4: 0x44 Value of the PC of logical core 4. 0x44: PC of logical core 4 Bits Perm 31:0 CRO C.14 Init Description Value. PC of logical core 5: 0x45 Value of the PC of logical core 5. 0x45: PC of logical core 5 X009587, Bits Perm 31:0 CRO Init Description Value. XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet C.15 52 PC of logical core 6: 0x46 Value of the PC of logical core 6. 0x46: PC of logical core 6 Bits Perm 31:0 CRO C.16 Init Description Value. PC of logical core 7: 0x47 Value of the PC of logical core 7. 0x47: PC of logical core 7 Bits Perm 31:0 CRO C.17 Init Description Value. SR of logical core 0: 0x60 Value of the SR of logical core 0 0x60: SR of logical core 0 Bits Perm 31:0 CRO C.18 Init Description Value. SR of logical core 1: 0x61 Value of the SR of logical core 1 0x61: SR of logical core 1 Bits Perm 31:0 CRO C.19 Init Description Value. SR of logical core 2: 0x62 Value of the SR of logical core 2 X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0x62: SR of logical core 2 Bits Perm 31:0 CRO C.20 Init 53 Description Value. SR of logical core 3: 0x63 Value of the SR of logical core 3 0x63: SR of logical core 3 Bits Perm 31:0 CRO C.21 Init Description Value. SR of logical core 4: 0x64 Value of the SR of logical core 4 0x64: SR of logical core 4 Bits Perm 31:0 CRO C.22 Init Description Value. SR of logical core 5: 0x65 Value of the SR of logical core 5 0x65: SR of logical core 5 Bits Perm 31:0 CRO C.23 Init Description Value. SR of logical core 6: 0x66 Value of the SR of logical core 6 0x66: SR of logical core 6 X009587, Bits Perm 31:0 CRO Init Description Value. XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet C.24 54 SR of logical core 7: 0x67 Value of the SR of logical core 7 0x67: SR of logical core 7 X009587, Bits Perm 31:0 CRO Init Description Value. XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet D 55 Node Configuration The digital node control registers can be accessed using configuration reads and writes (use write_node_config_reg(device, ...) and read_node_config_reg(device, > ...) for reads and writes). Number 0x00 Figure 33: Summary Perm Description RO Device identification 0x01 RO System switch description 0x04 RW Switch configuration 0x05 RW Switch node identifier 0x06 RW PLL settings 0x07 RW System switch clock divider 0x08 RW Reference clock 0x09 R System JTAG device ID register 0x0A R System USERCODE register 0x0C RW Directions 0-7 0x0D RW Directions 8-15 0x10 RW Reserved 0x11 RW Reserved. 0x1F RO Debug source 0x20 .. 0x28 RW Link status, direction, and network 0x40 .. 0x47 RO PLink status and network 0x80 .. 0x88 RW Link configuration and initialization 0xA0 .. 0xA7 RW Static link configuration D.1 Device identification: 0x00 This register contains version and revision identifiers and the mode-pins as sampled at boot-time. Bits 0x00: Device identification X009587, Perm Init - Description 31:24 RO 23:16 RO Reserved Sampled values of BootCtl pins on Power On Reset. 15:8 RO SSwitch revision. 7:0 RO SSwitch version. XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet D.2 56 System switch description: 0x01 This register specifies the number of processors and links that are connected to this switch. Bits 0x01: System switch description Perm Init RO 23:16 RO Number of SLinks on the SSwitch. 15:8 RO Number of processors on the SSwitch. 7:0 RO Number of processors on the device. D.3 - Description 31:24 Reserved Switch configuration: 0x04 This register enables the setting of two security modes (that disable updates to the PLL or any other registers) and the header-mode. Bits Perm 31 0x04: Switch configuration RW Init 0 30:9 RO - 8 RW 0 7:1 RO - 0 RW 0 D.4 Description 0 = SSCTL registers have write access. 1 = SSCTL registers can not be written to. Reserved 0 = PLL_CTL_REG has write access. 1 = PLL_CTL_REG can not be written to. Reserved 0 = 2-byte headers, 1 = 1-byte headers (reset as 0). Switch node identifier: 0x05 This register contains the node identifier. 0x05: Switch node identifier Bits Perm Init 31:16 RO - 15:0 RW 0 D.5 Description Reserved The unique ID of this node. PLL settings: 0x06 An on-chip PLL multiplies the input clock up to a higher frequency clock, used to clock the I/O, processor, and switch, see Oscillator. Note: a write to this register will cause the tile to be reset. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Bits Perm Init 57 Description 31 RW If set to 1, the chip will not be reset 30 RW If set to 1, the chip will not wait for the PLL to re-lock. Only use this if a gradual change is made to the PLL 29 DW If set to 1, set the PLL to be bypassed 28 DW If set to 1, set the boot mode to boot from JTAG 27:26 RO 25:23 RW 22:21 RO 20:8 RW 7 RO 6:0 RW 0x06: PLL settings D.6 - Reserved Output divider value range from 1 (8’h0) to 250 (8’hF9). P value. - Reserved Feedback multiplication ratio, range from 1 (8’h0) to 255 (8’hFE). M value. - Reserved Oscilator input divider value range from 1 (8’h0) to 32 (8’h0F). N value. System switch clock divider: 0x07 Sets the ratio of the PLL clock and the switch clock. 0x07: System switch clock divider Bits Perm Init 31:16 RO - 15:0 RW 0 D.7 Description Reserved SSwitch clock generation Reference clock: 0x08 Sets the ratio of the PLL clock and the reference clock used by the node. 0x08: Reference clock X009587, Bits Perm Init 31:16 RO - 15:0 RW 3 Description Reserved Software ref. clock divider XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet D.8 System JTAG device ID register: 0x09 Bits 0x09: System JTAG device ID register Perm 31:28 RO 27:12 RO 11:1 RO 0 RO D.9 0x0A: System USERCODE register 58 Init Description System USERCODE register: 0x0A Bits Perm Init Description 31:18 RO JTAG USERCODE value programmed into OTP SR 17:0 RO metal fixable ID code D.10 Directions 0-7: 0x0C This register contains eight directions, for packets with a mismatch in bits 7..0 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit. Bits 0x0C: Directions 0-7 Perm Init Description 31:28 RW 0 The direction for packets whose dimension is 7. 27:24 RW 0 The direction for packets whose dimension is 6. 23:20 RW 0 The direction for packets whose dimension is 5. 19:16 RW 0 The direction for packets whose dimension is 4. 15:12 RW 0 The direction for packets whose dimension is 3. 11:8 RW 0 The direction for packets whose dimension is 2. 7:4 RW 0 The direction for packets whose dimension is 1. 3:0 RW 0 The direction for packets whose dimension is 0. D.11 Directions 8-15: 0x0D This register contains eight directions, for packets with a mismatch in bits 15..8 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Bits 0x0D: Directions 8-15 Perm Init Description 31:28 RW 0 The direction for packets whose dimension is F. 27:24 RW 0 The direction for packets whose dimension is E. 23:20 RW 0 The direction for packets whose dimension is D. 19:16 RW 0 The direction for packets whose dimension is C. 15:12 RW 0 The direction for packets whose dimension is B. 11:8 RW 0 The direction for packets whose dimension is A. 7:4 RW 0 The direction for packets whose dimension is 9. 3:0 RW 0 The direction for packets whose dimension is 8. D.12 59 Reserved: 0x10 Reserved. Bits 0x10: Reserved Perm Init Description 31:2 RO - Reserved 1 RW 0 Reserved. 0 RW 0 Reserved. D.13 Reserved.: 0x11 Reserved. 0x11: Reserved. Bits Perm 31:2 RO - Reserved 1 RW 0 Reserved. 0 RW 0 Reserved. D.14 Init Description Debug source: 0x1F Contains the source of the most recent debug event. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0x1F: Debug source Bits Perm 31:5 RO Init Description - Reserved 4 RW 3:2 RO 1 RW If set, XCore1 is the source of last GlobalDebug event. 0 RW If set, XCore0 is the source of last GlobalDebug event. D.15 60 Reserved. - Reserved Link status, direction, and network: 0x20 .. 0x28 These registers contain status information for low level debugging (read-only), the network number that each link belongs to, and the direction that each link is part of. The registers control links 0..7. Bits Perm Init RO 25:24 RO Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 Undefine. 23:16 RO When the link is in use, this is the destination link number to which all packets are sent. 15:12 RO - 11:8 RW 0 7:6 RO - 5:4 RW 0 3 RO - 2 RO 1 when the current packet is considered junk and will be thrown away. 1 RO 1 when the dest side of the link is in use. 0 RO 1 when the source side of the link is in use. 0x20 .. 0x28: Link status, direction, and network D.16 - Description 31:26 Reserved Reserved The direction that this link operates in. Reserved Determines the network to which this link belongs, reset as 0. Reserved PLink status and network: 0x40 .. 0x47 These registers contain status information and the network number that each processor-link belongs to. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Bits Perm Init - 61 Description 31:26 RO Reserved 25:24 RO Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 Undefine. 23:16 RO When the link is in use, this is the destination link number to which all packets are sent. 15:6 RO - 5:4 RW 0 3 RO - 2 RO 1 when the current packet is considered junk and will be thrown away. 1 RO 1 when the dest side of the link is in use. 0 RO 1 when the source side of the link is in use. 0x40 .. 0x47: PLink status and network D.17 Reserved Determines the network to which this link belongs, reset as 0. Reserved Link configuration and initialization: 0x80 .. 0x88 These registers contain configuration and debugging information specific to external links. The link speed and width can be set, the link can be initialized, and the link status can be monitored. The registers control links 0..7. Bits 0x80 .. 0x88: Link configuration and initialization X009587, Perm Init Description 31 RW Write to this bit with ’1’ will enable the XLink, writing ’0’ will disable it. This bit controls the muxing of ports with overlapping xlinks. 30 RW 0 29:28 RO - 27 RO 26 RO 0 This end of the xlink has issued credit to allow the remote end to transmit 25 RO 0 This end of the xlink has credit to allow it to transmit. 24 WO Clear this end of the xlink’s credit and issue a HELLO token. 23 WO Reset the receiver. The next symbol that is detected will be the first symbol in a token. 0: operate in 2 wire mode; 1: operate in 5 wire mode Reserved Rx buffer overflow or illegal token encoding received. 22 RO - 21:11 RW 0 Reserved Specify min. number of idle system clocks between two continuous symbols witin a transmit token -1. 10:0 RW 0 Specify min. number of idle system clocks between two continuous transmit tokens -1. XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet D.18 62 Static link configuration: 0xA0 .. 0xA7 These registers are used for static (ie, non-routed) links. When a link is made static, all traffic is forwarded to the designated channel end and no routing is attempted. The registers control links C, D, A, B, G, H, E, and F in that order. Bits 0xA0 .. 0xA7: Static link configuration X009587, Perm Init 31 RW 0 30:9 RO - 8 RW 0 7:5 RO - 4:0 RW 0 Description Enable static forwarding. Reserved The destination processor on this node that packets received in static mode are forwarded to. Reserved The destination channel end on this node that packets received in static mode are forwarded to. XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet E 63 USB Node Configuration The USB node control registers can be accessed using configuration reads and writes (use write_node_config_reg(device, ...) and read_node_config_reg(device, > ...) for reads and writes). Number Figure 34: Summary Perm Description 0x00 RO Device identification register 0x04 RW Node configuration register 0x05 RW Node identifier 0x51 RW System clock frequency 0x80 RW Link Control and Status E.1 Device identification register: 0x00 This register contains version information, and information on power-on behavior. Bits 0x00: Device identification register Perm Init Description 31:24 RO 0x0F 23:16 RO - 15:8 RO 0x02 Revision number of the USB block 7:0 RO 0x00 Version number of the USB block E.2 Chip identifier Reserved Node configuration register: 0x04 This register is used to set the communication model to use (1 or 3 byte headers), and to prevent any further updates. Bits 0x04: Node configuration register X009587, Perm Init 31 RW 0 30:1 RO - 0 RW 0 Description Set to 1 to disable further updates to the node configuration and link control and status registers. Reserved Header mode. 0: 3-byte headers; 1: 1-byte headers. XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet E.3 Node identifier: 0x05 Bits 0x05: Node identifier Perm Init 31:16 RO - 15:0 RW 0 E.4 Bits Perm RO Init - 6:0 RW 25 16-bit node identifier. This does not need to be set, and is present for compatibility with XS1-switches. Reserved Oscillator clock frequency in MHz rounded up to the nearest integer value. Only values between 5 and 100 MHz are valid writes outside this range are ignored and will be NACKed. This field must be set on start up of the device and any time that the input oscillator clock frequency is changed. It must contain the system clock frequency in MHz rounded up to the nearest integer value. Link Control and Status: 0x80 Bits X009587, Reserved Description 0x51: System clock frequency 0x80: Link Control and Status Description System clock frequency: 0x51 31:7 E.5 64 Perm Init - Description 31:28 RO 27 RO Reserved 26 RO 0 This end of the xlink has issued credit to allow the remote end to transmit 25 RO 0 This end of the xlink has credit to allow it to transmit. 24 WO Clear this end of the xlink’s credit and issue a HELLO token. 23 WO Reset the receiver. The next symbol that is detected will be the first symbol in a token. 22 RO - 21:11 RW 1 Specify min. number of idle system clocks between two continuous symbols witin a transmit token -1. 10:0 RW 1 Specify min. number of idle system clocks between two continuous transmit tokens -1. Rx buffer overflow or illegal token encoding received. Reserved XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet F 65 USB PHY Configuration The USB PHY is connected to the ports shown in section 10. The USB PHY is peripheral 1. The control registers are accessed using 32-bit reads and writes (use write_periph_32(device, 1, ...) and read_periph_32(device, > 1, ...) for reads and writes). Number Figure 35: Summary F.1 Perm Description 0x00 WO UIFM reset 0x04 RW UIFM IFM control 0x08 RW UIFM Device Address 0x0C RW UIFM functional control 0x10 RW UIFM on-the-go control 0x14 RO UIFM on-the-go flags 0x18 RW UIFM Serial Control 0x1C RW UIFM signal flags 0x20 RW UIFM Sticky flags 0x24 RW UIFM port masks 0x28 RW UIFM SOF value 0x2C RO UIFM PID 0x30 RO UIFM Endpoint 0x34 RW UIFM Endpoint match 0x38 RW OTG Flags mask 0x3C RW UIFM power signalling 0x40 RW UIFM PHY control UIFM reset: 0x00 A write to this register with any data resets all UIFM state, but does not otherwise affect the phy. 0x00: UIFM reset Bits Perm 31:0 WO F.2 Init Description Value. UIFM IFM control: 0x04 General settings of the UIFM IFM state machine. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Bits Perm 31:8 RO - 7 RW 0 Set to 1 to enable XEVACKMODE mode. 6 RW 0 Set to 1 to enable SOFISTOKEN mode. 5 RW 0 Set to 1 to enable UIFM power signalling mode. 4 RW 0 Set to 1 to enable IF timing mode. 3 RO - 2 RW 0 Set to 1 to enable UIFM linestate decoder. 1 RW 0 Set to 1 to enable UIFM CHECKTOKENS mode. 0 RW 0 Set to 1 to enable UIFM DOTOKENS mode. 0x04: UIFM IFM control F.3 Init 66 Description Reserved Reserved UIFM Device Address: 0x08 The device address whose packets should be received. 0 until enumeration, it should be set to the assigned value after enumeration. 0x08: UIFM Device Address Bits Perm 31:7 RO - 6:0 RW 0 F.4 0x0C: UIFM functional control Init Description Reserved The enumerated USB device address must be stored here. Only packets to this address are passed on. UIFM functional control: 0x0C Bits Perm 31:5 RO - 4:2 RW 1 Set to 0 to disable UIFM to UTMI+ OPMODE mode. 1 RW 1 Set to 1 to switch UIFM to UTMI+ TERMSELECT mode. 0 RW 1 Set to 1 to switch UIFM to UTMI+ XCVRSELECT mode. F.5 Init Description Reserved UIFM on-the-go control: 0x10 This register is used to negotiate an on-the-go connection. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet Bits Perm 31:8 RO - 7 RW 0 Set to 1 to switch UIFM to EXTVBUSIND mode. 6 RW 0 Set to 1 to switch UIFM to DRVVBUSEXT mode. 5 RO - 4 RW 0 Set to 1 to switch UIFM to UTMI+ CHRGVBUS mode. 3 RW 0 Set to 1 to switch UIFM to UTMI+ DISCHRGVBUS mode. 2 RW 0 Set to 1 to switch UIFM to UTMI+ DMPULLDOWN mode. 1 RW 0 Set to 1 to switch UIFM to UTMI+ DPPULLDOWN mode. 0 RW 0 Set to 1 to switch UIFM to IDPULLUP mode. 0x10: UIFM on-the-go control F.6 Init 67 Description Reserved Reserved UIFM on-the-go flags: 0x14 Status flags used for on-the-go negotiation 0x14: UIFM on-the-go flags X009587, Bits Perm Init Description 31:6 RO - 5 RO 0 Value of UTMI+ Bvalid flag. 4 RO 0 Value of UTMI+ IDGND flag. 3 RO 0 Value of UTMI+ HOSTDIS flag. 2 RO 0 Value of UTMI+ VBUSVLD flag. 1 RO 0 Value of UTMI+ SESSVLD flag. 0 RO 0 Value of UTMI+ SESSEND flag. Reserved XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet F.7 UIFM Serial Control: 0x18 Bits Perm 31:7 RO - 6 RO 0 1 if UIFM is in UTMI+ RXRCV mode. 5 RO 0 1 if UIFM is in UTMI+ RXDM mode. 4 RO 0 1 if UIFM is in UTMI+ RXDP mode. 3 RW 0 Set to 1 to switch UIFM to UTMI+ TXSE0 mode. 0x18: UIFM Serial Control F.8 68 Init Description Reserved 2 RW 0 Set to 1 to switch UIFM to UTMI+ TXDATA mode. 1 RW 1 Set to 0 to switch UIFM to UTMI+ TXENABLE mode. 0 RW 0 Set to 1 to switch UIFM to UTMI+ FSLSSERIAL mode. UIFM signal flags: 0x1C Set of flags that monitor line and error states. These flags normally clear on the next packet, but they may be made sticky by using PER_UIFM_FLAGS_STICKY, in which they must be cleared explicitly. Bits Perm 31:7 RO - 6 RW 0 Set to 1 when the UIFM decodes a token successfully (e.g. it passes CRC5, PID check and has matching device address). 5 RW 0 Set to 1 when linestate indicates an SE0 symbol. 4 RW 0 Set to 1 when linestate indicates a K symbol. 3 RW 0 Set to 1 when linestate indicates a J symbol. 2 RW 0 Set to 1 if an incoming datapacket fails the CRC16 check. 1 RW 0 Set to the value of the UTMI_RXACTIVE input signal. 0 RW 0 Set to the value of the UTMI_RXERROR input signal 0x1C: UIFM signal flags F.9 Init Description Reserved UIFM Sticky flags: 0x20 These bits define the sticky-ness of the bits in the UIFM IFM FLAGS register. A 1 means that bit will be sticky (hold its value until a 1 is written to that bitfield), or normal, in which case signal updates to the UIFM IFM FLAGS bits may be over-written by subsequent changes in those signals. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0x20: UIFM Sticky flags Bits Perm 31:7 RO - 6:0 RW 0 F.10 Init 69 Description Reserved Stickyness for each flag. UIFM port masks: 0x24 Set of masks that identify how port 1N, port 1O and port 1P are affected by changes to the flags in FLAGS Bits 0x24: UIFM port masks Perm Init Description 31:24 RW 0 Bit mask that determines which flags in UIFM_IFM_FLAG[6:0] contribute to port 1?. If any flag listed in this bitmask is high, port 1? will be high. 23:16 RW 0 Bit mask that determines which flags in UIFM_IFM_FLAG[6:0] contribute to port 1P. If any flag listed in this bitmask is high, port 1P will be high. 15:8 RW 0 Bit mask that determines which flags in UIFM_IFM_FLAG[6:0] contribute to port 1O. If any flag listed in this bitmask is high, port 1O will be high. 7:0 RW 0 Bit mask that determines which flags in UIFM_IFM_FLAG[6:0] contribute to port 1N. If any flag listed in this bitmask is high, port 1N will be high. F.11 UIFM SOF value: 0x28 USB Start-Of-Frame counter Bits 0x28: UIFM SOF value Perm Init Description 31:11 RO - 10:8 RW 0 Most significant 3 bits of SOF counter 7:0 RW 0 Least significant 8 bits of SOF counter F.12 Reserved UIFM PID: 0x2C The last USB packet identifier received X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 0x2C: UIFM PID Bits Perm 31:4 RO - 3:0 RO 0 F.13 Init 70 Description Reserved Value of the last received PID. UIFM Endpoint: 0x30 The last endpoint seen 0x30: UIFM Endpoint Bits Perm 31:5 RO - 4 RO 0 1 if endpoint contains a valid value. 3:0 RO 0 A copy of the last received endpoint. F.14 Init Description Reserved UIFM Endpoint match: 0x34 This register can be used to mark UIFM endpoints as special. Bits 0x34: UIFM Endpoint match - 15:0 RW 0 X009587, Description Reserved This register contains a bit for each endpoint. If its bit is set, the endpoint will be supplied on the RX port when ORed with 0x10. OTG Flags mask: 0x38 Bits Perm 31:0 RW F.16 0x3C: UIFM power signalling Init RO F.15 0x38: OTG Flags mask Perm 31:16 Init 0 Description Data UIFM power signalling: 0x3C Bits Perm 31:9 RO Init - Description 8 RW 0 Valid 7:0 RW 0 Data Reserved XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet F.17 UIFM PHY control: 0x40 Bits 0x40: UIFM PHY control X009587, 71 Perm Init 31:19 RO - 18 RW 0 Description Reserved Set to 1 to disable pulldowns on ports 8A and 8B. 17:14 RO - 13 RW 0 Reserved After an auto-resume, this bit is set to indicate that the resume signalling was for reset (se0). Set to 0 to clear. 12 RW 0 After an auto-resume, this bit is set to indicate that the resume signalling was for resume (K). Set to 0 to clear. 11:8 RW 0 Log-2 number of clocks before any linestate change is propagated. 7 RW 0 Set to 1 to use the suspend controller handle to resume from suspend. Otherwise, the program has to poll the linestate_filt field in phy_teststatus. 6:4 RW 0 Control the the conf1,2,3 input pins of the PHY. 3:0 RO - Reserved XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet G 72 Device Errata This section describes minor operational differences from the data sheet and recommended workarounds. As device and documentation issues become known, this section will be updated the document revised. To guarantee a logic low is seen on the pins RST_N, MODE[1:0], TMS, and TDI, the driving circuit should present an impedance of less than 100 Ω to ground. Usually this is not a problem for CMOS drivers driving single inputs. If one or more of these inputs are placed in parallel, however, additional logic buffers may be required to guarantee correct operation. For static inputs tied high or low, the relevant input pin should be tied directly to GND or VDDIO. H JTAG, xSCOPE and Debugging If you intend to design a board that can be used with the XMOS toolchain and xTAG debugger, you will need an xSYS header on your board. Figure 36 shows a decision diagram which explains what type of xSYS connectivity you need. The three subsections below explain the options in detail. YES YES Is xSCOPE required YES Figure 36: Decision diagram for the xSYS header Use full xSYS header See section 3 H.1 Is debugging required? NO Is fast printf required ? NO YES Does the SPI flash need to be programmed? NO NO Use JTAG xSYS header See section 2 No xSYS header required See section 1 No xSYS header The use of an xSYS header is optional, and may not be required for volume production designs. However, the XMOS toolchain expects the xSYS header; if you do not have an xSYS header then you must provide your own method for writing to flash/OTP and for debugging. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet H.2 73 JTAG-only xSYS header The xSYS header connects to an xTAG debugger, which has a 20-pin 0.1" female IDC header. The design will hence need a male IDC header. We advise to use a boxed header to guard against incorrect plug-ins. If you use a 90 degree angled header, make sure that pins 2, 4, 6, ..., 20 are along the edge of the PCB. Connect pins 4, 8, 12, 16, 20 of the xSYS header to ground, and then connect: · TDI to pin 5 of the xSYS header · TMS to pin 7 of the xSYS header · TCK to pin 9 of the xSYS header · TDO to pin 13 of the xSYS header The RST_N net should be open-drain, active-low, and have a pull-up to VDDIO. H.3 Full xSYS header For a full xSYS header you will need to connect the pins as discussed in Section H.2, and then connect a 2-wire xCONNECT Link to the xSYS header. The links can be found in the Signal description table (Section 4): they are labelled XL0, XL1, etc in the function column. The 2-wire link comprises two inputs and outputs, labelled 0 0 1 1 out , out , in , and in . For example, if you choose to use XL0 for xSCOPE I/O, you need to connect up XL01out , XL00out , XL00in , XL01in as follows: · XL01out (X0D43) to pin 6 of the xSYS header with a 33R series resistor close to the device. · XL00out (X0D42) to pin 10 of the xSYS header with a 33R series resistor close to the device. · XL00in (X0D41) to pin 14 of the xSYS header. · XL01in (X0D40) to pin 18 of the xSYS header. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet I 74 Schematics Design Check List This section is a checklist for use by schematics designers using the XEF232-1024-FB374. Each of the following sections contains items to check for each design. I.1 Power supplies VDDIO and OTP_VCC supply is within specification before the VDD (core) supply is turned on. Specifically, the VDDIO and OTP_VCC supply is within specification before VDD (core) reaches 0.4V (Section 13). The VDD (core) supply ramps monotonically (rises constantly) from 0V to its final value (0.95V - 1.05V) within 10ms (Section 13). The VDD (core) supply is capable of supplying 600mA (Section 13). PLL_AVDD is filtered with a low pass filter, for example an RC filter, . see Section 13 I.2 Power supply decoupling The design has multiple decoupling capacitors per supply, for example at least four0402 or 0603 size surface mount capacitors of 100nF in value, per supply (Section 13). A bulk decoupling capacitor of at least 10uF is placed on each supply (Section 13). I.3 Power on reset The RST_N pins are asserted (low) during or after power up. The device is not used until these resets have taken place. As the errata in the datasheets show, the internal pull-ups on these two pins can occasionally provide stronger than normal pull-up currents. For this reason, an RC type reset circuit is discouraged as behavior would be unpredictable. A voltage supervisor type reset device is recommended to guarantee a good reset. This also has the benefit of resetting the system should the relevant supply go out of specification. I.4 Clock The CLK input pin is supplied with a clock with monotonic rising edges and low jitter. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 75 Pins MODE0 and MODE1 are set to the correct value for the chosen oscillator frequency. The MODE settings are shown in the Oscillator section, Section 7. If you have a choice between two values, choose the value with the highest multiplier ratio since that will boot faster. I.5 RGMII interface This section can be skipped if you do not have any device connected to the RGMII interface. RX_CLK will be low when the xCORE comes out of reset (see Section 11). VDDIOT has a 2.5V supply. RGMII signals are connected to the appropriate RGMII pins of the xCORE device. I.6 Boot X0D01 has a 1K pull-up to VDDIOL (Section 8). The device is kept in reset for at least 1 ms after VDDIOL has reached its minimum level (Section 8). I.7 JTAG, XScope, and debugging You have decided as to whether you need an XSYS header or not (Section H) If you have not included an XSYS header, you have devised a method to program the SPI-flash or OTP (Section H). I.8 GPIO You have not mapped both inputs and outputs to the same multi-bit port. Pins X0D04, X0D05, X0D06, and X0D07 are output only and are, after reset, pulled low or not connected (Section 8) I.9 Multi device designs Skip this section if your design only includes a single XMOS device. One device is connected to a SPI flash for booting. X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet 76 Devices that boot from link have MODE2 grounded and MODE3 NC. These device must have link XLB connected to a device to boot from (see 8). If you included an XSYS header, you have included buffers for RST_N, TMS, TCK, MODE2, and MODE3 (Section G). X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet J 77 PCB Layout Design Check List This section is a checklist for use by PCB designers using the XS2UEF32A-1024-FB374. Each of the following sections contains items to check for each design. J.1 Ground Plane Each ground ball has a via to minimize impedance and conduct heat away from the device. (Section ??) Other than ground vias, there are no (or only a few) vias underneath or closely around the device. This create a good, solid, ground plane. J.2 RGMII interface This section can be skipped if you do not have any device connected to the RGMII interface. The RGMII traces are length and impedance matched. J.3 Power supply decoupling The decoupling capacitors are all placed close to a supply pin (Section 13). The decoupling capacitors are spaced around the device (Section 13). The ground side of each decoupling capacitor has a direct path back to the center ground of the device. J.4 PLL_AVDD The PLL_AVDD filter (especially the capacitor) is placed close to the PLL_AVDD pin (Section 13). X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet K 78 Associated Design Documentation Document Title Information Document Number Estimating Power Consumption For XS1-UEF Devices Power consumption Programming XC on XMOS Devices Timers, ports, clocks, cores and channels X9577 xTIMEcomposer User Guide Compilers, assembler and linker/mapper X3766 Timing analyzer, xScope, debugger Flash and OTP programming utilities L Related Documentation Document Title Information Document Number The XMOS XS1 Architecture ISA manual X7879 XS1 Port I/O Timing Port timings X5821 xCONNECT Architecture Link, switch and system information X4249 XS1-UEF Link Performance and Design Guidelines Link timings XS1-UEF Clock Frequency Control Advanced clock control X009587, XS2-UEF32A-1024-FB374 PRELIMINARY XEF232-1024-FB374 Datasheet M 79 Revision History Date Description 2015-03-20 Preliminary release 2015-04-14 Added RST to pins to be pulled hard, and removed reference to TCK from Errata Removed TRST_N references in packages that have no TRST_N New diagram for boot from embedded flash showing ports Pull up requirements for shared clock and external resistor for QSPI 2015-05-06 Removed references tro DEBUG_N 2015-07-09 Updated electrical characteristics - Section 14 2015-08-19 Added I(USB_VDD) - Section 14 Added USB layout guidelines - Section 13 2015-08-27 Updated part marking and product code - Section 16 Copyright © 2015, All Rights Reserved. Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. X009587, XS2-UEF32A-1024-FB374