NuMicro™ Mini51 Series Data Sheet
ARM Cortex™-M0
32-BIT MICROCONTROLLER
NuMicro™ Family
Mini51 Series DataSheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
NUMICRO™ MINI51 SERIES DATASHEET
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
CONTENTS
1
2
3
GENERAL DESCRIPTION ..................................................................................................... 7
FEATURES ............................................................................................................................. 8
PARTS INFORMATION LIST AND PIN CONFIGURATION ................................................ 11
3.1
NuMicro Mini51 Series Product Selection Guide .................................................... 11
3.2
PIN CONFIGURATION .............................................................................................. 12
3.2.1
3.2.2
3.3
LQFP 48-pin ................................................................................................................... 12
QFN 33-pin ..................................................................................................................... 13
Pin Description ........................................................................................................... 14
4
BLOCK DIAGRAM ................................................................................................................ 18
4.1
NuMicro Mini51™ Block Diagram .............................................................................. 18
5
FUNCTIONAL DESCRIPTION.............................................................................................. 19
5.1
Memory Organization ................................................................................................. 19
5.1.1
5.1.2
5.2
Nested Vectored Interrupt Controller (NVIC) ............................................................. 21
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.3
Overview ........................................................................................................................ 36
Features ......................................................................................................................... 36
Flash Memory Controller (FMC) ................................................................................. 37
5.7.1
5.7.2
Feb 9, 2012
Overview ........................................................................................................................ 35
Features ......................................................................................................................... 35
Analog-to-Digital Converter (ADC) ............................................................................. 36
5.6.1
5.6.2
5.7
Overview ........................................................................................................................ 28
Clock Generator ............................................................................................................. 28
System Clock and SysTick Clock ................................................................................... 29
AHB Clock Source Selection .......................................................................................... 30
Peripheral Clock Source Selection ................................................................................. 31
Power-down Mode Clock................................................................................................ 33
Frequency Divider Output............................................................................................... 34
Comparator Controller (CMPC) .................................................................................. 35
5.5.1
5.5.2
5.6
Overview ........................................................................................................................ 25
System Reset ................................................................................................................. 25
System Power Distribution ............................................................................................. 25
Memory Mapping Table .................................................................................................. 27
Clock Controller .......................................................................................................... 28
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.5
Overview ........................................................................................................................ 21
Features ......................................................................................................................... 21
Exception Model and System Interrupt Map ................................................................... 21
Vector Table ................................................................................................................... 23
NVIC Operation .............................................................................................................. 24
System Manager ........................................................................................................ 25
5.3.1
5.3.2
5.3.3
5.3.4
5.4
Overview ........................................................................................................................ 19
System Memory Map...................................................................................................... 20
Overview ........................................................................................................................ 37
Features ......................................................................................................................... 37
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NuMicro™ Mini51 Series Data Sheet
5.8
General Purpose I/O .................................................................................................. 38
5.8.1
5.8.2
2
5.9
I C Serial Interface Controller (Master/Slave) ............................................................ 39
5.9.1
5.9.2
5.10
5.11
5.12
Overview ...................................................................................................................... 43
Features ....................................................................................................................... 43
Timer Controller .......................................................................................................... 44
5.12.1
5.12.2
5.13
Overview ...................................................................................................................... 44
Features ....................................................................................................................... 44
UART Interface Controller .......................................................................................... 45
5.13.1
5.13.2
5.14
Overview ...................................................................................................................... 45
Features ....................................................................................................................... 47
Watchdog Timer ......................................................................................................... 48
5.14.1
5.14.2
Overview ...................................................................................................................... 48
Features ....................................................................................................................... 49
®
ARM CORTEX™-M0 CORE ............................................................................................... 50
6.1
Overview .................................................................................................................... 50
6.2
Features ..................................................................................................................... 51
APPLICATION CIRCUIT ....................................................................................................... 52
ELECTRICAL CHARACTERISTICS ..................................................................................... 53
8.1
Absolute Maximum Ratings ....................................................................................... 53
DC Electrical Characteristics ...................................................................................... 54
8.3
AC Electrical Characteristics ...................................................................................... 59
8.4
External Input Clock ....................................................................................................... 59
External 4 ~ 24 MHz XTAL Oscillator ............................................................................. 59
Typical Crystal Application Circuit .................................................................................. 59
External 32.768 KHz XTAL Oscillator ............................................................................. 60
Internal 22.1184 MHz RC Oscillator ............................................................................... 60
Internal 10 KHz RC Oscillator......................................................................................... 60
Analog Characteristics ............................................................................................... 61
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
Brown-Out Reset (BOD) ................................................................................................. 61
Low Voltage Reset (LVR) ............................................................................................... 61
Analog Comparator ........................................................................................................ 61
Analog Comparator Reference Voltage (CRV) ............................................................... 62
10-bit ADC ...................................................................................................................... 62
Flash Memory Characteristics ........................................................................................ 63
PACKAGE DIMENSION ....................................................................................................... 64
Feb 9, 2012
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NUMICRO™ MINI51 SERIES DATASHEET
8.2
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
9
Overview ...................................................................................................................... 41
Features ....................................................................................................................... 41
Serial Peripheral Interface (SPI) Controller ................................................................ 43
5.11.1
5.11.2
7
8
Overview ........................................................................................................................ 39
Features ......................................................................................................................... 39
Enhanced PWM Generator ........................................................................................ 41
5.10.1
5.10.2
6
Overview ........................................................................................................................ 38
Features ......................................................................................................................... 38
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
10
9.1
48-pin LQFP ............................................................................................................... 64
9.2
33-pin QFN (4mm x 4mm) ......................................................................................... 65
9.3
33-pin QFN (5mm x 5mm) ......................................................................................... 66
REVISION HISTORY ............................................................................................................ 67
Feb 9, 2012
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NuMicro™ Mini51 Series Data Sheet
List of Figures
Figure 3.1-1 NuMicro Mini51 Series Product Selection Guide .................................................... 11
Figure 3.2-1 NuMicro Mini51 Series LQFP 48-pin Assignment .................................................. 12
Figure 3.2-2 NuMicro Mini51 Series QFN 33-pin Assignment .................................................... 13
Figure 4.1-1 NuMicro Mini51 Series Block Diagram ................................................................... 18
Figure 5.3-1 NuMicro Mini51 Series Power Distribution Diagram............................................... 26
Figure 5.4-1 Clock Generator Block Diagram ................................................................................ 28
Figure 5.4-2 System Clock Block Diagram .................................................................................... 29
Figure 5.4-3 SysTick Clock Control Block Diagram ....................................................................... 29
Figure 5.4-4 AHB Clock Source for HCLK ..................................................................................... 30
Figure 5.4-5 Peripherals Clock Source Selection for PCLK .......................................................... 31
Figure 5.4-6 Clock Source of Frequency Divider ........................................................................... 34
Figure 5.4-7 Block Diagram of Frequency Divider ......................................................................... 34
Figure 5.9-1 Bus Timing ................................................................................................................. 39
Figure 5.10-1 Application Circuit Diagram ..................................................................................... 42
Figure 5.14-1 Timing of Interrupt and Reset Signal ....................................................................... 49
Figure 6.1-1 Functional Block Diagram .......................................................................................... 50
Figure 8.3-1 Typical Crystal Application Circuit ............................................................................. 60
NUMICRO™ MINI51 SERIES DATASHEET
Feb 9, 2012
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
List of Tables
Table 3.3-1 NuMicro Mini51 Series Pin Description ................................................................... 17
Table 5.1-1 Address Space Assignments for On-Chip Modules ................................................... 20
Table 5.2-1 Exception Model ......................................................................................................... 22
Table 5.2-2 System Interrupt Map ................................................................................................. 23
Table 5.2-3 Vector Table Format ................................................................................................... 23
Table 5.3-1 Memory Mapping Table .............................................................................................. 27
Table 5.4-1 Peripherals Engine Clock Source Selection Table ..................................................... 32
Table 5.13-1 UART Baud Rate Setting Table ................................................................................ 45
Table 5.13-2 UART Baud Rate Setting Table ................................................................................ 45
Table 5.14-1 Watchdog Time-out Interval Selection ...................................................................... 48
Feb 9, 2012
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NuMicro™ Mini51 Series Data Sheet
1
GENERAL DESCRIPTION
®
The NuMicro Mini51™ series 32-bit microcontroller is embedded with an ARM Cortex™-M0 core
for industrial controls and applications which require high performance, high integration, and low
cost. The Cortex™-M0 is the newest ARM embedded processor with 32-bit performance at a cost
equivalent to the traditional 8-bit microcontroller.
The NuMicro Mini51™ series can run up to 24 MHz, and thus can afford to support a variety of
industrial controls and applications requiring high CPU performance. The NuMicro Mini51™
series provides 4K/8K/16K-byte embedded program flash, size configurable data flash (shared
with program flash), 2K-byte flash for the ISP, and 2K-byte embedded SRAM.
2
A number of system-level peripheral functions, such as I/O Port, Timer, UART, SPI, I C, PWM,
ADC, Watchdog Timer, and low voltage detector, have been incorporated in the NuMicro
Mini51™ series to reduce component count, board space, and system cost. These useful
functions make the NuMicro Mini51™ series powerful for a wide range of applications.
Additionally, the NuMicro Mini51™ series is equipped with ISP (In-System Programming) and ICP
(In-Circuit Programming) functions, allowing user to update program memory without removing a
chip from an actual end product.
NUMICRO™ MINI51 SERIES DATASHEET
Feb 9, 2012
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
2
FEATURES
Core
®
ARM Cortex™-M0 core running up to 24 MHz
One 24-bit system timer
Supports low power Idle mode
A single-cycle 32-bit hardware multiplier
NVIC for 32 interrupt inputs, each with 4-level priority
Supports Serial Wire Debug (SWD) with 2 watchpoints/4 breakpoints
Built-in LDO for Wide Operating Voltage Range: 2.5V to 5.5V
Memory
4KB/8KB/16KB flash memory for program memory (APROM)
Configurable flash memory for data memory (Data Flash)
2KB flash memory for loader (LDROM)
2KB SRAM for internal scratch-pad RAM (SRAM)
In-System Programming (ISP) and In-Circuit Programming (ICP)
Clock Control
Programmable system clock source
4 ~ 24 MHz crystal oscillator (HXT)
32.768K crystal oscillator (LXT) for idle wake-up and system operation clock
22.1184 MHz internal oscillator (HIRC) (1% accuracy at 25 C, 5V)
0
10 KHz internal low-power oscillator (LIRC) for watchdog and idle wake-up
Up to 30 GPIO (General Purpose I/O) pins for LQFP-48 package
Software-configured I/O type
Quasi-bidirectional input/output
Push-pull output
Open-drain output
Input-only (high impendence)
Optional Schmitt trigger input
Timer
Feb 9, 2012
0
Dynamically calibrating the HIRC OSC to 22.0 MHz ±1% from -40 C to
0
85 C by external 32.768K crystal oscillator (LXT)
I/O Port
Switch clock sources on-the-fly
Two 24-bit Timers with 8-bit prescaler
Supports Event Counter mode
Supports Toggle Output mode
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NuMicro™ Mini51 Series Data Sheet
Supports external trigger in Pulse Width Measurement mode
Feb 9, 2012
Watchdog Timer
Programmable clock source and time-out period
Supports wake-up function in Power-down mode and Idle mode
Interrupt or reset selectable when time-out happens
PWM
Up to three built-in 16-bit PWM generators with six PWM outputs or three
complementary paired PWM outputs
Supports edge alignment or center alignment
Supports fault detection
Individual clock source, clock divider, 8-bit prescalar and dead-zone generator
for each PWM generator
PWM interrupt synchronized to PWM period
UART (Universal Asynchronous Receiver/Transmitters)
One UART device
Buffered receiver and transmitter with 16-byte FIFO
Optional flow control function (CTSn and RTSn)
Supports IrDA (SIR) function
Programmable baud-rate generator up to 1/16 system clock
Supports RS-485 function
SPI (Serial Peripheral Interface)
One SPI device
Masters up to 12 MHz, and Slaves up to 4 MHz
Supports SPI Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 1 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
Byte Suspend mode in 32-bit transmission
2
IC
Supports Master/Slave mode
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization allowing devices with different bit rates to
communicate via one serial bus
Page 9 of 68
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NUMICRO™ MINI51 SERIES DATASHEET
Supports external trigger in Pulse Width Capture mode
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (4 slave addresses with mask option)
ADC (Analog-to-Digital Converter)
10-bit SAR ADC with 150K SPS
Up to 8-ch single-end input and one internal input from band-gap
Conversion started by software or external pin
Analog Comparator
Two analog comparators with programmable 16-level internal voltage reference
Built-in CRV (comparator reference voltage)
BOD (Brown-Out Detection) Reset
Three programmable threshold levels: 3.8V/2.7V/2.0V (default as 2.0V)
Optional BOD interrupt or reset
96-bit unique ID
Operating Temperature: -40℃~85℃
Packages:
Feb 9, 2012
Green package (RoHS)
LQFP 48-pin (7x7), QFN 33-pin (5x5), QFN 33-pin (4x4)
Page 10 of 68
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NuMicro™ Mini51 Series Data Sheet
3
3.1
PARTS INFORMATION LIST AND PIN CONFIGURATION
NuMicro Mini51 Series Product Selection Guide
Part Number
APROM RAM
Data Flash
ISP
Loader
ROM
Connectivity
I/O
Timer
Comp. PWM
UART SPI
ADC
ISP
ICP
IRC
22.1184
MHz
Package
2
IC
MINI51LAN
4 KB
2 KB Configurable
2 KB
up to 30 2x32-bit
1
1
1
2
6
8x10-bit
v
v
LQFP48
MINI51ZAN
4 KB
2 KB Configurable
2 KB
up to 29 2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(5x5)
MINI51TAN
4 KB
2 KB Configurable
2 KB
up to 29 2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(4x4)
MINI52LAN
8 KB
2 KB Configurable
2 KB
up to 30 2x32-bit
1
1
1
2
6
8x10-bit
v
v
LQFP48
MINI52ZAN
8 KB
2 KB Configurable
2 KB
up to 29 2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(5x5)
MINI52TAN
8 KB
2 KB Configurable
2 KB
up to 29 2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(4x4)
MINI54LAN
16 KB
2 KB Configurable
2 KB
up to 30 2x32-bit
1
1
1
2
6
8x10-bit
v
v
LQFP48
MINI54ZAN
16 KB
2 KB Configurable
2 KB
up to 29 2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(5x5)
MINI54TAN
16 KB
2 KB Configurable
2 KB
up to 29 2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(4x4)
Figure 3.1-1 NuMicro Mini51 Series Product Selection Guide
NUMICRO™ MINI51 SERIES DATASHEET
Feb 9, 2012
Page 11 of 68
Revision V1.03
3.2
3.2.1
PIN CONFIGURATION
LQFP 48-pin
NC
CPN0,AIN4,P1.4
TX ,AIN3,P1.3
RX ,AIN2, P1.2
AIN1,P1.0
AVDD
VDD
AIN0,P5.3
NC
NC
TX, CTSn, P0.0
SPISS, RX, RTSn, P0.1
48
47
46
45
44
43
42
41
40
39
38
37
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
NC
1
36
NC
CPP0, AIN5, P1.5
2
35
P0.4, SPISS,PWM5
/RESET
3
34
P0.5, MOSI
CPN1, AIN6, P3.0
4
33
P0.6, MISO
AVSS
5
32
P0.7, SPICLK
P5.4
6
31
NC
CPP1, AIN7, P3.1
7
30
P4.7, ICE_DAT
T0EX, STADC, INT0, P3.2
8
29
P4.6, ICE_CLK
SDA, T0, P3.4
9
28
NC
SCL, T1, P3.5
10
27
NC
NC
11
26
P2.6, PWM4, CPO1
NC
12
25
P2.5, PWM3
Mini51
LQFP 48-pin
18
19
20
21
22
23
24
VSS
LDO_CAP
P5.5
P5.2, INT1
NC
P2.2, PWM0
P2.3, PWM1
P2.4, PWM2
P5.1,XTAL2
17
15
P3.6, CKO,T1EX,CPO0
P5.0,XTAL1
14
NC
16
13
Figure 3.2-1 NuMicro Mini51 Series LQFP 48-pin Assignment
Feb 9, 2012
Page 12 of 68
Revision V1.03
NuMicro™ Mini51 Series Data Sheet
3.2.2
QFN 33-pin
SPISS,RX,RTSn, P0.1
TX,CTSn, P0.0
AIN0,P5.3
VDD
AIN1, P1.0
RX, AIN2, P1.2
TX, AIN3, P1.3
CPN0,AIN4, P1.4
32 31 30 29 28 27 26 25
CPP0,AIN5, P1.5
1
24 P0.4, SPISS,PWM5
/RESET
2
23 P0.5, MOSI
CPN1,AIN6, P3.0
3
22 P0.6, MISO
P5.4
4
CPP1,AIN7, P3.1
5
T0EX,STADC,INT0, P3.2
6
SDA, T0, P3.4
7
SCL, T1, P3.5
Mini51
QFN 33-pin
21 P0.7, SPICLK
20 P4.7, ICE_DAT
19 P4.6, ICE_CLK
18 P2.6, PWM4,CPO1
33 VSS
8
17 P2.5, PWM3
P2.4, PWM2
P2.3, PWM1
P2.2, PWM0
P5.1,XTAL2
P5.2,INT1
P3.6, CKO,T1EX,CPO0
VSS
10 11 12 13 14 15 16
P5.0,XTAL1
9
top transparent view
Feb 9, 2012
Page 13 of 68
Revision V1.03
NUMICRO™ MINI51 SERIES DATASHEET
Figure 3.2-2 NuMicro Mini51 Series QFN 33-pin Assignment
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
3.3
Pin Description
Pin Number
LQFP
48-pin
QFN
33-pin
1
2
3
4
NC
1
2
3
5
6
7
8
9
10
Pin Name Pin Type Description
4
5
Not connected
P1.5
I/O
Digital GPIO pin
AIN5
AI
ADC analog input pin
CPP0
AI
Analog comparator Positive input pin
/RESET
I(ST)
The Schmitt trigger input pin for hardware device reset. A
“Low” on this pin for 768 clock counter of Internal RC
22.1184 MHz while the system clock is running will reset the
device. /RESET pin has an internal pull-up resistor allowing
power-on reset by simply connecting an external capacitor to
GND.
P3.0
I/O
Digital GPIO pin
AIN6
AI
ADC analog input pin
CPN1
AI
Analog comparator negative input pin
AVSS
AP
Ground pin for analog circuit
P5.4
I/O
Digital GPIO pin
P3.1
I/O
Digital GPIO pin
AIN7
AI
ADC analog input pin
CPP1
AI
Analog comparator positive input pin
P3.2
I/O
Digital GPIO pin
INT0
I
External interrupt 0 input pin
STADC
I
ADC external trigger input pin
T0EX
I
Timer 0 external capture/reset trigger input pin
P3.4
I/O
Digital GPIO pin
T0
I/O
Timer 0 external event counter input pin
SDA
I/O
I C data I/O pin
P3.5
I/O
Digital GPIO pin
T1
I/O
Timer 1 external event counter input pin
SCL
I/O
I C clock I/O pin
6
7
8
2
2
11
NC
Not connected
12
NC
Not connected
13
NC
Not connected
Feb 9, 2012
Page 14 of 68
Revision V1.03
NuMicro™ Mini51 Series Data Sheet
Pin Number
LQFP
48-pin
14
15
16
QFN
33-pin
Pin Name Pin Type Description
P3.6
I/O
Digital GPIO pin
CPO0
O
Analog comparator output pin
CKO
O
Frequency divider output pin
T1EX
I
Timer 1 external capture/reset trigger input pin
P5.1
I/O
Digital GPIO pin
XTAL2
O
The output pin from the internal inverting amplifier. It emits
the inverted signal of XTAL1.
P5.0
I/O
Digital GPIO pin
9
10
11
XTAL1
I
The input pin to the internal inverting amplifier. The system
clock could be from external crystal or resonator.
VSS
P
Ground pin for digital circuit
18
LDO_CA
P
P
LDO output pin
19
P5.5
I/O
User program must enable pull-up resistor in the QFN-33
package.
P5.2
I/O
Digital GPIO pin
INT1
I
12
17
33
Digital GPIO pin
20
13
21
22
24
25
26
27
Feb 9, 2012
Not connected
P2.2
I/O
Digital GPIO pin
PWM0
O
PWM0 output of PWM unit
P2.3
I/O
Digital GPIO pin
PWM1
O
PWM1 output of PWM unit
P2.4
I/O
Digital GPIO pin
PWM2
O
PWM2 output of PWM unit
P2.5
I/O
Digital GPIO pin
PWM3
O
PWM3 output of PWM unit
P2.6
I/O
Digital GPIO pin
PWM4
O
PWM4 output of PWM unit
CPO1
O
Analog comparator output pin
14
NUMICRO™ MINI51 SERIES DATASHEET
23
NC
External interrupt 1 input pin
15
16
17
18
NC
Not connected
Page 15 of 68
Revision V1.03
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
Pin Number
LQFP
48-pin
QFN
33-pin
28
Pin Name Pin Type Description
NC
P4.6
29
33
34
35
38
I
Serial wired debugger clock pin
P4.7
I/O
Digital GPIO pin
ICE_DAT
I/O
Serial wired debugger data pin
NC
Not connected
P0.7
I/O
Digital GPIO pin
SPICLK
I/O
SPI serial clock pin
P0.6
I/O
Digital GPIO pin
MISO
I/O
SPI MISO (master in/slave out) pin
P0.5
I/O
Digital GPIO pin
MOSI
O
SPI MOSI (master out/slave in) pin
P0.4
I/O
Digital GPIO pin
SPISS
I/O
SPI slave select pin
PWM5
O
PWM5 output of PWM unit
21
22
23
24
36
37
Digital GPIO pin
20
31
32
I/O
19
ICE_CLK
30
Not connected
NC
Not connected
P0.1
I/O
Digital GPIO pin
RTSn
O
UART RTS pin
RX
I
UART data receiver input pin
25
26
SPISS
I/O
SPI slave select pin
P0.0
I/O
Digital GPIO pin
CTSn
I
UART CTS pin
TX
O
UART transmitter output pin
39
NC
Not connected
40
NC
Not connected
41
42
28
43
44
Feb 9, 2012
P5.3
I/O
Digital GPIO pin
AIN0
AI
ADC analog input pin
VDD
P
Power supply for digital circuit
AVDD
P
Power supply for analog circuit
27
29
P1.0
I/O
Digital GPIO pin
Page 16 of 68
Revision V1.03
NuMicro™ Mini51 Series Data Sheet
Pin Number
LQFP
48-pin
45
QFN
33-pin
30
Pin Name Pin Type Description
AIN1
AI
ADC analog input pin
P1.2
I/O
Digital GPIO pin
AIN2
AI
ADC analog input pin
RX
46
47
48
31
32
I
UART data receiver input pin
P1.3
I/O
Digital GPIO pin
AIN3
AI
ADC analog input pin
TX
O
UART transmitter output pin
P1.4
I/O
Digital GPIO pin
AIN4
I/O
PWM5: PWM output/Capture input
CPN0
AI
Analog comparator negative input pin
NC
Not connected
Table 3.3-1 NuMicro Mini51 Series Pin Description
[1] I/O type description: I: input, O: output, I/O: quasi bi-direction, D: open-drain, P: power pin,
ST: Schmitt trigger, A: Analog input.
NUMICRO™ MINI51 SERIES DATASHEET
Feb 9, 2012
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
4
4.1
BLOCK DIAGRAM
NuMicro Mini51™ Block Diagram
10K RC OSC
CONFIG
Info
22.1184M RC OSC
Cortex-M0
24 MHz
ROMMAP
Option
CLK_CTL
ISP 2KB
4KB
4~24M XTAL
AHB
Flash Control
AP ROM
16KB
8KB
4KB
Configurable
Data FLASH
(Share with
AP ROM)
32.768K XTAL
SRAM
2KB
LDO
2.5 ~ 5.5V
APBBridge
Watch Dog Timer
GPIO
P0~P5
Comparator
Timer 0/1
ADC
I2C
UART
SPI
PWM 0~5
BOD
CRV
2ch
Comparator
ADC
8ch/10bit
SARADC
150K SPS
PAD Control
Figure 4.1-1 NuMicro Mini51 Series Block Diagram
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NuMicro™ Mini51 Series Data Sheet
5
FUNCTIONAL DESCRIPTION
5.1
Memory Organization
5.1.1
Overview
The NuMicro Mini51 series provides a 4G-byte address space for programmers. The memory
locations assigned to each on-chip modules are shown in 錯誤! 找不到參照來源。. The detailed
register and memory addressing and programming will be described in the following sections for
individual on-chip modules. The NuMicro Mini51 series only supports little-endian data format.
NUMICRO™ MINI51 SERIES DATASHEET
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
5.1.2
System Memory Map
The memory locations assigned to each on-chip controllers are shown in the following table.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0000_3FFF
FLASH_BA
Flash Memory Space (16 KB)
0x2000_0000 – 0x2000_07FF
SRAM_BA
SRAM Memory Space (2 KB)
AHB Controllers Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
GCR_BA
Global Control Registers
0x5000_0200 – 0x5000_02FF
CLK_BA
Clock Control Registers
0x5000_0300 – 0x5000_03FF
INT_BA
Interrupt Multiplexer Control Registers
0x5000_4000 – 0x5000_7FFF
GP_BA
GPIO Control Registers
0x5000_C000 – 0x5000_FFFF FMC_BA
Flash Memory Control Registers
APB1 Controllers Space (0x4000_0000 – 0x401F_FFFF)
0x4000_4000 – 0x4000_7FFF
WDT_BA
Watchdog Timer Control Registers
0x4001_0000 – 0x4001_3FFF
TMR_BA
Timer0/Timer1 Control Registers
0x4002_0000 – 0x4002_3FFF
I2C_BA
I C Interface Control Registers
0x4003_0000 – 0x4003_3FFF
SPI_BA
SPI Control Registers
0x4004_0000 – 0x4004_3FFF
PWM_BA
PWM Control Registers
0x4005_0000 – 0x4005_3FFF
UART_BA
UART Control Registers
2
0x400D_0000 – 0x400D_3FFF CMP_BA
Analog Comparator Control Registers
0x400E_0000 – 0x400E_3FFF ADC_BA
Analog-Digital-Converter (ADC) Control Registers
System Controllers Space (0xE000_E000 – 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF SCS_BA
System Timer Control Registers
0xE000_E100 – 0xE000_ECFF SCS_BA
Nested Vectored Interrupt Control Registers
0xE000_ED00 – 0xE000_ED8F SCB_BA
System Control Block Registers
Table 5.1-1 Address Space Assignments for On-Chip Modules
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NuMicro™ Mini51 Series Data Sheet
5.2
Nested Vectored Interrupt Controller (NVIC)
5.2.1
Overview
The Cortex™-M0 CPU provides an interrupt controller as an integral part of the exception mode,
named “Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel
and provides the following features.
5.2.2
Features
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Dynamic priority change
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the Interrupt Service Routine (ISR) is
fetched from a vector table in memory. There is no need to determine which interrupt is accepted
and branch to the starting address of the correlated ISR by software. While the starting address is
fetched, the NVIC will also automatically save the processor state including the registers “PC,
PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned
registers from stack and resume the normal execution. Thus it will take less and deterministic time
to process the interrupt request.
For more detailed information, please refer to the “ARM
®
Manual” and “ARM v6-M Architecture Reference Manual”.
5.2.3
®
Cortex™-M0 Technical Reference
Exception Model and System Interrupt Map
The exception model supported by the NuMicro Mini51 series is listed in the following table.
Software can set four levels of priority on some of these exceptions as well as on all interrupts.
The highest user-configurable priority is denoted as “0” and the lowest priority is denoted as “3”.
The default priority of all the user-configurable interrupts is “0”. Note that the priority “0” is treated
as the fourth priority on the system, after the three system exceptions “Reset”, “NMI” and “Hard
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NUMICRO™ MINI51 SERIES DATASHEET
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
Fault”.
Exception Name
Exception Number
Priority
Reset
1
-3
NMI
2
-2
Hard Fault
3
-1
Reserved
4 ~ 10
Reserved
SVCall
11
Configurable
Reserved
12 ~ 13
Reserved
PendSV
14
Configurable
SysTick
15
Configurable
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Configurable
Table 5.2-1 Exception Model
IRQ Number
Exception
(Bit in Interrupt
Number
Registers)
Exception
Name
Source IP
1 ~ 15
-
-
-
16
0
BOD_OUT
Brown-out
17
1
WDT_INT
18
2
19
Power-down
Wake-up
Exception Description
System exceptions
-
Brown-out low voltage detected
interrupt
Yes
WDT
Watchdog Timer interrupt
Yes
EINT0
GPIO
External signal interrupt from P3.2
pin
Yes
3
EINT1
GPIO
External signal interrupt from P5.2
pin
Yes
20
4
GP0/1_INT
GPIO
External signal interrupt
GPIO group P0~P1
Yes
21
5
GP2/3/4_INT
GPIO
External signal interrupt from
GPIO group P2~P4 except P3.2
Yes
22
6
PWM_INT
PWM
PWM interrupt
No
23
7
BRAKE_INT
PWM
PWM interrupt
No
24
8
TMR0_INT
TMR0
Timer 0 interrupt
Yes
25
9
TMR1_INT
TMR1
Timer 1 interrupt
Yes
26 ~ 27
10 ~ 11
-
-
28
12
UART_INT
UART
29
13
-
-
Feb 9, 2012
from
UART interrupt
Yes
-
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NuMicro™ Mini51 Series Data Sheet
IRQ Number
Exception
(Bit in Interrupt
Number
Registers)
Exception
Name
Source IP
Power-down
Wake-up
Exception Description
30
14
SPI_INT
SPI
31
15
-
-
32
16
GP5_INT
GPIO
External signal interrupt
GPIO group P5 except P5.2
33
17
HFIRC_TRIM
_INT
HFIRC
HFIRC trim interrupt
34
18
I2C_INT
IC
35 ~ 40
19 ~ 24
-
-
41
25
ACMP_INT
ACMP
42 ~ 43
26 ~ 27
-
-
44
28
PWRWU_INT
CLKC
Clock controller interrupt for chip
wake-up from Power-down state
Yes
45
29
ADC_INT
ADC
ADC interrupt
No
46 ~ 47
30 ~ 31
-
-
2
SPI interrupt
No
from
Yes
No
2
No
I C interrupt
Analog Comparator
interrupt
0
or
1
Yes
-
-
Table 5.2-2 System Interrupt Map
5.2.4
Vector Table
Vector Table Word Offset (Bytes)
0x00
Exception Number × 0x04
Description
Initial Stack Pointer Value
Exception Entry Pointer using that Exception Number
Table 5.2-3 Vector Table Format
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NUMICRO™ MINI51 SERIES DATASHEET
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table
based address is fixed at 0x0000_0000. The vector table contains the initialization value for the
stack pointer on reset, and the entry point addresses for all exception handlers. The vector
number on previous page defines the order of entries in the vector table associated with the
exception handler entry as illustrated in the previous section.
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
5.2.5
NVIC Operation
NVIC interrupts can be enabled or disabled by writing to their corresponding Interrupt Set-Enable
or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-toclear policy, and both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending; however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in the next section.
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NuMicro™ Mini51 Series Data Sheet
5.3
System Manager
5.3.1
Overview
The following functions are included in the system manager section:
5.3.2
System Memory Map
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System management registers for product ID
System management registers for chip and module functional reset and multi-function
pin control
Brown-out and chip miscellaneous Control Register
Combined peripheral interrupt source identify
System Reset
The system reset includes one of the following as the event occurs. For these reset events flags
can be read by RSTSRC register.
5.3.3
Power-On Reset (POR)
Low level on the /RESET pin
Watchdog Time-out Reset (WDT)
Brown-out Detected Reset (BOD)
Cortex™-M0 CPU Reset
Software one shot Reset
System Power Distribution
In this device, the power distribution is divided into three segments.
Analog power from AVDD and AVSS supplies power for analog module operation
Digital power from VDD and VSS supplies power to the internal regulator which
provides a fixed 1.8V power for digital operation and I/O pins
Built-in capacitor for internal voltage regulator
The output of internal voltage regulator, LDO_CAP, requires an external capacitor which should
be located close to the corresponding pin. 錯誤! 找不到參照來源。 shows the power architecture
of this device.
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NUMICRO™ MINI51 SERIES DATASHEET
Mini51™ Power Distribution
AVDD
AVSS
Comparator
10-bit
SAR-ADC
Brown Out Detector
CRV
FLASH
Digital Logic
(Timer/UART/I2C/SPI…)
IRC
22.1184MHz
& 10KHz Osc.
1.8V
POR18
POR50
5V to 1.8V
LDO
P0~P5
IO cell
VDD
VSS
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
Figure 5.3-1 NuMicro Mini51 Series Power Distribution Diagram
Feb 9, 2012
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NuMicro™ Mini51 Series Data Sheet
5.3.4
Memory Mapping Table
Mini51/52/54
4 GB
System Control
0xFFFF_FFFF
Reserved
|
0xE000_F000
System Control
System Control
0xE000_ED00 SCS_BA
External Interrupt Control
0xE000_E100
SCS_BA
System Timer Control
0xE000_E010
SCS_BA
0xE000_EFFF
0xE000_E000
0xE000_E00F
Reserved
|
0x6002_0000
Reserved
0x6001_FFFF
0x6000_0000
0x5FFF_FFFF
Reserved
|
0x5020_0000
AHB
Reserved
AHB peripherals
0x501F_FFFF
FMC
0x5000_C000 FMC_BA
0x5000_0000
GPIO Control
0x5000_4000 GP_BA
0x4FFF_FFFF
Interrupt Multiplexer Control
0x5000_0300 INT_BA
Clock Control
0x5000_0200 CLK_BA
System Global Control
0x5000_0000 GCR_BA
|
0x4020_0000
0x401F_FFFF
APB
1 GB
|
0x4000_0000
0x3FFF_FFFF
APB peripherals
Reserved
0.5 GB
2 KB SRAM
Reserved
|
ADC Control
0x400E_0000
ACMP Control
0x400D_0000 CMP_BA
ADC_BA
UART Control
0x4005_0000 UART_BA
0x2000_0800
PWM Control
0x4004_0000 PWM_BA
0x2000_07FF
SPI Control
0x4003_0000 SPI_BA
0x2000_0000
I2C Control
0x4002_0000 I2C_BA
0x1FFF_FFFF
Timer0/Timer1 Control
0x4001_0000 TMR_BA
WDT Control
0x4000_4000 WDT_BA
|
NUMICRO™ MINI51 SERIES DATASHEET
0x0000_4000
16 KB on-chip Flash (Mini54) 0x0000_3FFF
8 KB on-chip Flash (Mini52) 0x0000_1FFF
0 GB
4 KB on-chip Flash (Mini51)
0x0000_0FFF
0x0000_0000
Table 5.3-1 Memory Mapping Table
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
5.4
Clock Controller
5.4.1
Overview
The clock controller generates the clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and a 4-bit clock divider. The chip will
not enter Power-down mode until CPU sets the power-down enable bit (PWR_DOWN_EN) and
Cortex-M0 core executes the WFI instruction. After that, the chip enters Power-down mode and
wait for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the
clock controller turns off the external crystal and internal 22.1184 MHz oscillator to reduce the
overall system power consumption.
5.4.2
Clock Generator
The clock generator consists of 3 sources which are listed below:
One external 12 MHz (HXT) or 32 KHz (LXT) crystal
One internal 22.1184 MHz RC oscillator (HIRC)
One internal 10 KHz oscillator (LIRC)
XTLCLK_EN(PWRCON[1:0])
XT_IN
XTL12M
Or
32KHz
12 MHz or 32 KHz
12 MHz or 32 KHz
XT_OUT
OSC22M_EN(PWRCON[2])
OSC22M
22.1184 MHz
22.1184 MHz
OSC10K_EN(PWRCON[3])
OSC10K
10 KHz
10 KHz
Figure 5.4-1 Clock Generator Block Diagram
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NuMicro™ Mini51 Series Data Sheet
5.4.3
System Clock and SysTick Clock
The system clock has 3 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown below.
HCLK_S (CLKSEL0[2:0])
22.1184M
10K
Reserved
Reserved
12M or 32K
111
CPUCLK
CPU
HCLK
AHB
PCLK
APB
011
010
001
÷ (HCLK_N+1)
PWD_DOWN_EN (PWRCON[7])
HCLK_N (CLKDIV[3:0])
000
Figure 5.4-2 System Clock Block Diagram
The clock source of SysTick in Cortex-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in 錯誤! 找不到參照來源。.
STCLK_S (CLKSEL0[5:3])
22.1184M
HCLK
12M or 32K
12M or 32K
÷2
÷2
111
÷2
010
011
STCLK
000
NUMICRO™ MINI51 SERIES DATASHEET
Figure 5.4-3 SysTick Clock Control Block Diagram
Feb 9, 2012
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
5.4.4
AHB Clock Source Selection
HCLK
ISP (In System
Programmer)
ISP_EN (AHBCLK[2])
Figure 5.4-4 AHB Clock Source for HCLK
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NuMicro™ Mini51 Series Data Sheet
5.4.5
Peripheral Clock Source Selection
The peripheral clock has different clock source switch settings depending on different peripherals.
Please refer to the CLKSEL1 and APBCLK register description in section 錯誤! 找不到參照來
源。.
PCLK
Watch Dog Timer
WDT_EN (APBCLK[0])
Timer0
TMR0_EN (APBCLK[2])
Timer1
TMR1_EN (APBCLK[3])
Frequency Divider
FDIV_EN (APBCLK[6])
I2C
I2C_EN (APBCLK[8])
SPI
SPI_EN (APBCLK[12])
UART
PWM01_EN (APBCLK[20])
PWM01
PWM23_EN (APBCLK[21])
PWM23
PWM45_EN (APBCLK[22])
PWM45
ADC_EN (APBCLK[28])
ADC
CMP_EN (APBCLK[30])
ACMP
NUMICRO™ MINI51 SERIES DATASHEET
UART_EN (APBCLK[16])
Figure 5.4-5 Peripherals Clock Source Selection for PCLK
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
Ext. CLK (12M or 32K)
IRC22.1184M
IRC10K
PCLK
WDT
Yes
No
Yes
Yes
Timer0
Yes
Yes
Yes
Yes
Timer1
Yes
Yes
Yes
Yes
IC
No
No
No
Yes
SPI
No
No
No
Yes
UART
Yes
Yes
No
No
PWM
No
No
No
Yes
ADC
Yes
Yes
No
Yes
ACMP
No
No
No
Yes
2
Table 5.4-1 Peripherals Engine Clock Source Selection Table
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NuMicro™ Mini51 Series Data Sheet
5.4.6
Power-down Mode Clock
When entering Power-down mode, some clock sources and peripheral clocks and system clocks
will be disabled. Some clock sources and peripheral clocks are still active in Power-down mode.
Clocks that still be kept active are listed below.
Clock Generator
Internal 10 KHz RC oscillator (LIRC) clock
External 32.768 KHz crystal oscillator (LXT) clock (If PD_32K = “1” and
XTLCLK_EN[1:0] = “10”)
Peripherals Clock (When these IP adopt 10 KHz as clock source)
Watchdog Clock
Timer 0/1 Clock
NUMICRO™ MINI51 SERIES DATASHEET
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
5.4.7
Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed of 16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to P3.6. Therefore, there are 16 options of power-of-2 divided clocks with
the frequency from Fin/21 to Fin/217 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FREQDIV.FSEL[3:0].
When FREQDIV.FDIV_EN[4] is set to high, the rising transition will reset the chained counter and
starts counting. When FREQDIV.FDIV_EN[4] is written with zero, the chained counter
continuously runs until the divided clock reaches low state and stays in low state.
CLKSEL2.FRQDIV_S[3:2]
APBCLK.FRQDIV_EN[6]
22.1184M
HCLK
11
FRQDIV_CLK
10
12M or 32K
00
Figure 5.4-6 Clock Source of Frequency Divider
FREQDIV.FDIV_EN[4]
0 to 1
16 chained
divide-by-2 counter
Reset Clock
Divider
FRQDIV_CLK
1/2
1/22
1/23
…...
1/21
5
1/21
6
000
001
:
:
110
111
16 to 1
MUX
10
P3_DOUT[6]
FREQDIV.FSEL[3:0]
P3.6/CPO0/C
LKO
00
P3_ALT[6]
P3_MFP[6]
Figure 5.4-7 Block Diagram of Frequency Divider
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NuMicro™ Mini51 Series Data Sheet
5.5
Comparator Controller (CMPC)
5.5.1
Overview
The NuMicro Mini51 Series contains two comparators which can be used in a number of
different configurations. The comparator output is a logical one when positive input is greater than
negative input; otherwise, the output is zero. Each comparator can be configured to cause an
interrupt when the comparator output value changes. The block diagram is shown in 錯誤! 找不到
參照來源。.
Note that the analog input port pins must be configured as the input type before Analog
Comparator function is enabled.
5.5.2
Features
Analog input voltage range: 0 ~ 5.0V
Hysteresis function support
Two analog comparators with optional internal reference voltage input at negative end
One comparator interrupt requested by one of the comparators
NUMICRO™ MINI51 SERIES DATASHEET
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
5.6
Analog-to-Digital Converter (ADC)
5.6.1
Overview
The NuMicro Mini51 series contains one 10-bit successive approximation analog-to-digital
converters (SAR A/D converter) with 8 input channels. The A/D converters can be started by
software and external STADC/P3.2 pin.
Note that the analog input pins must be configured as input type before ADC function is enabled.
5.6.2
Features
Analog input voltage range: 0 ~ Vref (Max to 5.0 V)
10-bit resolution and 8-bit accuracy is guaranteed
Up to 8 single-end analog input channels
Maximum ADC clock frequency is 6 MHz
Up to 150K SPS conversion rate
An A/D conversion is performed one time on a specified channel
An A/D conversion can be started by:
Software write “1” to ADST bit
External pin STADC
Conversion results are held in data register with valid and overrun indicators
Conversion results can be compared with specified value and user can select whether
to generate an interrupt when conversion results are equal to the compare register
settings
Channel 7 supports 2 input sources: External analog voltage and internal fixed bandgap voltage
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NuMicro™ Mini51 Series Data Sheet
5.7
Flash Memory Controller (FMC)
5.7.1
Overview
TM
The NuMicro Mini51 series is equipped with 4K/8K/16K bytes on chip embedded Flash EPROM
for application program memory (APROM) that can be updated through ISP procedure. In System
Programming (ISP) function enables user to update program memory when chip is soldered on
PCB. After chip powered on Cortex-M0 CPU fetches code from APROM or LDROM decided by
TM
boot select (CBS) in Config0. By the way, the NuMicro Mini51 series also provides DATA Flash
Region, where the data flash is shared with original program memory and its start address is
configurable and defined by user in Config1. The data flash size is defined by user depending on
the application request.
5.7.2
Features
Compatible with AHB interface
Running up to 24 MHz with zero wait state for discontinuous address read access
4K/8K/16KB application program memory (APROM)
2KB in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page erase unit
In System Program (ISP) to update on chip Flash EPROM
NUMICRO™ MINI51 SERIES DATASHEET
Feb 9, 2012
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
5.8
General Purpose I/O
5.8.1
Overview
There are 30 General Purpose I/O pins shared with special feature functions in this MCU. The 30
pins are arranged in 6 ports named P0, P1, P2, P3, P4 and P5. Each of the 30 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each I/O pin can be independently software configured as input, output, opendrain, or Quasi-bidirectional mode. After reset, the I/O type of all pins stay in input mode and port
data register Px_DOUT[n] resets to “1”. For Quasi-bidirectional mode, each I/O pin is equipped
with a very weak individual pull-up resistor about 110K ~ 300K for VDD from 5.0V to 2.5V.
5.8.2
Features
Four I/O modes:
Quasi bi-direction
Push-Pull output
Open-Drain output
Input-only with high impendence
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
High driver and high sink IO mode support
Feb 9, 2012
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NuMicro™ Mini51 Series Data Sheet
I2C Serial Interface Controller (Master/Slave)
5.9
5.9.1
Overview
2
I C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
2
exchange between devices. The I C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously. Serial 8-bit oriented bi-directional data transfers can be made up 1.0
Mbps.
Data is transferred between a master and a slave synchronously to SCL on the SDA line on a
byte-by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is
sampled during the high period of SCL; therefore, the SDA line may be changed only during the
low period of SCL and must be held stable during the high period of SCL. A transition on the SDA
line while SCL is high is interpreted as a command (START or STOP). Please refer to the
2
following figure for more detailed I C BUS Timing.
STOP
Repeated
START
START
STOP
SDA
tBUF
tLOW
tr
SCL
tHD;STA
tf
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
Figure 5.9-1 Bus Timing
2
2
5.9.2
Features
2
The I C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the bus are:
Supports Master/Slave mode
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Feb 9, 2012
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NUMICRO™ MINI51 SERIES DATASHEET
The device’s on-chip I C logic provides the serial interface that meets the I C bus standard mode
2
specification. The I C port handles byte transfers autonomously. To enable this port, the bit ENSI
2
2
in I2CON should be set to “1”. The I C hardware interfaces to the I C bus via two pins: SDA (P3.4,
serial data line) and SCL (P3.5, serial clock line). Since the pull-up resistor is needed for Pin P3.4
2
2
and P3.5 for I C operation as these are open-drain pins. When the I/O pins are used as I C port,
2
user must set the pins function to I C in advance.
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
2
2
Built-in 14-bit time-out counter that requests the I C interrupt if the I C bus hangs up
and timer-out counter overflows
External pull-up needed for higher output pull-up speed
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave address registers with mask option)
Feb 9, 2012
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NuMicro™ Mini51 Series Data Sheet
5.10 Enhanced PWM Generator
5.10.1 Overview
The NuMicro Mini51 series has built one PWM unit which is specially designed for motor driving
control applications. The PWM unit supports 6 PWM generators which can be configured as 6
independent PWM outputs, PWM0~PWM5, or as 3 complementary PWM pairs, (PWM0, PWM1),
(PWM2, PWM3) and (PWM4, PWM5) with 3 programmable dead-zone generators.
Each PWM generator shares the 8-bit prescaler, clock divider providing 5 divided frequencies (1,
1/2, 1/4, 1/8, 1/16). Each PWM output has independent 16-bit counter for PWM period control,
and 16-bit comparators for PWM duty control. The 6 PWM generators provide six independent
PWM interrupt flags which are set by hardware when the corresponding PWM period counter
comparison matched. Each PWM interrupt source with its corresponding enable bit can request
PWM interrupt. The PWM generators can be configured as One-shot mode to produce only one
PWM cycle signal or Auto-reload mode to output PWM waveform continuously.
5.10.2 Features
The PWM unit supports the following features:
Six independent 16-bit PWM duty control units with maximum 6 port pins:
6 independent PWM outputs – PWM0, PWM1, PWM2, PWM3, PWM4, and
PWM5
3 complementary PWM pairs, with each pin in a pair mutually complement to
each other and capable of programmable dead-zone insertion – (PWM0,
PWM1), (PWM2, PWM3) and (PWM4, PWM5)
3 synchronous PWM pairs, with each pin in a pair in-phase – (PWM0, PWM1),
(PWM2, PWM3) and (PWM4, PWM5)
Group control bit – PWM2 and PWM4 are synchronized with PWM0
One-shot (only support edge alignment mode) or Auto-reload mode PWM
Up to 16-bit resolution
Supports Edge-aligned and Center-aligned mode
Programmable dead-zone insertion between complementary paired PWMs
Each pin of PWM0 to PWM5 has independent polarity setting control
Hardware fault brake protections
Feb 9, 2012
Two Interrupt source types:
Synchronously requested at PWM frequency when down counter
comparison matched (edge- and center-aligned mode) or underflow (edgealigned mode)
Requested when external fault brake asserted
BKP0: EINT0
BKP1: EINT1 or CPO0
The PWM signals before polarity control stage are defined in view of positive logic.
Whether the PWM ports are active high or active low is controlled by the polarity
control register.
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NUMICRO™ MINI51 SERIES DATASHEET
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
HyperTerminal
Trapezoidal Commutation System Architecture
+VDC Bus
DC Bus +
BLDC
Isolation
circuit
UART
N
UART Interface
MINI51
+5V
UART
Timer
nINT0
Push
Button
S
+5V
CPO0
Enhanced
PWM0
PWM PWM1
PWM2
PWM3
PWM4
PWM5
DC Bus -
3-Phase Inverter
(IPM, MOSFET, IGBT)
AIN[6]
AIN[0]
AIN[1]
AIN[2]
AIN[7] AIN[3]
ADC
+VDC Bus
+5V
Option 1
Option 2
Sensorless circuit
Figure 5.10-1 Application Circuit Diagram
Feb 9, 2012
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NuMicro™ Mini51 Series Data Sheet
5.11 Serial Peripheral Interface (SPI) Controller
5.11.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which
operates in full duplex mode. Devices communicate in Master/Slave mode with 4-wire bi-direction
interface. NuMicro Mini51 series contain one set of SPI controller performing a serial-to-parallel
conversion on data received from a peripheral device, and a parallel-to-serial conversion on data
transmitted to a peripheral device. SPI controller can be set as a master; it also can be set as a
slave controlled by an off-chip master device.
5.11.2 Features
Supports Master or Slave mode operation
MSB or LSB first transfer
Byte or word Suspend mode
Variable output serial clock frequency in Master mode
Supports two programmable serial clock frequencies in Master mode
NUMICRO™ MINI51 SERIES DATASHEET
Feb 9, 2012
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
5.12 Timer Controller
5.12.1 Overview
The timer module includes two channels, TIMER0~TIMER1, which allow user to easily implement
a timer control for applications. The timer can perform functions like frequency measurement,
interval measurement, clock generation, delay timing, and so on. The timer can generate an
interrupt signal upon time-out, or provide the current value of count during operation.
5.12.2 Features
Two sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter
Independent clock source for each channel (TMR0_CLK, TMR1_CLK)
Provides one-shot, periodic, toggle and continuous counting operation modes
Time-out period = (period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit
TCMP)
Maximum counting cycle time = (1 / T MHz) * (2 ) * (2 ); T is the period of timer clock
Internal 24-bit up timer is readable through TDR (Timer Data Register)
Supports event counting function to count the event from external pin
Supports input capture function to capture or reset counter value
Feb 9, 2012
8
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24
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NuMicro™ Mini51 Series Data Sheet
5.13 UART Interface Controller
The NuMicro Mini51 series provides one channel of Universal Asynchronous
Receiver/Transmitters (UART). UART performs Normal Speed UART, and support flow control
function.
5.13.1 Overview
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel
conversion on data received from the peripheral, and a parallel-to-serial conversion on data
transmitted from the CPU. The UART controller also supports IrDA SIR function, and RS-485
mode functions. Each UART channel supports six types of interrupts, including transmitter FIFO
empty interrupt (INT_THRE), receiver threshold level reaching interrupt (INT_RDA), line status
interrupt (parity error or framing error or break interrupt) (INT_RLS), receiver buffer time-out
interrupt (INT_TOUT), MODEM/Wake-up status interrupt (INT_MODEM), and Buffer error
interrupt (INT_BUF_ERR). Interrupt number 12 (vector number is 28) supports UART interrupt.
Refer to Nested Vectored Interrupt Controller chapter for System Interrupt Map.
The UART is built-in with a 16-byte transmitter FIFO (TX_FIFO) and a 16-byte receiver FIFO
(RX_FIFO) that reduces the number of interrupts presented to the CPU and the CPU can read the
status of the UART at any time during the operation. The reported status information includes the
type and condition of the transfer operations being performed by the UART, as well as 4 error
conditions (parity error, framing error, break interrupt and buffer error) probably occur while
receiving data. The UART includes a programmable baud rate generator that is capable of
dividing crystal clock input by divisors to produce the clock that transmitter and receiver need. The
baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2], where M and BRD are defined in
Baud Rate Divider Register (UA_BAUD). The following table lists the equations in the various
conditions and the UART baud rate setting table.
Table 5.13-1 UART Baud Rate Setting Table
DIV_X_EN
DIV_X_ONE
Divider X
BRD Baud Rate Equation
0
0
0
B
A
UART_CLK / [16 * (A+2)]
1
1
0
B
A
UART_CLK / [(B+1) * (A+2)] , B must
>= 8
2
1
1
Don’t care
A
UART_CLK / (A+2), A must >=3
Table 5.13-2 UART Baud Rate Setting Table
System clock = 22.1184 MHz
Baud rate
Mode0
Mode1
Mode2
921600
Not Support
A=0, B=11
A=22
460800
A=1
A=1, B=15
A=2, B=11
A=46
230400
A=4
A=4, B=15
A=6, B=11
A=94
115200
A=10
A=10, B=15
A=190
Feb 9, 2012
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NUMICRO™ MINI51 SERIES DATASHEET
Mode
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
A=14, B=11
57600
A=22
A=22, B=15
A=30, B=11
A=382
38400
A=34
A=62, B=8
A=46, B=11
A=34, B=15
A=574
19200
A=70
A=126, B=8
A=94, B=11
A=70, B=15
A=1150
9600
A=142
A=254, B=8
A=190, B=11
A=142, B=15
A=2302
4800
A=286
A=510, B=8
A=382, B=11
A=286, B=15
A=4606
5.13.1.1 Auto-Flow Control
The UART controller supports auto-flow control function that uses two low-level signals, CTSn
(clear-to-send) and RTSn (request-to-send), to control the flow of data transfer between the
UART and external devices (ex: Modem). When auto-flow is enabled, the UART is not allowed to
receive data until the UART asserts RTSn to external device. When the number of bytes in the
RX FIFO equals the value of RTS_TRI_LEV (UA_FCR[19:16]), the RTSn is de-asserted. The
UART sends data out when UART controller detects CTSn is asserted from external device. If a
validly asserted CTSn is not detected the UART controller will not send data out.
5.13.1.2 IrDA Function Mode
The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (user must set
IrDA_EN (UA_FUN_SEL[1:0]) to enable IrDA function). The SIR specification defines a shortrange infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop
bit. The maximum data rate is 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA SIR
Protocol encoder/decoder. The IrDA SIR protocol is half-duplex only. Thus it cannot transmit and
receive data at the same time. The IrDA SIR physical layer specifies a minimum 10ms transfer
delay between transmission and reception. This delay feature must be implemented by software.
5.13.1.3 RS-485 Function Mode
Alternate function of UART controllers is RS-485 9 bit mode function, direction control provided by
RTSn pin or can program GPIO (P0.1 for RTSn) to implement the function by software. The RS485 mode is selected by setting the UA_FUN_SEL register to select RS-485 function. The RS485 driver control is implemented using the RTSn control signal from an asynchronous serial port
to enable the RS-485 driver. In RS-485 mode, many characteristics of the RX and TX are the
same as UART.
Feb 9, 2012
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NuMicro™ Mini51 Series Data Sheet
5.13.2 Features
Full duplex, asynchronous communications
Separates receive/transmit 16 bytes entry FIFO for data payloads
Supports hardware auto flow control/flow control function (CTSn, RTSn) and
programmable RTSn flow control trigger level
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTSn wake-up function
Supports 7-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start
bit by setting UA_TOR[DLY] register
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5, 6, 7, 8 character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Supports 3/16-bit duration for normal mode
Supports RS-485 function mode
Supports RS-485 9-bit mode
Supports hardware or software RTSn control or software GPIO control to control
transfer direction
NUMICRO™ MINI51 SERIES DATASHEET
Feb 9, 2012
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
5.14 Watchdog Timer
5.14.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset after software runs into a
problem. This prevents system from hanging for an infinite period of time. Besides, the Watchdog
Timer supports another function to wake up CPU from Power-down mode. The Watchdog timer
includes an 18-bit free running counter with programmable time-out intervals. The following table
shows the Watchdog time-out interval selection and the following figure shows the timing of
Watchdog interrupt signal and reset signal.
Setting WTE (WTCR[7]) will enable the watchdog timer and the WDT counter starts counting up.
When the counter reaches the selected time-out interval, the Watchdog timer interrupt flag WTIF
will be set immediately to request a WDT interrupt if the Watchdog timer interrupt enable bit WTIE
is set; in the meanwhile, a specified delay time (1024 * TWDT) follows the time-out event. User
must set WTR (WTCR[0]) (Watchdog Timer Reset) high to reset the 18-bit WDT counter to avoid
CPU from Watchdog Timer Reset before the delay time expires. The WTR bit is cleared
automatically by hardware after the WDT counter is reset. There are eight time-out intervals with
specific delay time which are selected by Watchdog timer interval select bits WTIS (WTCR[10:8]).
If the WDT counter has not been cleared after the specific delay time expires, the Watchdog timer
will set Watchdog Timer Reset Flag (WTRF) high and reset CPU. This reset will last 63 WDT
clocks (TRST) and then CPU restarts executing program from reset vector (0x0000_0000). WTRF
will not be cleared by Watchdog reset. User may poll WTRF through software to recognize the
reset source. WDT also provides the wake-up function. When chip is powered down and the
Watchdog Timer Wake-up Function Enable bit (WTCR[4]) is set, if the WDT counter has not been
cleared after the specific delay time expires, the chip will be waked up from Power-down state.
WTIS
WTR Timeout
Interval
TTIS
Interrupt Period
TINT
WTR Timeout Interval
(WDT_CLK = 10 KHz)
TTIS
WTR Reset Interval
(WDT_CLK = 10 KHz)
TWTR
000
24 * TWDT
1024 * TWDT
1.6 ms
104 ms
001
26
* TWDT
1024 * TWDT
6.4 ms
108.8 ms
010
28 * TWDT
1024 * TWDT
25.6 ms
128 ms
011
210 * TWDT
1024 * TWDT
102.4 ms
204.8 ms
100
212 * TWDT
1024 * TWDT
407 ms
512 ms
101
214 * TWDT
1024 * TWDT
1.638 s
1.741 s
110
216 * TWDT
1024 * TWDT
6.553 s
6.6.656 s
111
218 * TWDT
1024 * TWDT
26.214 s
26.316 s
Table 5.14-1 Watchdog Time-out Interval Selection
Feb 9, 2012
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NuMicro™ Mini51 Series Data Sheet
TWDT
TTIS
INT
TINT
1024 * TWDT
TRST
RST
Minimum TWTR
63 * TWDT
Maximum TWTR
TWDT : Watchdog Engine Clock Time Period
TTIS : Watchdog Timeout Interval Selection Period
TINT : Watchdog Interrupt Period
TRST : Watchdog Reset Period
TWTR : Watchdog Timeout Interval Period
Figure 5.14-1 Timing of Interrupt and Reset Signal
5.14.2 Features
18-bit free running counter to avoid CPU from Watchdog Timer Reset before the delay
time expires.
Selectable time-out interval (24 ~ 218) and the time-out interval is 104 ms ~ 26.3168 s
(if WDT_CLK = 10 KHz).
Reset period = (1 / 10 KHz) * 63, if WDT_CLK = 10 KHz.
NUMICRO™ MINI51 SERIES DATASHEET
Feb 9, 2012
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Revision V1.03
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
6
6.1
ARM® CORTEX™-M0 CORE
Overview
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex-M
profile processors. The profile supports two modes - Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset and can be entered as a result of an exception return. 錯
誤! 找不到參照來源。 shows the functional controller of the processor.
Cortex-M0 components
Cortex-M0 processor
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Wakeup
Interrupt
Controller
(WIC)
Debug
Cortex-M0
Processor
core
Breakpoint
and
Watchpoint
unit
Bus matrix
Debugger
interface
AHB-Lite interface
Debug
Access Port
(DAP)
Serial Wire or
JTAG debug port
Figure 6.1-1 Functional Block Diagram
Feb 9, 2012
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NuMicro™ Mini51 Series Data Sheet
6.2
Features
A low gate count processor
®
ARMv6-M Thumb instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
Supports little-endian data accesses
Deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
C Application Binary Interface compliant exception model:
ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model
that enables the use of pure C functions as interrupt handlers
Feb 9, 2012
NVIC
32 external interrupt inputs, each with four levels of priority
Dedicated Non-Maskable Interrupt (NMI) input
Supports both level-sensitive and pulse-sensitive interrupt lines
Wake-up Interrupt Controller (WIC) with ultra-low power Idle mode support
Debug support
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
Single 32-bit slave port that supports the Debug Access Port DAP (DAP)
Page 51 of 68
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NUMICRO™ MINI51 SERIES DATASHEET
Low power Idle mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
7
APPLICATION CIRCUIT
VCC
DAVDD
R1
10K
R0603
SW1
CB1
0.1uF
C0603
TICERST
C1
10uF/10V
TANT-A
Reset Circuit
48
47
46
45
44
43
42
41
40
39
38
37
PIN48
PIN47
PIN46
PIN45
PIN44
PIN43
PIN42
PIN41
PIN40
PIN39
PIN38
PIN37
SW
PUSH BOTTOM
NC
CPN0/AIN4/P1.4
TXD/AIN3/P1.3
RXD/AIN2/P1.2
AIN1/P1.0
AVDD
VDD
AIN0/P5.3
NC
NC
TXD/CTS/P0.0
SPISS/RXD/RTS/P0.1
U1
From ICE Bridge's USB Power
VCC
1
3
5
7
9
2
4
6
8
10
TICERST
TICEDAT
TICECLK
TICERST
HEADER 5X2
HEADER5x2
ICE Interface
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
PIN8
PIN9
PIN10
PIN11
PIN12
1
2
3
4
5
6
7
8
9
10
11
12
NC
CPP0/AIN5/P1.5
RST
CPN1/AIN6/P3.0
AVSS
P5.4
CPP1/AIN7/P3.1
T0EX/STADC/INT0/P3.2
SDA/T0/P3.4
SCL/T1/P3.5
NC
NC
NC
P0.4/SPISS/PWM5
P0.5/MOSI
P0.6/MISO
P0.7/SPICLK
NC
P4.7/ICE_DAT
P4.6/ICE_CLK
NC
NC
P2.6/PWM4/CPO1
P2.5/PWM3
NC
P3.6/CKO/T1EX/CPO0
P5.1/XTAL2
P5.0/XTAL1
VSS
LDO_CAP
P5.5
P5.2/INT1
NC
P2.2/PWM0
P2.3/PWM1
P2.4/PWM2
JP4
ADAVSS
C3
XTAL2
36
35
34
33
32
31
30
29
28
27
26
25
PIN36
PIN35
PIN34
PIN33
PIN32
PIN31
PIN30
PIN29
PIN28
PIN27
PIN26
PIN25
TICEDAT
TICECLK
13
14
15
16
17
18
19
20
21
22
23
24
MINI54LAN LQFP48
20pF/NC
C0603
X2
12MHz
XTAL3-1
PIN13
PIN14
PIN15
PIN16
PIN17
PIN18
PIN19
PIN20
PIN21
PIN22
PIN23
PIN24
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
C5
XTAL1
20pF/NC
C0603
VCC
L1
L0603
XTAL2
XTAL1
Crystal
Feb 9, 2012
DAVDD
C2
10uF/10V
TANT-A
L2
L0603
ADAVSS
Page 52 of 68
Revision V1.03
NuMicro™ Mini51 Series Data Sheet
8
8.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
SYMBOL
PARAMETER
Min
MAX
UNIT
VDDVSS
-0.3
+7.0
V
VIN
VSS-0.3
VDD+0.3
V
1/tCLCL
4
24
MHz
TA
-40
+85
C
TST
-55
+150
C
-
120
mA
Maximum current out of VSS
120
mA
Maximum current sunk by a I/O pin
35
mA
Maximum current sourced by a I/O pin
35
mA
Maximum current sunk by total I/O pins
100
mA
Maximum current sourced by total I/O pins
100
mA
DC power supply
Input voltage
Oscillator frequency
Operating temperature
Storage temperature
Maximum current into VDD
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and
reliability of the device.
NUMICRO™ MINI51 SERIES DATASHEET
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NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
8.2
DC Electrical Characteristics
(VDD-VSS = 5.0 V, TA = 25C, FOSC = 24 MHz unless otherwise specified.)
Specification
PARAMETER
Sym.
TEST CONDITIONS
Min.
TYP.
Max.
Unit
5.5
V
Operation voltage
VDD
2.5
VDD rise rate to ensure
internal operation
correctly
VRISE
0.05
V/mS
-0.3
V
Power ground
VSS
AVSS
LDO output voltage
VLDO
-10%
Analog operating
voltage
AVDD
0
Operating current
1.8
+10%
V
VDD
V
VDD = 2.5 V ~ 5.5 V up to 24 MHz
VDD = 2.5V ~ 5.5V
IDD1
9.5
mA
VDD = 5.5V at 24 MHz, all IP Enabled
IDD2
7.5
mA
VDD = 5.5V at 24 MHz, all IP Disabled
IDD3
7.5
mA
VDD = 3.3V at 24 MHz, all IP Enabled
IDD4
6
mA
VDD = 3.3V at 24 MHz, all IP Disabled
IDD5
5.5
mA
VDD = 5.5V at 12 MHz, all IP Enabled
IDD6
4.5
mA
VDD = 5.5V at 12 MHz, all IP Disabled
IDD7
4
mA
VDD = 3.3V at 12 MHz, all IP Enabled
IDD8
3
mA
VDD = 3.3V at 12 MHz, all IP Disabled
IDD9
3.6
mA
VDD = 5.5V at 4 MHz, all IP Enabled
IDD10
3.3
mA
VDD = 5.5V at 4 MHz, all IP Disabled
IDD11
1.7
mA
VDD = 3.3V at 4 MHz, all IP Enabled
IDD12
1.4
mA
VDD = 3.3V at 4 MHz, all IP Disabled
IDD13
6.6
mA
IDD14
5
mA
IDD15
6.6
mA
IDD16
5
mA
Normal run mode
at 24 MHz
Operating current
Normal run mode
at 12 MHz
Operating current
Normal run mode
at 4 MHz
Operating current
VDD = 5.5V at 22.1184 MHz,
all IP Enabled
VDD = 5.5V at 22.1184 MHz,
all IP Disabled
Normal run mode
at 22.1184 MHz IRC
Feb 9, 2012
Page 54 of 68
VDD = 3.3V at 22.1184 MHz,
all IP Enabled
VDD = 3.3V at 22.1184 MHz,
all IP Disabled
Revision V1.03
NuMicro™ Mini51 Series Data Sheet
Specification
PARAMETER
Sym.
TEST CONDITIONS
Min.
Operating current
TYP.
Max.
Unit
116
A
IDD18
113
A
IDD19
112
A
IDD20
100
A
IDD21
109
A
VDD = 5.5V at 10 KHz, all IP Enabled
IDD22
108
A
VDD = 5.5V at 10 KHz, all IP Disabled
IDD23
100
A
VDD = 3.3V at 10 KHz, all IP Enabled
IDD24
98
A
VDD = 3.3V at 10 KHz, all IP Disabled
IIDLE1
5.5
mA
VDD = 5.5V at 24 MHz, all IP Enabled
IIDLE2
3.5
mA
VDD = 5.5V at 24 MHz, all IP Disabled
IIDLE3
3.8
mA
VDD = 3.3V at 24 MHz, all IP Enabled
IIDLE4
1.8
mA
VDD = 3.3V at 24 MHz, all IP Disabled
IIDLE5
3.3
mA
VDD = 5.5V at 12 MHz, all IP Enabled
IIDLE6
2.6
mA
VDD = 5.5V at 12 MHz, all IP Disabled
IIDLE7
2
mA
VDD = 3.3V at 12 MHz, all IP Enabled
IIDLE8
1
mA
VDD = 3.3V at 12 MHz, all IP Disabled
IIDLE9
3
mA
VDD = 5.5V at 4 MHz, all IP Enabled
IIDLE10
2.3
mA
VDD = 5.5V at 4 MHz, all IP Disabled
IIDLE11
1
mA
VDD = 3.3V at 4 MHz, all IP Enabled
IIDLE12
0.7
mA
VDD = 3.3V at 4 MHz, all IP Disabled
IIDLE13
3.0
mA
IIDLE14
1.2
mA
IIDLE15
3.0
mA
Normal run mode
at 32.768 KHz crystal
oscillator
Operating current
Normal run mode
at 10 KHz IRC
Operating current
VDD = 5.5V at 32.768 KHz,
IDD17
all IP Enabled
VDD = 5.5V at 32.768 KHz,
all IP Disabled
VDD = 3.3V at 32.768 KHz,
all IP Enabled
VDD = 3.3V at 32.768 KHz,
all IP Disabled
Idle mode
at 24 MHz
Operating current
Idle mode
at 12 MHz
Idle mode
at 4 MHz
Operating current
Idle mode
at 22.1184 MHz IRC
Feb 9, 2012
Page 55 of 68
VDD = 5.5V at 22.1184 MHz,
all IP Enabled
VDD = 5.5V at 22.1184 MHz,
all IP Disabled
VDD = 3.3V at 22.1184 MHz,
all IP Enabled
Revision V1.03
NUMICRO™ MINI51 SERIES DATASHEET
Operating current
NUMICRO™ MINI51 SERIES DATASHEET
NuMicro™ Mini51 Series Data Sheet
Specification
PARAMETER
Sym.
TEST CONDITIONS
Min.
Operating current
TYP.
Max.
Unit
1.2
mA
IIDLE17
110
A
IIDLE18
107
A
IIDLE19
105
A
IIDLE20
102
A
IIDLE21
103
A
VDD = 5.5V at 10 KHz, all IP Enabled
IIDLE22
102
A
VDD = 5.5V at 10 KHz, all IP Disabled
IIDLE23
96
A
VDD = 3.3V at 10 KHz, all IP Enabled
IIDLE24
95
A
VDD = 3.3V at 10 KHz, all IP Disabled
IPWD1
10
A
IPWD2
5
A
Idle mode
at 32.768 KHz crystal
oscillator
Operating current
Idle mode
at 10 KHz IRC
VDD = 3.3V at 22.1184 MHz,
IIDLE16
Standby current
Power-down mode
all IP Disabled
VDD = 5.5V at 32.768 KHz,
all IP Enabled
VDD = 5.5V at 32.768 KHz,
all IP Disabled
VDD = 3.3V at 32.768 KHz,
all IP Enabled
VDD = 3.3V at 32.768 KHz,
all IP Disabled
VDD = 5.0V, CPU STOP
All IP and Clock OFF
VDD = 3.3V, CPU STOP
All IP and Clock OFF
VDD = 5.0V, CPU STOP
IPWD3
12
A
IPWD4
7
A
Input current P0~P5
(Quasi-bidirectional
mode)
IIN1
-50
-60
A
VDD = 5.5 V, VIN = 0 V or VIN = VDD
Input current at
[1]
/RESET
IIN2
-55
-45
-30
A
VDD = 3.3 V, VIN = 0.45 V
Input leakage current
PA, PB, PC, PD, PE
ILK
-0.1
-
+0.1
A
VDD = 5.5 V, 0
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