RLST236A054LV Series
ULTRA LOW CAPACITANCE
TVS/ESD ARRAY
Description
Features
RLST236A054LV are surge rated diode arrays designed
to protect high speed data interfaces. The LV series has
been specifically designed to protect sensitive
components which are connected to data and
transmission lines from overvoltage caused by
electrostatic discharge (ESD), electrical fast transients
(EFT), and lightning.
The unique design of the LV series devices incorporates
eight surge rated, low capacitance steering diodes
and a TVS diode in a single package. During transient
conditions, the steering diodes direct the transient
to either the positive side of the power supply line
or to ground. The internal TVS diode prevents overvoltage on the power line, protecting any downstream
components.
The RLST236A054LV has a low typical capacitance
of 3pF and operates with virtually no insertion loss to
1GHz. This makes the device ideal for protection of
high-speed data lines such as USB 2.0, Firewire, DVI,
and gigabit Ethernet interfaces. The low capacitance
array configuration allows the user to protect four highspeed data or transmission lines.The low inductance
construction minimizes voltage overshoot during high
current surges. They may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(±15kV air, ±8kV contact discharge).
• Srand-off Voltage:5v
• Peak Power up to 300W@8*20μs Pulse
• Low Leakage current IEC61000-4-2
• Level 4 ESD Protection IEC61000-4-4
• Level 4 EFT Protection
• Low capacitance:0.7pF typical
Circuit Diagram
Pin Configuration
Mechanical Characteristics
• SOT-23 6L package
• Molding compound flammability rating: UL 94V-0
• Packaging : Tape and Reel per EIA 481
• pb-Free Packages are Auailable
Applications
• USB 2.0 Power and Data Line Protection
• Video Graphics Cards
• Monitors and Flat Panel Displays
• Digital Video Interface (DVI)
• 10/100/1000 Ethernet
• Notebook Computers
• SIM Ports
• ATM Interfaces
• IEEE 1394 Firewire Ports
5
1
3
4
6
2
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©2012 RuiLong Yuan,Inc.
ESD 01
Protection Products
Absolute Maximum Rating
Rating
Symbol
Value
Units
Peak Pulse Power (tp =8/20μs)
PPK
300
Watts
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
VESD
15
8
kV
Lead Soldering Temperature
TK
260 (10 sec.)
°C
Operating Temperature
TJ
-55 to +125
°C
TSTG
-55 to +150
°C
Storage Temperature
Electrical Characteristics (T=25oC)
RLST236A054LV
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Symbol
Conditions
Minimum
Typical
Maximum
Units
VRWM
-
-
-
5
V
VBR
It=1mA
6
7
-
V
-
-
5
μA
-
-
12
V
VR = 0V, f = 1MHz
Any I/O pin to Ground
-
1.2
1.5
pF
VR = 0V, f = 1MHz
Between I/O pins
-
0.7
-
pF
Reverse Leakage Current
IR
Clamping Voltage
VC
Junction Capacitance
ESD 02
Cj
VRWM=5V ,T=25°C
Pin 5 to 2
IPP=1A,tp= 8/20μs
Any I/O pin to Ground
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©2012 RuiLong Yuan,Inc.
Protection Products
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
Power Derating Curve
10
110
90
% of Rated Power or I PP
Peak Pulse Power - P
Pk
(kW)
100
1
0.1
80
70
60
50
40
30
20
10
0
0.01
0.1
1
10
100
0
1000
25
Pulse Duration - tp (µs)
Pulse Waveform
Waveform
Parameters:
tr = 8µs
td = 20µs
Clamping Voltage -V
Percent of I PP
80
-t
e
50
td = IPP/2
30
A
20
20.00
15.00
10.00
Waveform
Parameters:
tr = 8µs
td = 20µs
5.00
0
5
10
15
150
25.00
10
0
125
(o C)
30.00
(V)
90
40
100
C
100
60
75
Clamping Voltage vs. Peak Pulse Current
110
70
50
Ambient Temperature - T
20
25
0.00
30
0.00
2.00
Time (µs)
4.00
6.00
8.00
Peak Pulse Current - I
10.00
12.00
PP (A)
Normalized Capacitance vs. Reverse Voltage
Forward Voltage vs. Forward Current
1.4
7.00
CJ (V R) / C J (V R=0)
Forward Voltage -V
F
(V)
1.2
6.00
5.00
4.00
3.00
Waveform
Parameters:
tr = 8µs
td = 20µs
2.00
1.00
0.8
0.6
0.4
0.2
f = 1 MHz
0
0.00
0.00
1
0
2.00
4.00
6.00
Forward Current - I
8.00
F
10.00
1
12.00
2
3
Reverse Voltage - V
R
(V)
4
5
(A)
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©2012 RuiLong Yuan,Inc.
ESD 03
Protection Products
Typical Characteristics
Insert i on Loss S2 1
CH1S
21
LOG
START.
ESD 04
3 dB/
0300 00 MHzS
REF 0 dB
TOP3 000 . 0000 00 MHz
Anal og Cross Tal k
CH1S
21
LOG
START.
20 dB/
REF 0 dB
0300 00 MHz
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STOP3 000 . 0000 00 MHz
©2012 RuiLong Yuan,Inc.
Protection Products
Applications Information
Device Connection Options for Protection of Four
High-Speed Data Lines
The RLST236A054LV TVS is designed to protect four
data lines from transient over-voltages by clamping
them to afixed reference. When the voltage on the
protected line exceeds the reference voltage (plus diode
VF) the steering diodes are forward biased, conducting
the transient current away from the sensitive circuitry.
Data lines are connected at pins 1, 3, 4 and 6. The
negative reference (REF1) is connected at pin 2. This
pin should be connected directly to a ground plane on
the board for best results. The path length is kept as
short as possible to minimize parasitic inductance. The
positive reference (REF2) is connected at pin 5.The
options for connecting the positive reference are as
follows:
1. To protect data lines and the power line, connect
pin 5 directly to the positive supply rail (VCC). In this
configuration the data lines are referenced to the supply
voltage. The internal TVS diode prevents over-voltage
on the supply rail.
2. The RLST236A054LV can be isolated from the
power supply by adding a series resistor between pin 5
and VCC. A value of 100kΩ is recommended. The
internal TVS and steering diodes remain biased,
providing the advantage of lower capacitance.3. In
applications where no positive supply reference is
available, or complete supply isolation is desired,
the internal TVS may be used as the reference.
In this case, pin 5 is not connected. The steering
diodes will begin to conduct when the voltage on the
protected line exceeds the working voltage of the
TVS (plus one diode drop
). ESD Protection With
RLST236A054LV. RLST236A054LV are optimized
for ESD protection using the rail-to-rail topology. Along
with good board layout, these devices virtually eliminate
the disadvantages of using discrete components to
implement this topology. Consider the situation shown
in Figure 1 where discrete diodes or diode arrays are
configured for rail-torail protection on a high speed line.
During positive duration ESD events, the top diode will
be forward biased when the voltage on the protected
line exceeds
Data Line and Power Supply Protection Using Vcc as
reference
Data Line Protection with Bias and Power Supply
Isolation Resistor
Data Line Protection Using Internal T VS Diode as
Referenc e
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©2012 RuiLong Yuan,Inc.
ESD 05
Protection Products
Applications Information
the reference voltage plus the VF drop of the diode.
For negative events, the bottom diode will be biased
when the voltage exceeds the VF of the diode. At
first approximation, the clamping voltage due to the
characteristics of the protection diodes is given by:
VC = VCC + VF (for positive duration pulses)
VC = -VF (for negative duration pulses)
However, for fast rise time transient events, the effects of
parasitic inductance must also be considered as shown in
Figure 2. Therefore, the actual clamping voltage seen by
the protected circuit will be:
VC = VCC + VF + LP diESD/dt (for positive duration pulses)
VC = -VF - LG diESD/dt (for negative duration pulses)
ESD current reaches a peak amplitude of 30A in 1ns
for a level 4 ESD contact discharge per IEC 61000-42. Therefore, the voltage overshoot due to 1nH of series
inductance is:
V = LP diESD/dt = 1X10-9 (30 / 1X10-9) = 30V
Example:
Consider a VCC = 5V, a typical VF of 30V (at 30A) for the
steering diode and a series trace inductance of 10nH.
The clamping voltage seen by the protected IC for a
positive 8kV (30A) ESD pulse will be:
VC = 5V + 30V + (10nH X 30V/nH) = 335V
This does not take into account that the ESD current is
directed into the supply rail, potentially damaging any
components that are attached to that rail. Also note that it
is not uncommon for the VF of discrete diodes to exceed
the damage threshold of the protected IC. This is due
to the relatively small junction area of typical discrete
components. It is also possible that the power dissipation
capability of the discrete diode will be exceeded, thus
destroying the device. The RLST236A054LV is designed
to overcome the inherent disadvantages of using discrete
signal diodes for ESD suppression. The RLST236A054LV
integrated TVS diode
opology
Figure 11 -- ““RailRail-To-Rail” Prot ection TTopology
(First Approximation)
Figure 2 - The Effects o f Parasitic Inductance
When Using Discrete Components to Implement
RailTo-Rail P rot ection
Rail-T
Figure 3 - RailTo-Rail P o
r t ection U
sing
Using
RailClamp T
VS Arrays
TV
ESD 06
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©2012 RuiLong Yuan,Inc.
Protection Products
Applications Information
helps to mitigate the effects of parasitic inductance in
the power supply connection. During an ESD event,
the current will be directed through the integrated TVS
diode to ground. The maximum voltage seen by the
protected IC due to this path will be the clamping
voltage of the device.
Video Interface Protection
Video interfaces are susceptible to transient voltages
resulting from electrostatic discharge (ESD) and
“hot plugging” cables. If left unprotected, the video
interface IC may be damaged or even destroyed.
Protecting a high-speed video port presents some
unique challenges. First, any added protection
device must have extremely low capacitance and
low leakage current so that the integrity of the video
signal is not compromised. Second, the protection
component must be able to absorb high voltage
transients without
damage or degradation. As a minimum, the device
should be rated to handle ESD voltages per IEC
61000-4-2, level 4 (±15kV air, ±8kV contact). The
clamping voltage of the device (when conducting high
current ESD pulses) must be sufficiently low enough
to protect the sensitive CMOS IC. If the clamping
voltage is too high, the “protected” device may latchup or be destroyed. Finally, the device must take up
a relatively small amount of board space, particularly
in portable applications such as notebooks and
handhelds. The RLST236A054LV is designed to
meet or exceed all of the above criteria. A typical
video interface protection circuit is shown in Figure
4. All exposed lines are protected including R, G, B,
H-Sync, V-Sync , and the ID lines for plug and play
monitors.
Figure 4 - Video Interface Protection
Figure 5 - Dual USB Port Protection
Universal Serial Bus ESD Protection
The RLST236A054LV may also be used to protect
the USB ports on monitors, computers, peripherals or
portable systems. Each device will protect up to two
USB ports (Figure 5). When the voltage on the data
lines exceed the bus voltage (plus one diode drop),
the internal rectifiers are forward biased conducting
the transient current away from the protected
controller chip. The TVS diode directs the surge to
ground. The TVS diode also acts to suppress ESD
strikes directly on the voltage bus. Thus, both power
and data pins are protected with a single device.
Figure 6 - SIM Port
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©2012 RuiLong Yuan,Inc.
ESD 07
DVI Protection
The small geometry of a typical digital-visual interface
(DVI) graphic chip will make it more susceptible to
electrostatic discharges (ESD) and cable discharge
events (CDE). Transient protection of a DVI port can be
challenging. Digital-visual interfaces can often transmit
and receive at a rate equal to or above 1Gbps. The
high-speed data transmission requires the protection
device to have low capacitance to maintain signal
integrity and low clamping voltage to reduce stress on
the protected IC. The RLST236A054LV has a low typical
insertion loss of 1.5kV. If more common mode protection is needed,
figure 9 shows how to design the RLST236A054LV on
the IC side of the 10/100
Figure 7 - Digital Video Interface (DVI) Protection
ESD 08
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©2012 RuiLong Yuan,Inc.
Protection Products
Applications Information - Spice Model
Figure 8 - 10/100 Ethernet Differential Protection
Figure 9 - 10/100 Ethernet Differential and Common Mode Protection
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©2012 RuiLong Yuan,Inc.
ESD 09
Protection Products
Outline Drawing - SOT-23 6L
DIM
A
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A
A1
A2
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2X N/2 TIPS
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SEATING
PLANE
A2
DIMENSIONS
MILLIMETERS
INCHES
MIN NOM MAXM IN NOM MAX
.057
.035
.000
.006
.035 .045 .051
.010
.020
.003
.009
.110 .114 .122
.060 .063 .069
.110 BSC
.037 BSC
.075 BSC
.012 .018 .024
(.024)
6
0°
10°0
.004
.008
.008
A
H
A1
C
bxN
bbb
1.45
0.90
0.15
0.00
.90 1.15 1.30
0.25
0.50
0.22
0.08
2.80 2.90 3.10
1.50 1.60 1.75
2.80 BSC
0.95 BSC
1.90 BSC
0.30 0.45 0.60
(0.60)
6
°
10°
0.10
0.20
0.20
C A-B D
c
GAGE
PLANE
0.25
L
(L1)
SEE DETAIL
DETAIL
A
01
A
SIDE VIEW
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
Land Pattern - SOT-23 6L
X
DIM
(C)
G
Z
Y
P
C
G
P
X
Y
Z
DIMENSIONS
MILLIMETERS
INCHES
(.098)
.055
.037
.024
.043
.141
(2.50)
1.40
0.95
0.60
1.10
3.60
NOTES:
1.
ESD 10
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
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©2012 RuiLong Yuan,Inc.
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©2012 RuiLong Yuan,Inc.
ESD 11