RTL8152B-VB-CG
INTEGRATED 10/100M ETHERNET CONTROLLER
FOR USB APPLICATIONS
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.0
21 March 2013
Track ID: JATR-8275-15
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8152B-VB
Datasheet
COPYRIGHT
©2013 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
LICENSE
This product is covered by one or more of the following patents: US5,307,459, US5,434,872,
US5,732,094, US6,570,884, US6,115,776, and US6,327,625.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
Release Date
2013/03/21
Summary
First release.
Integrated 10/100M Ethernet Controller for USB Applications
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Datasheet
Table of Contents
1.
GENERAL DESCRIPTION ..............................................................................................................................................1
2.
FEATURES .........................................................................................................................................................................3
3.
SYSTEM APPLICATIONS...............................................................................................................................................3
4.
PIN ASSIGNMENTS .........................................................................................................................................................3
4.1.
5.
PIN DESCRIPTIONS.........................................................................................................................................................4
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
6.
PACKAGE IDENTIFICATION ...........................................................................................................................................3
POWER MANAGEMENT PIN ..........................................................................................................................................4
USB INTERFACE PINS ..................................................................................................................................................4
TRANSCEIVER INTERFACE PINS....................................................................................................................................4
CLOCK PINS .................................................................................................................................................................5
LDO REGULATOR AND REFERENCE PINS .....................................................................................................................5
SPI FLASH PINS ...........................................................................................................................................................5
LED PINS .....................................................................................................................................................................6
POWER AND GROUND PINS ..........................................................................................................................................6
GPIO PIN .....................................................................................................................................................................6
FUNCTIONAL DESCRIPTION.......................................................................................................................................7
6.1.
USB INTERFACE ..........................................................................................................................................................7
6.1.1. USB Configurations................................................................................................................................................7
6.1.2. Endpoint 0 ..............................................................................................................................................................7
6.1.3. Endpoint 1 Bulk-IN.................................................................................................................................................7
6.1.4. Endpoint 2 Bulk-OUT.............................................................................................................................................7
6.1.5. Endpoint 3 Interrupt-IN..........................................................................................................................................7
6.2.
CUSTOMIZABLE LED CONFIGURATION ........................................................................................................................8
6.2.1. LED Blinking Frequency Control...........................................................................................................................9
6.3.
PHY TRANSCEIVER ...................................................................................................................................................10
6.3.1. PHY Transmitter...................................................................................................................................................10
6.3.2. PHY Receiver .......................................................................................................................................................10
6.3.3. Link Down Power Saving Mode ...........................................................................................................................10
6.4.
SPI FLASH..................................................................................................................................................................11
6.5.
ENERGY EFFICIENT ETHERNET (EEE)........................................................................................................................11
6.6.
LINK POWER MANAGEMENT (LPM) ..........................................................................................................................11
6.7.
LAN DISABLE MODE .................................................................................................................................................12
6.8.
POWER MANAGEMENT...............................................................................................................................................12
6.9.
PROTOCOL OFFLOAD .................................................................................................................................................13
6.10.
XTAL-LESS WAKE-ON-LAN....................................................................................................................................13
6.11.
WAKE PACKET DETECTION (WPD) ...........................................................................................................................14
6.12.
‘REALWOW!’ (WAKE-ON-WAN) TECHNOLOGY ......................................................................................................14
6.13.
ALWAYS ON ALWAYS CONNECTED ...........................................................................................................................14
7.
LDO REGULATOR .........................................................................................................................................................14
8.
CHARACTERISTICS......................................................................................................................................................15
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................15
RECOMMENDED OPERATING CONDITIONS .................................................................................................................15
CRYSTAL REQUIREMENTS ..........................................................................................................................................16
OSCILLATOR REQUIREMENTS ....................................................................................................................................16
ENVIRONMENTAL CHARACTERISTICS ........................................................................................................................16
DC CHARACTERISTICS ...............................................................................................................................................17
REFLOW PROFILE RECOMMENDATIONS .....................................................................................................................17
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8.8.
AC CHARACTERISTICS ...............................................................................................................................................18
8.8.1. SPI Flash Commands ...........................................................................................................................................18
8.8.2. SPI Flash Interface Timing Sequences .................................................................................................................18
8.8.3. SPI Flash Type Supported ....................................................................................................................................20
9.
10.
MECHANICAL DIMENSIONS......................................................................................................................................21
ORDERING INFORMATION ...................................................................................................................................22
List of Tables
TABLE 1.
TABLE 2.
TABLE 3.
TABLE 4.
TABLE 5.
TABLE 6.
TABLE 7.
TABLE 8.
TABLE 9.
TABLE 10.
TABLE 11.
TABLE 12.
TABLE 13.
TABLE 14.
TABLE 15.
TABLE 16.
TABLE 17.
TABLE 18.
TABLE 19.
TABLE 20.
TABLE 21.
TABLE 22.
TABLE 23.
TABLE 24.
TABLE 25.
TABLE 26.
POWER MANAGEMENT PIN ...........................................................................................................................................4
USB INTERFACE PINS ...................................................................................................................................................4
TRANSCEIVER INTERFACE PINS ....................................................................................................................................4
CLOCK PINS ..................................................................................................................................................................5
LDO REGULATOR AND REFERENCE PINS .....................................................................................................................5
SPI FLASH PINS ............................................................................................................................................................5
LED PINS......................................................................................................................................................................6
POWER AND GROUND PINS ...........................................................................................................................................6
GPIO PIN ......................................................................................................................................................................6
LED SELECT ................................................................................................................................................................8
CUSTOMIZED LEDS .....................................................................................................................................................8
LED FEATURE CONTROL-1..........................................................................................................................................8
LED FEATURE CONTROL-2..........................................................................................................................................8
LED OPTION 1 & OPTION 2 SETTINGS .........................................................................................................................9
LED BLINKING FREQUENCY CONTROL ........................................................................................................................9
SPI FLASH INTERFACE ...............................................................................................................................................11
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................15
RECOMMENDED OPERATING CONDITIONS .................................................................................................................15
CRYSTAL REQUIREMENTS ..........................................................................................................................................16
OSCILLATOR REQUIREMENTS ....................................................................................................................................16
ENVIRONMENTAL CHARACTERISTICS ........................................................................................................................16
DC CHARACTERISTICS ...............................................................................................................................................17
REFLOW PROFILE RECOMMENDATIONS .....................................................................................................................17
SPI FLASH COMMANDS..............................................................................................................................................18
SPI FLASH TYPE SUPPORTED .....................................................................................................................................20
ORDERING INFORMATION ..........................................................................................................................................22
List of Figures
FIGURE 1.
FIGURE 2.
FIGURE 3.
FIGURE 4.
FIGURE 5.
FIGURE 6.
FIGURE 7.
PIN ASSIGNMENTS .......................................................................................................................................................3
LED BLINKING FREQUENCY AND DUTY CYCLE ..........................................................................................................9
WREN/WRDI TIMING SEQUENCE ............................................................................................................................18
READ TIMING SEQUENCE ..........................................................................................................................................18
PAGE PROGRAM TIMING SEQUENCE ..........................................................................................................................19
SECTOR/BLOCK ERASE TIMING SEQUENCE ...............................................................................................................19
CHIP ERASE TIMING SEQUENCE ................................................................................................................................19
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1.
General Description
The Realtek RTL8152B-VB-CG 10/100M Ethernet controller combines an IEEE 802.3u compliant
Media Access Controller (MAC), USB bus controller, and embedded memory. A linear regulator (LDO)
is incorporated for reduced BOM cost.
With state-of-the-art DSP technology and mixed-mode signal technology, the RTL8152B-VB offers
high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as
Crossover Detection and Auto-Correction, polarity correction, adaptive equalization, cross-talk
cancellation, echo cancellation, timing recovery, and error correction are implemented to provide robust
transmission and reception capabilities. The RTL8152B-VB features embedded One-Time-Programmable
(OTP) memory.
Advanced Configuration Power management Interface (ACPI)—power management for modern
operating systems that are capable of Operating System-directed Power Management (OSPM)—is
supported to achieve the most efficient power management possible. In addition to the ACPI feature,
remote wake-up (including AMD Magic Packet and Microsoft Wake-Up Frame) is supported in both
ACPI and APM (Advanced Power Management) environments.
The RTL8152B-VB supports Microsoft Wake Packet Detection (WPD) to provide Wake-Up Frame
information to the OS, e.g., PatternID, OriginalPacketSize, SavedPacketSize, SavedPacketOffset, etc.
WPD helps prevent unwanted/unauthorized wake-up of a sleeping computer.
The RTL8152B-VB supports ‘RealWoW!’ technology that enables remote wake-up of a sleeping PC
through the Internet. This feature allows PCs to reduce power consumption by remaining in low power
sleeping state until needed.
Note: The ‘RealWoW!’ service requires registration on first time use.
The RTL8152B-VB is fully compliant with Microsoft NDIS5, NDIS6 (IPv4, IPv6, TCP, UDP)
Checksum features, and supports IEEE 802 IP Layer 2 priority encoding and IEEE 802.1Q Virtual
bridged Local Area Network (VLAN). The above features contribute to lowering CPU utilization,
especially benefiting performance when in operation on a network server.
The RTL8152B-VB supports Protocol offload. It offloads some of the most common protocols to NIC
hardware in order to prevent spurious wake-up and further reduce power consumption. The
RTL8152B-VB can offload ARP (IPv4) and NS (IPv6) protocols while in the D3 power saving state.
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The RTL8152B-VB supports the ECMA (European Computer Manufacturers Association) proxy for
sleeping hosts standard. The standard specifies maintenance of network connectivity and presence via
proxies in order to extend the sleep duration of higher-powered hosts. It handles some network tasks on
behalf of the host, allowing the host to remain in sleep mode for longer periods. Required and optional
behavior of an operating proxy includes generating reply packets, ignoring packets, and waking the host.
The RTL8152B-VB supports IEEE 802.3az-2010, also known as Energy Efficient Ethernet (EEE). IEEE
802.3az operates with the IEEE 802.3 Media Access Control (MAC) Sublayer to support operation in
Low Power Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on both
sides of the link to save power.
The device also features USB 2.0 technology. It provides higher bandwidth and improved protocols for
data exchange between the host and the device. In addition, USB 2.0 offers a more aggressive power
management feature that enables selective suspend to save energy.
The RTL8152B-VB is suitable for multiple market segments and emerging applications, such as desktop,
mobile, workstation, server, communications platforms, docking station, and embedded applications.
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2.
Features
Hardware
Software Offload
Integrated 10/100M transceiver
Auto-Negotiation with Next Page capability
Supports USB 2.0 and 1.1
Supports pair swap/polarity/skew correction
IEEE
Crossover Detection & Auto-Correction
Supports Wake-On-LAN and ‘RealWoW!’
(Wake-On-WAN) Technology (see note 1)
Supports Full Duplex flow control
(IEEE 802.3x)
Supports ECMA-393 ECMA ProxZzzy
Standard for sleeping hosts (see note 1)
Fully compliant with IEEE 802.3,
IEEE 802.3u
Supports IEEE 802.1P Layer 2 Priority
Encoding
Microsoft NDIS5, NDIS6 Checksum
Offload (IPv4, IPv6, TCP, UDP) and
Segmentation Task-offload (Large send v1
and Large send v2) support
XTAL-Less Wake-On-LAN
Supports 25MHz or 48MHz external clock
(from oscillator or system clock source)
Supports IEEE 802.1Q VLAN tagging
Supports IEEE 802.3az-2010 (EEE)
Supports power down/link down power
saving
Microsoft AOAC (Always On Always
Connected)
Transmit/Receive on-chip buffer support
Embedded OTP memory
Built-in linear regulator (LDO)
Supports Customizable LEDs
Controllable LED Blinking Frequency and
Duty Cycle
Supports hardware CRC (Cyclic
Redundancy Check) function
LAN disable with GPIO pin
Supports LPM (Link Power Management)
SPI Flash Interface
Supports CDC-ECM
24-pin QFN ‘Green’ package
Integrated 10/100M Ethernet Controller for USB Applications
Supports 16-set 128-byte Wake-Up Frame
pattern exact matching
Supports link change wake up
Supports Microsoft WPD (Wake Packet
Detection)
Supports Protocol Offload (ARP & NS)
Intel CPPM (Converged Platform Power
Management)
Supports L1 with 3ms BESL
Supports selective suspend
Note 1. Select between RealWoW! or ECMA, only one
feature can be active at a time.
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3.
4.
System Applications
USB 10/100M Ethernet on Motherboard, Dongle, Notebook, Docking station, or Embedded system
Pin Assignments
Figure 1.
Pin Assignments
4.1. Package Identification
Green package is indicated by the ‘G’ in GXXXV (Figure 1). The version number is shown in the
location marked ‘V’.
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5.
Pin Descriptions
The signal type codes below are used in the following tables:
I: Input
O: Output
P: Power
5.1. Power Management Pin
Symbol
LANWAKEB
Type
Pin No
O
19
Table 1. Power Management Pin
Description
Power Management Event Output Pin (Active Low), minimum 7ms,
maximum 9ms.
5.2. USB Interface Pins
Symbol
U2DP
U2DM
Type
IO
IO
Pin No
8
7
Table 2. USB Interface Pins
Description
USB 2.0/USB 1.1 Differential Signal Pair.
5.3. Transceiver Interface Pins
Symbol
MDIP0
Type
IO
MDIN0
IO
MDIP1
IO
MDIN1
IO
Table 3. Transceiver Interface Pins
Pin No Description
2
In MDI mode, this pair acts as the BI_DA+/- pair, and is the transmit pair in
10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive
3
pair in 10Base-T and 100Base-TX.
4
In MDI mode, this pair acts as the BI_DB+/- pair, and is the receive pair in
10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the
5
transmit pair in 10Base-T and 100Base-TX.
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5.4. Clock Pins
Table 4. Clock Pins
Symbol
Type
Pin No Description
CKXTAL1
I
21
Input of 25MHz Clock Reference.
CKXTAL2
IO
22
Output of 25MHz Clock Reference.
Input of 25MHz or 48MHz External Clock Source.
XTALDET/SPISDI
I
18
Power-Up Strapping Pin.
Pull High: 25MHz clock source
Pull Low: 48MHz clock source
Note: When a 25MHz clock is used the XTALDET pin must be pulled high by a resistor during power-up. When a 48MHz
clock is used the XTALDET pin must be pulled low by a resistor during power-up.
5.5. LDO Regulator and Reference Pins
Symbol
AVDD33
Type
P
AVDD10
P
DVDD10_UPS
P
RSET
I
Table 5. LDO Regulator and Reference Pins
Pin No Description
10
Linear Regulator (LDO) 3.3V Output.
Note: The embedded LDO is designed for RTL8152B-VB internal use only. Do
not provide this power source to other devices.
23
Linear Regulator (LDO) 1.05V Output.
Note: The embedded LDO is designed for RTL8152B-VB internal use only. Do
not provide this power source to other devices.
12
Linear Regulator (LDO) 1.05V Output.
Note: The embedded LDO is designed for RTL8152B-VB internal use only. Do
not provide this power source to other devices.
24
Reference. External resistor reference.
5.6. SPI Flash Pins
Symbol
SPICSB
SPISDO
SPISDI/XTALDET
SPISCK
Type
O
I
O
O
Pin No
15
20
18
17
Table 6. SPI Flash Pins
Description
SPI Flash Chip Select.
Input from SPI Flash Serial Data Output Pin.
Output to SPI Flash Serial Data Input Pin.
SPI Flash Serial Data Clock.
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5.7. LED Pins
Table 7. LED Pins
Description
See section 6.2 Customizable LED Configuration, page 8 for details.
Symbol
Type
Pin No
LED0
O
15
LED1
O
17
Note: During power down mode, the LED signals are logic high.
5.8. Power and Ground Pins
Table 8. Power and Ground Pins
Symbol
Type
Pin No Description
VDD5
P
11
Analog 5.0V Power Supply.
AVDD33
P
1, 10
Analog 3.3V Power Supply.
DVDD33
P
13
Digital 3.3V Power Supply.
AVDD10
P
23
Analog 1.05V Power Supply.
DVDD10
P
16
Digital 1.05V Power Supply.
DVDD10_UPS
P
12
Digital 1.05V Uninterruptible Power Supply.
U2VDD10
P
9
USB 2.0/USB 1.1 Digital 1.05V Power Supply.
U2GND
P
6
USB 2.0/USB 1.1 Ground.
GND
P
25
Ground (Exposed Pad).
Note: Refer to the latest schematic circuit for correct configuration.
5.9. GPIO Pin
Symbol
GPIO
Type
IO
Pin No
14
Table 9. GPIO Pin
Description
General Purpose Input/Output Pin.
Link OK Feature: Output Pin (Active High)
Power Saving Feature: Output Pin (Active Low)
LAN Disable Mode: Input Pin (Active Low)
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6.
Functional Description
6.1. USB Interface
The SIE (Serial Interface Engine) employs a robust hardwired USB protocol implementation so that the
entire USB interface operation can be done without firmware intervention. For all three types of End
Points (Bulk-IN, Bulk-OUT, and Interrupt-IN), appropriate responses and handshake signals are
generated by the SIE. The SIE analog transceiver complies fully with driver and receiver characteristics
defined in USB Specification Rev. 2.0
6.1.1.
USB Configurations
The RTL8152B-VB supports two networking configurations, ECM (Ethernet Networking Control Model)
configuration, and in-house configuration. The ECM configuration complies with CDC-ECM, and is a
general Ethernet networking model that enables network communication without installing additional
vendor specific drivers. The in-house configuration requires a vendor specific driver to support enhanced
features and optimized performance.
6.1.2.
Endpoint 0
All USB devices support a common access mechanism for accessing information through this control
pipe. Associated with the control pipe at endpoint 0 is the information required to completely describe the
USB device. This pipe also provides the register read and write to the RTL8152B-VB.
6.1.3.
Endpoint 1 Bulk-IN
The maximum Bulk-IN packet size is 512 bytes. Each Ethernet packet is transferred to the HOST by this
Endpoint. If the Ethernet packet is larger than 512 bytes, the RTL8152B-VB splits the Ethernet packet
into multiples of 512 bytes. The HOST treats USB packets that are less than 512 bytes or are equal to
zero as End of Ethernet packets.
6.1.4.
Endpoint 2 Bulk-OUT
The HOST sends the USB packet to Ethernet. If the Ethernet packet is larger than 512 bytes, the Host will
send the Ethernet packet in multiples of 512 bytes. A USB packet that is less than 512 bytes or is equal to
zero is treated as an End of Ethernet packet.
The Ethernet packet (containing multiple USB packets) will be queued in the TX FIFO and transmitted
when possible. If the Ethernet packet is transmitted without error, the TX FIFO space that was occupied
by the transmitted Ethernet packet will be released. If the 2K TX FIFO is full, the RTL8152B-VB will
respond with a NYET when the host tries to Bulk-OUT more USB packets.
It is possible to have multiple Ethernet packets in the TX FIFO simultaneously. If an Ethernet packet is to
be transmitted but experiences collisions more than 16 times (default), this is called a transmit abort and
the packet will be skipped for transmission by the RTL8152B-VB.
6.1.5.
Endpoint 3 Interrupt-IN
The Interrupt Endpoint (EP3) can be used to poll the current link speed and link ok status of the
RTL8152B-VB.
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6.2. Customizable LED Configuration
The RTL8152B-VB supports customizable LED operation modes via OCP register offset 0xDD90h.
Table 10 describes the different LED actions.
Bit
7:4
3:0
Symbol
LEDSEL1
LEDSEL0
RW
RW
RW
Table 10. LED Select
Description
LED Select for PINLED1
LED Select for PINLED0
Configure OCP register offset 0xDD90h to support your own LED signals. For example, if the value in
the OCP offset 0xDD90 is 0xA1h (10100001b), the LED actions are:
•
LED 0: On only in 10M mode, with no blinking during TX/RX
•
LED 1: On only in 100M mode, with TX/RX blinking
Speed
LED 0
LED 1
Link 10M
Bit 0
Bit 4
Table 11. Customized LEDs
LINK
Link 100M
Bit 1
Bit 5
Table 12. LED Feature Control-1
Bit13
Bit14
Feature Control
Bit12
0
LED0 Low Active
LED1 Low Active
RSVD
1
LED0 High Active
LED1 High Active
RSVD
ACT
Bit 3
Bit 7
Bit15
Indicates Option 1 of Table 14
is selected
Indicates Option 2 of Table 14
is selected
Table 13. LED Feature Control-2
LED Pin
ACT=0
ACT=1
LINK=0
Floating
All Speed ACT
LINK>0
Selected Speed LINK Option 1 (see Table 14): Selected Speed LINK+ Selected Speed ACT
Option 2 (see Table 14): Selected Speed LINK+ All Speed ACT
Note 1: ACT means blinking TX and RX. LINK indicates Link 10M and Link 100M.
Note 2: There is a special mode: LED OFF ModeÆ Set all bits to 0.
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Table 14. LED Option 1 & Option 2 Settings
Link Bit
Active Bit
Description
10
100
Link
Option 1 LED Activity
0
0
0
LED Off
0
0
1
Act10+Act100
0
1
0
Link100
0
1
1
Link100
Act100
1
0
0
Link10
1
0
1
Link10
Act10
1
1
0
Link10+Link100
1
1
1
Link10+Link100
Act10+Act100
Note:
Act10 = LED blinking when Ethernet packets transmitted/received at 10Mbps.
Act100 = LED blinking when Ethernet packets transmitted/received at 100Mbps.
Link10 = LED lit when Ethernet connection established at 10Mbps.
Link100 = LED lit when Ethernet connection established at 100Mbps.
6.2.1.
Option 2 LED Activity
Act10+Act100
Act10+Act100
Act10+Act100
Act10+Act100
LED Blinking Frequency Control
The RTL8152B-VB also supports LED blinking frequency and duty cycle control via OCP register offset
DD92h to control user’s LED blinking frequency and duty cycle (see Table 15). For example, if the OCP
register offset 0xDD92 is 0x0B (00001011b), the LED blinking frequency is 80ms and duty cycle is 75%.
The LED state is shown in Figure 2 (assumes the LED is low active).
Bit
RW
3:2
RW
1:0
RW
Table 15. LED Blinking Frequency Control
Description
LED Blinking Frequency
0: 240ms
1: 160ms (Default)
2: 80ms
3: Link Speed Dependent
LED Blinking Duty Cycle
0: 12.5%
1: 25%
2: 50% (Default)
3: 75%
Figure 2.
LED Blinking Frequency and Duty Cycle
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Datasheet
6.3. PHY Transceiver
Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the
RTL8152B-VB operates at 10/100Mbps over standard CAT.5 UTP cable (100Mbps), and CAT.3 UTP
cable (10Mbps).
6.3.1.
PHY Transmitter
MII (100Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into
5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are
converted to 125MHz NRZ and NRZI signals. The NRZI signals are passed to the MLT3 encoder, then to
the D/A converter and transmitted onto the media.
MII (10Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into
10Mbps serial data. The 10Mbps serial data is converted into a Manchester-encoded data stream and is
transmitted onto the media by the D/A converter.
6.3.2.
PHY Receiver
MII (100Mbps) Mode
The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing
recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII
interface in 4-bit-wide nibbles at a clock speed of 25MHz.
MII (10Mbps) Mode
The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is
processed with a Manchester decoder and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are
presented to the MII interface at a clock speed of 2.5MHz.
6.3.3.
Link Down Power Saving Mode
The RTL8152B-VB implements link-down power saving mode, greatly improving power consumption
when the network cable is disconnected. The RTL8152B-VB automatically enters link down power
saving mode within three seconds after the cable is disconnected from it. Once it enters link down power
saving mode, it transmits normal link pulses on its TX pins and continues to monitor the RX pins to
detect incoming signals. After it detects an incoming signal, it wakes up from link down power saving
mode and operates in normal mode according to the result of the connection.
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6.4. SPI Flash
SPI (Serial Peripheral Interface) Flash is enabled by the RTL8152B-VB through the Chip Select pin, and
accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). The SPI flash utilizes an 8-bit instruction register. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low transition.
Compared to a parallel bus interface, the Serial Peripheral Interface provides simpler wiring and much
less interaction (crosstalk) among the conductors in the cable. This minimizes the number of conductors,
pins, and the IC package size, reducing the cost of making, assembling, and testing the electronics.
SPI Flash
SO
SI
SCK
CS
Table 16. SPI Flash Interface
Description
Input Data Bus.
Output Data Bus.
SPI Flash Serial Data Clock.
SPI Flash Chip Select.
6.5. Energy Efficient Ethernet (EEE)
The RTL8152B-VB supports IEEE 802.3az-2010, also known as Energy Efficient Ethernet (EEE), at
10Mbps and 100Mbps. It provides a protocol to coordinate transitions to/from a lower power
consumption level (Low Power Idle mode) based on link utilization. When no packets are being
transmitted, the system goes to Low Power Idle mode to save power. Once packets need to be
transmitted, the system returns to normal mode, and does this without changing the link status and
without dropping/corrupting frames.
To save power, when the system is in Low Power Idle mode, most of the circuits are disabled, however,
the transition time to/from Low Power Idle mode is kept small enough to be transparent to upper layer
protocols and applications.
EEE also specifies a negotiation method to enable link partners to determine whether EEE is supported
and to select the best set of parameters common to both devices.
Refer to http://www.ieee802.org/3/az/index.html for more details.
6.6. Link Power Management (LPM)
The RTL8152B-VB supports Link Power Management (LPM). It provides an efficient way to manage
bus and system power via hosts and hubs. It implements a power sleep state that reduces power
consumption by providing faster suspend and resume times. The four power management states for USB
are L0 (On), L1 (Sleep), L2 (Suspend) and L3 (Off). To reduce power consumption when the system is in
Low Power State, some of the circuits are disabled.
Refer to http://www.usb.org/developers/docs/.
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6.7. LAN Disable Mode
The RTL8152B-VB supports ‘LAN Disable Mode’, which uses an external signal to control whether the
NIC is enabled or disabled.
6.8. Power Management
The RTL8152B-VB complies with ACPI (Rev 1.0, 1.0b, 2.0), Network Device Class Power Management
Reference Specification (V1.0a), such as to support an Operating System-directed Power Management
(OSPM) environment.
The RTL8152B-VB can monitor the network for a Wake-Up Frame or a Magic Packet, and notify the
system via the USB interface when such a packet or event occurs. The system is then restored to a normal
state to process incoming jobs.
When the RTL8152B-VB is in power down mode:
•
The RX state machine is stopped. The RTL8152B-VB monitors the network for wake-up events such
as a Magic Packet and Wake-Up Frame in order to wake up the system. When in power down mode,
the RTL8152B-VB will not reflect the status of any incoming packets in the ISR register and will not
receive any packets into the RX on-chip buffer.
•
The on-chip buffer status and packets that have already been received into the RX on-chip buffer
before entering power down mode are held by the RTL8152B-VB.
•
Transmission is stopped. USB transactions are stopped. The TX on-chip buffer is held.
•
After being restored to D0 state, the RTL8152B-VB transmits data that was not moved into the TX
on-chip buffer during power down mode. Packets that were not transmitted completely last time are
re-transmitted.
Magic Packet Wake-Up occurs only when the following conditions are met:
•
The destination address of the received Magic Packet is acceptable to the RTL8152B-VB, e.g., a
broadcast, multicast, or unicast packet addressed to the current RTL8152B-VB adapter.
•
The received Magic Packet does not contain a CRC error.
•
The Magic Packet pattern matches, i.e., 6 * FFh + MISC (can be none) + 16 * DID (Destination ID)
in any part of a valid Ethernet packet.
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A Wake-Up Frame event occurs only when the following conditions are met:
•
The destination address of the received Wake-Up Frame is acceptable to the RTL8152B-VB, e.g., a
broadcast, multicast, or unicast address to the current RTL8152B-VB adapter.
•
The received Wake-Up Frame does not contain a CRC error.
•
The 16-bit CRC of the received Wake-Up Frame matches the 16-bit CRC of the sample Wake-Up
Frame pattern given by the local machine’s OS. Or, the RTL8152B-VB is configured to allow direct
packet wake-up, e.g., a broadcast, multicast, or unicast network packet.
•
The 128-byte of the received Wake-Up Frame matches the 128-byte of the sample Wake-Up Frame
pattern given by the local machine’s OS.
Note 1: 16-bit CRC: The RTL8152B-VB supports 16-set 16-bit CRC wake-up frames (covering 128 mask
bytes from offset 0 to 127 of any incoming network packet). CRC16 polynomial=x16+x12+x5+1.
Note 2: 128-byte Wake-Up Frame: The RTL8152B-VB supports 16-set 128-byte wake-up frames. If
enabled, the 16-bit CRC wake-up match will be disabled.
6.9. Protocol Offload
Protocol offload is a task offload supported by Microsoft Windows 7. It maintains a network presence for
a sleeping higher power host. Protocol offload prevents spurious wake-up and further reduces power
consumption. It maintains connectivity while hosts are asleep, including receiving requests from other
nodes on the network, ignoring packets, generating packets while in the sleep state (e.g., the Ethernet
Controller will generate ARP responses if the same MAC and IPv4 address are provided in the
configuration data), and intelligently wake-up host systems. The RTL8152B-VB supports the ECMA
(European Computer Manufacturers Association) specification including proxy configuration and
management, IPv4 ARP, IPv6 NDP, and wake-up packets. The RTL8152B-VB also supports optional
ECMA items such as QoS tagged packets and duplicate address detection.
6.10. XTAL-Less Wake-On-LAN
The RTL8152B-VB supports board level design with an external 25MHz or 48MHz clock source instead
of the crystal.
The external clock source may stop generating the clock when in suspend mode (S3/S4/S5). To support
the Wake-On-LAN function without the external clock source, the RTL8152B-VB will automatically
change its source clock from the external clock to an internal self-oscillating auxiliary clock when it
enters suspend mode. Note that when in suspend mode, the auxiliary clock can establish only a 10Mbps
link and does not support ARP/NS offload and ECMA ProxZzzy.
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6.11. Wake Packet Detection (WPD)
The RTL8152B-VB supports Microsoft Wake Packet Detection (WPD) to provide Wake-Up Frame
information to the OS, e.g., PatternID, OriginalPacketSize, SavedPacketSize, SavedPacketOffset, etc.
WPD helps prevent unwanted/unauthorized wake-up of a sleeping computer.
Refer to the Microsoft Wake Packet Detection (WPD) Interface Specification for details
(http://msdn.microsoft.com/en-us/library/hh440160(v=vs.85).aspx).
6.12. ‘RealWoW!’ (Wake-On-WAN) Technology
The RTL8152B-VB supports Realtek 'RealWoW!' technology that allows the RTL8152B-VB
to send keep alive packets to the Wake Server when the PC is in sleeping mode. Realtek
'RealWoW!' can pass wake-up packets through a NAT (Network Address Translation) device.
This feature allows PCs to reduce power consumption by remaining in low power sleeping
state until needed.
Users can login into the Wake Server via the Internet to wake the selected sleeping PC. Registration of
Account information to the Wake Server is required on first time use.
6.13. Always On Always Connected
The RTL8152B-VB supports Microsoft’s AOAC (Always On Always Connected) model. The AOAC
platform can enter the system state ‘Connected Standby’ and allow the RTL8152B-VB to enter a
low-power state. The RTL8152B-VB will maintain Layer 2 connectivity and generate a wake signal when
one of the following conditions is satisfied:
•
Link status becomes ‘connected’
•
Link status becomes ‘disconnected’
•
Receives a WOL pattern
•
Receives a wildcard pattern
7.
LDO Regulator
The RTL8152B-VB incorporates three linear Low-Dropout (LDO) regulators that feature high power
supply ripple rejection and low output noise. The RTL8152B-VB embedded LDO regulators do not
require power inductors on the PCB; only an output capacitor between its output and analog ground for
phase compensation, which saves cost and PCB real estate.
The output capacitors (and bypass capacitors) should be placed as close as possible to the power pins for
adequate filtering.
Note 1: The embedded LDO is designed for RTL8152B-VB internal use only. Do not provide this power
source to other devices.
Note 2: The LDO 1.05V output pin (DVDD10_UPS) must be separated from the other LDO 1.05V output
pin (AVDD10).
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8.
Characteristics
8.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability will be affected. All voltages are specified reference to GND unless
otherwise specified.
Table 17. Absolute Maximum Ratings
Description
Minimum
Maximum
Supply Voltage 5.0V
-0.3
5.5
Symbol
VDD5IN
VDD33OUT, AVDD33,
Supply Voltage 3.3V
-0.3
3.63
DVDD33
AVDD10, DVDD10,
Supply Voltage 1.05V
-0.3
1.32
DVDD10_UPS
Dcinput
Input Voltage
-0.3
Corresponding Supply Voltage + 10%
Dcoutput
Output Voltage
-0.3
Corresponding Supply Voltage + 10%
N/A
Storage Temperature
-55
+125
Note: Refer to the latest schematic circuit for correct configuration.
Unit
V
V
V
V
V
°C
8.2. Recommended Operating Conditions
Table 18. Recommended Operating Conditions
Description
Symbol
Minimum
VDD5
4.75
Supply Voltage VDD
AVDD33, DVDD33
3.14
AVDD10, DVDD10, DVDD10_UPS
1.0
Ambient Operating Temperature TA 0
Maximum Junction Temperature
Note: Refer to the latest schematic circuit for correct configuration.
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Typical
5.0
3.3
1.05
-
Maximum Unit
5.25
V
3.46
V
1.1
V
70
°C
125
°C
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Datasheet
8.3. Crystal Requirements
Table 19. Crystal Requirements
Symbol
Description/Condition
Minimum
Typical
Maximum
Unit
Parallel resonant crystal reference
Fref
25/48
MHz
frequency, fundamental mode, AT-cut type.
Parallel resonant crystal frequency stability,
fundamental mode, AT-cut type.
Fref Stability
-30
+30
ppm
Ta = 0°C ~ +70°C.
Parallel resonant crystal frequency
tolerance, fundamental mode, AT-cut type.
Fref Tolerance
-50
+50
ppm
Ta = 25°C.
Fref Duty Cycle
Reference Clock Input Duty Cycle.
40
60
%
ESR
Equivalent Series Resistance.
70
Ω
CL
Load Capacitance.
16
20
pF
DL
Drive Level.
0.5
mW
Note 1: The CLK source can come from other places in the system, but it must accord with the parameters above.
Note 2: Broadband RMS=9ps; 25KHz to 25MHz RMS=3ps.
Note 3: The ESR maximum value of 70ohm is based on shunt capacitance (Co) less than 7pF.
Note 4: The accuracy of the crystal resonance frequency can be achieved by matching the load capacitance correctly to
the designed-in circuit. The latest schematic circuit recommends two external capacitors of 27pF connected between the
crystal and ground. To match this use the load capacitance specified by the crystal manufacturer of 16~20pF.
8.4. Oscillator Requirements
Table 20. Oscillator Requirements
Parameter
Condition
Minimum
Typical
Maximum
Unit
Frequency
25/48
MHz
Frequency Stability
-30
+30
ppm
Ta = 0°C~+70°C
Frequency Tolerance
-50
+50
ppm
Ta = 25°C
Duty Cycle
40
60
%
Broadband Peak-to-Peak Jitter
200
ps
Vp-p
3.15
3.3
3.45
V
Rise Time
10
ns
Fall Time
10
ns
0
70
Operation Temp Range
°C
Note 1: The CLK source can come from other places in the system, but it must accord with the parameters above.
Note 2: Broadband RMS=9ps; 25KHz to 25MHz RMS=3ps.
8.5. Environmental Characteristics
Parameter
Storage Temperature
Ambient Operating Temperature
Table 21. Environmental Characteristics
Minimum
Maximum
-55
+125
0
Integrated 10/100M Ethernet Controller for USB Applications
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16
Units
°C
°C
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Datasheet
8.6. DC Characteristics
Symbol
VDD5
AVDD33,
DVDD33
AVDD10,
DVDD10,
DVDD10_UPS
Parameter
5.0V Supply Voltage
Table 22. DC Characteristics
Conditions
Minimum
4.75
Typical
5.00
Maximum
5.25
Units
V
3.3V Supply Voltage
-
3.14
3.30
3.46
V
1.05V Supply Voltage
-
1.00
1.05
1.10
V
0.9*VDD33
-
VDD33
V
0
-
0.1*VDD33
V
2.0
-
-
V
-
-
0.8
V
0
-
0.5
µA
-
0.4
-
mA
-
24
-
mA
-
60
-
mA
Minimum High Level
Ioh = -4mA
Output Voltage
Maximum Low Level
Iol = 4mA
Vol
Output Voltage
Minimum High Level
Vih
Input Voltage
Maximum Low Level
Vil
Input Voltage
Iin
Input Current
Vin = VDD33 or GND
Average Operating
At 100Mbps with
Icc5
Supply Current from
heavy network traffic
5.0V
Average Operating
At 100Mbps with
Icc33
Supply Current from
heavy network traffic
3.3V
Average Operating
At 100Mbps with
Icc10
Supply Current from
heavy network traffic
1.05V
Note: Refer to the latest schematic circuit for correct configuration.
Voh
8.7. Reflow Profile Recommendations
Table 23. Reflow Profile Recommendations
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Minimum Preheat Temperature (Tsmin)
100°C
150°C
Maximum Preheat Temperature (Tsmax)
150°C
200°C
Preheat Time (tS) from Tsmin to Tsmax
60~120 seconds
60~120 seconds
Ramp-Up Rate (TL to Tp)
3°C/second max.
3°C/second max.
Liquidus Temperature (TL)
183°C
217°C
Time (tL) Maintained above TL
60~150 seconds
60~150 seconds
Peak Package Body Temperature (Tp)
235°C
260°C
Time (tp)2 within 5°C of Peak TP
20 seconds
20 seconds
Ramp-Down Rate (Tp to TL)
6°C/second max.
6°C/second max.
Time 25°C to Peak Temperature (Tp)
6 minutes max.
8 minutes max.
Note 1: All temperatures refer to the topside of the package, measured on the package body surface.
Note 2: Tolerance for Tp is defined as a supplier’s minimum and a user’s maximum.
Note 3: Reference document: IPC/JEDEC J-STD-020D.1.
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8.8. AC Characteristics
8.8.1.
SPI Flash Commands
Command
WREN
WRDI
RDID
RDSR
WRSR
Read
Page Program
Sector Erase (4K)
Block Erase (64K)
Chip Erase
8.8.2.
Table 24. SPI Flash Commands
Operation Code
Action
06h
Write Enable.
04h
Write Disable.
9Fh
Read Manufacturer and Product ID.
05h
Read Status Register.
01h
Write Status Register.
03h
Read.
02h
Page Program.
20h
Erase The Selected Sector.
D8h
Erase The Selected Block.
60h or C7h
Erase Whole Chip.
SPI Flash Interface Timing Sequences
Figure 3.
WREN/WRDI Timing Sequence
Figure 4.
Read Timing Sequence
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Figure 5.
Figure 6.
Page Program Timing Sequence
Sector/Block Erase Timing Sequence
Figure 7.
Chip Erase Timing Sequence
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8.8.3.
SPI Flash Type Supported
Table 25. SPI Flash Type Supported
Flash Part No.
Density (Mb)
Maximum Freq. (MHz)
MX25L4006E
4
86
MX25L8006E
8
86
MX25L1606E
16
86
Winbond
W25X40CV
4
80
W25Q40BV
4
80
W25Q80BV
8
80
W25Q16CV
16
80
Micron
M25P40
4
75
M25PX80
8
75
M25PX16
16
75
Note 1: The Flash clock frequency should be 33MHz or higher.
Note 2: Flash density should be 4Mb or more. 4Mb is only for single OS driver. For feature extensions, 8Mb is
recommended.
Manufacturer
MXIC
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9.
Mechanical Dimensions
Symbol
Dimension in mm
Nom
Max
A
0.85
0.90
A1
0.02
0.05
A2
0.65
0.70
A3
0.20REF
b
0.18
0.25
0.30
D/E
4.00BSC
D2/E2
2.45
2.70
2.95
e
0.50BSC
L
0.30
0.40
0.50
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MO-220.
Min
0.80
0.00
-
Integrated 10/100M Ethernet Controller for USB Applications
Min
0.031
0.000
0.007
0.096
0.012
21
Dimension in inch
Nom
0.033
0.001
0.026
0.008REF
0.010
0.158BSC
0.106
0.020BSC
0.016
Max
0.035
0.002
0.028
0.012
0.116
0.020
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10. Ordering Information
Table 26. Ordering Information
Part Number
Package
RTL8152B-VB-CG
24-Pin QFN ‘Green’ Package
Note: See page 3 for package ID information.
Status
-
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
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