74HC04M/TR

74HC04 Hex Inverter High−Performance Silicon−Gate CMOS 14 The 74HC04 is identical in pinout to the LS04 and the MC14069. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The device consists of six three−stage inverters. 1 SOIC−14 Features • • • • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 36 FETs or 9 Equivalent Gates These are Pb−Free Devices 14 1 TSSOP−14 Pinout: 14−Lead Packages (Top View) LOGIC DIAGRAM A1 A2 A3 1 2 3 4 5 6 A5 A6 9 8 11 10 13 http://www.hgsemi.com.cn 12 A6 Y6 A5 Y5 A4 Y4 14 13 12 11 10 9 8 1 2 3 4 5 6 7 A1 Y1 A2 Y2 A3 Y3 GND Y1 Y2 Y3 Y=A A4 VCC Y4 Y5 FUNCTION TABLE Y6 1 Inputs Outputs A Y L H H L 2018 MAR 74HC04 MAXIMUM RATINGS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds SOIC Package† TSSOP Package† _C SOIC or TSSOP Package 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. †Derating − SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) http://www.hgsemi.com.cn VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 2 Max Unit 2.0 6.0 V 0 VCC V – 55 + 125 _C 0 0 0 1000 500 400 ns 2018 MAR 74HC04 DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Guaranteed Limit VCC (V) −55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High−Level Input Voltage Vout = 0.1V or VCC −0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low−Level Input Voltage Vout = 0.1V or VCC − 0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Vin =VIH or VIL VOL Maximum Low−Level Output Voltage |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA Vin = VIH or VIL |Iout| ≤ 20mA Vin = VIH or VIL |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0mA 6.0 2.0 20 40 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns) Symbol Guaranteed Limit −55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns 10 10 10 pF Cin Parameter VCC (V) Maximum Input Capacitance NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD 20 Power Dissipation Capacitance (Per Inverter)* pF * Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). http://www.hgsemi.com.cn 3 2018 MAR 74HC04 tf INPUT A tr VCC 90% 50% 10% GND tPLH tPHL 90% OUTPUT Y 50% 10% tTLH tTHL Figure 1. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST C L* *Includes all probe and jig capacitance Figure 2. Test Circuit A Y Figure 3. Expanded Logic Diagram (1/6 of the Device Shown) http://www.hgsemi.com.cn 4 2018 MAR