CD4094BM/TR

CD4094B 8-Bit Shift Register/Latch with 3-STATE Outputs General Description the latch to 3-STATE output gates. These gates are enabled when OUTPUT ENABLE is taken HIGH. The CD4094B consists of an 8-bit shift register and a 3STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (QS) can be used to cascade several devices. Data on the QS output is transferred to a second output, Q′S, on the following negative clock edge. Features ■ Wide supply voltage range: ■ High noise immunity: 3.0V to 18V 0.45 VDD (typ.) ■ Low power TTL compatibility: The output of each stage of the shift register feeds a latch, which latches data on the negative edge of the STROBE input. When STROBE is HIGH, data propagates through Fan out of 2 driving 74L or 1 driving 74LS ■ 3-STATE outputs Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOP Top View Truth Table Clock   X = Don't Care = HIGH-to-LOW = LOW-to-HIGH       Output Strobe Data Parallel Outputs Enable Serial Outputs Q1 QN QS (Note 1) Q′Σ Hi-Z Hi-Z Q7 No Change Hi-Z Hi-Z No Change Q7 Q7 No Change 0 X X 0 X X 1 0 X 1 1 0 0 QN−1 Q7 No Change 1 1 1 1 QN−1 Q7 No Change 1 1 1 No Change No Change No Change No Change No Change Q7 Note 1: At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS. http://www.hgsemi.com.cn 1 2018 JUN CD4094B Block Diagram http://www.hgsemi.com.cn 2 2018 JUN CD4094B Absolute Maximum Ratings(Note 2) Recommended Operating Conditions (Note 3) (Note 3) −0.5 to +18 VDC Supply Voltage (VDD) Input Voltage (VIN) Input Voltage (VIN) −65°C to +150°C Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) (Soldering, 10 seconds) 260°C +3.0 to +15 VDC DC Supply Voltage (VDD) −0.5 to VDD +0.5 VDC 0 to VDD VDC −40°C to +85°C Operating Temperature Range (TA) Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Note 3: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 3) Symbol IDD VOL Parameter −40°C Conditions Min IOL IOH IIN IOZ +85°C Max Min Max Units VDD = 5.0V 20 20 150 µA VDD = 10V 40 40 300 µA VDD = 15V 80 80 600 µA LOW Level VDD = 5.0V 0.05 0 0.05 0.05 V Output Voltage VDD = 10V 0.05 0 0.05 0.05 V 0.05 0 0.05 0.05 V HIGH Level VDD = 5.0V Output Voltage VDD = 10V LOW Level Input Voltage VIH Typ Device Current |IO| ≤ 1.0 µA |IO| ≤ 1 µA VDD = 15V VIL Min Quiescent VDD = 15V VOH +25°C Max 4.95 4.95 5.0 4.95 V 9.95 9.95 10.0 9.95 V 14.95 14.95 15.0 14.95 VDD = 5.0V, VO = 0.5V or 4.5V 1.5 1.5 V 1.5 V VDD = 10V, VO = 1.0V or 9.0V 3.0 3.0 3.0 V VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 V HIGH Level VDD = 5.0V, VO = 0.5V or 4.5V 3.5 3.5 3.5 Input Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 7.0 V VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V LOW Level VDD = 5.0V, VO = 0.4V 0.52 0.44 0.88 0.36 mA Output Current VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA mA V (Note 4) VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 HIGH Level VDD = 5.0V, VO = 4.6V −0.52 −0.44 0.88 −0.36 mA Output Current VDD = 10V, VO = 9.5V −1.3 −1.1 2.25 −0.9 mA (Note 4) VDD = 15V, VO = 13.5V −3.6 −3.0 8.8 Input Current VDD = 15V, VIN = 0V −0.3 −0.3 −1.0 µA VDD = 15V, VIN = 15V 0.3 0.3 1.0 µA 1 1 10 µA 3-STATE Output VDD = 15V, VIN = 0V or 15V −2.4 mA Leakage Current Note 4: IOH and IOL are tested one output at a time. http://www.hgsemi.com.cn 3 2018 JUN CD4094B AC Electrical Characteristics (Note 5) TA = 25°C, CL = 50 pF Symbol tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHZ tPLZ tPZH tPZL tTHL, tTLH tSU tr , tf Parameter tPS fmax CIN Min Typ Max Units Propagation Delay VDD = 5.0V 300 600 ns Clock to QS VDD = 10V 125 250 ns ns VDD = 15V 95 190 Propagation Delay VDD = 5.0V 230 460 ns Clock to Q′Σ VDD = 10V 110 220 ns VDD = 15V 75 150 ns Propagation Delay Clock VDD = 5.0V 420 840 ns to Parallel Out VDD = 10V 195 390 ns VDD = 15V 135 270 ns Propagation Delay Strobe VDD = 5.0V 290 580 ns to Parallel Out VDD = 10V 145 290 ns VDD = 15V 100 200 ns Propagation Delay HIGH VDD = 5.0V 140 280 ns Level to HIGH Impedance VDD = 10V 75 150 ns VDD = 15V 55 110 ns Propagation Delay LOW VDD = 5.0V 140 280 ns Level to HIGH Impedance VDD = 10V 75 150 ns VDD = 15V 55 110 ns Propagation Delay HIGH VDD = 5.0V 140 280 ns Impedance to HIGH Level VDD = 10V 75 150 ns VDD = 15V 55 110 ns Propagation Delay HIGH VDD = 5.0V 140 280 ns Impedance to LOW Level VDD = 10V 75 150 ns VDD = 15V 55 110 ns VDD = 5.0V 100 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns Transition Time Set-Up Time VDD = 5.0V 80 40 ns Data to Clock VDD = 10V 40 20 ns VDD = 15V 20 10 VDD = 5.0V 1 ms ms Maximum Clock Rise ns VDD = 10V 1 VDD = 15V 1 Minimum Clock VDD = 5.0V 200 100 Pulse Width VDD = 10V 100 50 ns VDD = 15V 83 40 ns Minimum Strobe VDD = 5.0V 200 100 ns Pulse Width VDD = 10V 80 40 ns VDD = 15V 70 35 ns Maximum Clock Frequency VDD = 5.0V 1.5 3.0 MHz VDD = 10V 3.0 6.0 MHz VDD = 15V 4.0 8.0 and Fall Time tPC Conditions Input Capacitance Any Input ms 5.0 ns MHz 7.5 pF Note 5: AC Parameters are guaranteed by DC correlated testing. http://www.hgsemi.com.cn 4 2018 JUN CD4094B Timing Diagram Test Circuits and Timing Diagrams for 3-STATE http://www.hgsemi.com.cn 5 2018 JUN