74HC00PW,118

74HC00-Q100; 74HCT00-Q100 Quad 2-input NAND gate Rev. 2 — 24 November 2015 Product data sheet 1. General description The 74HC00-Q100; 74HCT00-Q100 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Input levels:  For 74HC00-Q100: CMOS level  For 74HCT00-Q100: TTL level  Complies with JEDEC standard no. 7A  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )  Multiple package options 74HC00-Q100; 74HCT00-Q100 NXP Semiconductors Quad 2-input NAND gate 3. Ordering information Table 1. Ordering information Type number 74HC00D-Q100 Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5  3  0.85 mm 74HCT00D-Q100 74HC00PW-Q100 74HCT00PW-Q100 74HC00BQ-Q100 74HCT00BQ-Q100 4. Functional diagram   $  % <   $  % <   $  % <   $  % <            $ <  % PQD Fig 1. Logic symbol 74HC_HCT00_Q100 Product data sheet PQD Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 November 2015 PQD Fig 3. Logic diagram (one gate) © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 15 74HC00-Q100; 74HCT00-Q100 NXP Semiconductors Quad 2-input NAND gate 5. Pinning information 5.1 Pinning +&4 +&74  $ WHUPLQDO LQGH[DUHD  <   $ $  $   < %  %   % <  <   $   $ % *1'   < <  %    < *1' %  9&&  % $   9&& +&4 +&74  < *1'  %  $ DDD 7UDQVSDUHQWWRSYLHZ DDD (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nB nY L X H X L H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 74HC_HCT00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 15 74HC00-Q100; 74HCT00-Q100 NXP Semiconductors Quad 2-input NAND gate 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA 50 mA IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.5 V < VO < VCC + 0.5 V ICC supply current - IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 500 mW [2] total power dissipation Ptot [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage Conditions 74HC00-Q100 74HCT00-Q100 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate - - 625 - - - VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 74HC_HCT00_Q100 Product data sheet VCC = 2.0 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 November 2015 ns/V © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 15 74HC00-Q100; 74HCT00-Q100 NXP Semiconductors Quad 2-input NAND gate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 1.2 - 1.5 - 1.5 - V VCC = 4.5 V - 2.4 - 3.15 - 3.15 - V VCC = 6.0 V - 3.2 - 4.2 - 4.2 - V 74HC00-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V - 0.8 - - 0.5 - 0.5 V VCC = 4.5 V - 2.1 - - 1.35 - 1.35 V VCC = 6.0 V - 2.8 - - 1.8 - 1.8 V VI = VIH or VIL IO = 20 A; VCC = 2.0 V - 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V - 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V - 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V - 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V - 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 - - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 - - 0.1 - 0.1 V VI = VIH or VIL IO = 20 A; VCC = 6.0 V - 0 - - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 - - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 - - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - - - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - - - 20 - 40 A CI input capacitance - 3.5 - - - - - pF 74HC_HCT00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 15 74HC00-Q100; 74HCT00-Q100 NXP Semiconductors Quad 2-input NAND gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HCT00-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V - 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 - - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 4.5 - 4.4 - 4.4 - V IO = 4.0 mA - 4.32 - 3.84 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A; VCC = 4.5 V - 0 - - 0.1 - 0.1 V IO = 5.2 mA; VCC = 6.0 V - 0.15 - - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - - - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - - - 20 - 40 A ICC additional supply current per input pin; VI = VCC  2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 150 - - 675 - 735 A CI input capacitance - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) VCC = 2.0 V - 25 - 115 135 ns VCC = 4.5 V - 9 - 23 27 ns VCC = 5.0 V; CL = 15 pF - 7 - - - ns - 7 - 20 23 ns VCC = 2.0 V - 19 - 95 110 ns VCC = 4.5 V - 7 - 19 22 ns 74HC00-Q100 tpd propagation delay nA, nB to nY; see Figure 6 [1] VCC = 6.0 V tt transition time [2] see Figure 6 VCC = 6.0 V CPD power dissipation capacitance 74HC_HCT00_Q100 Product data sheet per package; VI = GND to VCC [3] - 6 - 16 19 ns - 22 - - - pF All information provided in this document is subject to legal disclaimers. Rev. 2 — 24 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 15 74HC00-Q100; 74HCT00-Q100 NXP Semiconductors Quad 2-input NAND gate Table 7. Dynamic characteristics …continued GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 12 - 24 29 ns - 10 - - - ns 74HCT00-Q100 [1] propagation delay nA, nB to nY; see Figure 6 tpd VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt transition time VCC = 4.5 V; see Figure 6 [2] CPD power dissipation capacitance per package; VI = GND to VCC  1.5 V [3] [1] - - - 29 22 ns - 22 - - - pF tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD  VCC2  fi  N +  (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching;  (CL  VCC2  fo) = sum of outputs. 11. Waveforms 9, Q$Q%LQSXW 90 *1' W3+/ 92+ 90 9; Q