PCF8574AP

PCF8574 Remote 8-bit I/O expander for I2C-bus FEATURES GENERAL DESCRIPTION • Operating supply voltage 2.5 to 6 V The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C). • Low standby current consumption of 10 µA maximum • I2C to parallel port expander • Open-drain interrupt output • 8-bit remote I/O port for the I2C-bus • Compatible with most microcontrollers • Latched outputs with high current drive capability for directly driving LEDs • Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A) • DIP16, or space-saving SO16 or SSOP20 packages. The device consists of an 8-bit quasi-bidirectional port and an I2C-bus interface. The PCF8574 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. This means that the PCF8574 can remain a simple slave device. The PCF8574 and PCF8574A versions differ only in their slave address as shown in Fig.9. BLOCK DIAGRAM handbook, full pagewidth INT 13 INTERRUPT LOGIC A0 A1 A2 SCL SDA LP FILTER PCF8574 1 2 4 3 5 6 14 15 INPUT FILTER I 2 C BUS CONTROL 7 SHIFT REGISTER 8 BIT I/O PORT 9 10 11 12 P0 P1 P2 P3 P4 P5 P6 P7 WRITE pulse VDD V SS 16 8 READ pulse POWER-ON RESET Fig.1 Block diagram (SOT38-1 and SOT162-1). http://www.hgsemi.com.cn 1 2018 AUG PCF8574 PINNING DIP16 and SO16 packages SYMBOL PIN DESCRIPTION A0 1 address input 0 A1 2 address input 1 A2 3 address input 2 P0 4 quasi-bidirectional I/O 0 P1 5 quasi-bidirectional I/O 1 P2 6 quasi-bidirectional I/O 2 P3 7 quasi-bidirectional I/O 3 VSS 8 supply ground P4 9 quasi-bidirectional I/O 4 P5 10 quasi-bidirectional I/O 5 P6 11 quasi-bidirectional I/O 6 P7 12 quasi-bidirectional I/O 7 INT 13 interrupt output (active LOW) SCL 14 serial clock line SDA 15 serial data line VDD 16 supply voltage handbook, halfpage A0 1 16 VDD A1 2 15 SDA A1 A2 3 14 SCL handbook, halfpage P0 4 A0 1 16 VDD 2 15 SDA A2 3 14 SCL PCF8574P 13 INT PCF8574AP 12 P7 P1 5 P0 P2 6 11 P6 P2 6 11 P6 P3 7 10 P5 P3 7 10 P5 VSS 8 9 P1 5 VSS P4 Fig.2 Pin configuration (DIP16). http://www.hgsemi.com.cn 4 8 PCF8574T 13 INT PCF8574AT 12 P7 9 P4 Fig.3 Pin configuration (SO16). 2 2018 AUG PCF8574 2C-BUS CHARACTERISTICS OF THE I Start and stop conditions The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Fig.5). System configuration Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Fig.4). A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Fig.6). SDA SCL data line stable; data valid change of data allowed Fig.4 Bit transfer. SDA SDA SCL SCL S P START condition STOP condition Fig.5 Definition of start and stop conditions. SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER / RECEIVER Fig.6 System configuration. http://www.hgsemi.com.cn 3 2018 AUG PCF8574 Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START CONDITION Fig.7 Acknowledgment on the I2C-bus. http://www.hgsemi.com.cn 4 2018 AUG PCF8574 FUNCTIONAL DESCRIPTION VDD handbook, full pagewidth write pulse 100 µA data from shift register D Q FF CI S P0 to P7 power-on reset V SS D Q FF CI read pulse S to interrupt logic data to shift register Fig.8 Simplified schematic diagram of each I/O. Addressing For addressing see Figs 9, 10 and 11. slave address handbook, full pagewidth S 0 1 0 0 A2 slave address A1 A0 0 A S a. 0 1 1 1 A2 A1 A0 0 A b. (a) PCF8574. (b) PCF8574A. Fig.9 PCF8574 and PCF8574A slave addresses. Each of the PCF8574’s eight I/Os can be independently used as an input or output. Input data is transferred from the port to the microcontroller by the READ mode (see Fig.11). Output data is transmitted to the port by the WRITE mode (see Fig.10). http://www.hgsemi.com.cn 5 2018 AUG http://www.hgsemi.com.cn DATA OUT FROM PORT WRITE TO PORT 3 4 5 6 1 0 0 A2 A1 slave address (PCF8574) 2 start condition 0 SDA S 1 SCL A0 7 R/W 0 8 6 DATA 1 t pv Fig.10 WRITE mode (output). acknowledge from slave A data to port acknowledge from slave A DATA 1 VALID DATA 2 data to port t pv DATA 2 VALID acknowledge from slave A PCF8574 2018 AUG http://www.hgsemi.com.cn 7 0 1 t iv start condition S 0 0 A2 A1 A0 t ph R/W 1 t ir DATA 2 acknowledge from slave A DATA 3 t ps t ir acknowledge from slave DATA 4 DATA 4 DATA 1 A data from port data from port htdiwegap lluf ,koobdnah P stop condition 1 Fig.11 READ mode (input). A LOW-to-HIGH transition of SDA, while SCL is HIGH is defined as the stop condition (P). Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. INT DATA INTO PORT READ FROM PORT SDA slave address (PCF8574) PCF8574 2018 AUG PCF8574 • Interrupts which occur during the acknowledge clock pulse may be lost (or very short) due to the resetting of the interrupt during this pulse. Interrupt (see Figs 12 and 13) The PCF8574 provides an open drain output (INT) which can be fed to a corresponding input of the microcontroller. This gives these chips a type of master function which can initiate an action elsewhere in the system. Each change of the I/Os after resetting will be detected and, after the next rising clock edge, will be transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv the signal INT is valid. Quasi-bidirectional I/Os (see Fig.14) Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from or written to the port which has generated the interrupt. A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. Resetting occurs as follows: • In the READ mode at the acknowledge bit after the rising edge of the SCL signal • In the WRITE mode at the acknowledge bit after the HIGH-to-LOW transition of the SCL signal handbook, full pagewidth V DD MICROCOMPUTER PCF8574 (1) PCF8574 (2) PCF8574 (16) INT INT INT INT Fig.12 Application of multiple PCF8574s with interrupt. slave address (PCF8574) handbook, full pagewidth SDA S 0 1 0 0 A2 A1 data from port A0 start condition SCL 1 2 1 R/W 3 4 5 6 7 A 1 acknowledge P5 from slave 1 P stop condition 8 DATA INTO P5 INT t iv t ir Fig.13 Interrupt generated by a change of input to I/O P5. http://www.hgsemi.com.cn 8 2018 AUG http://www.hgsemi.com.cn 9 P3 PULL-UP OUTPUT CURRENT P3 OUTPUT VOLTAGE SCL SDA 0 1 2 3 1 4 1 5 A2 6 A1 7 A0 8 R/W 0 acknowledge from slave A P3 1 I OHt A P3 0 data to port Fig.14 Transient pull-up current IOHt while P3 changes from LOW-to-HIGH and back to LOW. 1 start condition S data to port handbook, full pagewidth slave address (PCF8574A) I OH A P PCF8574 2018 AUG PCF8574 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage −0.5 +7.0 V VI input voltage VSS − 0.5 VDD + 0.5 V II DC input current − ±20 mA IO DC output current − ±25 mA IDD supply current − ±100 mA ISS supply current − ±100 mA Ptot total power dissipation − 400 mW PO power dissipation per output − 100 mW Tstg storage temperature −65 +150 °C Tamb operating ambient temperature −40 +85 °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under “Handling MOS Devices”. DC CHARACTERISTICS VDD = 2.5 to 6 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage IDD supply current Istb standby current VPOR Power-on reset voltage − 6.0 V operating mode; VDD = 6 V; − no load; VI = VDD or VSS; fSCL = 100 kHz 40 100 µA standby mode; VDD = 6 V; no load; VI = VDD or VSS − 2.5 10 µA VDD = 6 V; no load; VI = VDD or VSS; note 1 − 1.3 2.4 V 2.5 Input SCL; input/output SDA VIL LOW level input voltage −0.5 − +0.3VDD V VIH HIGH level input voltage 0.7VDD − VDD + 0.5 V IOL LOW level output current VOL = 0.4 V 3 − − mA IL leakage current VI = VDD or VSS −1 − +1 µA Ci input capacitance VI = VSS − − 7 pF http://www.hgsemi.com.cn 10 2018 AUG PCF8574 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I/Os VIL LOW level input voltage −0.5 − +0.3VDD V VIH HIGH level input voltage 0.7VDD − VDD + 0.5 V IIHL(max) maximum allowed input current through protection diode VI ≥ VDD or VI ≤ VSS − − ±400 µA IOL LOW level output current VOL = 1 V; VDD = 5 V 10 25 − mA IOH HIGH level output current VOH = VSS 30 − 300 µA IOHt transient pull-up current HIGH during acknowledge (see Fig.14); VOH = VSS; VDD = 2.5 V − −1 − mA Ci input capacitance − − 10 pF Co output capacitance − − 10 pF Port timing; CL ≤ 100 pF (see Figs 10 and 11) tpv output data valid − − 4 µs tsu input data set-up time 0 − − µs th input data hold time 4 − − µs Interrupt INT (see Fig.13) IOL LOW level output current VOL = 0.4 V 1.6 − − mA IL leakage current VI = VDD or VSS −1 − +1 µA TIMING; CL ≤ 100 PF tiv input data valid time − − 4 µs tir reset delay time − − 4 µs Select inputs A0 to A2 VIL LOW level input voltage −0.5 − +0.3VDD V VIH HIGH level input voltage 0.7VDD − VDD + 0.5 V ILI input leakage current −250 − +250 nA pin at VDD or VSS Note 1. The Power-on reset circuit resets the I2C-bus logic with VDD < VPOR and sets all I/Os to logic 1 (with current source to VDD). http://www.hgsemi.com.cn 11 2018 AUG PCF8574 I 2 C-BUS TIMING CHARACTERISTICS SYMBOL PARAMETER MIN. TYP. MAX. UNIT I2C-BUS TIMING (see Fig.15; note 1) fSCL SCL clock frequency − − 100 kHz tSW tolerable spike width on bus − − 100 ns tBUF bus free time 4.7 − − µs tSU;STA START condition set-up time 4.7 − − µs tHD;STA START condition hold time 4.0 − − µs tLOW SCL LOW time 4.7 − − µs tHIGH SCL HIGH time 4.0 − − µs tr SCL and SDA rise time − − 1.0 µs tf SCL and SDA fall time − − 0.3 µs tSU;DAT data set-up time 250 − − ns tHD;DAT data hold time 0 − − ns tVD;DAT SCL LOW to data out valid − − 3.4 µs tSU;STO STOP condition set-up time 4.0 − − µs Note 1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD. handbook, full pagewidth t SU;STA BIT 6 (A6) BIT 7 MSB (A7) START CONDITION (S) PROTOCOL t LOW t HIGH BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1 / f SCL SCL t tf tr BUF SDA t HD;STA t SU;DAT t HD;DAT t VD;DAT t SU;STO Fig.15 I2C-bus timing diagram. http://www.hgsemi.com.cn 12 2018 AUG PCF8574 Important statement: Huaguan Semiconductor Co,Ltd. reserves the right to change the products and services provided without notice. Customers should obtain the latest relevant information before ordering, and verify the timeliness and accuracy of this information. Customers are responsible for complying with safety standards and taking safety measures when using our products for system design and machine manufacturing to avoid potential risks that may result in personal injury or property damage. Our products are not licensed for applications in life support, military, aerospace, etc., so we do not bear the consequences of the application of these products in these fields. Our documentation is only permitted to be copied without any tampering with the content, so we do not accept any responsibility or liability for the altered documents. http://www.hgsemi.com.cn 13 2018 AUG