TLC2543N

TLC2543 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS D D D D D DB, DW, J, OR N PACKAGE (TOP VIEW) AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC EOC I/O CLOCK DATA INPUT DATA OUT CS REF + REF – AIN10 AIN9 FK OR FN PACKAGE (TOP VIEW) AIN2 AIN1 AIN0 VCC EOC D D D D D D D 12-Bit-Resolution A/D Converter 10-µs Conversion Time Over Operating Temperature 11 Analog Input Channels 3 Built-In Self-Test Modes Inherent Sample-and-Hold Function Linearity Error . . . ± 1 LSB Max On-Chip System Clock End-of-Conversion Output Unipolar or Bipolar Output Operation (Signed Binary With Respect to 1/2 the Applied Voltage Reference) Programmable MSB or LSB First Programmable Power Down Programmable Output Data Length CMOS Technology Application Report Available† description The TLC2543C and TLC2543I are 12-bit, switchedcapacitor, successive-approximation, analog-todigital converters. Each device has three control inputs [chip select (CS), the input-output clock (I/O CLOCK), and the address input (DATA INPUT)] and is designed for communication with the serial port of a host processor or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host. AIN3 AIN4 AIN5 AIN6 AIN7 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 I/O CLOCK DATA INPUT DATA OUT CS REF + AIN8 GND AIN9 AIN10 REF – D D In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating temperature range. The TLC2543C is characterized for operation from TA = 0°C to 70°C. The TLC2543I is characterized for operation from TA = – 40°C to 85°C. The TLC2543M is characterized for operation from TA = – 55°C to 125°C. http://www.hgsemi.com.cn 1 2018 AUG TLC2543 functional block diagram AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 1 2 3 4 5 6 7 8 9 11 12 REF + REF – 14 13 12-Bit Analog-to-Digital Converter (Switched Capacitors) Sample-andHold Function 14-Channel Analog Multiplexer 12 4 Output Data Register Input Address Register 12 12-to-1 Data Selector and Driver 16 DATA OUT 4 3 Control Logic and I/O Counters Self-Test Reference 19 DATA INPUT I/O CLOCK CS 17 EOC 18 15 http://www.hgsemi.com.cn 2 2018 AUG TLC2543 Terminal Functions TERMINAL I/O DESCRIPTION 1 – 9, 11, 12 I Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and be capable of slewing the analog input voltage into a capacitance of 60 pF. CS 15 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup time. DATA INPUT 17 I Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next. The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK. After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order. DATA OUT 16 O The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB/LSB† value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB / LSB, and the remaining bits are shifted out in order. EOC 19 O End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and the data is ready for transfer. GND 10 I/O CLOCK 18 I Input /output clock. I/O CLOCK receives the serial input and performs the following four functions: 1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK with the multiplexer address available after the fourth rising edge. 2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input begins charging the capacitor array and continues to do so until the last falling edge of the I/O CLOCK. 3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK. 4. It transfers control of the conversion to the internal state controller on the falling edge of the last I/O CLOCK. REF + 14 I Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF – terminal. REF – 13 I Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF –. NAME NO. AIN0 – AIN10 Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. VCC 20 Positive supply voltage † MSB/LSB = Most significant bit /least significant bit http://www.hgsemi.com.cn 3 2018 AUG TLC2543 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Positive reference voltage, Vref + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.1 V Negative reference voltage, Vref – . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.1 V Peak input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Peak total input current, II (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA Operating free-air temperature range, TA: TLC2543C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLC2543I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C TLC2543M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminal with REF – and GND wired together (unless otherwise noted). recommended operating conditions Supply voltage, VCC MIN NOM MAX 4.5 5 5.5 Positive reference voltage, Vref + (see Note 2) UNIT V VCC 0 Negative reference voltage, Vref – (see Note 2) Differential reference voltage, Vref + – Vref – (see Note 2) 2.5 Analog input voltage (see Note 2) 0 High-level control input voltage, VIH VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V Low-level control input voltage, VIL Clock frequency at I/O CLOCK Hold time, address bits after I/O CLOCK↑, th(A) (see Figure 4) Hold time, CS low after last I/O CLOCK↓, th(CS) (see Figure 5) V VCC + 0.1 VCC 2 0 Setup time, address bits at DATA INPUT before I/O CLOCK↑, tsu(A) (see Figure 4) VCC V V V V 0.8 V 4.1 MHz 100 ns 0 ns 0 ns 1.425 µs Pulse duration, I/O CLOCK high, twH(I/O) 120 ns Pulse duration, I/O CLOCK low, twL(I/O) 120 Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 5) Transition time, I/O CLOCK high to low, tt(I/O) (see Note 4 and Figure 6) Transition time, DATA INPUT and CS, tt(CS) TLC2543C Operating free-air temperature, TA 0 ns 1 µs 10 µs 70 TLC2543I – 40 85 TLC2543M – 55 125 °C NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied to REF– convert as all zeros (000000000000). 3. To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed. 4. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor. http://www.hgsemi.com.cn 4 2018 AUG TLC2543 electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS TLC2543C, TLC2543I MIN TYP† MAX VOH High level output voltage High-level VCC = 4.5 V, VCC = 4.5 V to 5.5 V, IOH = –1.6 mA IOH = –20 µA VOL Low level output voltage Low-level VCC = 4.5 V, VCC = 4.5 V to 5.5 V, IOL = 1.6 mA IOL = 20 µA IOZ High-impedance g off-state output current VO = VCC, VO = 0, CS at VCC 1 2.5 CS at VCC 1 – 2.5 IIH IIL High-level input current VI = VCC VI = 0 1 2.5 Low-level input current 1 – 2.5 µA ICC Operating supply current CS at 0 V 1 2.5 mA ICC(PD) Power-down current For all digital inputs, 0 ≤ VI ≤ 0.5 V or VI ≥ VCC – 0.5 V 4 25 µA Selected channel leakage current Maximum static analog reference current into REF + Ci Input capacitance Selected channel at VCC, 2.4 UNIT V VCC – 0.1 0.4 0.1 Unselected channel at 0 V µA µA 1 Selected channel at 0 V, Unselected channel at VCC Vref + = VCC, V –1 Vref – = GND 1 2.5 Analog inputs 30 60 Control inputs 5 15 µA µA pF † All typical values are at VCC = 5 V, TA = 25°C. electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS TLC2543M MIN TYP† MAX VOH High level output voltage High-level VCC = 4.5 V, VCC = 4.5 V to 5.5 V, IOH = –1.6 mA IOH = –20 µA VOL Low level output voltage Low-level VCC = 4.5 V, VCC = 4.5 V to 5.5 V, IOL = 1.6 mA IOL = 20 µA IOZ High-impedance g off-state output current VO = VCC, VO = 0, CS at VCC 1 2.5 CS at VCC 1 – 2.5 IIH IIL High-level input current 1 10 Low-level input current VI = VCC VI = 0 1 – 10 µA ICC Operating supply current CS at 0 V 1 10 mA ICC(PD) Power-down current For all digital inputs, 0 ≤ VI ≤ 0.5 V or VI ≥ VCC – 0.5 V 4 25 µA Selected channel leakage current Maximum static analog reference current into REF + Ci Input capacitance Selected channel at VCC, 2.4 UNIT V VCC – 0.1 0.4 0.1 Unselected channel at 0 V – 10 Vref – = GND µA µA 10 Selected channel at 0 V, Unselected channel at VCC Vref + = VCC, V 1 2.5 Analog inputs 30 60 Control inputs 5 15 µA µA pF † All typical values are at VCC = 5 V, TA = 25°C. http://www.hgsemi.com.cn 5 2018 AUG TLC2543 operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT EL ED Linearity error (see Note 5) See Figure 2 ±1 LSB Differential linearity error See Figure 2 ±1 LSB EO Offset error (see Note 6) See Note 2 and Figure 2 ± 1.5 LSB EG Gain error (see Note 6) See Note 2 and Figure 2 ±1 LSB ET Total unadjusted error (see Note 7) ± 1.75 LSB DATA INPUT = 1011 Self-test output code (see Table 3 and Note 8) tconv DATA INPUT = 1100 0 DATA INPUT = 1101 4095 Conversion time See Figures 9 – 14 tc Total cycle time (access, sample, and conversion) See Figures 9 – 14 and Note 9 tacq Channel acquisition time (sample) See Figures 9 – 14 and Note 9 tv td(I/O-DATA) Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 6 Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 6 td(I/O-EOC) td(EOC-DATA) Delay time, last I/O CLOCK↓ to EOC↓ See Figure 7 Delay time, EOC↑ to DATA OUT (MSB / LSB) See Figure 8 tPZH, tPZL tPHZ, tPLZ Enable time, CS↓ to DATA OUT (MSB / LSB driven) See Figure 3 Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 tr(EOC) tf(EOC) Rise time, EOC tr(bus) tf(bus) td(I/O-CS) 2048 8 µs 10 10 + total I/O CLOCK periods + td(I/O-EOC) 4 12 10 µs I/O CLOCK periods ns 150 ns 2.2 µs 100 ns 0.7 1.3 µs 70 150 ns See Figure 8 15 50 ns Fall time, EOC See Figure 7 15 50 ns Rise time, data bus See Figure 6 15 50 ns Fall time, data bus See Figure 6 15 50 ns 5 µs Delay time, last I/O CLOCK↓ to CS↓ to abort conversion (see Note 10) 1.5 † All typical values are at TA = 25°C. NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (111111111111), while input voltages less than that applied to REF – convert as all zeros (000000000000). 5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. 6. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep value at the offset point. 7. Total unadjusted error comprises linearity, zero-scale, and full-scale errors. 8. Both the input address and the output codes are expressed in positive logic. 9. I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7). 10. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ≤ 5 µs of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 µs and 10 µs, the result is uncertain as to whether the conversion is aborted or the conversion results are valid. http://www.hgsemi.com.cn 6 2018 AUG TLC2543 PARAMETER MEASUREMENT INFORMATION 15 V 50 Ω C1 10 µF C2 0.1 µF C3 470 pF 10 Ω _ U1 + VI C1 10 µF TLC2543 AIN0 – AIN10 C3 470 pF C2 0.1 µF 50 Ω – 15 V LOCATION PART NUMBER DESCRIPTION OP27 10-µF 35-V tantalum capacitor 0.1-µF ceramic NPO SMD capacitor 470-pF porcelain Hi-Q SMD capacitor U1 C1 C2 C3 — — AVX 12105C104KA105 or equivalent Johanson 201S420471JG4L or equivalent Figure 1. Analog Input Buffer to Analog Inputs AIN0 – AIN10 VCC Test Point VCC Test Point RL = 2.18 kΩ RL = 2.18 kΩ EOC DATA OUT CL = 50 pF 12 kΩ 12 kΩ CL = 100 pF Figure 2. Load Circuits Data Valid 2V CS tPZH, tPZL DATA OUT tPHZ, tPLZ 2.4 V 90% 0.4 V 10% th(A) tsu(A) I/O CLOCK 0.8 V Figure 4. DATA INPUT and I/O CLOCK Voltage Waveforms Figure 3. DATA OUT to Hi-Z Voltage Waveforms http://www.hgsemi.com.cn 2V 0.8 V DATA INPUT 0.8 V 7 2018 AUG TLC2543 PARAMETER MEASUREMENT INFORMATION 2V CS 0.8 V tsu(CS) I/O CLOCK th(CS) Last Clock 0.8 V 0.8 V NOTE A: To ensure full conversion accuracy, it is recommended that no input signal change occurs while a conversion is ongoing. Figure 5. CS and I/O CLOCK Voltage Waveforms tt(I/O) tt(I/O) I/O CLOCK 2V 2V 0.8 V 0.8 V 0.8 V I/O CLOCK Period td(I/O-DATA) tv DATA OUT 2.4 V 0.4 V 2.4 V 0.4 V tr(bus), tf(bus) Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms I/O CLOCK Last Clock 0.8 V td(I/O-EOC) 2.4 V EOC 0.4 V tf(EOC) Figure 7. I/O CLOCK and EOC Voltage Waveforms tr(EOC) EOC 2.4 V 0.4 V td(EOC-DATA) 2.4 V 0.4 V DATA OUT Valid MSB Figure 8. EOC and DATA OUT Voltage Waveforms http://www.hgsemi.com.cn 8 2018 AUG TLC2543 PARAMETER MEASUREMENT INFORMATION CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B 8 11 12 Sample Cycle B ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ 1 Hi-Z State DATA OUT A11 A10 A9 A8 A7 A6 A5 A4 A1 A0 Previous Conversion Data ÎÎÎ ÎÎ ÎÎ Î Î Î ÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎ MSB DATA INPUT 7 B7 B6 B5 B4 MSB B3 B2 B1 B11 ÎÎ ÎÎ ÎÎÎÎ LSB C7 B0 LSB EOC tconv Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value A/D Conversion Interval Initialize Initialize NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 9. Timing for 12-Clock Transfer Using CS With MSB First CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B DATA OUT A11 A10 A9 8 11 A8 A7 A6 A5 A4 A1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ B7 B6 MSB B5 12 1 Sample Cycle B Previous Conversion Data MSB DATA INPUT 7 B4 B3 B2 B1 A0 Low Level LSB B11 ÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎ C7 B0 LSB EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize tconv A/D Conversion Interval Initialize NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First http://www.hgsemi.com.cn 9 2018 AUG TLC2543 PARAMETER MEASUREMENT INFORMATION CS (see Note A) 1 I/O CLOCK 2 3 4 5 Access Cycle B A7 DATA OUT A6 A5 7 8 Sample Cycle B A4 A3 A2 A1 Previous Conversion Data ÎÎÎÎÎÎ ÎÎÎÎÎÎ Hi-Z A0 1 B7 ÎÎÎ ÎÎ ÎÎ Î Î Î ÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ MSB DATA INPUT 6 B7 B6 B5 B4 MSB B3 LSB B2 B1 B0 C7 LSB EOC tconv Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value A/D Conversion Interval Initialize Initialize NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 11. Timing for 8-Clock Transfer Using CS With MSB First CS (see Note A) 1 I/O CLOCK 2 3 4 5 Access Cycle B DATA OUT A7 A6 A5 7 8 1 Sample Cycle B A4 A3 A2 A1 Previous Conversion Data A0 Low Level ÎÎÎ ÎÎ Î Î ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ MSB DATA INPUT 6 B7 MSB B6 B5 B4 B3 ÎÎ ÎÎ ÎÎÎÎ LSB B2 B1 B7 C7 B0 LSB EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize tconv A/D Conversion Interval Initialize NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First http://www.hgsemi.com.cn 10 2018 AUG TLC2543 PARAMETER MEASUREMENT INFORMATION CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B 7 8 15 16 Sample Cycle B ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ 1 Hi-Z State DATA OUT A15 A14 A13 A12 A11 A10 A9 A8 A1 A0 ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Previous Conversion Data MSB B15 ÎÎ ÎÎÎ LSB DATA INPUT B7 B6 B5 B3 B4 MSB B2 B1 B0 C7 LSB EOC tconv Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value A/D Conversion Interval Initialize Initialize NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 13. Timing for 16-Clock Transfer Using CS With MSB First CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B DATA OUT A15 A14 A13 7 8 15 1 Sample Cycle B A12 A11 A10 A9 A8 A1 ÎÎ Î ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Previous Conversion Data MSB 16 A0 Low Level ÎÎÎÎ Î ÎÎÎÎÎ LSB DATA INPUT B7 B6 MSB B5 B4 B3 B2 B1 B15 B0 C7 LSB EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize tconv A/D Conversion Interval NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 14. Timing for 16-Clock Transfer Not Using CS With MSB First http://www.hgsemi.com.cn 11 2018 AUG