SK6226Bx
Non-Crystal UFD Controller
for 2xnm MLC & TLC
Rev. 0.91
Jul. 29, 2011
9擎泰科技股份有限公司
Skymedi Corporation
-1-
Date: 2011-07-29
Version: 0.91
This specification is subject to change without notice. Skymedi Corporation reserves the right to make
changes to improve functions. Although the information in this document has been carefully reviewed,
Skymedi Corporation assumes no responsibility for any errors contained herein and does not assume any
liability arising out of the use of the product or circuit described herein.
Copyright by Skymedi Corporation., all rights reserved. No part of this specification may be reproduced
or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording,
without the written permission of Skymedi Corporation.
Revision History
Date
Rev
Mar. 1st, 2011
0.10
Establishment.
Jul. 25, 2011
0.90
Modify SK6226Ax to SK6226Bx
Modify 3.0V typo.
Jul. 29, 2011
0.91
Modify and redraw SK6226Ax typo
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Description
-2-
Version: 0.91
Table of Contents
1. Description ..................................................................................................................................................... 4
2. Order Information........................................................................................................................................... 4
3. Features ......................................................................................................................................................... 5
4. Block Diagram ............................................................................................................................................... 6
5. Pin Assignment .............................................................................................................................................. 6
5.1 48-pin LQFP SK6226BAPMC4 ................................................................................................................ 6
5.2 64-pin LQFP SK6226BAPQC .................................................................................................................. 8
6. Electrical Specifications ............................................................................................................................... 10
6.1 Absolute Maximum Ratings ................................................................................................................... 10
6.2 DC Characteristics ................................................................................................................................. 10
6.3 AC Characteristics, ONFI 2.0 Synchronous Interface ........................................................................... 11
7. Application Examples .................................................................................................................................. 15
7.1 Controller Selection vs. NAND ............................................................................................................... 15
7.2 Single Channel (Byte mode) .................................................................................................................. 15
8. Package Dimension ..................................................................................................................................... 16
8.1 48-pin LQFP ........................................................................................................................................... 16
8.2 64-pin LQFP ........................................................................................................................................... 17
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Version: 0.91
1. Description
The SK6226Bx is a Non-Crystal USB2.0 Flash Disk controller that complies with USB version2.0
specification and USB Mass Storage Class version 1.0 specification. Besides full speed 12 Mbps
complied with USB1.1 specification, SK6226Bx can provide a 480 Mbps transfer rate. Designed with an
enhanced power control circuit, the SK6226Bx fully complies with USB power specifications for buspowered devices, making it capable of bus-powered operation.
Besides rich features for UFD application, SK6226Bx is also the best solution for next generation
NAND which are manufactured in the most advance technology. In order to interface with 2x/3x nm MLC
and TLC, SK6226Bx ECC capability can correct up to 70 bits error.
Reliable ECC for 2x nm MLC and TLC
SK6226Bx ECC can provide 70-bit/1KB BCH correction code for 2x/3x nm MLC and TLC.
Advance Wear Leveling (AWL) to improve P/E cycle of NAND
Saving BOM Cost
Because SK6226 did not require an external crystal, it can save BOM cost a lot.
Performance & Low Power
When single-channel mode enabled, SK6226Bx can reach the theoretical limit at TBD MB/s for read
access and TBD MB/s for write access in HDBench.
In order to meet Vista Premium logo program, SK6226Bx also meet ReadyBoost™ requirement. Any
UFD with SK6226Bx can easily meet 5 MB/sec throughput for random 4KB reads and 3 MB/sec
throughput for random 512KB writes and market the UFD with enhancement for Windows®
ReadyBoost™.
Support 256/384 pages of NAND
With our superior designs, SK6226Bx runs smoothly on all available host systems and supports MLC
& TLC NAND Flash memories with 4KB and 8KB page and either 128, 192, 256 or 384 pages per block.
The SK6226Bx allows the direct connection of up to 8 NAND Flash chips in the configuration of single
channel by 8 CE.
Therefore, SK6226Bx will be best choice according to cost per performance.
2. Order Information
Part #
Description
Package
SK6226BAPQC
8 CE, 1 WE, 8-bit data width, Multi-Partition, 1.8V/3.3V VCCq.
64-pin LQFP
SK6226BAPMC4
4 CE, 1 WE, 8-bit data width, Multi-Partition, 1.8V/3.3V VCCq.
48-pin LQFP
SK6226BAWWC
8 CE, 1 WE, 8-bit data width, Multi-Partition, 1.8V/3.3V VCCq.
wafer
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-4-
Version: 0.91
3. Features
⌦ Support 2x/3x nm MLC and TLC NAND:
70-bit/1KB BCH error control coding (ECC) for MLC.
Sufficient embedded buffer for 8K page NAND in single channel configuration.
Total addressing space is 64GB.
⌦ Advance Wear Leveling can improve P/E cycle of NAND.
⌦ Saving BOM cost by removing external crystal.
⌦ Outstanding R/W performance:
HDBench: Read:TBD MB/s and Write: TBD MB/s with MLC in single channel.
Read: TBD MB/s and Write: TBD MB/s with TLC in single channel.
ReadyBoost™ : >5 MB/sec throughput for random 4KB reads and,
>3 MB/sec throughput for random 512KB writes
⌦ USB Interface:
Complied with high-speed USB 2.0 interface, backward compatible with USB 1.1.
Complied with USB Mass Storage Class specification v1.0.
Complied with USB bus-powered devices specification.
Support HID interface for password entry in non-administrator mode.
Integrated USB 2.0 Transceiver Macrocell Interface (UTMI) and Serial Interface Engine (SIE).
⌦ Varieties of Supported NAND:
Samsung 21nm MLC, 27nm MLC & TLC, 32 nm TLC.
IM 2xnm 8KB/page MLC, 25 nm MLC & TLC.
Hynix 26nm MLC, 32 nm TLC.
Toshiba 24nm MLC, 32 nm MLC.
Kinds of page size: 4KB and 8KB.
Kinds of page per block: 128 pages, 192 pages, 256 pages and 384 pages.
⌦ Async. NAND Interface with 3.3V VCCq:
SK6226BAPQC: single channel and 8 CE/channel.
SK6226BAPMC4: single channel and 4 CE/channel.
⌦ DDR NAND interface:
1.8V or 3.3V VCCq DDR NAND, either ONFI 2.x NAND or Toggle-mode NAND.
SK6226BAPQC: single channel and 8 CE/channel with 1.8V/3.3V VCCq.
SK6226BAPMC4: single channel and 4 CE/channel with 1.8V/3.3V VCCq.
⌦ Built-in Watch-Dog Timer (WDT)
⌦ Enable Multi-Partition features:
One Read-only Partition, two Read-Write Partitions and one Hidden Partition.
Read-only Partition is designated for AutoRun feature.
UFD can have up to two LUNs because to two Read-Write Partitions.
Each Read-Write Partition can be divided into Public Zone and Private Zone further.
Private Zone can be protected by password.
Capacity of each Partition and Zone can sizeable while factory initialization or by application
program through vendor specific command.
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Version: 0.91
4. Block Diagram
5. Pin Assignment
5.1 48-pin LQFP SK6226xxPMC4
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Pin Name
WP_SW
R/B_1
VDD
VCC
R/B_0
FNRE
FCE0
FCE1
VSS
FD7
FD6
FD5
FD4
VCC
VCC
VDD
VCC
FD3
FD2
FD1
FD0
VSS
FNWP
FNWE
FALE
FCLE
NC
VCC
VDD
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Type
In
In
Power In
Power In
In
O
O
O
Power
I/O
I/O
I/O
I/O
Power In
Power In
Power In
Power In
I/O
I/O
I/O
I/O
Power
O
O
O
O
-----Power In
Power In
Description
Write protect switch.
Flash ready/busy 1.
Core power.
I/O power.
Flash ready/busy 0.
Flash output enable.
Flash chip enable 0.
Flash chip enable 1.
Digital ground.
Flash data bus bit7.
Flash data bus bit6.
Flash data bus bit5.
Flash data bus bit4.
I/O power.
I/O power.
Core power.
I/O power.
Flash data bus bit3.
Flash data bus bit2.
Flash data bus bit1.
Flash data bus bit0.
Digital ground.
Flash write protect.
Flash write enable for flash data.
Flash address latch enable.
Flash command latch enable.
No connection for normal use.
I/O power.
Core power.
-6-
Version: 0.91
Pin #
30
31
Pin Name
VCC
FDQS
Type
Power In
I/O
32
NC
------
33
NC
------
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
FCE3
FCE2
VSS
VCCA5V
V33_OUT
V33_OUT
V18_OUT
AGND
DM
DP
RREF
AVDD
AGND
VSS
LED
O
O
Power
Power In
Power Out
Power Out
Power out
Power
I/O
I/O
In
Power In
Power
Power
O
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Description
I/O power.
Flash DQS pin for DDR flash.
No connection for normal use. The pin had a default
pull-up resistor.
No connection for normal use. The pin had a default
pull-up resistor.
Flash chip enable 3.
Flash chip enable 2.
Digital ground.
Vbus 5V power input.
Regulated 3.3V power output.
Regulated 3.3V power output.
Regulated 1.8V power output.
Analog ground.
USB D-.
USB D+.
USB PHY reference resistor.
Analog 3.3V input.
Analog ground.
Digital ground.
LED output.
-7-
Version: 0.91
5.2 64-pin LQFP SK6226xxPQC
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Pin Name
VSS
VSS
LED
NC
NC
NC
NC
WP_SW
R/B_1
VDD
VCC
R/B_0
FNRE
FCE0
FCE1
VSS
VSS
FD7
FD6
FD5
FD4
VCC
VCC
VDD
VDD
VCC
FD3
FD2
FD1
FD0
VSS
VSS
FNWP
FNWE
FALE
FCLE
NC
FCE7
FCE6
VDD
VCC
FDQS
FCE5
FCE4
Type
Power
Power
O
--------------------In
In
Power In
Power In
In
O
O
O
Power
Power
I/O
I/O
I/O
I/O
Power In
Power In
Power In
Power In
Power In
I/O
I/O
I/O
I/O
Power
Power
O
O
O
O
-----O
O
Power In
Power In
I/O
O
O
45
NC
------
46
NC
------
47
FCE3
48
FCE2
49
VSS
50
VCCA5V
51
VCCA5V
52
V33_OUT
53
V33_OUT
54
V18_OUT
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O
O
Power
Power In
Power In
Power Out
Power Out
Power out
Description
Digital ground.
Digital ground.
LED output.
No connection for normal use.
No connection for normal use.
No connection for normal use.
No connection for normal use.
Write protect switch.
Flash ready/busy 1.
Core power.
I/O power.
Flash ready/busy 0.
Flash output enable.
Flash chip enable 0.
Flash chip enable 1.
Digital ground.
Digital ground.
Flash data bus bit7.
Flash data bus bit6.
Flash data bus bit5.
Flash data bus bit4.
I/O power.
I/O power.
Core power.
Core power.
I/O power.
Flash data bus bit3.
Flash data bus bit2.
Flash data bus bit1.
Flash data bus bit0.
Digital ground.
Digital ground.
Flash write protect.
Flash write enable for flash data.
Flash address latch enable.
Flash command latch enable.
No connection for normal use.
Flash chip enable 7.
Flash chip enable 6.
Core power.
I/O power.
Flash DQS pin for DDR flash.
Flash chip enable 5.
Flash chip enable 4.
No connection for normal use. The pin had a default
pull-up resistor.
No connection for normal use. The pin had a default
pull-up resistor.
Flash chip enable 3.
Flash chip enable 2.
Digital ground.
Vbus 5V power input.
Vbus 5V power input.
Regulated 3.3V power output.
Regulated 3.3V power output.
Regulated 1.8V power output.
-8Version: 0.91
Pin #
55
56
57
58
59
60
61
62
63
64
Pin Name
V18_OUT
VSSA
AGND
AGND
DM
DP
RREF
AVDD
AVDD
AGND
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Type
Power out
Power
Power
Power
I/O
I/O
In
Power In
Power In
Power
Description
Regulated 1.8V power output.
Internal regulator analog ground.
Analog ground.
Analog ground.
USB D-.
USB D+.
USB PHY reference resistor.
Analog 3.3V input.
Analog 3.3V input.
Analog ground.
-9-
Version: 0.91
6. Electrical Specifications
6.1 Absolute Maximum Ratings
Following table shows SK6226Bx stress ratings only. Extended exposure to the maximum ratings
might degrade device reliability. Although has protective circuitry to resist damage from electrostatic
discharge (ESD), precautions should always be taken to avoid high voltage or electric field.
Symbol
Parameter
Min
Max
Unit
Tstorage
Storage Temperature
- 40
+125
°C
Ta
Ambient Operating Temperature,
Commercial
0
70
°C
VAVDD
Analog 3.3V Input Voltage
- 0.3
3.6
V
VVCC, VVDD
Digital 3.3V Input Voltage
- 0.3
3.6
V
VVCCA5V
USB +5.0V Input Voltage
-----
5.25
V
Typ.
Max.
Unit
6.2 DC Characteristics
Unless otherwise noted, all test conditions are as follows:
GND=0V, VCC, VDD =3.3V±10%, V18_OUT=1.8V±10%, Ta=25°C.
Symbol
Description
Min.
VAVDD
Analog 3.3V Input Voltage
3.0
3.3
3.6
V
VVCC, VVDD
Digital 3.3V Input Voltage
3.0
3.3
3.6
V
VVCCA5V
USB +5.0V Input Voltage
4.40
5.0
5.25
V
VV33_out
Regulated 3.3V Output Voltage
VV18_out
Regulated 1.8V Output Voltage
3.3
V
1.8
V
VIH
Input Voltage High
0.7VCC
VCC+0.3
V
VIL
Input Voltage Low
GND-0.3
0.25VCC
V
VOH
Output Voltage High
0.7VCC
VOL
Output Voltage Low
0.125VCC
V
Cin
Input Pin Capacitance
10
pF
IREG
5V => 3V regulator supply current
@VV33_OUT=3.15V
V
TBD
mA
IDD
Operating Current
TBD
mA
ISTD
Standby Current
TBD
mA
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Version: 0.91
6.3 AC Characteristics, ONFI 2.0 Synchronous Interface
The specification of timing parameters of ONFI 2.0 Source Synchronous modes are listed below.
The real AC timing is subjective to change due to FW revision.
Parameter
Mode 0
Mode 1
Mode 2
Unit
50
30
20
ns
~20
~33
~50
MHz
Min
Max
Min
Max
Min
Max
tAC
—
20
—
20
—
20
ns
tADL
100
—
100
—
70
—
ns
tCADf
25
—
25
—
25
—
ns
tCADs
45
—
45
—
45
—
ns
tCAH
10
—
5
—
4
—
ns
tCALH
10
—
5
—
4
—
ns
tCALS
10
—
5
—
4
—
ns
tCAS
10
—
5
—
4
—
ns
tCH
10
—
5
—
4
—
ns
tCK(avg) or
tCK
50
—
30
—
20
—
ns
Minimum: tCK(avg) + tJIT(per) min
Maximum: tCK(avg) + tJIT(per) max
tCK(abs)
ns
tCKH(abs)
0.43
0.57
0.43
0.57
0.43
0.57
tCK
tCKL(abs)
0.43
0.57
0.43
0.57
0.43
0.57
tCK
tCS
35
—
25
—
15
—
ns
tDH
5
—
2.5
—
1.7
—
ns
tDQSCK
—
20
—
20
—
20
ns
tDQSD
—
20
—
20
—
20
ns
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tDQSHZ
—
20
—
20
—
20
ns
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tDQSQ
—
5
—
2.5
—
1.7
ns
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
tDS
5
—
3
—
2
—
ns
tDSH
0.2
—
0.2
—
0.2
—
tCK
tDSS
0.2
—
0.2
—
0.2
—
tCK
tDVW
tFEAT
tDVW = tQH – tDQSQ
—
1
—
1
ns
—
1
tHP = min(tCKL, tCKH)
tHP
µs
ns
tITC
—
1
—
1
—
1
µs
tJIT(per)
0.7
0.7
0.7
0.7
0.7
0.7
ns
tQH = tHP – tQHS
tQH
tQHS
—
tRHW
tRR
tRST
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6
—
100
—
20
—
—
5/10/
500
ns
3
—
100
—
100
—
ns
20
—
20
—
ns
—
5/10/
500
—
5/10/
500
µs
- 11 -
2
ns
Version: 0.91
Parameter
tWB
Mode 0
—
100
Mode 1
—
100
Mode 2
—
100
Unit
ns
tWHR
80
—
60
—
60
—
ns
tWPRE
1.5
—
1.5
—
1.5
—
tCK
tWPST
1.5
—
1.5
—
1.5
—
tCK
tWRCK
20
—
20
—
20
—
ns
tWW
100
—
100
—
100
—
ns
NOTE:
tDQSHZ is not referenced to a specific voltage level, but specifies when the device
output is no longer driving.
tCK(avg) is the average clock period over any consecutive 200 cycle window.
tCKH(abs) and tCKL(abs) include static offset and duty cycle jitter.
6.3.1 Command Cycle
6.3.2 Address Cycle
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Version: 0.91
6.3.3 Data Input Cycle
6.3.4 Data Output Cycle
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Version: 0.91
6.3.5 Set Feature Cycle
Sub Feature
Parameter
P1
7
6
Reserved (0)
5
4
3
Data Interface
2
1
0
Timing Mode Number
P2
Reserved (0)
P3
Reserved (0)
P4
Reserved (0)
Timing Mode Number
Set to the numerical value of the maximum timing mode in use by the
host. Default power-on value is 0h.
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Version: 0.91
7. Application Examples
7.1 Controller Selection vs. NAND
Part#
Async. NAND
DDR NAND
# of channel
# of CE
VCCq
# of channel
# of CE
VCCq
SK6226BAPQC
Single
8
3.3V
Single
8
1.8V
3.3V
SK6226BAPMC4
Single
4
3.3V
Single
4
1.8V
3.3V
7.2 Single Channel (Byte mode)
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Version: 0.91
8. Package Dimension
8.1 48-pin LQFP
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- 16 -
Version: 0.91
8.2 64-pin LQFP
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- 17 -
Version: 0.91