P25Q80H Datasheet
P25Q80H
Ultra Low Power, 8M-bit
Serial Multi I/O Flash Memory Datasheet
May. 30, 2017
Performance Highlight
Wide Supply Range from 2.3 to 3.6V for Read, Erase and Program
Ultra Low Power consumption for Read, Erase and Program
X1, X2 and X4 Multi I/O Support
High reliability with 100K cycling and 20 Year-retention
Puya Semiconductor (Shanghai) Co., Ltd
Puya Semiconductor
Page 1 of 71
P25Q80H Datasheet
Contents
1
2
3
Overview ........................................................................................................................................................4
Description .....................................................................................................................................................5
Pin Definition .................................................................................................................................................6
3.1
Pin Configurations .............................................................................................................................6
3.2
Pin Descriptions .................................................................................................................................6
4 Block Diagram ...............................................................................................................................................7
5 Electrical Specifications .................................................................................................................................8
5.1
Absolute Maximum Ratings ...............................................................................................................8
5.2
DC Characteristics .............................................................................................................................9
5.3
AC Characteristics .......................................................................................................................... 10
5.4
AC Characteristics for Program and Erase ..................................................................................... 11
5.5
Operation Conditions ...................................................................................................................... 13
6 Data Protection ........................................................................................................................................... 15
7 Memory Address Mapping .......................................................................................................................... 17
8 Device Operation ........................................................................................................................................ 18
9 Hold Feature ............................................................................................................................................... 20
10
Commands ......................................................................................................................................... 21
10.1 Commands listing ........................................................................................................................... 21
10.2 Write Enable (WREN) ..................................................................................................................... 24
10.3 Write Disable (WRDI) ....................................................................................................................... 24
10.4 Write Enable for Volatile Status Register ....................................................................................... 25
10.5 Read Status Register (RDSR) .......................................................................................................... 25
10.6 Read Configure Register (RDCR) .................................................................................................... 28
10.7 Active Status Interrupt (ASI) ........................................................................................................... 29
10.8 Write Status Register (WRSR) ......................................................................................................... 29
10.9 Write Configure Register (WRCR) .................................................................................................... 30
10.10 Read Data Bytes (READ) ................................................................................................................. 31
10.11 Read Data Bytes at Higher Speed (FAST_READ) ............................................................................ 32
10.12 Dual Read Mode (DREAD) .............................................................................................................. 33
10.13 2 X IO Read Mode (2READ) ............................................................................................................ 34
10.14 2 X IO Read Performer Enhance Mode ............................................................................................ 35
10.15 Quad Read Mode (QREAD) ............................................................................................................. 36
10.16 4 X IO Read Mode (4READ) ............................................................................................................ 37
10.17 4 X IO Read Performance Enhance Mode ....................................................................................... 38
10.18 Burst Read....................................................................................................................................... 39
10.19 Page Erase (PE) .............................................................................................................................. 40
10.20 Sector Erase (SE) ............................................................................................................................ 40
10.21 Block Erase (BE32K) ....................................................................................................................... 41
10.22 Block Erase (BE).............................................................................................................................. 41
10.23 Chip Erase (CE) ............................................................................................................................... 42
10.24 Page Program (PP).......................................................................................................................... 43
10.25 Dual Input Page Program (DPP) ...................................................................................................... 44
10.26 Quad Page Program (QPP) ............................................................................................................. 45
10.27 Erase Security Registers (ERSCUR) ................................................................................................ 46
10.28 Program Security Registers (PRSCUR) ........................................................................................... 47
10.29 Read Security Registers (RDSCUR) ................................................................................................ 48
10.30 Deep Power-down (DP) ................................................................................................................... 49
10.31 Release form Deep Power-Down (RDP), Read Electronic Signature (RES) ...................................... 49
10.32 Read Electronic Manufacturer ID & Device ID (REMS) ..................................................................... 51
10.33 Dual I/O Read Electronic Manufacturer ID & Device ID (DREMS) .................................................... 52
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Page 2 of 71
P25Q80H Datasheet
10.34 Quad I/O Read Electronic Manufacturer ID & Device ID (QREMS)................................................... 53
10.35 Read Identification (RDID)................................................................................................................ 54
10.36 Program/Erase Suspend/Resume .................................................................................................... 55
10.37 Erase Suspend to Program .............................................................................................................. 56
10.38 Program Resume and Erase Resume .............................................................................................. 57
10.39 No Operation (NOP) ........................................................................................................................ 57
10.40 Software Reset (RSTEN/RST) ......................................................................................................... 58
10.41 Read Unique ID (RUID) ................................................................................................................... 59
10.42 Read SFDP Mode (RDSFDP) .......................................................................................................... 60
11
Ordering Information........................................................................................................................... 65
12
Package Information........................................................................................................................... 66
12.1 8-Lead SOP(150mil) ....................................................................................................................... 66
12.2 8-Lead SOP(200mil) ....................................................................................................................... 67
12.3 8-Lead TSSOP ............................................................................................................................... 68
12.4 8-Land USON(3x2mm) ................................................................................................................... 69
12.5 8-Land WSON(6x5mm) .................................................................................................................. 70
13
Revision History.................................................................................................................................. 71
Puya Semiconductor
Page 3 of 71
P25Q80H Datasheet
1 Overview
General
Single 2.3V to 3.60V supply
Industrial Temperature Range -40C to 85C
Serial Peripheral Interface (SPI) Compatible: Mode 0 and Mode 3
Single, Dual and Quad IO mode
-
8M x 1 bit
-
4M x 2 bits
-
2M x 4 bits
Flexible Architecture for Code and Data Storage
-
Uniform 256-byte
Page Program
-
Uniform 256-byte
Page Erase
-
Uniform 4K-byte
Sector Erase
-
Uniform 32K/64K-byte Block Erase
-
Full Chip Erase
Hardware Controlled Locking of Protected Sectors by WP Pin
One Time Programmable (OTP) Security Register
3*512-Byte Security Registers With OTP Lock
128 bit unique ID for each device
Fast Program and Erase Speed
-
2ms
Page program time
-
8ms
Page erase time
-
8ms
4K-byte sector erase time
-
8ms
32K-byte block erase time
-
8ms
64K-byte block erase time
JEDEC Standard Manufacturer and Device ID Read Methodology
Ultra Low Power Consumption
-
0.6uA
Deep Power Down current
-
9uA
Standby current
-
2.5mA
Active Read current at 33MHz
-
3.0mA
Active Program or Erase current
High Reliability
-
100,000 Program / Erase Cycles
-
20-year Data Retention
Industry Standard Green Package Options
-
8-pin
SOP (150mil/200mil)
-
8-land
USON (2x3mm)
-
8-land
WSON (6x5mm)
-
8-pin
TSSOP
-
WLCSP
-
KGD for SiP
Puya Semiconductor
Page 4 of 71
P25Q80H Datasheet
2 Description
The P25Q80H is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or
external RAM for execution. The flexible erase architecture of the device, with its page erase granularity it is
ideal for data storage as well, eliminating the need for additional data storage devices.
The erase block sizes of the device have been optimized to meet the needs of today's code and data storage
applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently.
Because certain code modules and data storage segments must reside by themselves in their own erase
regions, the wasted and unused memory space that occurs with large sectored and large block erase Flash
memory devices can be greatly reduced. This increased memory space efficiency allows additional code
routines and data storage segments to be added while still maintaining the same overall device density.
The device also contains an additional 3*512-byte security registers with OTP lock (One-Time
Programmable), can be used for purposes such as unique device serialization, system-level Electronic Serial
Number (ESN) storage, locked key storage, etc.
Specifically designed for use in many different systems, the device supports read, program, and erase
operations with a wide supply voltage range of 2.3V to 3.6V. No separate voltage is required for programming
and erasing.
Puya Semiconductor
Page 5 of 71
P25Q80H Datasheet
3 Pin Definition
3.1 Pin Configurations
CS#
1
8
VCC
SO
2
7
HOLD#
WP#
3
6
SLCK
4
5
SI
GND
CS#
1
8
VCC
SO
2
7
HOLD#
WP#
3
6
SLCK
4
5
SI
GND
8-PIN SOP (150mil/200mil) and TSSOP
8-Land UDFN (2x3mm/6x5mm)
3.2 Pin Descriptions
No.
Symbol
1
CS#
2
SO
SIO1
3
WP#
SIO2
4
GND
-
5
SI
SIO0
6
SCLK
-
7
HOLD#
SIO3
8
Vcc
-
Puya Semiconductor
Extension
Remarks
Chip select
Serial data output for 1 x I/O
Serial data input and output for 4 x I/O read mode
Write protection active low
Serial data input and output for 4 x I/O read mode
Ground of the device
Serial data input for 1x I/O
Serial data input and output for 4 x I/O read mode
Serial interface clock input
To pause the device without deselecting the device
Serial data input and output for 4 x I/O read mode
Power supply of the device
Page 6 of 71
P25Q80H Datasheet
4 Block Diagram
CS#
High Voltage Generator
Serial Bus
Control Logic
SCK
Data buffer
SI
SO
Control &
Logic
WP#
Address Latch
X -DECODER
Interface
Flash Memory Array
HOLD#
Serial MUX &
I/O buffers
Control and
Protection logic
VCC
GND
Puya Semiconductor
Y-DECODER
Page 7 of 71
P25Q80H Datasheet
5 Electrical Specifications
5.1 Absolute Maximum Ratings
NOTICE: Stresses above those listed under “Absolute
Storage Temperature .......................-65°C to +150°C
Operation Temperature ....................-40°C to +125°C
Maximum Operation Voltage............. 4.0V
Voltage on Any Pin with
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at those or any other conditions above those
indicated in the operational listings of this specification is not
respect to Ground. ..........................-0.6V to + 4.1V
implied. Exposure to maximum rating conditions for
DC Output Current ............................5.0 mA
extended periods may affect device reliability.
[1]
Table 5-1 Pin Capacitance
Symbol
Parameter
Max.
Units
Test Condition
COUT
Output Capacitance
8
pF
VOUT=GND
CIN
Input Capacitance
6
pF
VIN=GND
Note:
1.
Test Conditions: TA = 25°C, F = 1MHz, Vcc = 3.0V.
Figure 5-1 Maximum Overshoot Waveform
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
VCC+0.5V
20ns
0V
VCC
20ns
- 0.6V
Figure 5-2 Input Test Waveforms and Measurement Level
Input timing reference level
0.8VCC
Output timing reference level
0.7VCC
AC MeasurementLevel
0.5VCC
0.3VCC
0.2VCC
Note:Input pulse rise and fall time ara < 5ns
Figure 5-3 Output Loading
DEVICE
UNDER
TEST
25K ohm
VCC
CL
25K ohm
CL = 15/30pF Including jig capacitance
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Page 8 of 71
P25Q80H Datasheet
5.2 DC Characteristics
Table 5-2 DC parameters
Sym.
Parameter
IDPD
Deep power down
current
ISB
Standby current
ICC1
Low power read
current (03h)
ICC2
Read current (0Bh)
ICC3
ICC4
Conditions
2.3V to 3.6V
Min.
CS#=Vcc, all other inputs at 0V
or Vcc
CS#, HOLD#, WP#=VIH all inputs
at CMOS levels
Typ.
Max.
0.6
1.5
9
Units
uA
uA
f=1MHz; IOUT=0mA
2.0
3.0
mA
f=33MHz; IOUT=0mA
2.0
4.0
mA
f=50MHz; IOUT=0mA
2.5
4.0
mA
f=85MHz; IOUT=0mA
2.5
4.5
mA
Program current
CS#=Vcc
3.0
5.0
mA
Erase current
CS#=Vcc
3.0
5.0
mA
ILI
Input load current
All inputs at CMOS level
1.0
uA
ILO
Output leakage
All inputs at CMOS level
1.0
uA
VIL
Input low voltage
0.3Vcc
V
VIH
Input high voltage
VOL
Output low voltage
IOL=100uA
VOH
Output high voltage
IOH=-100uA
0.7Vcc
V
0.2
Vcc-0.2
V
V
Note
1. Typical values measured at 3.0V @ 25°C
Puya Semiconductor
Page 9 of 71
P25Q80H Datasheet
5.3 AC Characteristics
Table 5-3 AC parameters
Symbol
Alt.
Clock
fSCLK
fC
2.3V~3.6V
Parameter
Frequency
for
the
following
min
typ
max
Unit
104
MHz
instructions:
FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP, RES,
WREN, WRDI, RDID, RDSR, WRSR(7)
fRSCLK
fR
Clock Frequency for READ instructions
55
MHz
fTSCLK
fT
Clock Frequency for 2READ,DREAD instructions
104
MHz
fQ
Clock Frequency for 4READ,QREAD instructions
104
MHz
104
MHz
fQPP
Clock Frequency for QPP (Quad page program)
tCH(1)
tCLH
Clock High Time
4.5
ns
tCL(1)
tCLL
Clock Low Time (fSCLK) 45% x (1fSCLK)
4.5
ns
tCLCH(7)
Clock Rise Time (peak to peak)
0.1
v/ns
tCHCL(7)
Clock Fall Time (peak to peak)
0.1
v/ns
CS# Active Setup Time (relative to SCLK)
5
ns
CS# Not Active Hold Time (relative to SCLK)
5
ns
tSLCH
tCSS
tCHSL
tDVCH
tDSU
Data In Setup Time
2
ns
tCHDX
tDH
Data In Hold Time
3
ns
tCHSH
CS# Active Hold Time (relative to SCLK)
5
ns
tSHCH
CS# Not Active Setup Time (relative to SCLK)
5
ns
CS# Deselect Time From Read to next Read
15
ns
30
ns
tSHSL
tCSH
CS# Deselect Time From Write,Erase,Program to Read
Status Register
tSHQZ(7)
tDIS
tCLQV
tV
tCLQX
tHO
Output Disable Time
6
ns
Clock Low to Output Valid Loading 30pF
7
ns
6
ns
Clock Low to Output Valid Loading 15pF
Output Hold Time
0
ns
tHLCH
HOLD# Active Setup Time (relative to SCLK)
5
ns
tCHHH
HOLD# Active Hold Time (relative to SCLK)
5
ns
tHHCH
HOLD# Not Active Setup Time (relative to SCLK)
5
ns
tCHHL
HOLD# Not Active Hold Time (relative to SCLK)
5
ns
tHHQX
tLZ
HOLD# to Output Low-Z
6
ns
tHLQZ
tHZ
HOLD# to Output High-Z
6
ns
tWHSL(3)
Write Protect Setup Time
20
tSHWL(3)
Write Protect Hold Time
100
tDP
tRES1
tRES2
tW
ns
CS# High to Deep Power-down Mode
CS# High To Standby Mode Without Electronic Signature
Read
CS# High To Standby Mode With Electronic Signature
Read
Write Status Register Cycle Time
Reset recovery time(for erase/program operation
tReady
ns
except WRSR)
Reset recovery time(for WRSR operation)
Puya Semiconductor
8
30
12
3
us
8
us
8
us
12
ms
us
8
ms
Page 10 of 71
P25Q80H Datasheet
5.4 AC Characteristics for Program and Erase
Table 5-4 AC parameters fro program and erase
Sym.
2.3V to 3.6V
Parameter
Min.
Typ.
Max.
Units
TESL(6)
Erase Suspend Latency
30
us
TPSL(6)
Program Suspend Latency
30
us
TPRS(4)
Latency between Program Resume and next Suspend
0.3
us
TERS(5)
Latency between Erase Resume and next Suspend
0.3
us
tPP
Page program time (up to 256 bytes)
2
3
ms
tPE
Page erase time
8
12
ms
tSE
Sector erase time
8
12
ms
tBE1
Block erase time for 32K bytes
8
12
ms
tBE2
Block erase time for 64K bytes
8
12
ms
tCE
Chip erase time
8
12
ms
Note
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. Only applicable as a constraint for a WRSR instruction.
4. Program operation may be interrupted as often as system request. The minimum timing of tPRS must be
observed before issuing the next program suspend command. However, in order for an Program operation to
make progress, tPRS ≥ 100us must be included in resume-to-suspend loop(s). Not 100% tested.
5. Erase operation may be interrupted as often as system request. The minimum timing of tERS must be
observed before issuing the next erase suspend command. However, in order for an Erase operation to make
progress, tERS ≥ 200us must be included in resume-to-suspend loop(s). Notes. Not 100% tested.
6. Latency time is required to complete Erase/Program Suspend operation.
7. The value guaranteed by characterization, not 100% tested in production.
Figure 5-4 Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCLH tCLL
tCHSH
tSHCH
SCLK
tDVCH
tCHDX
SI
MSB
SO
High-Z
Puya Semiconductor
tCHCL
tCLCH
LSB
Page 11 of 71
P25Q80H Datasheet
Figure 5-5 Output Timing
CS#
tCLH
SCLK
tCLQV
tCLQV
tCLQX
tSHQZ
tCLL
tCLQX
tQLQH
SO
LSB
tQHQL
SI
Least significant address bit (LIB) in
Figure 5-6 Hold Timing
CS#
tCHHL
SCLK
tHLCH
tHLQZ
SO
tCHHH
tHHCH
tHHQX
HOLD#
SI do not care during HOLD operation.
Figure 5-7 WP Timing
CS#
tWHSL
tSHWL
WP#
SCLK
SI
Write status register is allowed
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Write status register is not allowed
Page 12 of 71
P25Q80H Datasheet
5.5 Operation Conditions
At Device Power-Up and Power-Down
AC timing illustrated in "Figure AC Timing at Device Power-Up" and "Figure Power-Down Sequence" are for
the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is
ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to
be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 5-8
AC Timing at Device Power-Up
VCC
VCC(min)
GND
tVR
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
LSB
MSB
SI
tCLCH
High-Z
SO
Figure 5-9 Power-up Timing
Vcc(max)
Chip Selection is not allowed
Vcc(min)
tVSL
Device is fully accessible
VWI
Time
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Page 13 of 71
P25Q80H Datasheet
Power Up/Down and Voltage Drop
For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing.
Please check the table below for more detail.
Figure 5-10 Power down-up Timing
Vcc(max)
Chip Selection is not allowed
Vcc(min)
tVSL
VPWD(max)
Device is fully
accessible
tPWD
Time
Symbol
Parameter
VPWD
VCC voltage needed to below VPWD for ensuring
initialization will occur
tPWD
tVSL
tVR
VWI
The minimum duration for ensuring initialization will occur
VCC(min.) to device operation
VCC Rise Time
Write Inhibit Voltage
min
300
70
1
1.45
max
unit
1
V
500000
1.55
us
us
us/V
V
Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The
Status Register contains 00h (all Status Register bits are 0).
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Page 14 of 71
P25Q80H Datasheet
6 Data Protection
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control
register architecture of the device constrains that the memory contents can only be changed after specific
command sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC
power-up and power-down or from system noise.
• Power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may
protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and
completed on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL)
before issuing other commands to change data.
• Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the
memory array that can be read but not change.
• Hardware Protection Mode: WP# going low to protected the BP0~BP4bits and SRP0~1bits
• Deep Power-Down Mode: By entering deep power down mode, the flash device is under protected from
writing all commands except the Release form Deep Power-Down Mode command.
Table 6-1. Protected Area Sizes
P25Q80H Protected Area Sizes (CMP bit = 0)
Status bit
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
x
x
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
15
0F0000H-0FFFFFH
64KB
Upper 1/16
0
0
0
1
0
14 and 15
0E0000H-0FFFFFH
128KB
Upper 1/8
0
0
0
1
1
12 to 15
0C0000H-0FFFFFH
256KB
Upper 1/4
0
0
1
0
0
8 to 15
080000H-0FFFFFH
512KB
Upper 1/2
0
1
0
0
1
0
000000H-00FFFFH
64KB
Lower 1/16
0
1
0
1
0
0 and 1
000000H-01FFFFH
128KB
Lower 1/8
0
1
0
1
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/4
0
1
1
0
0
0 to 7
000000H-07FFFFH
512KB
Lower 1/2
0
x
1
0
1
0 to 15
000000H-0FFFFFH
1MB
ALL
x
x
1
1
x
0 to 15
000000H-0FFFFFH
1MB
ALL
1
0
0
0
1
15
0FF000H-0FFFFFH
4KB
Upper 1/256
1
0
0
1
0
15
0FE000H-0FFFFFH
8KB
Upper 1/128
1
0
0
1
1
15
0FC000H-0FFFFFH
16KB
Upper 1/64
1
0
1
0
x
15
0F8000H- 0FFFFFH
32KB
Upper 1/32
1
1
0
0
1
0
000000H-000FFFH
4KB
Lower 1/256
1
1
0
1
0
0
000000H-001FFFH
8KB
Lower 1/128
1
1
0
1
1
0
000000H-003FFFH
16KB
Lower 1/64
1
1
1
0
x
0
000000H-007FFFH
32KB
Lower 1/32
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Page 15 of 71
P25Q80H Datasheet
P25Q80H Protected Area Sizes (CMP bit = 1)
Status bit
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
x
x
0
0
0
0 to 15
000000H-0FFFFFH
1MB
ALL
0
0
0
0
1
0 to 14
000000H-0EFFFFH
960KB
Lower 15/16
0
0
0
1
0
0 to 13
000000H-0DFFFFH
896KB
Lower 7/8
0
0
0
1
1
0 to 11
000000H-0BFFFFH
768KB
Lower 3/4
0
0
1
0
0
0 to 7
000000H-07FFFFH
512KB
Lower 1/2
0
1
0
0
1
1 to 15
010000H-0FFFFFH
960KB
Upper 15/16
0
1
0
1
0
2 to 15
020000H-0FFFFFH
896KB
Upper 7/8
0
1
0
1
1
4 to 15
040000H-0FFFFFH
768KB
Upper 3/4
0
1
1
0
0
8 to 15
080000H-0FFFFFH
512KB
Upper 1/2
0
x
1
0
1
NONE
NONE
NONE
NONE
x
x
1
1
x
NONE
NONE
NONE
NONE
1
0
0
0
1
0 to 15
000000H-0FEFFFH
1020KB
Lower 255/256
1
0
0
1
0
0 to 15
000000H-0FDFFFH
1016KB
Lower 127/128
1
0
0
1
1
0 to 15
000000H-0FBFFFH
1008KB
Lower 63/64
1
0
1
0
x
0 to 15
000000H-0F7FFFH
992KB
Lower 31/32
1
1
0
0
1
0 to 15
001000-0FFFFFH
1020KB
Upper 255/256
1
1
0
1
0
0 to 15
002000-0FFFFFH
1016KB
Upper 127/128
1
1
0
1
1
0 to 15
004000-0FFFFFH
1008KB
Upper 63/64
1
1
1
0
x
0 to 15
008000-0FFFFFH
992KB
Upper 31/32
Note:
1. X=don’t care
2. If any erase or program command specifies a memory that contains protected data portion, this command will be
ignored.
Puya Semiconductor
Page 16 of 71
P25Q80H Datasheet
7
Memory Address Mapping
The memory array can be erased in three levels of granularity including a full chip erase. The size of the
erase blocks is optimized for both code and data storage applications, allowing both code and data segments
to reside in their own erase regions.
P25Q80 Memory Organization
Block64K
……
……
Puya Semiconductor
1-0
0
……
3-2
1
……
5-4
2
29 - 28
14
31 - 30
15
Block32K
Sector
Address Range
255
0FF000H
0FFFFFH
……
……
……
240
0F0000H
0F0FFFH
239
0EF000H
0EFFFFH
……
……
……
224
0E0000H
0E0FFFH
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
47
02F000H
02FFFFH
……
……
……
32
020000H
020FFFH
31
01F000H
01FFFFH
……
……
……
16
010000H
010FFFH
15
00F000H
00FFFFH
……
……
……
0
000000H
000FFFH
Page 17 of 71
P25Q80H Datasheet
8 Device Operation
Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. When correct
command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS#
rising edge.
Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of serial peripheral interface mode 0 and mode 3 is shown as Figure 8-1.
For the following instructions: RDID, RDSR, RDSR1, RDSCUR, READ, FAST_READ, DREAD, 2READ,
4READ, QREAD, RDSFDP, RES, REMS, DREMS, QREMS, the shifted-in instruction sequence is followed
by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following
instructions: WREN, WRDI, WRSR, PE, SE, BE32K, BE, CE, PP, DPP, QPP, DP, ERSCUR, PRSCUR,
SUSPEND, RESUME, RSTEN, RST, the CS# must go high exactly at the byte boundary; otherwise, the
instruction will be rejected and not executed.
During the progress of Write Status Register, Program, Erase operation, to access the memory array is
neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 8-1 Serial Peripheral Interface Modes Supported
CPOL CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
SO
shift out
MSB
MSB
Note:
CPOL indicates clock polarity of serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA
indicates clock phase. The combination of CPOL bit and CPHA bit decides which serial mode is supported.
Standard SPI
The P25Q80H features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is
latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The P25Q80H supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast
Read”(3BHand BBH) commands. These commands allow data to be transferred to or from the device at two
Puya Semiconductor
Page 18 of 71
P25Q80H Datasheet
times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become
bidirectional I/O pins: IO0 and IO1.
Quad SPI
The P25Q80H supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast
Read”(6BH,EBH) commands. These commands allow data to be transferred to or from the device at four
times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become
bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 andIO3. Quad SPI commands
require the non-volatile Quad Enable bit(QE) in Status Register to be set.
Puya Semiconductor
Page 19 of 71
P25Q80H Datasheet
9 Hold Feature
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop
the operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of
HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low,
HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising
edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low,
HOLD operation will not end until Serial Clock being low).
Figure 9-1 Hold Condition Operation
CS#
SCLK
HOLD#
HOLD
HOLD
During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will
keep high impedance until Hold# pin goes high. The Serial Data Input (SI) is don't care if both Serial Clock
(SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip
Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start
communication with chip, the HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.
Puya Semiconductor
Page 20 of 71
P25Q80H Datasheet
10 Commands
10.1 Commands listing
Figure 10-1 Command set
Abbr.
Code
ADR
Bytes
DMY
Bytes
Data
Bytes
Read Array (fast)
FREAD
0Bh
3
1
1+
n bytes read out until CS# goes high
Read Array (low power)
READ
03h
3
0
1+
n bytes read out until CS# goes high
Read Dual Output
DREAD
3Bh
3
1
1+
n bytes read out by Dual output
Read 2x I/O
2READ
BBh
3
1
1+
n bytes read out by 2 x I/O
Read Quad Output
QREAD
6Bh
3
1
1+
n bytes read out by Quad output
Read 4x I/O
4READ
EBh
3
1
1+
n bytes read out by 4 x I/O
Page Erase
PE
81h
3
0
0
erase selected page
Sector Erase (4K bytes)
SE
20h
3
0
0
erase selected sector
Block Erase (32K bytes)
BE32
52h
3
0
0
erase selected 32K block
Block Erase (64K bytes)
BE64
D8h
3
0
0
erase selected 64K block
CE
60h
0
0
0
erase whole chip
C7h
0
0
0
erase whole chip
Commands
Function description
Read
Program and Erase
Chip Erase
Page Program
PP
02h
3
0
1+
program selected page
Dual-IN Page Program
2PP
A2h
3
0
1+
program selected page by Dual input
Quad page program
QPP
32h
3
0
1+
quad input to program selected page
Program/Erase Suspend
PES
75h
0
0
0
suspend program/erase operation
B0h
0
0
0
suspend program/erase operation
7Ah
0
0
0
continue program/erase operation
30h
0
0
0
continue program/erase operation
Program/Erase Resume
PER
Protection
Write Enable
WREN
06h
0
0
0
sets the write enable latch bit
Write Disable
WRDI
04h
0
0
0
resets the write enable latch bit
VWREN
50h
0
0
0
Write enable for volatile status
register
Erase Security Registers
ERSCUR
44h
3
0
0
Erase security registers
Program Security Registers
PRSCUR
42h
3
0
1+
Program security registers
Read Security Registers
RDSCUR
48h
3
1
1+
Read value of security register
RDSR
05h
0
0
1
read out status register
RDSR2
35h
0
0
1
Read out status register-1
Read Configure Register
RDCR
15h
0
0
1
Read out configure register
Active Status Interrupt
ASI
25h
0
1
0
Enable the active status interrupt
Write Status Register
WRSR
01h
0
0
2
Write data to status registers
Write Configure Register
WRCR
31h
0
0
1
Write data to configuration register
Volatile SR Write Enable
Security
Status Register
Read Status Register
Puya Semiconductor
Page 21 of 71
P25Q80H Datasheet
Command set (Cont’d)
Abbr.
Code
ADR
Bytes
DMY
Bytes
Data
Bytes
RSTEN
66h
0
0
0
Enable reset
Reset
RST
99h
0
0
0
Reset
Read Manufacturer/device ID
RDID
9Fh
0
0
1 to 3
output JEDEC ID: 1-byte manufacturer
ID & 2-byte device ID
Read Manufacture ID
REMS
90h
3
1+
Read manufacturer ID/device ID data
Dual Read Manufacture ID
DREMS
92h
3
1
1+
Quad Read Manufacture ID
QREMS
94h
3
1
1+
DP
B9h
0
0
0
enters deep power-down mode
RDP/RES
ABh
3
0
1
Read electronic ID data
SBL
77h
0
0
0
Set burst length
RDSFDP
5Ah
Read SFDP parameter
FFh
Release from read enhanced
Commands
Function
Other Commands
Reset Enable
Deep Power-down
Release Deep
Power-down/Read Electronic
ID
Set burst length
Read SFDP
Release read enhanced
Read unique ID
RUID
4Bh
4
1+
Dual output read manufacture/device
ID
Quad output read manufacture/device
ID
Read unique ID
NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
Puya Semiconductor
Page 22 of 71
P25Q80H Datasheet
IO3 = (x, x, x, x, D7, D3,…)
6. Security Registers Address:
Security Register1: A23-A16=00H, A15-A9=0001000, A8-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A9=0010000, A8-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A9=0011000, A8-A0= Byte Address;
Puya Semiconductor
Page 23 of 71
P25Q80H Datasheet
10.2 Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like
PP,DPP,QPP, PE,SE, BE32K,BE, CE, and WRSR,ERSCUR, PRSCUR which are intended to change the
device content, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes
high.
Figure 10-2 Write Enable (WREN) Sequence (Command 06)
CS#
SCLK
0
1
2
3
4
5
6
7
Command
SI
06H
High-Z
SO
10.3 Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes
high.
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Dual Input Page Program (DPP) instruction completion
- Quod Page Program (QPP) instruction completion
- Page Erase (PE) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE32K,BE) instruction completion
- Chip Erase (CE) instruction completion
- Erase Security Register (ERSCUR) instruction completion
- Program Security Register (PRSCUR) instruction completion
- Reset (RST) instruction completion
Figure 10-3 Write Disable (WRDI) Sequence (Command 04)
CS#
SCLK
SI
SO
Puya Semiconductor
0
1
2
3
4
5
6
7
Command
04H
High-Z
Page 24 of 71
P25Q80H Datasheet
10.4 Write Enable for Volatile Status Register
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to
change the system configuration and memory protection schemes quickly without waiting for the typical
non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write
Enable for Volatile Status Register command must be issued prior to a Write Status Register command. The
Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for
the Write Status Register command to change the volatile Status Register bit values.
The sequence of issuing Write Enable for Volatile Status Register instruction is: CS# goes low→ sending
Write Enable for Volatile Status Register instruction code→ CS# goes high.
Figure 10-4 Write Enable for Volatile Status Register Sequence (Command 50)
CS#
0
1
2
3
4
5
6
7
SCLK
Command(50H )
SI
SO
High-Z
10.5 Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time
(even in program/erase/write status register condition). It is recommended to check the Write in Progress
(WIP) bit before sending a new instruction when a program, erase, or write status register operation is in
progress. For command code “05H”, the SO will output Status Register bits S7~S0. The command code
“35H”, the SO will output Status Register bits S15~S8
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status
Register data out on SO.
The SIO[3:1] are "don't care".
Figure 10-5 Read Status Register (RDSR) Sequence (Command 05 or 35)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI
05Hor35H
SO
High-Z
S7~S0 or S15~S8 out
7 6
MSB
Puya Semiconductor
5
4
3
2
1
S7~S0 or S15~S8 out
0
7 6
MSB
5
4
3
2
1
0
7
Page 25 of 71
P25Q80H Datasheet
Status Register
S15
SUS1
S14
CMP
S13
LB3
S12
LB2
S11
LB1
S10
SUS2
S9
QE
S8
SRP1
S7
SRP0
S6
BP4
S5
BP3
S4
BP2
S3
BP1
S2
BP0
S1
WEL
S0
WIP
The definition of the status register bits is as below:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress,
when WIP bit sets 0, means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status
Register, Program or Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase commands. These bits are written with the Write Status
Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant
memory area (as defined in Table “Protected Area Sizes”).becomes protected against Page Program (PP),
Page Erase (PE), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2,
BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip
Erase (CE) command is executed, only if the Block Protect (BP4, BP3, BP2, BP1and BP0) are set to “None
protected”.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The
SRP bits control the method of write protection: software protection, hardware protection, power supply
lock-down or one time programmable protection
SRP1
SRP0
WP#
Status Register
0
0
x
Software Protected
0
1
0
0
1
1
1
0
x
1
1
x
Hardware Protected
Hardware Unprotected
Description
The Status Register can be written to after a Write
Enable command, WEL=1.(Default)
WP#=0, the Status Register locked and can not be
written to.
WP#=1, the Status Register is unlocked and can be
written to after a Write Enable command, WEL=1.
Power Supply
Status Register is protected and can not be written to
Lock-Down(1)
again until the next Power-Down, Power-Up cycle.
One Time Program(2)
Status Register is permanently protected and can not be
written to.
NOTE:
1. When SRP1, SRP0=(1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact PUYA for details.
Puya Semiconductor
Page 26 of 71
P25Q80H Datasheet
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation.
When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the
Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI
operation if the WP# or HOLD# pins are tied directly to the power supply or ground)
LB3, LB2, LB1, bits.
The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that
provide the write protect control and status to the Security Registers. The default state of LB3-LB1are0, the
security registers are unlocked. The LB3-LB1bitscan be set to 1 individually using the Write Register instruction.
The LB3-LB1bits are One Time Programmable, once its set to 1, the Security Registers will become read-only
permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register(S14). It is used in conjunction the BP4-BP0
bits to provide more flexibility for the array protection. Please see the table “Protected Area Size” for details.
The default setting is CMP=0.
SUS1, SUS2bit
The SUS1 and SUS2bit are read only bit in the status register (S15and S10) that are set to 1 after executing an
Program/Erase Suspend (75H or B0H) command (The Erase Suspend will set the SUS1 to 1,and the Program
Suspend will set the SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Program/Erase Resume (7AH or
30H) command as well as a power-down, power-up cycle.
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Page 27 of 71
P25Q80H Datasheet
10.6 Read Configure Register (RDCR)
The RDCR instruction is for reading Configure Register Bits. The Read Configure Register can be read at
any time (even in program/erase/write status register condition). It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write status register
operation is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configure
Register data out on SO.
The SIO[3:1] are "don't care".
Figure 10-6 Read Status Register (RDCR) Sequence (Command 15)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI
15H
High-Z
SO
Configure Register Out
7 6
MSB
5
4
3
2
1
Configure Register Out
0
7 6
MSB
5
4
3
2
1
0
7
Configure Register
Bit7
DP
Bit6
Reserved
Bit5
Reserved
Bit4
Reserved
Bit3
Reserved
Bit2
Reserved
Bit1
Reserved
Bit0
Reserved
DP bit.
The Dual Page (DP) bit is a non-volatile Read/Write bit in the Configure Register that allows Dual Page
operation. When the DP bit is set to 0 (Default) the page size is 256bytes. When the DP pin is set to 1, the page
size is 512bytes.
This bit controls the page programming buffer address wrap point. Legacy SPI devices generally have used a
256 Byte page programming buffer and defined that if data is loaded into the buffer beyond the 255 Byte
location, the address at which additional bytes are loaded would be wrapped to address zero of the buffer. The
P25Q80H provides a 512 Byte page programming buffer that can increase programming performance. For
legacy software compatibility, this configuration bit provides the option to continue the wrapping behavior at the
256 Byte boundary or to enable full use of the available 512 Byte buffer by not wrapping the load address at the
256 Byte boundary.
When the DP pin is set to 1, the page erase instruction (81h) will erase the data of the chosen Dual Page to be
"1".
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Page 28 of 71
P25Q80H Datasheet
10.7 Active Status Interrupt (ASI)
To simplify the readout of the WIP bit, the Active Status Interrupt command (25h) may be used. It is then not
necessary to continuously read the status register, it is sufficient to monitor the value of the SO line. If the SO
line is connected to an interrupt line on the host controller, the host controller may be in sleep mode until the
SO line indicates that the device is ready for the next command.
The WIP bit can be read at any time, including during an internally self-timed program or erase operation.
To enable the Active Status Interrupt command, the CS pin must first be asserted and the opcode of 25h
must be clocked into the device. For SPI Mode3, at least one dummy bit has to be clocked into the device
after the last bit of the opcode has been clocked in. (In most cases, this is most easily done by sending a
dummy byte to the device.) The value of the SI line after the opcode is clocked in is of no significance to the
operation. For SPI Mode 0, this dummy bit (dummy byte) is not required.
The value of WIP is then output on the SO line, and is continuously updated by the device for as long as the
CS pin remains asserted. Additional clocks on the SCK pin are not required. If the WIP bit changes from 1 to
0 while the CS pin is asserted, the SO line will change from 1 to 0. (The WIP bit cannot change from 0 to 1
during an operation, so if the SO line already is 0, it will not change.)
Deasserting the CS pin will terminate the Active Status Interrupt operation and put the SO pin into a
high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data
be read.
The sequence of issuing ASI instruction is: CS# goes low→ sending ASI instruction code→ WIP data out on
SO
Figure 10-7 Active Status Interrupt (ASI) Sequence (Command 25)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
SCLK
Command
SI
SO
25H
High - Z
RDY/BSY
High - Z
10.8 Write Status Register (WRSR)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it
can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write
Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register.
CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write
Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the
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P25Q80H Datasheet
CMP and QE and SRP1 bits will be cleared to 0. As soon as CS# is driven high, the self-timed Write Status
Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the
Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,
BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register
Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect
(SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is
entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status
Register data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected
and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#)
goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in
progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and
the Write Enable Latch (WEL) bit is reset.
Figure 10-8 Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20
21 22 23
SCLK
Command
SI
01H
Status Register in
7
MSB
SO
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
High-Z
10.9 Write Configure Register (WRCR)
The Write Configure Register (WRCR) command allows new values to be written to the Configure Register.
Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the
Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch
(WEL).
The sequence of issuing WRCR instruction is: CS# goes low→ sending WRCR instruction code→ Configure
Register data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits data boundary; otherwise, the instruction will be rejected and not
executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes
high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in progress.
The WIP sets 1 during the tW timing, and sets 0 when Write Configure Register Cycle is completed, and the
Write Enable Latch (WEL) bit is reset.
Puya Semiconductor
Page 30 of 71
P25Q80H Datasheet
Figure 10-9 Write Configure Register (WRCR) Sequence (Command 31)
CS#
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
SCLK
Command
SI
Configure Register in
31H
7
6
5
4
MSB
3
2
1
0
High - Z
SO
10.10 Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts
out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location.
The address is automatically increased to the next higher address after each byte data is shifted out, so the
whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the
highest address has been reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte
address on SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out.
Figure 10-10 Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
SO
03H
High - Z
24 - bit address
23
22 21
3
2
1
0
Data Out1
MSB
MSB
Puya Semiconductor
7
6
5
4
3
2
Data Out2
1
0
Page 31 of 71
P25Q80H Datasheet
10.11 Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK,
and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte
can be at any location. The address is automatically increased to the next higher address after each byte
data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address
counter rolls over to 0 when the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ
instruction code→3-byte address on SI→ 1-dummy byte address on SI→data out on SO→ to end
FAST_READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without
any impact on the Program/Erase/Write Status Register current cycle.
Figure 10-11 Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
0BH
23 22 21
3
2
1
0
High - Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
DummyByte
SI
7
6
5
4
3
2
1
0
Data Out1
SO
Puya Semiconductor
7 6
MSB
5
4
3
Data Out2
2
1
0
7 6
MSB
5
Page 32 of 71
P25Q80H Datasheet
10.12 Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched
on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of
SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically
increased to the next higher address after each byte data is shifted out, so the whole memory can be read out
at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached.
Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte
address on SI → 8-bit dummy cycle → data out interleave on SIO1 & SIO0 → to end DREAD operation can
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 10-12 Dual Read Mode Sequence (Command 3B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24- bit address
3BH
23
22 21
3
2
1
0
High - Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI
SO
Puya Semiconductor
6
0
6
Data Out1
Data Out2
7 5 3 1 7 5 3 1
MSB
MSB
4
2
0
6
4
2
7
Page 33 of 71
P25Q80H Datasheet
10.13 2 X IO Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial NOR Flash in read mode. The address is
latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge
of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is
automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has
been reached.
Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous
1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address
interleave on SIO1 & SIO0→ 8-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to
end 2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 10-13 2 X IO Read Mode Sequence (Command BB M5-4 ≠ (1,0))
CS#
0
1
2
3
4
5
6
7
8
9
6
10 11 12 13 14 15 16 17 18 19
20 21 22 23
4
2
0
6
5
3
1
7
SCLK
Command
SI(IO0)
BBH
SO(IO1)
7
A23-16
4
2
0
6
5
3
1
7
A15-8
4
2
0
6
5
3
1
7
A7-0
4
2
0
5
3
1
M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
Puya Semiconductor
Byte2
Byte3
Byte4
Page 34 of 71
P25Q80H Datasheet
10.14 2 X IO Read Performer Enhance Mode
“BBh” command supports 2 X IO Performance Enhance Mode which can further reduce command overhead
through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the
“Continuous Read Mode” bits (M5-4) = (1, 0), then the next 2 X IO Read command (after CS# is raised and
then lowered) does not require the BBH command code.
If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first BBH
command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used
to reset (M5-4) before issuing normal command.
Figure 10-14 2 X IO Read Performance Enhance Mode ( M5-4 = (1,0) )
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0)
BBH
6
SO(IO1)
7
4
2
0
6
5
3
1
7
A23-16
4
2
0
6
5
3
1
7
A15-8
4
2
0
6
5
3
1
7
4
2
0
5
3
1
M7-0
A7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
Byte2
Byte3
Byte4
CS#
0
1
2
3
4
5
6
7
8
SI(IO0)
6
4
2
0
6
4
2
0
6
SO(IO1)
7
5
3
1
7
5
3
1
7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
A23-16
A15-8
4
2
0
6
5
3
1
7
A7-0
4
2
0
6
4
2
0
6
4
2
0
6
5
3
1
7
5
3
1
7
5
3
1
7
M7-0
Byte1
Byte2
Note: 2 X IO Read Performance Enhance Mode, if M5-4 = 1, 0. If not using performance enhance
recommend to set M5-4 ≠ 1, 0.
Puya Semiconductor
Page 35 of 71
P25Q80H Datasheet
10.15 Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation
can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 10-15 Quad Read Mode Sequence (Command 6B)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
SI(IO0)
24-Bit address
6BH
23
SO(IO1)
High-Z
WP#(IO2)
High-Z
HOLD#(IO3)
High-Z
22 21
3
2
1
0
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI(IO0)
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
HOLD#(IO3)
Byte1
Puya Semiconductor
Byte2
Byte3
Byte4
Page 36 of 71
P25Q80H Datasheet
10.16 4 X IO Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address
interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0
→ to end 4READ operation can use CS# to high at any time during data out.
Another sequence of issuing 4READ instruction especially useful in random access is: CS# goes low→sending
4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 → “Continuous Read Mode”
byte M[7:0]→ 4 dummy cycles →data out still CS# goes high → CS# goes low (reduce 4 Read instruction)
→24-bit random access address.
In the performance-enhancing mode, the “Continuous Read Mode” bits M[5:4] = (1,0) can make this mode
continue and reduce the next 4READ instruction. Once M[5:4 ] ≠ (1,0) and afterwards CS# is raised and then
lowered, the system then will escape from performance enhance mode and return to normal operation. A
“Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 10-16 4 X IO Read Mode Sequence (Command EB M5-4 ≠ (1,0))
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21 22 23
SCLK
Command
SI(IO0)
EBH
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
A23-16 A15-8 A7-0
M7-0
Dummy
Byte1
Byte2
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. M[5-4] = (1,0) is inhibited.
Puya Semiconductor
Page 37 of 71
P25Q80H Datasheet
10.17 4 X IO Read Performance Enhance Mode
“EBh” command supports 4 X IO Performance Enhance Mode which can further reduce command overhead
through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the
“Continuous Read Mode” bits (M5-4) = (1, 0), then the next 4 X IO Read command (after CS# is raised and
then lowered) does not require the EBH command code.
If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first EBH
command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used
to reset (M5-4) before issuing normal command.
Figure 10-17 4 x I/O Read Performance Enhance Mode Sequence ( M5-4 = (1,0) )
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21 22 23
SCLK
Command
SI(IO0)
EBH
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
A23-16 A15-8 A7-0
M7-0
Dummy
Byte1 Byte2
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
A23-16 A15-8 A7-0
M7-0
Dummy
Byte1
Byte2
Note: 1. 4 X IO Read Performance Enhance Mode, if M5-4 = 1, 0. If not using performance enhance
recommend to set M5-4 ≠ 1, 0.
Puya Semiconductor
Page 38 of 71
P25Q80H Datasheet
10.18 Burst Read
The Set Burst with Wrap command is used in conjunction with “4 X IO Read” command to access a fixed length
of 8/16/32/64-byte section within a 256-byte page, in standard SPI mode.
The Set Burst with Wrap command sequence: CS# goes low → Send Set Burst with Wrap command → Send
24 dummy bits→ Send 8 bits “Wrap bits” → CS# goes high.
W6,W5
0,0
0,1
1,0
1,1
W4=0
Wrap Aroud
Yes
Yes
Yes
Yes
W4=1 (default)
Wrap Length
8-byte
16-byte
32-byte
64-byte
Wrap Aroud
No
No
No
No
Wrap Length
N/A
N/A
N/A
N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “4 X IO Read” command will
use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around”
function and return to normal read operation, another Set Burst with Wrap command should be issued to set
W4=1.
Figure 10-18 Burst Read (SBL) Sequence (Command 77)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCLK
Command
SI(IO0)
77H
X
X
X
X
X
X
4
X
SO(IO1)
X
X
X
X
X
X
5
X
WP#(IO2)
X
X
X
X
X
X
6
X
HOLD#(IO3)
X
X
X
X
X
X
X
X
W6-W4
Puya Semiconductor
Page 39 of 71
P25Q80H Datasheet
10.19 Page Erase (PE)
The Page Erase (PE) instruction is for erasing the data of the chosen Page to be "1". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Erase (PE).
To perform a Page Erase with the standard page size (256 bytes), an opcode of 81h must be clocked into the device
followed by three address bytes comprised of 2 page address bytes that specify the page in the main memory to be
erased, and 1 dummy byte.
The sequence of issuing PE instruction is: CS# goes low → sending PE instruction code→ 3-byte address on
SI → CS# goes high.
Figure 10-19 Page Erase Sequence (Command 81)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24-bit address
81H
23 22
MSB
2
1
0
10.20 Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any
address of the sector is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the
byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and
not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on
SI → CS# goes high.
The SIO[3:1] are don't care.
Figure 10-20 Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
20H
24-bit address
23 22
MSB
2
1
0
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The
Write in progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets
1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL)
bit is reset. If the sector is protected by BP4, BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will
not be executed on the sector.
Puya Semiconductor
Page 40 of 71
P25Q80H Datasheet
10.21 Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is
used for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write
Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block is a valid address
for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant
bit of address byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte
address on SI → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the
tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the block is protected by BP4, BP3, BP2, BP1,BP0 bits, the array data will be protected (no change)
and the WEL bit still be reset.
Figure 10-21 Block Erase 32K(BE32K)
Sequence (Command 52 )
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
52H
24-bit address
23 22
MSB
2
1
0
10.22 Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE). Any address of the block is a valid address for Block
Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte
been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on
SI→CS# goes high.
The SIO[3:1] are "don't care".
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the block is protected by BP4, BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed
on the block.
Puya Semiconductor
Page 41 of 71
P25Q80H Datasheet
Figure 10-22 Block Erase (BE)
Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24-bit address
D8H
23 22
MSB
2
1
0
10.23 Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The
CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high.
The SIO[3:1] are "don't care".
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets 1 during the
tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the chip is protected by BP4,BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It
will be only executed when all Block Protect(BP4, BP3, BP2, BP1, BP0) are set to “None protected”.
Figure 10-23 Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
Puya Semiconductor
60H or C7H
Page 42 of 71
P25Q80H Datasheet
10.24 Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP).
The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going
to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least
significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page
are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than
256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and
previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at
the requested address of the page without effect on other address of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on
SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1 during
the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is
reset. If the page is protected by BP4, BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be
executed.
The SIO[3:1] are "don't care".
Figure 10-24 Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
24- bit address
02H
23 22 21
3
Data Byte 1
2
1 0 7
MSB
6
5
4
3
2
1
0
MSB
2079
2077
2078
2076
2075
2073
2074
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
1
0
SCLK
Data Byte 2
SI
7
6
MSB
Puya Semiconductor
5
4
3
2
Data Byte 3
1
0 7
MSB
6
5
4
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
Page 43 of 71
P25Q80H Datasheet
10.25 Dual Input Page Program (DPP)
The Dual Input Page Program (DPP) instruction is similar to the standard Page Program command and can be
used to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory
locations. The Dual-Input Page Program command allows two bits of data to be clocked into the device on
every clock cycle rather than just one.
A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the
Dual Input Page Program (DPP). The Dual Input Page Programming takes two pins: SIO0, SIO1 as data input,
which can improve programmer performance and the effectiveness of application. The other function
descriptions are as same as standard page program.
The sequence of issuing DPP instruction is: CS# goes low→ sending DPP instruction code→ 3-byte address
on SI→at least 1-byte on data on SIO[1:0]→ CS# goes high.
Figure 10-25 Page Program (DPP) Sequence (Command A2)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32
33 34 35 36 37 38 39
SCLK
Command
SI(IO0)
24- bitaddress
A2H
23 22 21
Byte1
3
2
1
0
Byte2
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
MSB
SO(IO1)
Byte5
SI(IO0)
SO(IO1)
Byte6
Byte255
1055
1054
1053
1052
1051
1050
48 49 50 51 52 53 54 55
1049
40 41 42 43 44 45 46 47
SCLK
1048
CS#
Byte256
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Puya Semiconductor
Page 44 of 71
P25Q80H Datasheet
10.26 Quad Page Program (QPP)
The Quad Page Program (QPP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1"
before sending the Quad Page Program (QPP). The Quad Page Programming takes four pins: SIO0, SIO1,
SIO2, and SIO3 as data input, which can improve programmer performance and the effectiveness of
application. The QPP operation frequency supports as fast as fQPP. The other function descriptions are as
same as standard page program.
The sequence of issuing QPP instruction is: CS# goes low→ sending QPP instruction code→ 3-byte address
on SIO0 → at least 1-byte on data on SIO[3:0]→CS# goes high.
Figure 10-26 Quad Page Program (QPP) Sequence (Command 32)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI(IO0)
24- bit address
32H
23 22 21
Byte1 Byte2
3
2
1
0
4
0
4
0
4
0
4
0
SO(IO1)
5
1
5
1
5
1
5
1
WP#(IO2)
6
2
6
2
6
2
6
2
HOLD#(IO3)
7
3
7
3
7
3
7
3
MSB
543
542
541
540
539
538
537
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
536
CS#
SCLK
Byte11 Byte12
Byte253
Byte256
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Puya Semiconductor
Page 45 of 71
P25Q80H Datasheet
10.27 Erase Security Registers (ERSCUR)
The product provides three512-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information
separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low → sending ERSCUR instruction
→ sending 24 bit address → CS# goes high.
CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Erase
Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security
Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the
Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP)
bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. The Security
Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the
LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will
be ignored.
Address
A23-16
A15-12
A11-9
A8-0
Security Register #1
00H
0001
000
Don’t care
Security Register #2
00H
0010
000
Don’t care
Security Register #3
00H
0011
000
Don’t care
Figure 10-27 Erase Security Registers (ERSCUR) Sequence (Command 44)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
Puya Semiconductor
44H
24 bit address
23 22
MSB
2
1
0
Page 46 of 71
P25Q80H Datasheet
10.28 Program Security Registers (PRSCUR)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to
256/512 bytes Security Registers data to be programmed depend on DP bit set to “0 or 1”. A Write Enable
(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before
sending the Program Security Registers command.
The Program Security Registers command sequence: CS# goes low → sending PRSCUR instruction
→ sending 24 bit address → sending at least one byte data → CS# goes high.
As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is
initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program
Security Registers cycle, and is 0 when it is completed.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.
Address
A23-16
A15-12
A11-9
A8-0
Security Register #1
00H
0001
000
Byte Address
Security Register #2
00H
0010
000
Byte Address
Security Register #3
00H
0011
000
Byte Address
Figure 10-28 Program Security Registers (PRSCUR) Sequence (Command 42)
CS#
0
1
2
3
4
5
6
7
8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
42H
24- bit address
23 22 21
3
Data Byte 1
2
1 0 7
MSB
6
5
4
3
2
1
0
MSB
2079
2077
2078
2076
2075
2073
2074
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
1
0
SCLK
Data Byte 2
SI
7
6
MSB
Puya Semiconductor
5
4
3
2
Data Byte 3
1
0 7 6
MSB
5
4
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
Page 47 of 71
P25Q80H Datasheet
10.29 Read Security Registers (RDSCUR)
The Read Security Registers command is similar to Fast Read command. The command is followed by a
3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the
memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during
the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. Once the A8-A0 address reaches
the last byte of the register (Byte 1FFH), it will reset to 000H, the command is completed by driving CS# high.
The sequence of issuing RDSCUR instruction is : CS# goes low → sending RDSCUR instruction → sending 24
bit address → 8 bit dummy byte → Security Register data out on SO → CS# goes high.
Address
A23-16
A15-12
A11-9
A8-0
Security Register #1
00H
0001
000
Byte Address
Security Register #2
00H
0010
000
Byte Address
Security Register #3
00H
0011
000
Byte Address
Figure 10-29 Read Security Registers (RDSCUR) Sequence (Command 48)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24- bitaddress
23 22 21
48H
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
DummyByte
SI
7
6
5
4
3
2
1
0
Data Out1
SO
Puya Semiconductor
7 6
MSB
5
4
3
Data Out2
2
1
0
7 6
MSB
5
Page 48 of 71
P25Q80H Datasheet
10.30 Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to
entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep
Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down
mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's
only in standby mode not deep power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down
mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read
out). When Power- down, the deep power-down mode automatically stops, and when power-up, the device
automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary
(the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not be executed. As
soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode
and reducing the current to ISB2.
Figure 10-30 Deep Power-down (DP) Sequence (Command B9)
CS#
SCLK
SI
0
1
2
3
4
5
Command
6
7
tDP
Standby mode
Deep power-down mode
B9H
10.31 Release form Deep Power-Down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High.
When Chip Select (CS#) is driven high, the device is put in the Stand-by Power mode. If the device was not
previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the
device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode
is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max). Once in the
Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as
table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new
design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES
are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's
no effect on the current program/erase/ write cycle in progress.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs
repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not
previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device
was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must
remain to high at least tRES2 (max). Once in the standby mode, the device waits to be selected, so it can be
Puya Semiconductor
Page 49 of 71
P25Q80H Datasheet
receive, decode, and execute instruction.
The RDP instruction is for releasing from Deep Power-Down Mode.
Figure 10-31 Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
SO
tRES2
3 Dummy Bytes
23 22
ABH
2
1
0
MSB
High-Z
Electronic Signature Out
7
6
MSB
5
4
3
2
1
0
Deep Power-down mode
Standby Mode
Figure 10-32 Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
tRES1
SCLK
Command
SI
ABH
Deep Power- down mode
Puya Semiconductor
Stand-by mode
Page 50 of 71
P25Q80H Datasheet
10.32 Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID
values are listed in "Table ID Definitions".
The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by
two dummy bytes and one address byte (A7~A0). After which the manufacturer ID for PUYA (85h) and the
device ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte
is 00h, the manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the
device ID will be output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device
IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS#
high.
Figure 10-33 Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
2 dummy byte and
1 address byte
23 22 21
3 2
Command
SI
90H
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Device ID
Manufacturer ID
SO
7
MSB
Puya Semiconductor
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
Page 51 of 71
P25Q80H Datasheet
10.33 Dual I/O Read Electronic Manufacturer ID & Device ID (DREMS)
The DREMS instruction is similar to the REMS command and returns the JEDEC assigned manufacturer ID
which takes two pins: SIO0, SIO1 as address input and ID output I/O
The instruction is initiated by driving the CS# pin low and shift the instruction code "92h" followed by two
dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for PUYA (85h) and the
Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first. If the one-byte
address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID.
The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The
instruction is completed by driving CS# high.
Figure 10-34 DUAL I/O Read Electronic Manufacturer & Device ID (DREMS) Sequence (Command 92)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21 22 23
SCLK
Command
SI(IO0)
92H
SO(IO1)
6
4
2
0
6
4
2
0
6
7
5
3
1
7
5
3
1
7
Dummy byte
4
2
0
6
5
3
1
7
ADD byte
Dummy byte
4
2
0
5
3
1
M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI(IO0)
6
SO(IO1)
7
4
2
0
6
5
3
1
7
MFRID
Puya Semiconductor
4
2
0
6
5
3
1
7
DeviceID
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
MFRID
(Repeat)
DeviceID
(Repeat)
MFRID
(Repeat)
DeviceID
(Repeat)
Page 52 of 71
P25Q80H Datasheet
10.34 Quad I/O Read Electronic Manufacturer ID & Device ID (QREMS)
The QREMS instruction is similar to the REMS command and returns the JEDEC assigned manufacturer ID
which takes four pins: SIO0, SIO1,SIO2,SIO3 as address input and ID output I/O
The instruction is initiated by driving the CS# pin low and shift the instruction code "94h" followed by two
dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for PUYA (85h) and the
Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first. If the one-byte
address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID.
The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The
instruction is completed by driving CS# high.
Figure 10-35 QUAD I/O Read Electronic Manufacturer & Device ID (QREMS) Sequence (Command 94)
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
SI(IO0)
94H
4
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
A23-16 A15-8 A7-0 M7-0
Dummy
MFRID DID
CS#
24 25 26 27 28 29 30 31
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
SO(IO1)
5
1
5
1
5
1
5
1
WP#(IO2)
6
2
6
2
6
2
6
2
HOLD#(IO3) 7
3
7
3
7
3
7
3
MFRID DID MFRID DID
Repeat Repeat Repeat Repeat
Puya Semiconductor
Page 53 of 71
P25Q80H Datasheet
10.35 Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The
PUYA Manufacturer ID and Device ID are list as “as "Table . ID Definitionsi”.
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID
data out on SO→ to end RDID operation can use CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at
standby stage.
Figure 10-36 Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15
SCLK
SI
9FH
SO
7
6
Manufacturer ID
5 4 3 2 1
0
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
SO
7
Memory Type ID
6 5 4 3 2 1
MSB
0
7
6
Capacity ID
5 4 3 2
1
0
MSB
Table ID Definitions
P25Q80H
Puya Semiconductor
RDID
manufacturer ID
command
85
memory type
60
RES
electronic ID
command
13
memory density
14
REMS
manufacturer ID
device ID
command
85
13
Page 54 of 71
P25Q80H Datasheet
10.36 Program/Erase Suspend/Resume
The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access
to the memory array. After the program or erase operation has entered the suspended state, the memory
array can be read except for the page being programmed or the sector or block being erased.
Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended Operation
Readable Region of Memory Array
Page Program
All but the Page being programmed
Page Erase
All but the Page being erased
Sector Erase(4KB)
All but the 4KB Sector being erased
Block Erase(32KB)
All but the 32KB Block being erased
Block Erase(64KB)
All but the 64KB Block being erased
When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL before the
Write Enable Latch (WEL) bit clears to “0” and the SUS2 or SUS1 sets to “1”, after which the device is ready
to accept one of the commands listed in "Table Acceptable Commands During Program/Erase Suspend after
tPSL/tESL" (e.g. FAST READ). Refer to " AC Characteristics" for tPSL and tESL timings. "Table Acceptable
Commands During Suspend (tPSL/tESL not required)" lists the commands for which the tPSL and tESL
latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at any time after the
Suspend instruction.
Status Register bit 15 (SUS2) and bit 10 (SUS1) can be read to check the suspend status. The SUS2
(Program Suspend Bit) sets to “1” when a program operation is suspended. The SUS1 (Erase Suspend Bit)
sets to “1” when an erase operation is suspended. The SUS2 or SUS1 clears to “0” when the program or
erase operation is resumed.
Acceptable Commands During Program/Erase Suspend after tPSL/tESL
Command name
Command Code
Suspend Type
Program Suspend
Erase Suspend
READ
03H
•
•
FAST READ
0BH
•
•
DREAD
3BH
•
•
QREAD
6BH
•
•
2READ
BBH
•
•
4READ
EBH
•
•
RDSFDP
5AH
•
•
RDID
9FH
•
•
REMS
90H
•
•
DREMS
92H
•
•
QREMS
94H
•
•
RDSCUR
48H
•
•
SBL
77H
•
•
WREN
06H
•
RESUME
7AH OR 30H
•
•
PP
02H
•
DPP
A2H
•
QPP
32H
•
Puya Semiconductor
Page 55 of 71
P25Q80H Datasheet
Acceptable Commands During Suspend（tPSL/tESL not required）
Command name
Command Code
Suspend Type
Program Suspend
Erase Suspend
WRDI
04H
•
•
RDSR
05H
•
•
RDSR2
35H
•
•
ASI
25H
•
•
RES
ABH
•
•
RSTEN
66H
•
•
RST
99H
•
•
NOP
00H
•
•
Figure 10-37 Resume to Suspend Latency
tPRS / tERS
CS#
Resume Command
Suspend Command
tPRS: Program Resume to another Suspend
tERS: Erase Resume to another Suspend
10.37 Erase Suspend to Program
The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended.
Page Programming is permitted in any unprotected memory except within the sector of a suspended Sector
Erase operation or within the block of a suspended Block Erase operation. The Write Enable (WREN)
instruction must be issued before any Page Program instruction.
A Page Program operation initiated within a suspended erase cannot itself be suspended and must be
allowed to finish before the suspended erase can be resumed. The Status Register can be polled to
determine the status of the Page Program operation. The WEL and WIP bits of the Status Register will
remain “1” while the Page Program operation is in progress and will both clear to “0” when the Page Program
operation completes.
Figure 10-38 Suspend to Read/Program Latency
tPSL / tESL
CS#
Suspend Command
Read/Program command
tPSL: Program latency
tESL: Erase latency
Notes:
1. Please note that Program only available after the Erase-Suspend operation
2. To check suspend ready information, please read status register bit15 (SUS2) and bit10(SUS1)
Puya Semiconductor
Page 56 of 71
P25Q80H Datasheet
10.38 Program Resume and Erase Resume
The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation.
Before issuing the Resume instruction to restart a suspended erase operation, make sure that there is no
Page Program operation in progress.
Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to “1”
and the SUS2 or SUS1 is cleared to “0”. The program or erase operation will continue until finished
("Resume to Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency
of tPRS or tERS must be observed before issuing another Suspend instruction ("Resume to Suspend
Latency").
Figure 10-39 Resume to Read Latency
tSE /tBE / tPP
CS#
Resume Command
Read Command
10.39 No Operation (NOP)
The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not
affect any other command.
The SIO[3:1] are don't care.
Puya Semiconductor
Page 57 of 71
P25Q80H Datasheet
10.40 Software Reset (RSTEN/RST)
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset
(RST) command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then,
which makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform
the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the
Reset-Enable will be invalid.
The SIO[3:1] are "don't care".
If the Reset command is executed during program or erase operation, the operation will be disabled, the data
under processing could be damaged or lost.
Figure 10-40 Software Reset Recovery
CS#
66H
99H
tReady
Mode
Stand-by Mode
Figure 10-41 Reset Sequence
CS#
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCLK
SI
SO
Puya Semiconductor
Command
Command
66H
99H
High -Z
Page 58 of 71
P25Q80H Datasheet
10.41 Read Unique ID (RUID)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each
P25Qxx device. The Unique ID can be used in conjunction with user software methods to help prevent
copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low → sending Read Unique ID command →Dummy
Byte1 →Dummy Byte2 →Dummy Byte3 → Dummy Byte4 → 128bit Unique ID Out → CS# goes high.
The command sequence is show below.
Figure 10-42
Read Unique ID (RUID) Sequence (Command 4B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
3 bytes dummy
4BH
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43
164 165 166
SCLK
DummyByte
SI
128 bit unique serial number
SO
Puya Semiconductor
127 126 125 124
MSB
3
2
1
0
Page 59 of 71
P25Q80H Datasheet
10.42 Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to
accommodate divergent features from multiple vendors. The concept is similar to the one found in the
Introduction of JEDEC Standard, JESD68 on CFI.
The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→ send RDSFDP
instruction (5Ah)→send 3 address bytes on SI pin→ send 1 dummy byte on SI pin→ read SFDP code on
SO→ to end RDSFDP operation can use CS# to high at any time during data out.
SFDP is a JEDEC Standard, JESD216B.
Figure 10-43 Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
5AH
23 22 21
3
2
1
0
High - Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
DummyByte
SI
7
6
5
4
3
2
1
0
Data Out1
SO
Puya Semiconductor
7 6
MSB
5
4
3
Data Out2
2
1
0
7 6
MSB
5
Page 60 of 71
P25Q80H Datasheet
Figure 10-44 Serial Flash Discoverable Parameter (SFDP) Table
Table Signature and Parameter Identification Data Values
Description
SFDP Signature
Comment
Fixed:50444653H
Add(H)
DW Add
Data
Data
(Byte)
(Bit)
00H
07:00
53H
53H
01H
15:08
46H
46H
02H
23:16
44H
44H
03H
31:24
50H
50H
SFDP Minor Revision Number
Start from 00H
04H
07:00
00H
00H
SFDP Major Revision Number
Start from 01H
05H
15:08
01H
01H
Number of Parameters Headers
Start from 00H
06H
23:16
01H
01H
07H
31:24
FFH
FFH
08H
07:00
00H
00H
Start from 0x00H
09H
15:08
00H
00H
Start from 0x01H
0AH
23:16
01H
01H
0BH
31:24
09H
09H
0CH
07:00
30H
30H
0DH
15:08
00H
00H
0EH
23:16
00H
00H
0FH
31:24
FFH
FFH
10H
07:00
85H
85H
Start from 0x00H
11H
15:08
00H
00H
Start from 0x01H
12H
23:16
01H
01H
13H
31:24
03H
03H
Unused
Contains 0xFFH and can never be
changed
ID number (JEDEC)
00H: It indicates a JEDEC specified
header
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
How many DWORDs in the
Parameter table
First address of JEDEC Flash
Parameter table
Unused
Contains 0xFFH and can never be
changed
ID Number
It is indicates PUYA
(PUYADevice Manufacturer ID)
manufacturer ID
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
How many DWORDs in the
(in double word)
Parameter table
Parameter Table Pointer (PTP)
First address of PUYA Flash
14H
07:00
60H
60H
Parameter table
15H
15:08
00H
00H
16H
23:16
00H
00H
17H
31:24
FFH
FFH
Unused
Contains 0xFFH and can never be
changed
Puya Semiconductor
Page 61 of 71
P25Q80H Datasheet
Table
Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Add(H)
(Byte)
DW Add
Data
Data
(Bit
)
00: Reserved; 01: 4KB erase;
Block/Sector Erase Size
10: Reserved;
01:00
01b
02
1b
03
0b
11: not support 4KB erase
Write Granularity
Write Enable Instruction
Requested for Writing to Volatile
Status Registers
0: 1Byte, 1: 64Byte or larger
0: Nonvolatile status bit
1: Volatile status bit
(BP status register bit)
30H
E5H
0: Use 50H Opcode,
Write Enable Opcode Select for
Writing to Volatile Status Registers
1: Use 06H Opcode,
Note: If target flash status register is
04
0b
07:05
111b
15:08
20H
16
1b
18:17
00b
19
0b
Nonvolatile, then bits3 and 4 must
be set to 00b.
Unused
Contains 111b and can never be
changed
4KB Erase Opcode
(1-1- 2) Fast Read
31H
0=Not support, 1=Support
Address Bytes Number used in
00: 3Byte only, 01: 3 or 4Byte,
addressing flash array
10: 4Byte only, 11: Reserved
Double Transfer Rate (DTR)
clocking
0=Not support, 1=Support
32H
F1H
(1-2- 2) Fast Read
0=Not support, 1=Support
20
1b
(1-4- 4) Fast Read
0=Not support, 1=Support
21
1b
(1-1- 4) Fast Read
0=Not support, 1=Support
22
1b
23
1b
33H
31:24
FFH
37H:34H
31:00
Unused
Unused
Flash Memory Density
(1-4- 4) Fast Read Number of Wait
states
0 0000b: Wait states (Dummy
04:00
Clocks) not support
Mode Bits
000b:Mode Bits not support
(1-4- 4) Fast Read Opcode
(1-1- 4) Fast Read Number of Wait
states
39H
0 0000b: Wait states (Dummy
Clocks) not support
00100b
44H
07:05
010b
15:08
EBH
20:16
01000b
3AH
(1-1- 4) Fast Read Number of
Mode Bits
(1-1- 4) Fast Read Opcode
Puya Semiconductor
000b:Mode Bits not support
3BH
FFH
007FFFFFH
38H
(1-4- 4) Fast Read Number of
20H
EBH
08H
23:21
000b
31:24
6BH
6BH
Page 62 of 71
P25Q80H Datasheet
Description
Comment
(1-1- 2) Fast Read Number of Wait
0 0000b: Wait states (Dummy
states
Clocks) not support
Add(H)
DW Add
(Byte)
(Bit)
04:00
Data
01000b
3CH
(1-1- 2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
(1-1- 2) Fast Read Opcode
(1-2- 2) Fast Read Number
of Wait states
3DH
0 0000b: Wait states (Dummy
Clocks) not support
08H
07:05
000b
15:08
3BH
20:16
00000b
3EH
(1-2- 2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
(1-2- 2) Fast Read Opcode
(2-2- 2) Fast Read
3FH
0=not support 1=support
Unused
0=not support 1=support
Unused
3BH
80H
23:21
100b
31:24
BBH
00
0b
03:01
111b
04
0b
07:05
111b
40H
(4-4- 4) Fast Read
Data
BBH
EEH
Unused
43H:41H
31:08
0xFFH
0xFFH
Unused
45H:44H
15:00
0xFFH
0xFFH
20:16
00000b
23:21
000b
47H
31:24
FFH
FFH
49H:48H
15:00
0xFFH
0xFFH
20:16
00000b
(2-2- 2) Fast Read Number
of Wait states
(2-2- 2) Fast Read Number
of Mode Bits
0 0000b: Wait states (Dummy
Clocks) not support
46H
000b: Mode Bits not support
(2-2- 2) Fast Read Opcode
Unused
(4-4- 4) Fast Read Number of Wait
0 0000b: Wait states (Dummy
states
Clocks) not support
(4-4- 4) Fast Read Number
of Mode Bits
Sector Type 1 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector Type 4 erase Opcode
Puya Semiconductor
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
00H
4AH
000b: Mode Bits not support
(4-4- 4) Fast Read Opcode
00H
23:21
000b
4BH
31:24
FFH
FFH
4CH
07:00
0CH
0CH
4DH
15:08
20H
20H
4EH
23:16
0FH
0FH
4FH
31:24
52H
52H
50H
07:00
10H
10H
51H
15:08
D8H
D8H
52H
23:16
08H
08H
53H
31:24
81H
81H
Page 63 of 71
P25Q80H Datasheet
Table Parameter Table (1): PUYA Flash Parameter Tables
Description
Comment
Add(H)
DW Add
(Byte)
(Bit)
61H:60H
63H:62H
Data
Data
15:00
3600H
3600H
31:16
2300H
2300H
2000H=2.000V
Vcc Supply Maximum Voltage
2700H=2.700V
3600H=3.600V
1650H=1.650V
Vcc Supply Minimum Voltage
2250H=2.250V
2350H=2.350V
2700H=2.700V
HW Reset# pin
0=not support 1=support
00
0b
HW Hold# pin
0=not support 1=support
01
1b
0=not support 1=support
02
1b
0=not support 1=support
03
1b
Deep Power Down Mode
SW Reset
SW Reset Opcode
Should be issue Reset Enable(66H)
before Reset cmd.
65H:64H
11:04
1001 1001b
(99H)
F99EH
Program Suspend/Resume
0=not support 1=support
12
1b
Erase Suspend/Resume
0=not support 1=support
13
1b
14
1b
15
1b
66H
23:16
77H
77H
67H
31:24
64H
64H
00
0b
01
0b
09:02
FFH
10
0b
Unused
Wrap Around Read mode
0=not support 1=support
Wrap - Around Read mode Opcode
08H:support 8B wrap
- around read
Wrap - Around Read data length
16H:8B&16B
32H:8B&16B&32B
64H:8B&16B&32B&64B
Individual block lock
Individual block lock bit
(Volatile/Nonvolatile)
0=not support 1=support
0=Volatile
1=Nonvolatile
Individual block lock Opcode
Individual blocklock Volatile
protect bit default protect status
0=protect 1=unprotect
CBFCH
6BH:68H
Secured OTP
0=not support 1=support
11
1b
Read Lock
0=not support 1=support
12
0b
Permanent Lock
0=not support
1=support
13
0b
Unused
15:14
11b
Unused
31:16
FFFFH
Puya Semiconductor
FFFFH
Page 64 of 71
P25Q80H Datasheet
11 Ordering Information
P 25 Q 80 H A –SS H– I T
Company Designator
P = Puya Semiconductor
Product Family
25 = SPI interface flash
Product Serial
Q = Q serial
Memory Density
80 = 8 M bit
Operation Voltage
H = 2.3 V ~ 3.6 V
Generation
A = A Version
Default = blank
Package Type
SS = SOP8 150mil
SU = SOP8 200mil
UX =USON8 3X2 mm
WX=WSON8 6X5 mm
TS = TSSOP8
WF = WAFER
Plating Technology
H : RoHS Compliant, Halogen-free, Antimony- free
Device Grade
I = - 40 ~ 85C
K = - 40 ~ 105C
Packing Type
T = TUBE
R = TAPE & REEL
W = WAFER
Puya Semiconductor
Page 65 of 71
P25Q80H Datasheet
12 Package Information
12.1 8-Lead SOP(150mil)
h x45°
A2
A
b
e
C
D
8
0.25mm
GAUGE PLANE
E1
E
A1
k
1
L
L1
Common Dimensions
(Unit of Measure=millimeters)
Symbol
A
Min
Typ
Max
-
-
1.750
A1
0.100
-
0.250
A2
1.250
-
-
b
0.280
-
0.480
c
0.170
-
0.230
D
4.800
4.900
5.000
E
5.800
6.000
6.200
E1
3.800
3.900
4.000
e
-
1.270
-
h
0.250
-
0.500
k
0°
-
8°
L
0.400
-
1.270
L1
-
1.040
-
Note：1. Dimensions are not to scale
TITLE
DRAWING NO.
REV
SP-8
A
8-lead SOP
Puya Semiconductor
Page 66 of 71
P25Q80H Datasheet
12.2 8-Lead SOP(200mil)
A2
A
b
e
C
D
8
0.25mm
GAUGE PLANE
E1
E
A1
k
1
L
Common Dimensions
(Unit of Measure=millimeters)
Symbol
Min
Typ
A
-
-
2.150
A1
0.050
-
0.250
A2
1.700
-
1.900
b
0.350
-
0.500
c
0.100
-
0.250
D
5.130
-
5.330
E
7.700
E1
5.180
e
-
Max
8.100
5.380
1.270
-
k
0°
-
8°
L
0.500
-
0.850
Note：1. Dimensions are not to scale
TITLE
DRAWING NO.
REV
SP-8
A
8-lead SOP(200mil)
Puya Semiconductor
Page 67 of 71
P25Q80H Datasheet
12.3 8-Lead TSSOP
D
8
5
C
E
E1
1
4
A
A1
A2
b
e
CP
α
L
L1
Common Dimensions
(Unit of Measure=millimeters)
Symbol
A
Min
Typ
Max
-
-
1.200
A1
0.050
-
0.150
A2
0.800
1.000
1.050
b
0.190
-
0.300
c
0.090
-
0.200
-
0.100
CP
D
e
2.900
-
3.000
0.650
3.100
-
E
6.200
6.400
6.600
E1
4.300
4.400
4.500
L
0.450
0.600
0.750
L1
-
α
0°
1.000
-
8°
Note：1. Dimensions are not to scale
TITLE
8-lead TSSOP
Puya Semiconductor
DRAWING NO.
REV
TS-8
A
Page 68 of 71
P25Q80H Datasheet
12.4 8-Land USON(3x2mm)
D
e
L1
L
b
h
E
E2
D2
h
L
Pin1
1
2
Nd
EXPOSED THERMAL
PAD ZONE
BOTTOM VIEW
A1
c
A
TOP VIEW
Common Dimensions
SIDE VIEW
(Unit of Measure=millimeters)
Symbol
Min
Typ
Max
A
0.500
0.550
0.600
A1
0.000
0.020
0.050
b
0.180
0.250
0.300
2.100
D
1.900
2.000
D2
1.500
1.600
1.700
E
2.900
3.000
3.100
E2
0.100
0.200
0.300
e
0.500BSC
L
0.300
0.350
0.400
h
0.050
0.100
0.150
Nd
1.500BSC
L1
0.050
0.100
0.150
c
0.100
0.150
0.200
Note：1. Dimensions are not to scale
TITLE
DRAWING NO.
REV
DN-8
A
DFN8L(0203X0.55-0.5)
Puya Semiconductor
Page 69 of 71
P25Q80H Datasheet
12.5 8-Land WSON(6x5mm)
D
e
L
b
h
Pin1
h
E
E2
D2
A
A1
c
Common Dimensions
(Unit of Measure=millimeters)
Symbol
Min
Typ
Max
A
0.700
0.750
0.800
A1
0.000
0.020
0.050
b
0.350
0.400
0.450
D
4.900
5.000
5.100
D2(rev MC)
-
1.500
-
E
5.900
6.000
6.100
E2(rev MC)
4.000
4.100
4.200
e
-
1.270
-
L
0.450
0.500
0.550
h
0.300
0.350
0.400
c
0.180
0.203
0.250
Note：1. Dimensions are not to scale
TITLE
DRAWING NO.
REV
DN-8
A
DFN8(0506X0.75-1.27)
Puya Semiconductor
Page 70 of 71
P25Q80H Datasheet
13 Revision History
Rev.
Date
V1.0
2017-05-30
Description
Author
Cyx
Puya Semiconductor Co., Ltd.
IMPORTANT NOTICE
Puya Semiconductor reserves the right to make changes without further notice to any
products or specifications herein. Puya Semiconductor does not assume any responsibility
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