MM74C922WM

74C922/74C923 74C922 16-Key Encoder 74C923 20-Key Encoder General Description An internal register remembers the last key pressed even after the key is released. The 3-STATE outputs provide for easy expansion and bus operation and are LPTTL compatible. The 74C922 and 74C923 CMOS key encoders provide all the necessary logic to fully encode an array of SPST switches. The keyboard scan can be implemented by either an external clock or external capacitor. These encoders also have on-chip pull-up devices which permit switches with up to 50 kΩ on resistance to be used. No diodes in the switch array are needed to eliminate ghost switches. The internal debounce circuit needs only a single external capacitor and can be defeated by omitting the capacitor. A Data Available output goes to a high level when a valid keyboard entry has been made. The Data Available output returns to a low level when the entered key is released, even if another key is depressed. The Data Available will return high to indicate acceptance of the new key after a normal debounce period; this two-key roll-over is provided between any two switches. Features ■ 50 kΩ maximum switch on resistance ■ On or off chip clock ■ On-chip row pull-up devices ■ 2 key roll-over ■ Keybounce elimination with single capacitor ■ Last key register at outputs ■ 3-STATE output LPTTL compatible ■ Wide supply range: 3V to 15V ■ Low power consumption Connection Diagrams Pin Assignment for DIP Pin Assignment for SOIC 74C922 Top View 94C922 Top View http://www.hgsemi.com.cn 1 2018 AUG 74C922/74C923 Connection Diagrams (Continued) Pin Assignment for DIP and SOIC Package 74C923 Top View Truth Tables (Pins 0 through 11) Switch Position 0 1 2 3 4 5 6 Y1,X1 Y1,X2 Y1,X3 Y1,X4 Y2,X1 Y2,X2 7 8 9 10 Y2,X3 Y2,X4 Y3,X1 Y3,X2 Y3,X3 11 Y3,X4 D A A 0 1 0 1 0 1 0 1 0 1 0 T B 0 0 1 1 0 0 1 1 0 0 1 1 1 A C 0 0 0 0 1 1 1 1 0 0 0 0 O D 0 0 0 0 0 0 0 0 1 1 1 1 U E (Note 1) 0 0 0 0 0 0 0 0 0 0 0 0 T (Pins 12 through 19) Switch Position 12 13 14 15 Y4,X1 Y4,X2 Y4,X3 Y4,X4 16 17 18 A A 0 1 0 1 0 1 0 T B 0 0 1 1 0 0 1 1 A C 1 1 1 1 0 0 0 0 O D 1 1 1 1 0 0 0 0 U E (Note 1) 0 0 0 0 1 1 1 1 Y5(Note 1), Y5 (Note 1), Y5 (Note 1), X1 X2 X3 19 Y5 (Note 1), X4 D 1 T Note 1: Omit for 74C922 http://www.hgsemi.com.cn 1 2018 AUG 74C922/74C923 Block Diagram http://www.hgsemi.com.cn 1 2018 AUG 74C922/74C923 Absolute Maximum Ratings(Note 2) Operating VCC Range VCC − 0.3V to V CC + 0.3V Voltage at Any Pin 74C923 Storage Temperature Range (Soldering, 10 seconds) −40°C to +85°C −65°C to +150°C Power Dissipation (P D) Dual-In-Line 700 mW Small Outline 500 mW 18V Lead Temperature Operating Temperature Range 74C922, 3V to 15V VCC 260°C Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified Symbol Parameter Conditions Min Typ Max Units 3.0 3.6 4.3 V 6.0 6.8 8.6 V V CMOS TO CMOS VT+ Positive-Going Threshold Voltage at Osc and KBM Inputs VT− Negative-Going Threshold Voltage at Osc and KBM Inputs VIN(1) VIN(0) Irp VOUT(1) VOUT(0) VCC = 5V, IIN ≥ 0.7 mA VCC = 10V, IIN ≥ 1.4 mA VCC = 15V, IIN ≥ 2.1 mA 9.0 10 12.9 VCC = 5V, IIN ≥ 0.7 mA VCC = 10V, IIN ≥ 1.4 mA 0.7 1.4 2.0 V 1.4 3.2 4.0 V 6.0 V VCC = 15V, IIN ≥ 2.1 mA 2.1 5 Logical “1” Input Voltage, VCC = 5V 3.5 4.5 V Except Osc and KBM Inputs VCC = 10V 8.0 9 V VCC = 15V 12.5 13.5 Logical “0” Input Voltage, VCC = 5V Except Osc and KBM Inputs 1.5 V VCC = 10V 1 2 V VCC = 15V 1.5 2.5 V Row Pull-Up Current at Y1, Y2, VCC = 5V, VIN = 0.1 VCC −2 −5 µA Y3, Y4 and Y5 Inputs VCC = 10V −10 −20 µA VCC = 15V −22 −45 µA Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5V, IO = −10 µA VCC = 10V, IO = −10 µA 4.5 9 V VCC = 15V, IO = −10 µA 13.5 V V VCC = 5V, IO = 10 µA VCC = 10V, IO = 10 µA VCC = 15V, IO = 10 µA Ron ICC 0.5 V 1 V 1.5 V Column “ON” Resistance at VCC = 5V, VO = 0.5V 500 1400 Ω X1, X2, X3 and X4 Outputs VCC = 10V, VO = 1V 300 700 Ω VCC = 15V, VO = 1.5V 200 500 Ω VCC = 5V 0.55 1.1 mA VCC = 10V 1.1 1.9 mA VCC = 15V 1.7 2.6 mA 0.005 1.0 µA Supply Current Osc at 0V, (one Y low) IIN(1) V 0.5 Logical “1” Input Current VCC = 15V, VIN = 15V at Output Enable IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA at Output Enable CMOS/LPTTL INTERFACE VIN(1) Except Osc and KBM Inputs VCC = 4.75V VIN(0) Except Osc and KBM Inputs VCC = 4.75V VOUT(1) Logical “1” Output Voltage IO = −360 µA VCC − 1.5 V 0.8 VCC = 4.75V 2.4 V V IO = −360 µA VOUT(0) Logical “0” Output Voltage IO = −360 µA VCC = 4.75V 0.4 V IO = −360 µA http://www.hgsemi.com.cn 1 2018 AUG 74C922/74C923 DC Electrical Characteristics Symbol (Continued) Parameter Conditions Min Typ Max Units −1.75 −3.3 mA −8 −15 mA 1.75 3.6 mA 8 16 mA Min Typ Max Units ns OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE ISOURCE ISINK ISINK Output Source Current VCC = 5V, VOUT = 0V, (P-Channel) TA = 25°C Output Source Current VCC = 10V, VOUT = 0V, (P-Channel) TA = 25°C Output Sink Current VCC = 5V, VOUT = VCC, (N-Channel) TA = 25°C Output Sink Current VCC = 10V, VOUT = VCC, (N-Channel) TA = 25°C AC Electrical Characteristics (Note 3) TA = 25°C, CL = 50 pF, unless otherwise noted Symbol tpd0, tpd1 t0H, t1H Parameter Conditions Propagation Delay Time to CL = 50 pF (Figure 1) Logical “0” or Logical “1” VCC = 5V 60 150 from D.A. VCC = 10V 35 80 ns VCC = 15V 25 60 ns 80 200 ns 50 110 ns Propagation Delay Time from RL = 10k, CL = 10 pF (Figure 2) Logical “0” or Logical “1” VCC = 5V, RL = 10k into High Impedance State VCC = 10V, C L = 10 pF65150ns Propagation Delay Time from RL = 10k, CL = 50 pF (Figure 2) VCC = 15V tH0, tH1 High Impedance State to a VCC = 5V, RL = 10k 100 250 ns Logical “0” or Logical “1” VCC = 10V, CL = 50 pF 55 125 ns VCC = 15V 40 90 ns 5 7.5 pF CIN Input Capacitance Any Input (Note 4) COUT 3-STATE Output Capacitance Any Output (Note 4) 10 pF Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: Capacitance is guaranteed by periodic testing. http://www.hgsemi.com.cn 1 2018 AUG 74C922/74C923 Switching Time Waveforms T1 ≈ T2 ≈ RC, T3 ≈ 0.7 RC, where R ≈ 10k and C is external capacitor at KBM input. FIGURE 1. FIGURE 2. http://www.hgsemi.com.cn 1 2018 AUG 74C922/74C923 Typical Performance Characteristics Typical Irp vs VIN at Any Y Input Typical Ron vs VOUT at Any X Output Typical FSCAN vs COSC Typical Debounce Period vs CKBM Typical Applications Synchronous Handshake (74C922) The keyboard may be synchronously scanned by omitting the capacitor at osc. and driving osc. directly if the system clock rate is lower than 10 kHz Synchronous Data Entry Onto Bus (74C922) Outputs are enabled when valid entry is made and go into 3-STATE when key is released. The keyboard may be synchronously scanned by omitting the capacitor at osc. and driving osc. directly if the system clock rate is lower than 10 kHz http://www.hgsemi.com.cn 1 2018 AUG 74C922/74C923 Asynchronous Data Entry Onto Bus (74C922) Outputs are in 3-STATE until key is pressed, then data is placed on bus. When key is released, outputs return to 3-STATE. Expansion to 32 Key Encoder (74C922) Theory of Operation going low also initiates the key bounce circuit timing and locks out the other Y inputs. The key code to be output is a combination of the frozen counter value and the decoded Y inputs. Once the key bounce circuit times out, the data is latched, and the Data Available (DAV) output goes high. The 74C922/74C923 Keyboard Encoders implement all the logic necessary to interface a 16 or 20 SPST key switch matrix to a digital system. The encoder will convert a key switch closer to a 4(74C922) or 5(74C923) bit nibble. The designer can control both the keyboard scan rate and the key debounce period by altering the oscillator capacitor, COSE, and the key bounce mask capacitor, C MSK . Thus, the 74C922/74C923’s performance can be optimized for many keyboards. If, during the key closure the switch bounces, Y1 input will go high again, restarting the scan and resetting the key bounce circuitry. The key may bounce several times, but as soon as the switch stays low for a debounce period, the closure is assumed valid and the data is latched. The keyboard encoders connect to a switch matrix that is 4 rows by 4 columns (74C922) or 5 rows by 4 columns (74C923). When no keys are depressed, the row inputs are pulled high by internal pull-ups and the column outputs sequentially output a logic “0”. These outputs are open drain and are therefore low for 25% of the time and otherwise off. The column scan rate is controlled by the oscillator input, which consists of a Schmitt trigger oscillator, a 2bit counter, and a 2–4-bit decoder. A key may also bounce when it is released. To ensure that the encoder does not recognize this bounce as another key closure, the debounce circuit must time out before another closure is recognized. The two-key roll-over feature can be illustrated by assuming a key is depressed, and then a second key is depressed. Since all scanning has stopped, and all other Y inputs are disabled, the second key is not recognized until the first key is lifted and the key bounce circuitry has reset. When a key is depressed, key 0, for example, nothing will happen when the X1 input is off, since Y1 will remain high. When the X1 column is scanned, X1 goes low and Y1 will go low. This disables the counter and keeps X1 low. Y1 http://www.hgsemi.com.cn The output latches feed 3-STATE, which is enabled when the Output Enable (OE) input is taken low. 1 2018 AUG