LM324M/TR

oct 2010 LM324 Low power quad operational amplifiers Features ■ Wide gain bandwidth: 1.3 MHz ■ Input common-mode voltage range includes ground ■ Large voltage gain: 100 dB ■ Very low supply current per amplifier: 375 µA ■ Low input bias current: 20 nA ■ Low input offset voltage: 5 mV max. ■ Low input offset current: 2 nA ■ Wide power supply range: – Single supply: +3 V to +30 V ■ Dual supplies: ±1.5 V to ±15 V N DIP14 (Plastic package) Description These circuits consist of four independent, high gain, internally frequency-compensated operational amplifiers. They operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. www.hgsemi.net 1 D SO-14 (Plastic micropackage) 19 oct 2010 LM324 1 Pin and schematic diagram Figure 1. Pin connections (top view) 14 Output 4 Output 1 1 Inverting Input 1 2 - - 13 Inverting Input 4 Non-inverting Input 1 3 + + 12 Non-inverting Input 4 11 VCC - VCC + 4 Non-inverting Input 2 5 + + 10 Non-inverting Input 3 Inverting Input 2 6 - - 9 Inverting Input 3 8 Output 3 Output 2 7 Figure 2. Schematic diagram (1/4 LM124) www.hgsemi.net 2 oct 2010 LM324 2 Absolute maximum ratings Table 1. Absolute maximum ratings Symbol VCC Vin Vid Parameter Supply voltage Input voltage (1) Differential input voltage LM324 Unit ±16 or 32 V -0.3 to 32 V 32 V (2) Output short-circuit duration (3) Infinite (4): 5 mA in DC or 50 mA in AC (duty cycle = 10%, T=1s) Input current Vin driven negative Input current (5): Vin driven positive above AMR value 0.4 mA Toper Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range -65 to +150 °C 150 °C Iin Tj Rthja Rthjc Maximum junction temperature Thermal resistance junction to SO14 103 DIP14 83 Thermal resistance junction to case SO14 31 DIP14 33 HBM: human body model ESD ambient(6) MM: machine model (7) °C/W 250 (8) CDM: charged device °C/W 150 model(9) V 1500 1. Either or both input voltages must not exceed the magnitude of VCC+ or VCC-. All voltage values, except differential voltages are with respect to ground terminal. 2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. 3. Short-circuits from the output to VCC can cause excessive heating if VCC > 15 V. The maximum output current is approximately 40 mA independent of the magnitude of VCC. Destructive dissipation can result from simultaneous shortcircuits on all amplifiers. 4. This input current only exists when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistor becoming forward-biased and thereby acting as input diode clamp. In addition to this diode action, there is NPN parasitic action on the IC chip. This transistor action can cause the output voltages of the opamps to go to the VCC voltage level (or to ground for a large overdrive) for the time during which an input is driven negative. This is not destructive and normal output is restored for input voltages above -0.3 V. 5. The junction base/substrate of the input PNP transistor polarized in reverse must be protected by a resistor in series with the inputs to limit the input current to 400 µA max (R = (Vin - 32 V)/400 µA). 6. Short-circuits can cause excessive heating. Destructive dissipation can result from simultaneous short-circuits on all amplifiers. These are typical values given for a single layer board (except for TSSOP, a two-layer board). 7. Human body model, 100 pF discharged through a 1.5 kΩ resistor into pin of device. 8. Machine model ESD: a 200 pF capacitor is charged to the specified voltage, then discharged directly into the IC with no external series resistor (internal resistor < 5 Ω), into pin-to-pin of device. 9. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to ground. www.hgsemi.net 3 oct 2010 LM324 3 Electrical characteristics Table 2. VCC+ = +5 V, VCC-= ground, Vo = 1.4 V, Tamb = +25° C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit 7 mV Input offset voltage (1) Tamb = +25° C Vio LM324 Tmin ≤ Tamb ≤ Tmax LM324 9 Iio Input offset current Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 2 30 100 nA Iib Input bias current (2) Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 20 150 300 nA Avd Large signal voltage gain VCC+ = +15 V, RL = 2 kΩ, Vo = 1.4 V to 11.4 V Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 50 25 100 SVR Supply voltage rejection ratio (Rs ≤ 10 kΩ) VCC+ = 5 V to 30 V Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 65 65 110 ICC Supply current, all Amp, no load Tamb = +25° C VCC = +5 V VCC = +30 V Tmin ≤ Tamb ≤ Tmax VCC = +5 V VCC = +30 V dB 0.7 1.5 1.2 3 0.8 1.5 1.2 3 Vicm Input common mode voltage range VCC = +30 V (3) Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 0 0 CMR Common mode rejection ratio (Rs ≤ 10 kΩ) Tamb = +25° C Tmin ≤ Tamb ≤ Tmax 70 60 80 Isource Output current source (Vid = +1 V) VCC = +15 V, Vo = +2 V 20 40 www.hgsemi.net 4 V/mV VCC -1.5 VCC -2 mA V dB 70 mA oct 2010 LM324 Table 2. VCC+ = +5 V, VCC-= ground, Vo = 1.4 V, Tamb = +25° C (unless otherwise specified) (continued) Symbol Isink VOH Parameter Min. Typ. Output sink current (Vid = -1 V) VCC = +15 V, Vo = +2 V VCC = +15 V, Vo = +0.2 V 10 12 20 50 High level output voltage VCC = +30 V Tamb = +25° C, RL = 2 kΩ Tmin ≤ Tamb ≤ Tmax Tamb = +25° C, RL = 10 kΩ Tmin ≤ Tamb ≤ Tmax 26 26 27 27 27 VCC = +5 V, RL = 2 kΩ Tamb = +25°C Tmin ≤ Tamb ≤ Tmax 3.5 3 Max. Unit mA µA 28 V VOL Low level output voltage (RL = 10 kΩ) Tamb = +25°C Tmin ≤ Tamb ≤ Tmax SR Slew rate VCC = 15 V, Vi = 0.5 to 3 V, RL = 2 kΩ, CL = 100 pF, unity gain 0.4 V/µs GBP Gain bandwidth product VCC = 30 V, f = 100 kHz, Vin = 10 mV, RL = 2 kΩ, CL = 100 pF 1.3 MHz THD Total harmonic distortion f = 1 kHz, Av = 20 dB, RL = 2 kΩ, Vo = 2 Vpp, CL = 100 pF, VCC = 30 V 0.015 % Equivalent input noise voltage f = 1 kHz, Rs = 100 Ω, VCC = 30 V 40 nV -----------Hz DVio Input offset voltage drift 7 30 µV/°C DIio Input offset current drift 10 200 pA/°C en Vo1/Vo2 Channel separation 1 kHz ≤ f ≤ 20 kHZ 5 20 20 mV (4) 120 dB 1. Vo = 1.4 V, Rs = 0 Ω, 5 V < VCC+ < 30 V, 0 < Vic < VCC+ - 1.5 V. 2. The direction of the input current is out of the IC. This current is essentially constant, independent of the state of the output so there is no change in the load on the input lines. 3. The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0. V. The upper end of the common-mode voltage range is VCC+ - 1.5 V, but either or both inputs can go to +32 V without damage. 4. Due to the proximity of the external components, ensure that stray capacitance between these external parts does not cause coupling. Coupling can be detected because this type of capacitance increases at higher frequencies. www.hgsemi.net 5 oct 2010 LM324 Figure 3. Input bias current vs. ambient temperature Figure 4. Current limiting 90 IB (nA) 24 80 18 70 Input current (mA) 21 15 12 9 6 3 IO + 60 50 40 30 20 10 0 -55-35-15 0 5 25 45 65 85 105 125 -55 -35 -15 5 Ambient temperature (°C) Figure 5. Temperature (°C) Input voltage range Figure 6. Supply current 15 4 VCC ID Supply current (mA) mA Input voltage (V) 25 45 65 85 105 125 10 Negative Positive 5 3 2 Tamb = 0°C to +125°C 1 Tamb = -55°C 0 5 10 0 15 Power supply voltage (V) Figure 7. Gain bandwidth product Figure 8. 20 30 Common mode rejection ratio 120 Common-mode rejection ratio (dB) GBP (MHz) Gain bandwidth product (MHz) 10 Positive supply voltage (V) 1.35 1.30 1.25 1.2 1.15 1.1 1.05 1 0.95 0.9 -55 -35 -15 5 25 45 65 85 105 125 100 80 +7.5 V 100 kΩ 60 100 Ω 40 eI 100 kΩ 20 0 100 1k eO 100 Ω 10k +7.5 V 100k Frequency (Hz) Ambient temperature (°C) www.hgsemi.net 6 1M oct 2010 LM324 Figure 9. Open loop frequency response 140 Figure 10. Large signal frequency response 20 10 MΩ 100 kΩ 0.1 uF 1 kΩ 120 VCC+ VCC+/2 80 VCC+ = +30 V & -55°C Tamb +125°C 60 40 VCC+ = +10 to +15 V & -55°C Tamb +125°C 20 10 5 0 1.0 100 1.0k 10k 100k 1.0M 10M 10 1k 10k Frequency (Hz) 1M 100k Frequency (Hz) Figure 11. Voltage follower pulse response Figure 12. Output characteristics (current sinking) 10 4 VCC+ = +5 V VCC+ = +15 V VCC+ = +30 V RL 2 kΩ VCC+ = +15 V 3 2 Output voltage (V) Input voltage (V) - output voltage (V) 2 kΩ +7 V 0 1 0 3 2 1 VCC+/2 IO VO Tamb = +25°C 0.01 10 20 40 30 0.001 0.01 Figure 13. Voltage follower pulse response (small signal) Output voltage referenced to VCC+ (V) 450 eO 50 pF eI Input 350 Output 300 Tamb = +25°C VCC+ = +30 V 0 1 2 3 4 1 100 10 Figure 14. Output characteristics (current sourcing) 500 250 0.1 Output sink current (mA) Time (μS) 400 VCC+ 0.1 1 0 Output voltage (mV) eO eI 15 Output swing (Vpp) Voltage gain (dB) 100 +15 V eO eI 5 6 7 8 Time (μS) 8 VCC+ 7 6 VCC+/2 VO 5 IO 4 Independent of VCC+ 3 Tamb = +25°C 2 1 0.001 0.01 0.1 1 10 100 Output source current (mA) www.hgsemi.net 7 oct 2010 LM324 Figure 15. Input current Figure 16. Large signal voltage gain Avd (dB) 100 Large signal voltage gain 120 Input current (nA) 75 50 Tamb = +25°C 25 20 110 105 100 -55 -35 -15 0 10 115 30 25 45 65 80 105 125 Ambient temperature (°C) Power supply voltage (V) Figure 17. Power supply and common mode rejection ratio Figure 18. Voltage gain 160 (dB) 120 115 SVR 110 RL = 20 kΩ 120 105 100 95 90 85 80 CMR Voltage gain (dB) Power supply & common mode rejection ratio (dB) 5 RL = 2 kΩ 80 40 75 70 -55 -35 -15 5 25 45 65 85 105 125 Ambient temperature (°C) 0 10 20 Power supply voltage (V) www.hgsemi.net 8 30 oct 2010 LM324 4 Typical single-supply applications Figure 19. AC coupled inverting amplifier Figure 20. High input Z adjustable gain DC instrumentation amplifier 2 Vpp if R1 = R5 and R3 = R4 = R6 = R7 2R e0 = 1 + ----------1- (e2 -e1) R 2 Figure 21. AC coupled non inverting amplifier Figure 22. DC summing amplifier 2 Vpp e0 = e1 +e2 -e3 -e4 Where (e1 +e2) ≥ (e3 +e4) to keep e0 ≥ 0V Figure 23. Non-inverting DC gain Figure 24. Low drift peak detector www.hgsemi.net 9 oct 2010 LM324 Figure 25. Active bandpass filter Figure 26. High input Z, DC differential amplifier R R 1 4 For ------- = ------R R 2 3 (CMRR depends on this resistor ratio match) Fo = 1kHz Q = 50 Av = 100 (40dB) e0 ⎛ 1 + R-------4⎞ ⎝ R3⎠ (e2 - e1) As shown e0 = (e2 - e1) Figure 27. Using symmetrical amplifiers to reduce input current (general concept) Order codes Part number Temperature range Package Packing DIP14 Tube LM124D/DT SO-14 Tube or tape & reel LM224N DIP14 Tube SO-14 Tube or tape & reel LM124N -55°C, +125°C LM224D/DT -40°C, +105°C LM224PT (Thin shrink outline package) LM324N LM324D/DT 0°C, +70°C DIP14 Tube SO-14 Tube or tape & reel (Thin shrink outline package) www.hgsemi.net 10 Tape & reel Tape & reel oct 2010 LM324 6.1 DIP14 package information Figure 28. DIP14 package mechanical drawing Table 4. DIP14 package mechanical data Dimensions Millimeters Inches Ref. Min. Typ. A Max. Min. Typ. 5.33 Max. 0.21 A1 0.38 0.015 A2 2.92 3.30 4.95 0.11 0.13 0.19 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.04 0.06 0.07 c 0.20 0.25 0.36 0.007 0.009 0.01 D 18.67 19.05 19.69 0.73 0.75 0.77 E 7.62 7.87 8.26 0.30 0.31 0.32 E1 6.10 6.35 7.11 0.24 0.25 0.28 e 2.54 0.10 e1 15.24 0.60 eA 7.62 0.30 eB L 10.92 2.92 3.30 3.81 www.hgsemi.net 11 0.43 0.11 0.13 0.15 oct 2010 LM324 6.2 SO-14 package information Figure 29. SO-14 package mechanical drawing Table 5. SO-14 package mechanical data Dimensions Millimeters Inches Ref. Min. Typ. Max. Min. Typ. Max. A 1.35 1.75 0.05 0.068 A1 0.10 0.25 0.004 0.009 A2 1.10 1.65 0.04 0.06 B 0.33 0.51 0.01 0.02 C 0.19 0.25 0.007 0.009 D 8.55 8.75 0.33 0.34 E 3.80 4.0 0.15 0.15 e 1.27 0.05 H 5.80 6.20 0.22 0.24 h 0.25 0.50 0.009 0.02 L 0.40 1.27 0.015 0.05 k ddd 8° (max.) 0.10 www.hgsemi.net 12 0.004