VS1053B

VS1053 B VS1053b preliminary VS1053b Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC Features Description • Decodes Ogg Vorbis; VS1053b is a single-chip Ogg Vorbis/MP3/AAC/MPEG 1 & 2 audio layer III (CBR +VBR WMA/MIDI audio decoder and an IMA ADPCM +ABR); layers I & II optional; and user-loadable Ogg Vorbis encoder. It contains MPEG4 / 2 AAC-LC(+PNS), a high-performance, proprietary low-power DSP HE-AAC v2 (Level 3) (SBR + PS); processor core VS DSP4 , working data memory, WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps); 16 KiB instruction RAM and 0.5+ KiB data RAM WAV (PCM + IMA ADPCM); for user applications running simultaneously with General MIDI 1 / SP-MIDI format 0 files any built-in decoder, serial control and input data • Encodes Ogg Vorbis with software pluinterfaces, upto 8 general purpose I/O pins, an gin (available Q4/2007) UART, as well as a high-quality variable-samplerate stereo ADC (mic, line, line + mic or 2×line) • Encodes IMA ADPCM from mic/line (stereo) and stereo DAC, followed by an earphone ampli• Streaming support for MP3 and WAV fier and a common voltage buffer. • EarSpeaker Spatial Processing • Bass and treble controls VS1053b receives its input bitstream through a • Operates with a single 12..13 MHz clock serial input bus, which it listens to as a system • Can also be used with a 24..26 MHz clock slave. The input stream is decoded and passed through a digital volume control to an 18-bit over• Internal PLL clock multiplier sampling, multi-bit, sigma-delta DAC. The decod• Low-power operation ing is controlled via a serial control bus. In addi• High-quality on-chip stereo DAC with no tion to the basic decoding, it is possible to add phase error between channels application specific features, like DSP effects, to • Zero-cross detection for smooth volume the user RAM memory. change • Stereo earphone driver capable of driving a Optional factory-programmable unique chip ID pro30 Ω load vides basis for digital rights management or unit • Quiet power-on and power-off identification features. • I2S interface for external DAC I2S • Separate voltages for analog, digital, I/O audio VS1053 L Stereo Ear− Stereo Stereo • On-chip RAM for user code and data differential MUX MIC AMP mic / line 1 phone Driver ADC DAC R line 2 output • Serial control and data interfaces 8 GPIO GPIO • Can be used as a slave co-processor X ROM DREQ • SPI flash boot for special applications SO Serial SI X RAM Data/ • UART for debugging purposes 4 SCLK Control VSDSP Interface • New functions may be added with software XCS XDCS Y ROM and upto 8 GPIO pins RX • Lead-free RoHS-compliant package (Green) TX UART Y RAM Clock multiplier Version 0.5, 2007-12-03 Instruction RAM Instruction ROM 1 VLSI VS1053b preliminary y Solution VS1053 B CONTENTS Contents 1 Licenses 9 2 Disclaimer 9 3 Definitions 9 4 Characteristics & Specifications 10 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.6 Switching Characteristics - Boot Initialization . . . . . . . . . . . . . . . . . . . . . . . 12 5 Packages and Pin Descriptions 13 5.1 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.1 13 LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagram, LQFP-48 16 7 SPI Buses 18 7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 SPI Bus Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2.1 VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2.2 VS1001 Compatibility Mode (deprecated) . . . . . . . . . . . . . . . . . . . . . 18 Data Request Pin DREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 Version 0.5, 2007-12-03 2 VLSI VS1053b preliminary y Solution 7.4 CONTENTS Serial Protocol for Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . 19 7.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4.2 SDI in VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . . 19 7.4.3 SDI in VS1001 Compatibility Mode (deprecated) . . . . . . . . . . . . . . . . . 20 7.4.4 Passive SDI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial Protocol for Serial Command Interface (SCI) . . . . . . . . . . . . . . . . . . . . 20 7.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.5.2 SCI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.5.3 SCI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.5.4 SCI Multiple Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.6 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.7 SPI Examples with SM SDINEW and SM SDISHARED set . . . . . . . . . . . . . . . 24 7.7.1 Two SCI Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.7.2 Two SDI Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.7.3 SCI Operation in Middle of Two SDI Bytes . . . . . . . . . . . . . . . . . . . . 25 7.5 8 VS1053 B Functional Description 26 8.1 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 Supported Audio Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2.1 Supported MP3 (MPEG layer III) Formats . . . . . . . . . . . . . . . . . . . . 26 8.2.2 Supported MP1 (MPEG layer I) Formats . . . . . . . . . . . . . . . . . . . . . 27 8.2.3 Supported MP2 (MPEG layer II) Formats . . . . . . . . . . . . . . . . . . . . . 27 8.2.4 Supported Ogg Vorbis Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2.5 Supported AAC (ISO/IEC 13818-7 and ISO/IEC 14496-3) Formats . . . . . . . 28 8.2.6 Supported WMA Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Version 0.5, 2007-12-03 3 VLSI VS1053b preliminary y Solution 9 VS1053 B CONTENTS 8.2.7 Supported RIFF WAV Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.2.8 Supported MIDI Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.3 Data Flow of VS1053b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.4 EarSpeaker Spatial Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.5 Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.6 Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.7 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.7.1 SCI MODE (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.7.2 SCI STATUS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.7.3 SCI BASS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.7.4 SCI CLOCKF (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.7.5 SCI DECODE TIME (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.7.6 SCI AUDATA (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.7.7 SCI WRAM (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.7.8 SCI WRAMADDR (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.7.9 SCI HDAT0 and SCI HDAT1 (R) . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.7.10 SCI AIADDR (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.7.11 SCI VOL (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.7.12 SCI AICTRL[x] (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Operation 48 9.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.4 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Version 0.5, 2007-12-03 4 VLSI VS1053b preliminary y Solution 9.5 VS1053 B CONTENTS Play and Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.5.1 Playing a Whole File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.5.2 Cancelling Playback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.5.3 Fast Play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.5.4 Fast Forward and Rewind without Audio . . . . . . . . . . . . . . . . . . . . . 50 9.5.5 Maintaining Correct Decode Time . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.6 Feeding PCM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.7 Ogg Vorbis Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.8 ADPCM Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.8.1 Activating ADPCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.8.2 Reading IMA ADPCM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.8.3 Adding a RIFF Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.8.4 Playing ADPCM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.8.5 Sample Rate Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.10 Real-Time MIDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.11 Extra Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.11.1 Common Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.11.2 WMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.11.3 AAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.11.4 Midi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.11.5 Ogg Vorbis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.12 SDI Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.12.1 Sine Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.9 Version 0.5, 2007-12-03 5 VLSI VS1053b preliminary y Solution VS1053 B CONTENTS 9.12.2 Pin Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.12.3 SCI Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.12.4 Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.12.5 New Sine and Sweep Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10 VS1053b Registers 65 10.1 Who Needs to Read This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.2 The Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.3 VS1053b Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.4 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.5 Serial Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.6 DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.7 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.8 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.9 Watchdog v1.0 2002-08-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.9.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.10UART v1.1 2004-10-09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.10.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.10.2 Status UARTx STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.10.3 Data UARTx DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.10.4 Data High UARTx DATAH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.10.5 Divider UARTx DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.10.6 Interrupts and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.11Timers v1.0 2002-04-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.11.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Version 0.5, 2007-12-03 6 VLSI VS1053b preliminary y Solution VS1053 B CONTENTS 10.11.2 Configuration TIMER CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.11.3 Configuration TIMER ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.11.4 Timer X Startvalue TIMER Tx[L/H] . . . . . . . . . . . . . . . . . . . . . . . 73 10.11.5 Timer X Counter TIMER TxCNT[L/H] . . . . . . . . . . . . . . . . . . . . . . 73 10.11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.12VS1053b Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.13I2S DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.13.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.13.2 Configuration I2S CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11 VS1053 Version Changes 11.1 Changes Between VS1033c and VS1053a/b Firmware, 2007-03-08 . . . . . . . . . . . . 76 76 12 Document Version Changes 78 13 Contact Information 79 Version 0.5, 2007-12-03 7 VLSI VS1053b preliminary y Solution VS1053 B LIST OF FIGURES List of Figures 1 Pin Configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 VS1053b in LQFP-48 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Typical Connection Diagram Using LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . 16 4 BSYNC Signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 BSYNC Signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 SCI Word Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 SCI Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 SCI Multiple Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 Two SCI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11 Two SDI Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12 Two SDI Bytes Separated By an SCI Operation. . . . . . . . . . . . . . . . . . . . . . . 25 13 Data Flow of VS1053b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 14 EarSpeaker externalized sound sources vs. normal inside-the-head sound . . . . . . . . . 35 15 RS232 Serial Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16 VS1053b ADC and DAC data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17 I2S Interface, 192 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Version 0.5, 2007-12-03 8 VLSI VS1053b preliminary y Solution 1 VS1053 B 1. LICENSES Licenses MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and Thomson. Note: If you enable Layer I and Layer II decoding, you are liable for any patent issues that may arise from using these formats. Joint licensing of MPEG 1.0 / 2.0 Layer III does not cover all patents pertaining to layers I and II. VS1053b contains WMA decoding technology from Microsoft. This product is protected by certain intellectual property rights of Microsoft and cannot be used or further distributed without a license from Microsoft. VS1053b contains AAC technology (ISO/IEC 13818-7 and ISO/IEC 14496-3) which cannot be used without a proper license from Via Licensing Corporation or individual patent holders. VS1053b contains spectral band replication (SBR) and parametric stereo (PS) technologies developed by Coding Technologies. Licensing of SBR is handled within MPEG4 through Via Licensing Corporation. Licensing of PS is handled with Coding Technologies. See http://www.codingtechnologies.com/licensing/aacplus.htm for more information. To the best of our knowledge, if the end product does not play a specific format that otherwise would require a customer license: MPEG 1.0/2.0 layers I and II, WMA, or AAC, the respective license should not be required. Decoding of MPEG layers I and II are disabled by default, and WMA and AAC format exclusion can be easily performed based on the contents of the SCI HDAT1 register. Also PS and SBR decoding can be separately disabled. 2 Disclaimer This is a preliminary datasheet. All properties and figures are subject to change. 3 Definitions B Byte, 8 bits. b Bit. Ki “Kibi” = 210 = 1024 (IEC 60027-2). Mi “Mebi” = 220 = 1048576 (IEC 60027-2). VS DSP VLSI Solution’s DSP core. W Word. In VS DSP, instruction words are 32-bit and data words are 16-bit wide. Version 0.5, 2007-12-03 9 VLSI VS1053b preliminary y Solution 4 4. CHARACTERISTICS & SPECIFICATIONS Characteristics & Specifications 4.1 Absolute Maximum Ratings Parameter Analog Positive Supply Digital Positive Supply I/O Positive Supply Current at Any Digital Output Voltage at Any Digital Input Operating Temperature Storage Temperature 1 VS1053 B Symbol AVDD CVDD IOVDD Min -0.3 -0.3 -0.3 -0.3 -40 -65 Max 3.6 2.0 3.6 ±50 IOVDD+0.31 +85 +150 Unit V V V mA V ◦C ◦C Must not exceed 3.6 V 4.2 Recommended Operating Conditions Parameter Ambient Operating Temperature Analog and Digital Ground 1 Positive Analog Positive Digital I/O Voltage Input Clock Frequency2 Internal Clock Frequency Internal Clock Multiplier3 Master Clock Duty Cycle Symbol AGND DGND AVDD CVDD IOVDD XTALI CLKI Min -40 2.5 1.65 CVDD-0.6V 12 12 1.0× 40 Typ 0.0 2.8 1.8 2.8 12.288 36.864 3.0× 50 Max +85 3.6 2.0 3.6 13 55.3 4.5× 60 Unit ◦C V V V V MHz MHz % 1 Must be connected together as close the device as possible for latch-up immunity. The maximum samplerate is XTALI/256. XTALI must be at least 12.288 MHz to play 48 kHz at correct speed. 3 Reset value is 1.0×. Recommended SC MULT=3.5×, SC ADD=1.0× (SCI CLOCKF=0x8800). 2 Version 0.5, 2007-12-03 10 VLSI VS1053b preliminary y Solution 4.3 VS1053 B 4. CHARACTERISTICS & SPECIFICATIONS Analog Characteristics Unless otherwise noted: AVDD=2.5..2.85V, CVDD=1.8V, IOVDD=CVDD-0.6V..3.6V, TA=-40..+85◦ C, XTALI=12..13MHz, Internal Clock Multiplier 3.5×. DAC tested with 1307.894 Hz full-scale output sinewave, measurement bandwidth 20..20000 Hz, analog output load: LEFT to GBUF 30Ω, RIGHT to GBUF 30Ω. Microphone test amplitude 50 mVpp, fs =1 kHz, Line input test amplitude 1.1 V, fs =1 kHz. Parameter DAC Resolution Total Harmonic Distortion Dynamic Range (DAC unmuted, A-weighted) S/N Ratio (full scale signal) Interchannel Isolation (Cross Talk) Interchannel Isolation (Cross Talk), with GBUF Interchannel Gain Mismatch Frequency Response Full Scale Output Voltage (Peak-to-peak) Deviation from Linear Phase Analog Output Load Resistance Analog Output Load Capacitance Microphone input amplifier gain Microphone input amplitude Microphone Total Harmonic Distortion Microphone S/N Ratio Line input amplitude Line input Total Harmonic Distortion Line input S/N Ratio Line and Microphone input impedances Symbol Min THD IDR SNR 50 -0.5 -0.1 1.3 AOLR 16 Typ 18 0.03 100 94 75 40 1.51 Max 0.1 0.5 0.1 1.7 5 302 100 MICG MTHD MSNR 50 LTHD LSNR 26 50 0.02 62 2200 0.06 92 100 1403 0.10 28003 0.10 Unit bits % dB dB dB dB dB dB Vpp ◦ Ω pF dB mVpp AC % dB mVpp AC % dB kΩ 1 3.0 volts can be achieved with +-to-+ wiring for mono difference sound. AOLR may be much lower, but below Typical distortion performance may be compromised. 3 Above typical amplitude the Harmonic Distortion increases. 2 4.4 Power Consumption Tested with an MPEG 1.0 Layer-3 128 kbps sample and generated sine. Output at full volume. Internal clock multiplier 3.0×. Parameter Power Supply Consumption AVDD, Reset Power Supply Consumption CVDD = 1.8V, Reset Power Supply Consumption AVDD, sine test, 30Ω + GBUF Power Supply Consumption CVDD = 1.8V, sine test Power Supply Consumption AVDD, no load Power Supply Consumption AVDD, output load 30Ω Power Supply Consumption AVDD, 30Ω + GBUF Power Supply Consumption CVDD = 1.8V Version 0.5, 2007-12-03 Min Typ 0.6 4 36.9 6 7 11 16 10 Max 5.0 50.0 Unit µA µA mA mA mA mA mA mA 11 VLSI VS1053b preliminary y Solution 4.5 2 4. CHARACTERISTICS & SPECIFICATIONS Digital Characteristics Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at IO = -2.0 mA Low-Level Output Voltage at IO = 2.0 mA Input Leakage Current SPI Input Clock Frequency 2 Rise time of all output pins, load = 50 pF 1 VS1053 B Symbol Must not exceed 3.6V Value for SCI reads. SCI and SDI writes allow Min 0.7×IOVDD -0.2 0.7×IOVDD Typ Max IOVDD+0.31 0.3×IOVDD 0.3×IOVDD 1.0 -1.0 CLKI 6 50 Unit V V V V µA MHz ns CLKI 4 . 4.6 Switching Characteristics - Boot Initialization Parameter XRESET active time XRESET inactive to software ready Power on reset, rise time to CVDD 1 Symbol Min 2 22000 10 Max 500001 Unit XTALI XTALI V/s DREQ rises when initialization is complete. You should not send any data or commands before that. Version 0.5, 2007-12-03 12 VLSI VS1053b preliminary y Solution 5 VS1053 B 5. PACKAGES AND PIN DESCRIPTIONS Packages and Pin Descriptions 5.1 Packages LPQFP-48 is a lead (Pb) free and also RoHS compliant package. RoHS is a short name of Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment. 5.1.1 LQFP-48 48 1 Figure 1: Pin Configuration, LQFP-48. LQFP-48 package dimensions are at http://www.vlsi.fi/ . Figure 2: VS1053b in LQFP-48 Packaging. Version 0.5, 2007-12-03 13 VLSI VS1053b preliminary y Solution Pad Name MICP / LINE1 MICN XRESET DGND0 CVDD0 IOVDD0 CVDD1 DREQ GPIO2 / DCLK1 GPIO3 / SDATA1 GPIO6 / I2S SCLK3 GPIO7 / I2S SDATA3 XDCS / BSYNC1 IOVDD1 VCO DGND1 XTALO XTALI IOVDD2 DGND2 DGND3 DGND4 XCS CVDD2 GPIO5 / I2S MCLK3 RX TX SCLK SI SO CVDD3 XTEST GPIO0 GPIO1 GND GPIO4 / I2S LROUT3 AGND0 AVDD0 RIGHT AGND1 AGND2 GBUF AVDD1 RCAP AVDD2 LEFT AGND3 LINE2 LQFP Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Type AI AI DI DGND CPWR IOPWR CPWR DO DIO DIO DIO DIO DI IOPWR DO DGND AO AI IOPWR DGND DGND DGND DI CPWR DIO DI DO DI DI DO3 CPWR DI DIO DIO DGND DIO APWR APWR AO APWR APWR AO APWR AIO APWR AO APWR AI VS1053 B 5. PACKAGES AND PIN DESCRIPTIONS Function Positive differential mic input, self-biasing / Line-in 1 Negative differential mic input, self-biasing Active low asynchronous reset, schmitt-trigger input Core & I/O ground Core power supply I/O power supply Core power supply Data request, input bus General purpose IO 2 / serial input data bus clock General purpose IO 3 / serial data input General purpose IO 6 / I2S SCLK General purpose IO 7 / I2S SDATA Data chip select / byte sync I/O power supply For testing only (Clock VCO output) Core & I/O ground Crystal output Crystal input I/O power supply Core & I/O ground Core & I/O ground Core & I/O ground Chip select input (active low) Core power supply General purpose IO 5 / I2S MCLK UART receive, connect to IOVDD if not used UART transmit Clock for serial bus Serial input Serial output Core power supply Reserved for test, connect to IOVDD Gen. purp. IO 0 (SPIBOOT), use 100 kΩ pull-down resistor2 General purpose IO 1 I/O Ground General purpose IO 4 / I2S LROUT Analog ground, low-noise reference Analog power supply Right channel output Analog ground Analog ground Common buffer for headphones, do NOT connect to ground! Analog power supply Filtering capacitance for reference Analog power supply Left channel output Analog ground Line-in 2 (right channel) 1 First pin function is active in New Mode, latter in Compatibility Mode. Unless pull-down resistor is used, SPI Boot is tried. See Chapter 9.9 for details. 3 If I2S CF ENA is ’0’ the pins are used for GPIO. See Chapter 10.13 for details. 2 Version 0.5, 2007-12-03 14 VLSI VS1053b preliminary y Solution VS1053 B 5. PACKAGES AND PIN DESCRIPTIONS Pin types: Type DI DO DIO DO3 AI Version 0.5, Description Digital input, CMOS Input Pad Digital output, CMOS Input Pad Digital input/output Digital output, CMOS Tri-stated Output Pad Analog input 2007-12-03 Type AO AIO APWR DGND CPWR IOPWR Description Analog output Analog input/output Analog power supply pin Core or I/O ground pin Core power supply pin I/O power supply pin 15 VLSI VS1053b preliminary y Solution 6 VS1053 B 6. CONNECTION DIAGRAM, LQFP-48 Connection Diagram, LQFP-48 Figure 3: Typical Connection Diagram Using LQFP-48. Figure 3 shows a typical connection diagram for VS1053. Figure Note 1: Connect either Microphone In or Line In, but not both at the same time. Note: This connection assumes SM SDINEW is active (see Chapter 8.7.1). If also SM SDISHARE is used, xDCS should be tied low or high (see Chapter 7.2.1). Version 0.5, 2007-12-03 16 VLSI VS1053b preliminary y Solution VS1053 B 6. CONNECTION DIAGRAM, LQFP-48 The common buffer GBUF can be used for common voltage (1.24 V) for earphones. This will eliminate the need for large isolation capacitors on line outputs, and thus the audio output pins from VS1053b may be connected directly to the earphone connector. GBUF must NOT be connected to ground under any circumstances. If GBUF is not used, LEFT and RIGHT must be provided with coupling capacitors. To keep GBUF stable, you should always have the resistor and capacitor even when GBUF is not used. See application notes for details. Unused GPIO pins should have a pull-down resistor. Unused line and microphone inputs should not be connected. If UART is not used, RX should be connected to IOVDD and TX be unconnected. Do not connect any external load to XTALO. Version 0.5, 2007-12-03 17 VLSI VS1053b preliminary y Solution 7 VS1053 B 7. SPI BUSES SPI Buses 7.1 General The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1053b’s Serial Data Interface SDI (Chapters 7.4 and 8.5) and Serial Control Interface SCI (Chapters 7.5 and 8.6). 7.2 SPI Bus Pin Descriptions 7.2.1 VS1002 Native Modes (New Mode) These modes are active on VS1053b when SM SDINEW is set to 1 (default at startup). DCLK and SDATA are not used for data transfer and they can be used as general-purpose I/O pins (GPIO2 and GPIO3). BSYNC function changes to data interface chip select (XDCS). SDI Pin XDCS SCI Pin XCS SCK SI - 7.2.2 SO Description Active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state. If SM SDISHARE is 1, pin XDCS is not used, but the signal is generated internally by inverting XCS. Serial clock input. The serial clock is also used internally as the master clock for the register interface. SCK can be gated or continuous. In either case, the first rising clock edge after XCS has gone low marks the first bit to be written. Serial input. If a chip select is active, SI is sampled on the rising CLK edge. Serial output. In reads, data is shifted out on the falling SCK edge. In writes SO is at a high impedance state. VS1001 Compatibility Mode (deprecated) This mode is active when SM SDINEW is set to 0. In this mode, DCLK, SDATA and BSYNC are active. SDI Pin - SCI Pin XCS BSYNC DCLK SCK SDATA - SI SO Version 0.5, 2007-12-03 Description Active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state. SDI data is synchronized with a rising edge of BSYNC. Serial clock input. The serial clock is also used internally as the master clock for the register interface. SCK can be gated or continuous. In either case, the first rising clock edge after XCS has gone low marks the first bit to be written. Serial input. SI is sampled on the rising SCK edge, if XCS is low. Serial output. In reads, data is shifted out on the falling SCK edge. In writes SO is at a high impedance state. 18 VLSI VS1053b preliminary y Solution 7.3 VS1053 B 7. SPI BUSES Data Request Pin DREQ The DREQ pin/signal is used to signal if VS1053b’s 2048-byte FIFO is capable of receiving data. If DREQ is high, VS1053b can take at least 32 bytes of SDI data or one SCI command. DREQ is turned low when the stream buffer is too full and for the duration of a SCI command. Because of the 32-byte safety area, the sender may send upto 32 bytes of SDI data at a time without checking the status of DREQ, making controlling VS1053b easier for low-speed microcontrollers. Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should only be used to decide whether to send more bytes. It does not need to abort a transmission that has already started. Note: In VS10XX products upto VS1002, DREQ was only used for SDI. In VS1053b DREQ is also used to tell the status of SCI. There are cases when you still want to send SCI commands when DREQ is low. Because DREQ is shared between SDI and SCI, you can not determine if a SCI command has been executed if SDI is not ready to receive. In this case you need a long enough delay after every SCI command to make certain none of them is missed. The SCI Registers table in section 8.7 gives the worst-case handling time for each SCI register write. 7.4 7.4.1 Serial Protocol for Serial Data Interface (SDI) General The serial data interface operates in slave mode so DCLK signal must be generated by an external circuit. Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 8.7). VS1053b assumes its data input to be byte-sychronized. SDI bytes may be transmitted either MSb or LSb first, depending of contents of SCI MODE (Chapter 8.7.1). The firmware is able to accept the maximum bitrate the SDI supports. 7.4.2 SDI in VS1002 Native Modes (New Mode) In VS1002 native modes (SM NEWMODE is 1), byte synchronization is achieved by XDCS. The state of XDCS may not change while a data byte transfer is in progress. To always maintain data synchronization even if there may be glitches in the boards using VS1053b, it is recommended to turn XDCS every now and then, for instance once after every disk data block, just to make sure the host and VS1053b are in sync. If SM SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input. For new designs, using VS1002 native modes are recommended. Version 0.5, 2007-12-03 19 VLSI y Solution 7.4.3 VS1053 B VS1053b preliminary 7. SPI BUSES SDI in VS1001 Compatibility Mode (deprecated) BSYNC SDATA D7 D6 D5 D4 D3 D2 D1 D0 DCLK Figure 4: BSYNC Signal - one byte transfer. When VS1053b is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensure correct bit-alignment of the input bitstream. The first DCLK sampling edge (rising or falling, depending on selected polarity), during which the BSYNC is high, marks the first bit of a byte (LSB, if LSB-first order is used, MSB, if MSB-first order is used). If BSYNC is ’1’ when the last bit is received, the receiver stays active and next 8 bits are also received. BSYNC SDATA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DCLK Figure 5: BSYNC Signal - two byte transfer. 7.4.4 Passive SDI Mode If SM NEWMODE is 0 and SM SDISHARE is 1, the operation is otherwise like the VS1001 compatibility mode, but bits are only received while the BSYNC signal is ’1’. Rising edge of BSYNC is still used for synchronization. 7.5 Serial Protocol for Serial Command Interface (SCI) 7.5.1 General The serial bus protocol for the Serial Command Interface SCI (Chapter 8.6) consists of an instruction byte, address byte and one 16-bit data word. Each read or write operation can read or write a single register. Data bits are read at the rising edge, so the user should update data at the falling edge. Bytes are always send MSb first. XCS should be low for the full duration of the operation, but you can have pauses between bits if needed. The operation is specified by an 8-bit instruction opcode. The supported instructions are read and write. See table below. Instruction Name Opcode Operation READ 0b0000 0011 Read data WRITE 0b0000 0010 Write data Note: VS1053b sets DREQ low after each SCI operation. The duration depends on the operation. It is not allowed to finish a new SCI/SDI operation before DREQ is high again. Version 0.5, 2007-12-03 20 VLSI y Solution 7.5.2 VS1053 B VS1053b preliminary 7. SPI BUSES SCI Read XCS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 0 0 0 0 0 1 1 0 0 0 30 31 SCK 3 SI instruction (read) 2 1 0 don’t care 0 data out address 15 14 SO 0 0 0 0 0 0 0 0 0 0 0 0 0 don’t care 0 0 1 0 0 X execution DREQ Figure 6: SCI Word Read VS1053b registers are read from using the following sequence, as shown in Figure 6. First, XCS line is pulled low to select the device. Then the READ opcode (0x3) is transmitted via the SI line followed by an 8-bit word address. After the address has been read in, any further data on SI is ignored by the chip. The 16-bit data corresponding to the received address will be shifted out onto the SO line. XCS should be driven high after data has been shifted out. DREQ is driven low for a short while when in a read operation by the chip. This is a very short time and doesn’t require special user attention. 7.5.3 SCI Write XCS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SI 0 0 0 0 0 0 1 0 0 0 0 SO 0 0 0 0 0 0 0 30 31 SCK 3 instruction (write) 0 0 0 0 2 1 0 15 14 1 data out address 0 0 X 0 0 0 0 0 0 0 0 0 X execution DREQ Figure 7: SCI Word Write VS1053b registers are written from using the following sequence, as shown in Figure 7. First, XCS line is pulled low to select the device. Then the WRITE opcode (0x2) is transmitted via the SI line followed by an 8-bit word address. Version 0.5, 2007-12-03 21 VLSI y Solution VS1053 B VS1053b preliminary 7. SPI BUSES After the word has been shifted in and the last clock has been sent, XCS should be pulled high to end the WRITE sequence. After the last bit has been sent, DREQ is driven low for the duration of the register update, marked “execution” in the figure. The time varies depending on the register and its contents (see table in Chapter 8.7 for details). If the maximum time is longer than what it takes from the microcontroller to feed the next SCI command or SDI byte, status of DREQ must be checked before finishing the next SCI/SDI operation. 7.5.4 SCI Multiple Write XCS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SI 0 0 0 0 0 0 1 0 0 0 0 SO 0 0 0 0 0 0 0 29 30 31 32 33 m−2m−1 SCK 3 instruction (write) 0 0 0 0 2 1 0 15 14 1 0 data out 1 address 0 15 14 1 0 X 0 0 0 0 0 0 0 X data out 2 d.out n 0 0 0 execution 0 0 0 X execution DREQ Figure 8: SCI Multiple Word Write VS1053b allows for the user to send multiple words to the same SCI register, which allows fast SCI uploads, shown in Figure 8. The main difference to a single write is that instead of bringing XCS up after sending the last bit of a data word, the next data word is sent immediately. After the last data word, XCS is driven high as with a single word write. After the last bit of a word has been sent, DREQ is driven low for the duration of the register update, marked “execution” in the figure. The time varies depending on the register and its contents (see table in Chapter 8.7 for details). If the maximum time is longer than what it takes from the microcontroller to feed the next SCI command or SDI byte, status of DREQ must be checked before finishing the next SCI/SDI operation. Version 0.5, 2007-12-03 22 VLSI y Solution 7.6 VS1053 B VS1053b preliminary 7. SPI BUSES SPI Timing Diagram tWL tXCSS tWH tXCSH XCS 0 1 14 15 30 16 31 tXCS SCK SI tH tSU SO tZ tV tDIS Figure 9: SPI Timing Diagram. Symbol tXCSS tSU tH tZ tWL tWH tV tXCSH tXCS tDIS 1 Min 5 -26 2 0 2 2 Max 2 (+ 25ns1 ) -26 2 10 Unit ns ns CLKI cycles ns CLKI cycles CLKI cycles CLKI cycles ns CLKI cycles ns 25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance. Note: tWL and tWH, as well as tH require at least 2 clock cycles, so the maximum speed for the SPI bus that can easily be used is 1/6 of VS1053b’s internal clock speed CLKI. Slightly higher speed can be achieved with very careful timing tuning. For details, see Application Notes for VS10XX. Note: The system always starts up in 1.0× mode, thus CLKI=XTALI at startup. Note: Negative numbers mean that the signal can change in different order from what is shown in the diagram. Version 0.5, 2007-12-03 23 VLSI y Solution 7.7 7.7.1 VS1053 B VS1053b preliminary 7. SPI BUSES SPI Examples with SM SDINEW and SM SDISHARED set Two SCI Writes SCI Write 1 SCI Write 2 XCS 0 1 2 3 30 31 1 0 32 33 61 62 63 2 1 0 SCK SI 0 0 0 0 X 0 0 X DREQ up before finishing next SCI write DREQ Figure 10: Two SCI Operations. Figure 10 shows two consecutive SCI operations. Note that xCS must be raised to inactive state between the writes. Also DREQ must be respected as shown in the figure. 7.7.2 Two SDI Bytes SDI Byte 1 SDI Byte 2 XCS 0 1 2 3 7 6 5 4 6 7 8 9 1 0 7 6 13 14 15 2 1 0 SCK 3 SI 5 X DREQ Figure 11: Two SDI Bytes. SDI data is synchronized with a raising edge of xCS as shown in Figure 11. However, every byte doesn’t need separate synchronization. Version 0.5, 2007-12-03 24 VLSI y Solution 7.7.3 VS1053 B VS1053b preliminary 7. SPI BUSES SCI Operation in Middle of Two SDI Bytes SDI Byte SDI Byte SCI Operation XCS 0 1 7 8 9 39 40 41 7 6 46 47 1 0 SCK 7 SI 6 5 1 0 0 5 X 0 DREQ high before end of next transfer DREQ Figure 12: Two SDI Bytes Separated By an SCI Operation. Figure 12 shows how an SCI operation is embedded in between SDI operations. xCS edges are used to synchronize both SDI and SCI. Remember to respect DREQ as shown in the figure. Version 0.5, 2007-12-03 25 VLSI y Solution 8 VS1053 B VS1053b preliminary 8. FUNCTIONAL DESCRIPTION Functional Description 8.1 Main Features VS1053b is based on a proprietary digital signal processor, VS DSP. It contains all the code and data memory needed for Ogg Vorbis, MP3, AAC, WMA and WAV PCM + ADPCM audio decoding, MIDI synthesizer, together with serial interfaces, a multirate stereo audio DAC and analog output amplifiers and filters. Also ADPCM audio encoding is supported using a microphone amplifier and/or line-level inputs and a stereo A/D converter. A UART is provided for debugging purposes. 8.2 Supported Audio Codecs Mark + ? - 8.2.1 Conventions Description Format is supported Format is supported but not thoroughly tested Format exists but is not supported Format doesn’t exist Supported MP3 (MPEG layer III) Formats MPEG 1.01 : Samplerate / Hz 48000 44100 32000 32 + + + 40 + + + 48 + + + 56 + + + 64 + + + 80 + + + Bitrate / kbit/s 96 112 128 + + + + + + + + + 160 + + + 192 + + + 224 + + + 256 + + + 320 + + + 8 + + + 16 + + + 24 + + + 32 + + + 40 + + + 48 + + + Bitrate / kbit/s 56 64 80 + + + + + + + + + 96 + + + 112 + + + 128 + + + 144 + + + 160 + + + 8 + + + 16 + + + 24 + + + 32 + + + 40 + + + 48 + + + Bitrate / kbit/s 56 64 80 + + + + + + + + + 96 + + + 112 + + + 128 + + + 144 + + + 160 + + + MPEG 2.01 : Samplerate / Hz 24000 22050 16000 MPEG 2.51 : Samplerate / Hz 12000 11025 8000 1 Also all variable bitrate (VBR) formats are supported. Version 0.5, 2007-12-03 26 VLSI y Solution 8.2.2 VS1053 B VS1053b preliminary 8. FUNCTIONAL DESCRIPTION Supported MP1 (MPEG layer I) Formats Note: Layer I / II decoding must be specifically enabled from register SCI MODE. MPEG 1.0: Samplerate / Hz 48000 44100 32000 32 + + + 64 + + + 96 + + + 128 + + + 160 + + + Bitrate / kbit/s 192 224 256 288 + + + + + + + + + + + + 320 + + + 352 + + + 384 + + + 416 + + + 448 + + + 32 ? ? ? 48 ? ? ? 56 ? ? ? 64 ? ? ? 80 ? ? ? 96 ? ? ? Bitrate / kbit/s 112 128 144 ? ? ? ? ? ? ? ? ? 160 ? ? ? 176 ? ? ? 192 ? ? ? 224 ? ? ? 256 ? ? ? MPEG 2.0: Samplerate / Hz 24000 22050 16000 8.2.3 Supported MP2 (MPEG layer II) Formats Note: Layer I / II decoding must be specifically enabled from register SCI MODE. MPEG 1.0: Samplerate / Hz 48000 44100 32000 32 + + + 48 + + + 56 + + + 64 + + + 80 + + + 96 + + + Bitrate / kbit/s 112 128 160 + + + + + + + + + 192 + + + 224 + + + 256 + + + 320 + + + 384 + + + 8 + + + 16 + + + 24 + + + 32 + + + 40 + + + 48 + + + Bitrate / kbit/s 56 64 80 + + + + + + + + + 96 + + + 112 + + + 128 + + + 144 + + + 160 + + + MPEG 2.0: Samplerate / Hz 24000 22050 16000 8.2.4 Supported Ogg Vorbis Formats Parameter Channels Window size Samplerate Bitrate Min 64 Max 2 4096 48000 500 Unit samples Hz kbit/sec Only floor 1 is supported. No known current encoder uses floor 0. All one- and two-channel Ogg Vorbis files should be playable with this decoder. Version 0.5, 2007-12-03 27 VLSI VS1053b preliminary y Solution 8.2.5 VS1053 B 8. FUNCTIONAL DESCRIPTION Supported AAC (ISO/IEC 13818-7 and ISO/IEC 14496-3) Formats VS1053b decodes MPEG2-AAC-LC-2.0.0.0 and MPEG4-AAC-LC-2.0.0.0 streams, i.e. the low complexity profile with maximum of two channels can be decoded. If a stream contains more than one element and/or element type, you can select which one to decode from the 16 single-channel, 16 channelpair, and 16 low-frequency elements. The default is to select the first one that appears in the stream. Dynamic range control (DRC) is supported and can be controlled by the user to limit or enhance the dynamic range of the material that contains DRC information. Both Sine window and Kaiser-Bessel-derived window are supported. For MPEG4 pseudo-random noise substitution (PNS) is supported. Short frames (120 and 960 samples) are not supported. Spectral Band Replication (SBR) level 3, and Parametric Stereo (PS) level 3 are supported (HE-AAC v2). Level 3 means that maximum of 2 channels, samplerates upto and including 48 kHz without and with SBR (with or without PS) are supported. Also, both mixing modes (Ra and Rb ), IPD/OPD synthesis and 34 frequency bands resolution are implemented. The downsampled synthesis mode (core coder samplerates > 24 kHz and 0 for automatic m4a, ADIF, WMA resyncs */ union { struct { u_int32 curPacketSize; u_int32 packetSize; } wma; struct { u_int16 sceFoundMask; /*1e2a SCE’s found since last clear */ u_int16 cpeFoundMask; /*1e2b CPE’s found since last clear */ u_int16 lfeFoundMask; /*1e2c LFE’s found since last clear */ u_int16 playSelect; /*1e2d 0 = first any, initialized at aac init */ s_int16 dynCompress; /*1e2e -8192=1.0, initialized at aac init */ s_int16 dynBoost; /*1e2f 8192=1.0, initialized at aac init */ u_int16 sbrAndPsStatus; /*0x1e30 1=SBR, 2=upsample, 4=PS, 8=PS active */ } aac; struct { u_int32 bytesLeft; } midi; struct { s_int16 gain; /* 0x1e2a proposed gain offset in 0.5dB steps, default = -12 */ } vorbis; } i; }; Notice that reading two-word variables through the SCI WRAMADDR and SCI WRAM interface is not protected in any way. The variable can be updated between the read of the low and high parts. The problem arises when both the low and high parts change values. To determine if the value is correct, you should read the value twice and compare the results. The following example shows what happens when bytesLeft is decreased from 0x10000 to 0xffff and the update happens between low and high part reads or after high part read. Read Invalid Address Value 0x1e2a 0x0000 change after this 0x1e2b 0x0000 0x1e2a 0xffff 0x1e2b 0x0000 Version 0.5, 2007-12-03 Address 0x1e2a 0x1e2b 0x1e2a 0x1e2b Read Valid Value 0x0000 0x0001 change after this 0xffff 0x0000 No Update Address Value 0x1e2a 0x0000 0x1e2b 0x0001 0x1e2a 0x0000 0x1e2b 0x0001 57 VLSI VS1053b preliminary y Solution VS1053 B 9. OPERATION You can see that in the invalid read the low part wraps from 0x0000 to 0xffff while the high part stays the same. In this case the second read gives a valid answer, otherwise always use the value of the first read. The second read is needed when it is possible that the low part wraps around, changing the high part, i.e. when the low part is small. bytesLeft is only decreased by one at a time, so a reread is needed only if the low part is 0. 9.11.1 Common Parameters These parameters are common for all codecs. Other fields are only valid when the corresponding codec is active. The currently active codec can be determined from SCI HDAT1. Parameter chipID version config1 playSpeed byteRate endFillByte jumpPoints[8] latestJump positionMsec resync Address 0x1e00-01 0x1e02 0x1e03 0x1e04 0x1e05 0x1e06 0x1e16-25 0x1e26 0x1e27-28 0x1e29 Usage Fuse-programmed unique ID (cosmetic copy of the fuses) Structure version – 0x0003 Miscellaneous configuration 0,1 = normal speed, 2 = twice, 3 = three times etc. average byterate byte to send after file Packet offsets for WMA and AAC Index to latest jumpPoint File position in milliseconds, if available Automatic resync selector The fuse-programmed ID is read at startup and copied into the chipID field. If not available, the value will be all zeros. The version field can be used to determine the layout of the rest of the structure. The version number is changed when the structure is changed. For VS1053b the structure version is 3. config1 controls MIDI Reverb and AAC’s SBR and PS settings. playSpeed makes it possible to fast forward songs. Decoding of the bitstream is performed, but only each playSpeed frames are played. For example by writing 4 to playSpeed will play the song four times as fast as normal, if you are able to feed the data with that speed. Write 0 or 1 to return to normal speed. SCI DECODE TIME will also count faster. All current codecs support the playSpeed configuration. byteRate contains the average bitrate in bytes per second for every code. The value is updated once per second and it can be used to calculate an estimate of the remaining playtime. This value is also available in SCI HDAT0 for all codecs except MP3, MP2, and MP1. endFillByte indicates what byte value to send after file is sent before SM CANCEL. jumpPoints contain 32-bit file offsets. Each valid (non-zero) entry indicates a start of a packet for WMA or start of a raw data block for AAC (ADIF, .mp4 / .m4a). latestJump contains the index of the entry that was updated last. If you only read entry pointed to by latestJump you do not need to read the entry twice to ensure validity. Jump point information can be used to implement perfect fast forward and rewind for WMA and AAC (ADIF, .mp4 / .m4a). Version 0.5, 2007-12-03 58 VLSI VS1053b preliminary y Solution VS1053 B 9. OPERATION positionMsec is a field that gives the current play position in a file in milliseconds, regardless of rewind and fast forward operations. The value is only available in codecs that can determine the play position from the stream itself. Currently WMA and Ogg Vorbis provide this information. If the position is unknown, this field contains -1. resync field is used to force a resynchronization to the stream for WMA and AAC (ADIF, .mp4 / .m4a) instead of ending the decode at first error. This field can be used to implement almost perfect fast forward and rewind for WMA and AAC (ADIF, .mp4 / .m4a). The user should set this field before performing data seeks if they are not in packet or data block boundaries. The field value tells how many tries are allowed before giving up. The value 32767 gives infinite tries. The resync field is set to 32767 after a reset to make resynchronization the default action, but it can be cleared after reset to restore the old action. When resync is set, every file decode should always end as described in Chapter 9.5.1. Seek fields no longer exist. When resync is required, WMA and AAC codecs now enter broadcast/stream mode where file size information is ignored. Also, the file size and sample size information of WAV files are ignored when resync is non-zero. The user must use SM CANCEL or software reset to end decoding. Note: WAV, WMA, ADIF, and .mp4 / .m4a files begin with a metadata or header section, which must be fully processed before any fast forward or rewind operation. SS DO NOT JUMP (in SCI STATUS) is clear when the header information has been processed and jumps are allowed. 9.11.2 WMA Parameter curPacketSize packetSize Address 0x1e2a/2b 0x1e2c/2d Usage The size of the packet being processed The packet size in ASF header The ASF header packet size is available in packetSize. With this information and a packet start offset from jumpPoints you can parse the packet headers and skip packets in ASF files. WMA decoder can also increase the internal clock automatically when it detects that a file can not be decoded correctly with the current clock. The maximum allowed clock is configured with the SCI CLOCKF register. Version 0.5, 2007-12-03 59 VLSI VS1053b preliminary y Solution 9.11.3 VS1053 B 9. OPERATION AAC Parameter config1 sceFoundMask cpeFoundMask lfeFoundMask playSelect dynCompress dynBoost sbrAndPsStatus Address 0x1e03(7:4) 0x1e2a 0x1e2b 0x1e2c 0x1e2d 0x1e2e 0x1e2f 0x1e30 Usage SBR and PS select Single channel elements found Channel pair elements found Low frequency elements found Play element selection Compress coefficient for DRC, -8192=1.0 Boost coefficient for DRC, 8192=1.0 SBR and PS available flags playSelect determines which element to decode if a stream has multiple elements. The value is set to 0 each time AAC decoding starts, which causes the first element that appears in the stream to be selected for decoding. Other values are: 0x01 - select first single channel element (SCE), 0x02 - select first channel pair element (CPE), 0x03 - select first low frequency element (LFE), S ∗ 16 + 5 - select SCE number S, P ∗ 16 + 6 - select CPE number P, L ∗ 16 + 7 - select LFE number L. When automatic selection has been performed, playSelect reflects the selected element. sceFoundMask, cpeFoundMask, and lfeFoundMask indicate which elements have been found in an AAC stream since the variables have last been cleared. The values can be used to present an element selection menu with only the available elements. dynCompress and dynBoost change the behavior of the dynamic range control (DRC) that is present in some AAC streams. These are also initialized when AAC decoding starts. sbrAndPsStatus indicates spectral band replication (SBR) and parametric stereo (PS) status. Bit 0 1 2 3 Usage SBR present upsampling active PS present PS active Bits 7 to 4 in config1 can be used to control the SBR and PS decoding. Bits 5 and 4 select SBR mode and bits 7 and 6 select PS mode. These configuration bits are useful if your AAC license does not cover SBR and/or PS. config1(5:4) ’00’ ’01’ ’10’ ’11’ Version 0.5, Usage normal mode, upsample